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Updated and Validated
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal_cec.h
blob0d394813cd6894f5e82e44c5c30db7f071b90f48
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_cec.h
4 * @author MCD Application Team
5 * @brief Header file of CEC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_HAL_CEC_H
38 #define __STM32F3xx_HAL_CEC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(STM32F373xC) || defined(STM32F378xx)
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f3xx_hal_def.h"
47
48 /** @addtogroup STM32F3xx_HAL_Driver
49 * @{
50 */
51
52 /** @addtogroup CEC
53 * @{
54 */
55
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup CEC_Exported_Types CEC Exported Types
58 * @{
59 */
60
61 /**
62 * @brief CEC Init Structure definition
63 */
64 typedef struct
65 {
66 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
67 It can be one of @ref CEC_Signal_Free_Time
68 and belongs to the set {0U,...,7} where
69 0x0 is the default configuration
70 else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
71
72 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
73 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
74 or CEC_EXTENDED_TOLERANCE */
75
76 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
77 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
78 CEC_RX_STOP_ON_BRE: reception is stopped. */
79
80 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
81 CEC line upon Bit Rising Error detection.
82 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
83 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
84
85 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
86 CEC line upon Long Bit Period Error detection.
87 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
88 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
89
90 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
91 upon an error detected on a broadcast message.
92
93 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
94
95 1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
96 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
97 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
98 b) LBPE detection: error-bit generation on the CEC line
99 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
100
101 2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
102 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
103 there is no error-bit generation in case of Short Bit Period Error detection in
104 a broadcast message while LSTN bit is set. */
105
106 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
107 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
108 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
109
110 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
111
112 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
113 own address (OAR). Messages addressed to different destination are ignored.
114 Broadcast messages are always received.
115
116 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
117 address (OAR) with positive acknowledge. Messages addressed to different destination
118 are received, but without interfering with the CEC bus: no acknowledge sent. */
119
120 uint16_t OwnAddress; /*!< Own addresses configuration
121 This parameter can be a value of @ref CEC_OWN_ADDRESS */
122
123 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
124
125
126 }CEC_InitTypeDef;
127
128 /**
129 * @brief HAL CEC State structures definition
130 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
131 * - gState contains CEC state information related to global Handle management
132 * and also information related to Tx operations.
133 * gState value coding follow below described bitmap :
134 * b7 (not used)
135 * x : Should be set to 0
136 * b6 Error information
137 * 0 : No Error
138 * 1 : Error
139 * b5 IP initilisation status
140 * 0 : Reset (IP not initialized)
141 * 1 : Init done (IP initialized. HAL CEC Init function already called)
142 * b4-b3 (not used)
143 * xx : Should be set to 00
144 * b2 Intrinsic process state
145 * 0 : Ready
146 * 1 : Busy (IP busy with some configuration or internal operations)
147 * b1 (not used)
148 * x : Should be set to 0
149 * b0 Tx state
150 * 0 : Ready (no Tx operation ongoing)
151 * 1 : Busy (Tx operation ongoing)
152 * - RxState contains information related to Rx operations.
153 * RxState value coding follow below described bitmap :
154 * b7-b6 (not used)
155 * xx : Should be set to 00
156 * b5 IP initilisation status
157 * 0 : Reset (IP not initialized)
158 * 1 : Init done (IP initialized)
159 * b4-b2 (not used)
160 * xxx : Should be set to 000
161 * b1 Rx state
162 * 0 : Ready (no Rx operation ongoing)
163 * 1 : Busy (Rx operation ongoing)
164 * b0 (not used)
165 * x : Should be set to 0.
166 */
167 typedef enum
168 {
169 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
170 Value is allowed for gState and RxState */
171 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
172 Value is allowed for gState and RxState */
173 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
174 Value is allowed for gState only */
175 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
176 Value is allowed for RxState only */
177 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
178 Value is allowed for gState only */
179 HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
180 Value is allowed for gState only */
181 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
182 }HAL_CEC_StateTypeDef;
183
184 /**
185 * @brief CEC handle Structure definition
186 */
187 typedef struct
188 {
189 CEC_TypeDef *Instance; /*!< CEC registers base address */
190
191 CEC_InitTypeDef Init; /*!< CEC communication parameters */
192
193 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
194
195 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
196
197 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
198
199 HAL_LockTypeDef Lock; /*!< Locking object */
200
201 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
202 and also related to Tx operations.
203 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
204
205 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
206 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
207
208 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
209 in case error is reported */
210 }CEC_HandleTypeDef;
211 /**
212 * @}
213 */
214
215 /* Exported constants --------------------------------------------------------*/
216 /** @defgroup CEC_Exported_Constants CEC Exported Constants
217 * @{
218 */
219
220 /** @defgroup CEC_Error_Code CEC Error Code
221 * @{
222 */
223 #define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
224 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
225 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
226 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
227 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
228 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
229 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
230 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
231 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
232 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
233 /**
234 * @}
235 */
236
237 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
238 * @{
239 */
240 #define CEC_DEFAULT_SFT (0x00000000U)
241 #define CEC_0_5_BITPERIOD_SFT (0x00000001U)
242 #define CEC_1_5_BITPERIOD_SFT (0x00000002U)
243 #define CEC_2_5_BITPERIOD_SFT (0x00000003U)
244 #define CEC_3_5_BITPERIOD_SFT (0x00000004U)
245 #define CEC_4_5_BITPERIOD_SFT (0x00000005U)
246 #define CEC_5_5_BITPERIOD_SFT (0x00000006U)
247 #define CEC_6_5_BITPERIOD_SFT (0x00000007U)
248 /**
249 * @}
250 */
251
252 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
253 * @{
254 */
255 #define CEC_STANDARD_TOLERANCE (0x00000000U)
256 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
257 /**
258 * @}
259 */
260
261 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
262 * @{
263 */
264 #define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
265 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
266 /**
267 * @}
268 */
269
270 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
271 * @{
272 */
273 #define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
274 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
275 /**
276 * @}
277 */
278
279 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
280 * @{
281 */
282 #define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
283 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
284 /**
285 * @}
286 */
287
288 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
289 * @{
290 */
291 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
292 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
293 /**
294 * @}
295 */
296
297 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option
298 * @{
299 */
300 #define CEC_SFT_START_ON_TXSOM (0x00000000U)
301 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
302 /**
303 * @}
304 */
305
306 /** @defgroup CEC_Listening_Mode CEC Listening mode option
307 * @{
308 */
309 #define CEC_REDUCED_LISTENING_MODE (0x00000000U)
310 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
311 /**
312 * @}
313 */
314
315 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
316 * @{
317 */
318 #define CEC_CFGR_OAR_LSB_POS (16U)
319 /**
320 * @}
321 */
322
323 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
324 * @{
325 */
326 #define CEC_INITIATOR_LSB_POS (4U)
327 /**
328 * @}
329 */
330
331 /** @defgroup CEC_OWN_ADDRESS CEC Own Address
332 * @{
333 */
334 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
335 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
336 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
337 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
338 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
339 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
340 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
341 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
342 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
343 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
344 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
345 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
346 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
347 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
348 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
349 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
350 /**
351 * @}
352 */
353
354 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
355 * @{
356 */
357 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
358 #define CEC_IT_TXERR CEC_IER_TXERRIE
359 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
360 #define CEC_IT_TXEND CEC_IER_TXENDIE
361 #define CEC_IT_TXBR CEC_IER_TXBRIE
362 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
363 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
364 #define CEC_IT_LBPE CEC_IER_LBPEIE
365 #define CEC_IT_SBPE CEC_IER_SBPEIE
366 #define CEC_IT_BRE CEC_IER_BREIE
367 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
368 #define CEC_IT_RXEND CEC_IER_RXENDIE
369 #define CEC_IT_RXBR CEC_IER_RXBRIE
370 /**
371 * @}
372 */
373
374 /** @defgroup CEC_Flags_Definitions CEC Flags definition
375 * @{
376 */
377 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
378 #define CEC_FLAG_TXERR CEC_ISR_TXERR
379 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
380 #define CEC_FLAG_TXEND CEC_ISR_TXEND
381 #define CEC_FLAG_TXBR CEC_ISR_TXBR
382 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
383 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
384 #define CEC_FLAG_LBPE CEC_ISR_LBPE
385 #define CEC_FLAG_SBPE CEC_ISR_SBPE
386 #define CEC_FLAG_BRE CEC_ISR_BRE
387 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
388 #define CEC_FLAG_RXEND CEC_ISR_RXEND
389 #define CEC_FLAG_RXBR CEC_ISR_RXBR
390 /**
391 * @}
392 */
393
394 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
395 * @{
396 */
397 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
398 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
399 /**
400 * @}
401 */
402
403 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
404 * @{
405 */
406 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
407 /**
408 * @}
409 */
410
411 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
412 * @{
413 */
414 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
415 /**
416 * @}
417 */
418
419 /**
420 * @}
421 */
422
423 /* Exported macros -----------------------------------------------------------*/
424 /** @defgroup CEC_Exported_Macros CEC Exported Macros
425 * @{
426 */
427
428 /** @brief Reset CEC handle gstate & RxState
429 * @param __HANDLE__ CEC handle.
430 * @retval None
431 */
432 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
433 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
434 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
435 } while(0U)
436
437 /** @brief Checks whether or not the specified CEC interrupt flag is set.
438 * @param __HANDLE__ specifies the CEC Handle.
439 * @param __FLAG__ specifies the flag to check.
440 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
441 * @arg CEC_FLAG_TXERR: Tx Error.
442 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
443 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
444 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
445 * @arg CEC_FLAG_ARBLST: Arbitration Lost
446 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
447 * @arg CEC_FLAG_LBPE: Rx Long period Error
448 * @arg CEC_FLAG_SBPE: Rx Short period Error
449 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
450 * @arg CEC_FLAG_RXOVR: Rx Overrun.
451 * @arg CEC_FLAG_RXEND: End Of Reception.
452 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
453 * @retval ITStatus
454 */
455 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
456
457 /** @brief Clears the interrupt or status flag when raised (write at 1U)
458 * @param __HANDLE__ specifies the CEC Handle.
459 * @param __FLAG__ specifies the interrupt/status flag to clear.
460 * This parameter can be one of the following values:
461 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
462 * @arg CEC_FLAG_TXERR: Tx Error.
463 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
464 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
465 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
466 * @arg CEC_FLAG_ARBLST: Arbitration Lost
467 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
468 * @arg CEC_FLAG_LBPE: Rx Long period Error
469 * @arg CEC_FLAG_SBPE: Rx Short period Error
470 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
471 * @arg CEC_FLAG_RXOVR: Rx Overrun.
472 * @arg CEC_FLAG_RXEND: End Of Reception.
473 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
474 * @retval none
475 */
476 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
477
478 /** @brief Enables the specified CEC interrupt.
479 * @param __HANDLE__ specifies the CEC Handle.
480 * @param __INTERRUPT__ specifies the CEC interrupt to enable.
481 * This parameter can be one of the following values:
482 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
483 * @arg CEC_IT_TXERR: Tx Error IT Enable
484 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
485 * @arg CEC_IT_TXEND: End of transmission IT Enable
486 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
487 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
488 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
489 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
490 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
491 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
492 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
493 * @arg CEC_IT_RXEND: End Of Reception IT Enable
494 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
495 * @retval none
496 */
497 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
498
499 /** @brief Disables the specified CEC interrupt.
500 * @param __HANDLE__ specifies the CEC Handle.
501 * @param __INTERRUPT__ specifies the CEC interrupt to disable.
502 * This parameter can be one of the following values:
503 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
504 * @arg CEC_IT_TXERR: Tx Error IT Enable
505 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
506 * @arg CEC_IT_TXEND: End of transmission IT Enable
507 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
508 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
509 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
510 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
511 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
512 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
513 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
514 * @arg CEC_IT_RXEND: End Of Reception IT Enable
515 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
516 * @retval none
517 */
518 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
519
520 /** @brief Checks whether or not the specified CEC interrupt is enabled.
521 * @param __HANDLE__ specifies the CEC Handle.
522 * @param __INTERRUPT__ specifies the CEC interrupt to check.
523 * This parameter can be one of the following values:
524 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
525 * @arg CEC_IT_TXERR: Tx Error IT Enable
526 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
527 * @arg CEC_IT_TXEND: End of transmission IT Enable
528 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
529 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
530 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
531 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
532 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
533 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
534 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
535 * @arg CEC_IT_RXEND: End Of Reception IT Enable
536 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
537 * @retval FlagStatus
538 */
539 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
540
541 /** @brief Enables the CEC device
542 * @param __HANDLE__ specifies the CEC Handle.
543 * @retval none
544 */
545 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
546
547 /** @brief Disables the CEC device
548 * @param __HANDLE__ specifies the CEC Handle.
549 * @retval none
550 */
551 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
552
553 /** @brief Set Transmission Start flag
554 * @param __HANDLE__ specifies the CEC Handle.
555 * @retval none
556 */
557 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
558
559 /** @brief Set Transmission End flag
560 * @param __HANDLE__ specifies the CEC Handle.
561 * @retval none
562 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
563 */
564 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
565
566 /** @brief Get Transmission Start flag
567 * @param __HANDLE__ specifies the CEC Handle.
568 * @retval FlagStatus
569 */
570 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
571
572 /** @brief Get Transmission End flag
573 * @param __HANDLE__ specifies the CEC Handle.
574 * @retval FlagStatus
575 */
576 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
577
578 /** @brief Clear OAR register
579 * @param __HANDLE__ specifies the CEC Handle.
580 * @retval none
581 */
582 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
583
584 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
585 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
586 * @param __HANDLE__ specifies the CEC Handle.
587 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
588 * @retval none
589 */
590 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
591
592 /**
593 * @}
594 */
595
596 /* Exported functions --------------------------------------------------------*/
597 /** @addtogroup CEC_Exported_Functions
598 * @{
599 */
600
601 /** @addtogroup CEC_Exported_Functions_Group1
602 * @{
603 */
604 /* Initialization and de-initialization functions ****************************/
605 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
606 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
607 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
608 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
609 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
610 /**
611 * @}
612 */
613
614 /** @addtogroup CEC_Exported_Functions_Group2
615 * @{
616 */
617 /* I/O operation functions ***************************************************/
618 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
619 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
620 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
621 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
622 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
623 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
624 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
625 /**
626 * @}
627 */
628
629 /** @addtogroup CEC_Exported_Functions_Group3
630 * @{
631 */
632 /* Peripheral State functions ************************************************/
633 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
634 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
635 /**
636 * @}
637 */
638
639 /**
640 * @}
641 */
642
643 /* Private types -------------------------------------------------------------*/
644 /** @defgroup CEC_Private_Types CEC Private Types
645 * @{
646 */
647
648 /**
649 * @}
650 */
651
652 /* Private variables ---------------------------------------------------------*/
653 /** @defgroup CEC_Private_Variables CEC Private Variables
654 * @{
655 */
656
657 /**
658 * @}
659 */
660
661 /* Private constants ---------------------------------------------------------*/
662 /** @defgroup CEC_Private_Constants CEC Private Constants
663 * @{
664 */
665
666 /**
667 * @}
668 */
669
670 /* Private macros ------------------------------------------------------------*/
671 /** @defgroup CEC_Private_Macros CEC Private Macros
672 * @{
673 */
674
675 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
676
677 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
678 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
679
680 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
681 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
682
683 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
684 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
685
686 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
687 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
688
689 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
690 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
691
692 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
693 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
694
695 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
696 ((__MODE__) == CEC_FULL_LISTENING_MODE))
697
698 /** @brief Check CEC message size.
699 * The message size is the payload size: without counting the header,
700 * it varies from 0 byte (ping operation, one header only, no payload) to
701 * 15 bytes (1 opcode and up to 14 operands following the header).
702 * @param __SIZE__ CEC message size.
703 * @retval Test result (TRUE or FALSE).
704 */
705 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
706
707 /** @brief Check CEC device Own Address Register (OAR) setting.
708 * OAR address is written in a 15-bit field within CEC_CFGR register.
709 * @param __ADDRESS__ CEC own address.
710 * @retval Test result (TRUE or FALSE).
711 */
712 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
713
714 /** @brief Check CEC initiator or destination logical address setting.
715 * Initiator and destination addresses are coded over 4 bits.
716 * @param __ADDRESS__ CEC initiator or logical address.
717 * @retval Test result (TRUE or FALSE).
718 */
719 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
720 /**
721 * @}
722 */
723 /* Private functions ---------------------------------------------------------*/
724 /** @defgroup CEC_Private_Functions CEC Private Functions
725 * @{
726 */
727
728 /**
729 * @}
730 */
731
732 /**
733 * @}
734 */
735
736 /**
737 * @}
738 */
739
740 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
741
742 #ifdef __cplusplus
743 }
744 #endif
745
746 #endif /* __STM32F3xx_HAL_CEC_H */
747
748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
749