lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of NAND HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_HAL_NAND_H
  38 #define __STM32F3xx_HAL_NAND_H
  39
  40 #ifdef __cplusplus
  41  extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  46 #include "stm32f3xx_ll_fmc.h"
  47
  48 /** @addtogroup STM32F3xx_HAL_Driver
  49   * @{
  50   */
  51
  52 /** @addtogroup NAND
  53   * @{
  54   */
  55
  56 /* Exported typedef ----------------------------------------------------------*/
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup NAND_Exported_Types NAND Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  HAL NAND State structures definition
  64   */
  65 typedef enum
  66 {
  67   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  68   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  69   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  70   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  71 }HAL_NAND_StateTypeDef;
  72
  73 /**
  74   * @brief  NAND Memory electronic signature Structure definition
  75   */
  76 typedef struct
  77 {
  78   /*<! NAND memory electronic signature maker and device IDs */
  79
  80   uint8_t Maker_Id;
  81
  82   uint8_t Device_Id;
  83
  84   uint8_t Third_Id;
  85
  86   uint8_t Fourth_Id;
  87 }NAND_IDTypeDef;
  88
  89 /**
  90   * @brief  NAND Memory address Structure definition
  91   */
  92 typedef struct
  93 {
  94   uint16_t Page;   /*!< NAND memory Page address    */
  95
  96   uint16_t Plane;   /*!< NAND memory Plane address  */
  97
  98   uint16_t Block;  /*!< NAND memory Block address   */
  99
 100 }NAND_AddressTypeDef;
 101
 102 /**
 103   * @brief  NAND Memory info Structure definition
 104   */
 105 typedef struct
 106 {
 107   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
 108                                               for 8 bits adressing or words for 16 bits addressing             */
 109
 110   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
 111                                               for 8 bits adressing or words for 16 bits addressing             */
 112
 113   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 114
 115   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 116
 117   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 118
 119   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks               */
 120
 121   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 122                                               parameter is mandatory for some NAND parts after the read
 123                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 124                                               Example: Toshiba THTH58BYG3S0HBAI6.
 125                                               This parameter could be ENABLE or DISABLE
 126                                               Please check the Read Mode sequnece in the NAND device datasheet */
 127 }NAND_DeviceConfigTypeDef;
 128
 129 /**
 130   * @brief  NAND handle Structure definition
 131   */
 132 typedef struct
 133 {
 134   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 135
 136   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 137
 138   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 139
 140   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 141
 142   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 143
 144 }NAND_HandleTypeDef;
 145 /**
 146   * @}
 147   */
 148
 149 /* Exported constants --------------------------------------------------------*/
 150 /* Exported macros ------------------------------------------------------------*/
 151 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 152  * @{
 153  */
 154
 155 /** @brief Reset NAND handle state
 156   * @param  __HANDLE__ specifies the NAND handle.
 157   * @retval None
 158   */
 159 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 160
 161 /**
 162   * @}
 163   */
 164
 165 /* Exported functions --------------------------------------------------------*/
 166 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 167   * @{
 168   */
 169
 170 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 171   * @{
 172   */
 173
 174 /* Initialization/de-initialization functions  ********************************/
 175 /* Initialization/de-initialization functions  ********************************/
 176 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 177 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 178
 179 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 180
 181 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 182
 183 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 184 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 185 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 186 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 187
 188 /**
 189   * @}
 190   */
 191
 192 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 193   * @{
 194   */
 195
 196 /* IO operation functions  ****************************************************/
 197 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 198
 199 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 200 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 201 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 202 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 203
 204 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 205 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 206 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 207 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 208
 209 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 210
 211 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 212 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 213
 214 /**
 215   * @}
 216   */
 217
 218 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 219   * @{
 220   */
 221
 222 /* NAND Control functions  ****************************************************/
 223 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 224 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 225 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 226
 227 /**
 228   * @}
 229   */
 230
 231 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 232   * @{
 233   */
 234 /* NAND State functions *******************************************************/
 235 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 236 /**
 237   * @}
 238   */
 239
 240 /**
 241   * @}
 242   */
 243
 244 /* Private types -------------------------------------------------------------*/
 245 /* Private variables ---------------------------------------------------------*/
 246 /* Private constants ---------------------------------------------------------*/
 247 /** @defgroup NAND_Private_Constants NAND Private Constants
 248   * @{
 249   */
 250 #define NAND_DEVICE1               FMC_BANK2
 251 #define NAND_DEVICE2               FMC_BANK3
 252 #define NAND_WRITE_TIMEOUT         0x01000000U
 253
 254 #define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16 = CLE high */
 255 #define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17 = ALE high */
 256
 257 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
 258 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
 259 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
 260 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
 261
 262 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
 263 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
 264 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
 265 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
 266 #define NAND_CMD_READID            ((uint8_t)0x90)
 267 #define NAND_CMD_STATUS            ((uint8_t)0x70)
 268 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
 269 #define NAND_CMD_RESET             ((uint8_t)0xFF)
 270
 271 /* NAND memory status */
 272 #define NAND_VALID_ADDRESS         0x00000100U
 273 #define NAND_INVALID_ADDRESS       0x00000200U
 274 #define NAND_TIMEOUT_ERROR         0x00000400U
 275 #define NAND_BUSY                  0x00000000U
 276 #define NAND_ERROR                 0x00000001U
 277 #define NAND_READY                 0x00000040U
 278 /**
 279   * @}
 280   */
 281
 282 /* Private macros ------------------------------------------------------------*/
 283 /** @defgroup NAND_Private_Macros NAND Private Macros
 284   * @{
 285   */
 286
 287 /**
 288   * @brief  NAND memory address computation.
 289   * @param  __ADDRESS__ NAND memory address.
 290   * @param  __HANDLE__ NAND handle.
 291   * @retval NAND Raw address value
 292   */
 293 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 294                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 295
 296 /**
 297   * @brief  NAND memory Column address computation.
 298   * @param  __HANDLE__ NAND handle.
 299   * @retval NAND Raw address value
 300   */
 301 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 302
 303 /**
 304   * @brief  NAND memory address cycling.
 305   * @param  __ADDRESS__ NAND memory address.
 306   * @retval NAND address cycling value.
 307   */
 308 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 309 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 310 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 311 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 312
 313 /**
 314   * @brief  NAND memory Columns cycling.
 315   * @param  __ADDRESS__ NAND memory address.
 316   * @retval NAND Column address cycling value.
 317   */
 318 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
 319 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 320
 321 /**
 322   * @}
 323   */
 324
 325 /**
 326   * @}
 327   */
 328 /**
 329   * @}
 330   */
 331
 332 /**
 333   * @}
 334   */
 335
 336 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 337
 338 #ifdef __cplusplus
 339 }
 340 #endif
 341
 342 #endif /* __STM32F3xx_HAL_NAND_H */
 343
 344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/