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Updated and Validated
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal_rcc.h
blobb2e8f19d89eb52ae19ae2c889d8d89653c7f38b2
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_HAL_RCC_H
38 #define __STM32F3xx_HAL_RCC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx_hal_def.h"
46
47 /** @addtogroup STM32F3xx_HAL_Driver
48 * @{
49 */
50
51 /** @addtogroup RCC
52 * @{
53 */
54
55 /** @addtogroup RCC_Private_Constants
56 * @{
57 */
58
59 /** @defgroup RCC_Timeout RCC Timeout
60 * @{
61 */
62
63 /* Disable Backup domain write protection state change timeout */
64 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
65 /* LSE state change timeout */
66 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
67 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
68 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
69 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
70 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
71 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
72 /**
73 * @}
74 */
75
76 /** @defgroup RCC_Register_Offset Register offsets
77 * @{
78 */
79 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
80 #define RCC_CR_OFFSET 0x00
81 #define RCC_CFGR_OFFSET 0x04
82 #define RCC_CIR_OFFSET 0x08
83 #define RCC_BDCR_OFFSET 0x20
84 #define RCC_CSR_OFFSET 0x24
85
86 /**
87 * @}
88 */
89
90 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
91 * @brief RCC registers bit address in the alias region
92 * @{
93 */
94 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
95 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
96 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
97 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
98 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
99
100 /* --- CR Register ---*/
101 /* Alias word address of HSION bit */
102 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
103 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
104 /* Alias word address of HSEON bit */
105 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
106 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
107 /* Alias word address of CSSON bit */
108 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
109 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
110 /* Alias word address of PLLON bit */
111 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
112 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
113
114 /* --- CSR Register ---*/
115 /* Alias word address of LSION bit */
116 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
117 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
118
119 /* Alias word address of RMVF bit */
120 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
121 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
122
123 /* --- BDCR Registers ---*/
124 /* Alias word address of LSEON bit */
125 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
126 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
127
128 /* Alias word address of LSEON bit */
129 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
130 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
131
132 /* Alias word address of RTCEN bit */
133 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
134 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
135
136 /* Alias word address of BDRST bit */
137 #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
138 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
139
140 /**
141 * @}
142 */
143
144 /* CR register byte 2 (Bits[23:16]) base address */
145 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
146
147 /* CIR register byte 1 (Bits[15:8]) base address */
148 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
149
150 /* CIR register byte 2 (Bits[23:16]) base address */
151 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
152
153 /* Defines used for Flags */
154 #define CR_REG_INDEX ((uint8_t)1U)
155 #define BDCR_REG_INDEX ((uint8_t)2U)
156 #define CSR_REG_INDEX ((uint8_t)3U)
157 #define CFGR_REG_INDEX ((uint8_t)4U)
158
159 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
160
161 /**
162 * @}
163 */
164
165 /** @addtogroup RCC_Private_Macros
166 * @{
167 */
168 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
169 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
170 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
171 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
172 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
173 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
174 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
175 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
176 ((__HSE__) == RCC_HSE_BYPASS))
177 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
178 ((__LSE__) == RCC_LSE_BYPASS))
179 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
180 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
181 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
182 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
183 ((__PLL__) == RCC_PLL_ON))
184 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
185 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
186 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
187 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
188 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
189 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
190 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
191 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
192 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
193 #else
194 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
195 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
196 #endif
197 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
198 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
199 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
200 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
201 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
202 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
203 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
204 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
205 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
206 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
207
208 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
209 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
210 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
211 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
212 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
213 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
214 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
215 ((__MUL__) == RCC_PLL_MUL16))
216 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
217 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
218 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
219 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
220 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
221 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
222 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
223 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
224 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
225 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
226 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
227 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
228 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
229 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
230 ((__HCLK__) == RCC_SYSCLK_DIV512))
231 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
232 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
233 ((__PCLK__) == RCC_HCLK_DIV16))
234 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
235 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
236 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
237 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
238 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
239 #if defined(RCC_CFGR3_USART2SW)
240 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
241 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
242 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
243 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
244 #endif /* RCC_CFGR3_USART2SW */
245 #if defined(RCC_CFGR3_USART3SW)
246 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
247 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
248 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
249 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
250 #endif /* RCC_CFGR3_USART3SW */
251 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
252 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
253
254 /**
255 * @}
256 */
257
258 /* Exported types ------------------------------------------------------------*/
259
260 /** @defgroup RCC_Exported_Types RCC Exported Types
261 * @{
262 */
263
264 /**
265 * @brief RCC PLL configuration structure definition
266 */
267 typedef struct
268 {
269 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
270 This parameter can be a value of @ref RCC_PLL_Config */
271
272 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
273 This parameter must be a value of @ref RCC_PLL_Clock_Source */
274
275 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
276 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
277
278 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
279 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
280 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
281
282 #endif
283 } RCC_PLLInitTypeDef;
284
285 /**
286 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
287 */
288 typedef struct
289 {
290 uint32_t OscillatorType; /*!< The oscillators to be configured.
291 This parameter can be a value of @ref RCC_Oscillator_Type */
292
293 uint32_t HSEState; /*!< The new state of the HSE.
294 This parameter can be a value of @ref RCC_HSE_Config */
295
296 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
297 uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
298 This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
299
300 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
301 uint32_t LSEState; /*!< The new state of the LSE.
302 This parameter can be a value of @ref RCC_LSE_Config */
303
304 uint32_t HSIState; /*!< The new state of the HSI.
305 This parameter can be a value of @ref RCC_HSI_Config */
306
307 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
308 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
309
310 uint32_t LSIState; /*!< The new state of the LSI.
311 This parameter can be a value of @ref RCC_LSI_Config */
312
313 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
314
315 } RCC_OscInitTypeDef;
316
317 /**
318 * @brief RCC System, AHB and APB busses clock configuration structure definition
319 */
320 typedef struct
321 {
322 uint32_t ClockType; /*!< The clock to be configured.
323 This parameter can be a value of @ref RCC_System_Clock_Type */
324
325 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
326 This parameter can be a value of @ref RCC_System_Clock_Source */
327
328 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
329 This parameter can be a value of @ref RCC_AHB_Clock_Source */
330
331 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
332 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
333
334 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
335 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
336 } RCC_ClkInitTypeDef;
337
338 /**
339 * @}
340 */
341
342 /* Exported constants --------------------------------------------------------*/
343 /** @defgroup RCC_Exported_Constants RCC Exported Constants
344 * @{
345 */
346
347 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
348 * @{
349 */
350
351 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
352 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
353 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
354 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
355 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
356 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
357 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
358
359 /**
360 * @}
361 */
362
363 /** @defgroup RCC_Oscillator_Type Oscillator Type
364 * @{
365 */
366 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
367 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
368 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
369 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
370 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
371 /**
372 * @}
373 */
374
375 /** @defgroup RCC_HSE_Config HSE Config
376 * @{
377 */
378 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
379 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
380 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
381 /**
382 * @}
383 */
384
385 /** @defgroup RCC_LSE_Config LSE Config
386 * @{
387 */
388 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
389 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
390 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
391
392 /**
393 * @}
394 */
395
396 /** @defgroup RCC_HSI_Config HSI Config
397 * @{
398 */
399 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
400 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
401
402 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
403
404 /**
405 * @}
406 */
407
408 /** @defgroup RCC_LSI_Config LSI Config
409 * @{
410 */
411 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
412 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
413
414 /**
415 * @}
416 */
417
418 /** @defgroup RCC_PLL_Config PLL Config
419 * @{
420 */
421 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
422 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
423 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
424
425 /**
426 * @}
427 */
428
429 /** @defgroup RCC_System_Clock_Type System Clock Type
430 * @{
431 */
432 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
433 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
434 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
435 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
436
437 /**
438 * @}
439 */
440
441 /** @defgroup RCC_System_Clock_Source System Clock Source
442 * @{
443 */
444 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
445 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
446 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
447
448 /**
449 * @}
450 */
451
452 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
453 * @{
454 */
455 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
456 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
457 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
458
459 /**
460 * @}
461 */
462
463 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
464 * @{
465 */
466 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
467 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
468 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
469 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
470 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
471 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
472 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
473 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
474 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
475
476 /**
477 * @}
478 */
479
480 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
481 * @{
482 */
483 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
484 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
485 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
486 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
487 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
488
489 /**
490 * @}
491 */
492
493 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
494 * @{
495 */
496 #define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */
497 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
498 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
499 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
500 /**
501 * @}
502 */
503
504 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
505 * @{
506 */
507 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
508 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
509 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
510 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
511 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
512 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
513 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
514 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
515 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
516 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
517 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
518 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
519 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
520 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
521 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
522
523 /**
524 * @}
525 */
526
527 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
528 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
529 * @{
530 */
531
532 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
533 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
534 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
535 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
536 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
537 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
538 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
539 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
540 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
541 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
542 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
543 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
544 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
545 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
546 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
547 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
548
549 /**
550 * @}
551 */
552
553 #endif
554 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
555 /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
556 * @{
557 */
558
559 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
560 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
561 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
562 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
563 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
564 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
565 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
566 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
567 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
568 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
569 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
570 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
571 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
572 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
573 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
574 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
575
576 /**
577 * @}
578 */
579 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
580
581 #if defined(RCC_CFGR3_USART2SW)
582 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
583 * @{
584 */
585 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
586 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
587 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
588 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
589
590 /**
591 * @}
592 */
593 #endif /* RCC_CFGR3_USART2SW */
594
595 #if defined(RCC_CFGR3_USART3SW)
596 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
597 * @{
598 */
599 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
600 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
601 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
602 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
603
604 /**
605 * @}
606 */
607 #endif /* RCC_CFGR3_USART3SW */
608
609 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
610 * @{
611 */
612 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
613 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
614
615 /**
616 * @}
617 */
618 /** @defgroup RCC_MCO_Index MCO Index
619 * @{
620 */
621 #define RCC_MCO1 (0x00000000U)
622 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
623
624 /**
625 * @}
626 */
627
628 /** @defgroup RCC_Interrupt Interrupts
629 * @{
630 */
631 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
632 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
633 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
634 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
635 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
636 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
637 /**
638 * @}
639 */
640
641 /** @defgroup RCC_Flag Flags
642 * Elements values convention: XXXYYYYYb
643 * - YYYYY : Flag position in the register
644 * - XXX : Register index
645 * - 001: CR register
646 * - 010: BDCR register
647 * - 011: CSR register
648 * - 100: CFGR register
649 * @{
650 */
651 /* Flags in the CR register */
652 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
653 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
654 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
655
656 /* Flags in the CSR register */
657 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
658 #if defined(RCC_CSR_V18PWRRSTF)
659 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
660 #endif
661 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
662 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
663 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
664 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
665 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
666 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
667 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
668
669 /* Flags in the BDCR register */
670 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
671
672 /* Flags in the CFGR register */
673 #if defined(RCC_CFGR_MCOF)
674 #define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
675 #endif /* RCC_CFGR_MCOF */
676
677 /**
678 * @}
679 */
680
681 /**
682 * @}
683 */
684
685 /* Exported macro ------------------------------------------------------------*/
686
687 /** @defgroup RCC_Exported_Macros RCC Exported Macros
688 * @{
689 */
690
691 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
692 * @brief Enable or disable the AHB peripheral clock.
693 * @note After reset, the peripheral clock (used for registers read/write access)
694 * is disabled and the application software has to enable this clock before
695 * using it.
696 * @{
697 */
698 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
699 __IO uint32_t tmpreg; \
700 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
701 /* Delay after an RCC peripheral clock enabling */ \
702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
703 UNUSED(tmpreg); \
704 } while(0U)
705 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
706 __IO uint32_t tmpreg; \
707 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
708 /* Delay after an RCC peripheral clock enabling */ \
709 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
710 UNUSED(tmpreg); \
711 } while(0U)
712 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
713 __IO uint32_t tmpreg; \
714 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
715 /* Delay after an RCC peripheral clock enabling */ \
716 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
717 UNUSED(tmpreg); \
718 } while(0U)
719 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
720 __IO uint32_t tmpreg; \
721 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
722 /* Delay after an RCC peripheral clock enabling */ \
723 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
724 UNUSED(tmpreg); \
725 } while(0U)
726 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
727 __IO uint32_t tmpreg; \
728 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
729 /* Delay after an RCC peripheral clock enabling */ \
730 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
731 UNUSED(tmpreg); \
732 } while(0U)
733 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
734 __IO uint32_t tmpreg; \
735 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
736 /* Delay after an RCC peripheral clock enabling */ \
737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
738 UNUSED(tmpreg); \
739 } while(0U)
740 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
741 __IO uint32_t tmpreg; \
742 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
743 /* Delay after an RCC peripheral clock enabling */ \
744 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
745 UNUSED(tmpreg); \
746 } while(0U)
747 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
748 __IO uint32_t tmpreg; \
749 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
750 /* Delay after an RCC peripheral clock enabling */ \
751 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
752 UNUSED(tmpreg); \
753 } while(0U)
754 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
755 __IO uint32_t tmpreg; \
756 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
757 /* Delay after an RCC peripheral clock enabling */ \
758 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
759 UNUSED(tmpreg); \
760 } while(0U)
761 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
762 __IO uint32_t tmpreg; \
763 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
764 /* Delay after an RCC peripheral clock enabling */ \
765 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
766 UNUSED(tmpreg); \
767 } while(0U)
768
769 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
770 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
771 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
772 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
773 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
774 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
775 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
776 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
777 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
778 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
779 /**
780 * @}
781 */
782
783 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
784 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
785 * @note After reset, the peripheral clock (used for registers read/write access)
786 * is disabled and the application software has to enable this clock before
787 * using it.
788 * @{
789 */
790 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
791 __IO uint32_t tmpreg; \
792 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
793 /* Delay after an RCC peripheral clock enabling */ \
794 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
795 UNUSED(tmpreg); \
796 } while(0U)
797 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
798 __IO uint32_t tmpreg; \
799 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
800 /* Delay after an RCC peripheral clock enabling */ \
801 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
802 UNUSED(tmpreg); \
803 } while(0U)
804 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
805 __IO uint32_t tmpreg; \
806 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
807 /* Delay after an RCC peripheral clock enabling */ \
808 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
809 UNUSED(tmpreg); \
810 } while(0U)
811 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
812 __IO uint32_t tmpreg; \
813 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
814 /* Delay after an RCC peripheral clock enabling */ \
815 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
816 UNUSED(tmpreg); \
817 } while(0U)
818 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
819 __IO uint32_t tmpreg; \
820 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
821 /* Delay after an RCC peripheral clock enabling */ \
822 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
823 UNUSED(tmpreg); \
824 } while(0U)
825 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
826 __IO uint32_t tmpreg; \
827 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
828 /* Delay after an RCC peripheral clock enabling */ \
829 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
830 UNUSED(tmpreg); \
831 } while(0U)
832 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
833 __IO uint32_t tmpreg; \
834 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
835 /* Delay after an RCC peripheral clock enabling */ \
836 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
837 UNUSED(tmpreg); \
838 } while(0U)
839 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
840 __IO uint32_t tmpreg; \
841 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
842 /* Delay after an RCC peripheral clock enabling */ \
843 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
844 UNUSED(tmpreg); \
845 } while(0U)
846
847 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
848 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
849 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
850 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
851 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
852 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
853 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
854 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
855 /**
856 * @}
857 */
858
859 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
860 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
861 * @note After reset, the peripheral clock (used for registers read/write access)
862 * is disabled and the application software has to enable this clock before
863 * using it.
864 * @{
865 */
866 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
867 __IO uint32_t tmpreg; \
868 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
869 /* Delay after an RCC peripheral clock enabling */ \
870 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
871 UNUSED(tmpreg); \
872 } while(0U)
873 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
874 __IO uint32_t tmpreg; \
875 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
876 /* Delay after an RCC peripheral clock enabling */ \
877 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
878 UNUSED(tmpreg); \
879 } while(0U)
880 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
881 __IO uint32_t tmpreg; \
882 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
883 /* Delay after an RCC peripheral clock enabling */ \
884 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
885 UNUSED(tmpreg); \
886 } while(0U)
887 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
888 __IO uint32_t tmpreg; \
889 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
890 /* Delay after an RCC peripheral clock enabling */ \
891 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
892 UNUSED(tmpreg); \
893 } while(0U)
894 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
895 __IO uint32_t tmpreg; \
896 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
897 /* Delay after an RCC peripheral clock enabling */ \
898 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
899 UNUSED(tmpreg); \
900 } while(0U)
901
902 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
903 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
904 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
905 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
906 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
907 /**
908 * @}
909 */
910
911 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
912 * @brief Get the enable or disable status of the AHB peripheral clock.
913 * @note After reset, the peripheral clock (used for registers read/write access)
914 * is disabled and the application software has to enable this clock before
915 * using it.
916 * @{
917 */
918 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
919 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
920 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
921 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
922 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
923 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
924 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
925 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
926 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
927 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
928
929 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
930 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
931 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
932 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
933 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
934 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
935 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
936 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
937 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
938 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
939 /**
940 * @}
941 */
942
943 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
944 * @brief Get the enable or disable status of the APB1 peripheral clock.
945 * @note After reset, the peripheral clock (used for registers read/write access)
946 * is disabled and the application software has to enable this clock before
947 * using it.
948 * @{
949 */
950 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
951 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
952 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
953 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
954 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
955 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
956 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
957 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
958
959 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
960 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
961 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
962 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
963 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
964 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
965 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
966 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
967 /**
968 * @}
969 */
970
971 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
972 * @brief EGet the enable or disable status of the APB2 peripheral clock.
973 * @note After reset, the peripheral clock (used for registers read/write access)
974 * is disabled and the application software has to enable this clock before
975 * using it.
976 * @{
977 */
978 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
979 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
980 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
981 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
982 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
983
984 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
985 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
986 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
987 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
988 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
989 /**
990 * @}
991 */
992
993 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
994 * @brief Force or release AHB peripheral reset.
995 * @{
996 */
997 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
998 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
999 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
1000 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
1001 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
1002 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
1003 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
1004
1005 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
1006 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
1007 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
1008 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
1009 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
1010 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
1011 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
1017 * @brief Force or release APB1 peripheral reset.
1018 * @{
1019 */
1020 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
1021 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1022 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1023 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
1024 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1025 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1026 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
1027 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
1028 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
1029
1030 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
1031 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1032 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1033 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
1034 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1035 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1036 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
1037 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
1038 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
1044 * @brief Force or release APB2 peripheral reset.
1045 * @{
1046 */
1047 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
1048 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
1049 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1050 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
1051 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
1052 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
1053
1054 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
1055 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
1056 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1057 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
1058 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
1059 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup RCC_HSI_Configuration HSI Configuration
1065 * @{
1066 */
1067
1068 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
1069 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
1070 * It is used (enabled by hardware) as system clock source after startup
1071 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
1072 * of the HSE used directly or indirectly as system clock (if the Clock
1073 * Security System CSS is enabled).
1074 * @note HSI can not be stopped if it is used as system clock source. In this case,
1075 * you have to select another source of the system clock then stop the HSI.
1076 * @note After enabling the HSI, the application software should wait on HSIRDY
1077 * flag to be set indicating that HSI clock is stable and can be used as
1078 * system clock source.
1079 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
1080 * clock cycles.
1081 */
1082 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
1083 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
1084
1085 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
1086 * @note The calibration is used to compensate for the variations in voltage
1087 * and temperature that influence the frequency of the internal HSI RC.
1088 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
1089 * (default is RCC_HSICALIBRATION_DEFAULT).
1090 * This parameter must be a number between 0 and 0x1F.
1091 */
1092 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
1093 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
1094
1095 /**
1096 * @}
1097 */
1098
1099 /** @defgroup RCC_LSI_Configuration LSI Configuration
1100 * @{
1101 */
1102
1103 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
1104 * @note After enabling the LSI, the application software should wait on
1105 * LSIRDY flag to be set indicating that LSI clock is stable and can
1106 * be used to clock the IWDG and/or the RTC.
1107 */
1108 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
1109
1110 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
1111 * @note LSI can not be disabled if the IWDG is running.
1112 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
1113 * clock cycles.
1114 */
1115 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
1116
1117 /**
1118 * @}
1119 */
1120
1121 /** @defgroup RCC_HSE_Configuration HSE Configuration
1122 * @{
1123 */
1124
1125 /**
1126 * @brief Macro to configure the External High Speed oscillator (HSE).
1127 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
1128 * supported by this macro. User should request a transition to HSE Off
1129 * first and then HSE On or HSE Bypass.
1130 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
1131 * software should wait on HSERDY flag to be set indicating that HSE clock
1132 * is stable and can be used to clock the PLL and/or system clock.
1133 * @note HSE state can not be changed if it is used directly or through the
1134 * PLL as system clock. In this case, you have to select another source
1135 * of the system clock then change the HSE state (ex. disable it).
1136 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
1137 * @note This function reset the CSSON bit, so if the clock security system(CSS)
1138 * was previously enabled you have to enable it again after calling this
1139 * function.
1140 * @param __STATE__ specifies the new state of the HSE.
1141 * This parameter can be one of the following values:
1142 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
1143 * 6 HSE oscillator clock cycles.
1144 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
1145 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
1146 */
1147 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
1148 do{ \
1149 if ((__STATE__) == RCC_HSE_ON) \
1150 { \
1151 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1152 } \
1153 else if ((__STATE__) == RCC_HSE_OFF) \
1154 { \
1155 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
1156 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
1157 } \
1158 else if ((__STATE__) == RCC_HSE_BYPASS) \
1159 { \
1160 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
1161 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1162 } \
1163 else \
1164 { \
1165 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
1166 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
1167 } \
1168 }while(0U)
1169
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup RCC_LSE_Configuration LSE Configuration
1175 * @{
1176 */
1177
1178 /**
1179 * @brief Macro to configure the External Low Speed oscillator (LSE).
1180 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
1181 * @note As the LSE is in the Backup domain and write access is denied to
1182 * this domain after reset, you have to enable write access using
1183 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
1184 * (to be done once after reset).
1185 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
1186 * software should wait on LSERDY flag to be set indicating that LSE clock
1187 * is stable and can be used to clock the RTC.
1188 * @param __STATE__ specifies the new state of the LSE.
1189 * This parameter can be one of the following values:
1190 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
1191 * 6 LSE oscillator clock cycles.
1192 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
1193 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
1194 */
1195 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
1196 do{ \
1197 if ((__STATE__) == RCC_LSE_ON) \
1198 { \
1199 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1200 } \
1201 else if ((__STATE__) == RCC_LSE_OFF) \
1202 { \
1203 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1204 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1205 } \
1206 else if ((__STATE__) == RCC_LSE_BYPASS) \
1207 { \
1208 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1209 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1210 } \
1211 else \
1212 { \
1213 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1214 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1215 } \
1216 }while(0U)
1217
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
1223 * @{
1224 */
1225
1226 /** @brief Macro to configure the USART1 clock (USART1CLK).
1227 * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
1228 * This parameter can be one of the following values:
1229 @if STM32F302xC
1230 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1231 @endif
1232 @if STM32F303xC
1233 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1234 @endif
1235 @if STM32F358xx
1236 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1237 @endif
1238 @if STM32F302xE
1239 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1240 @endif
1241 @if STM32F303xE
1242 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1243 @endif
1244 @if STM32F398xx
1245 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1246 @endif
1247 @if STM32F373xC
1248 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1249 @endif
1250 @if STM32F378xx
1251 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1252 @endif
1253 @if STM32F301x8
1254 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1255 @endif
1256 @if STM32F302x8
1257 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1258 @endif
1259 @if STM32F318xx
1260 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1261 @endif
1262 @if STM32F303x8
1263 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1264 @endif
1265 @if STM32F334x8
1266 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1267 @endif
1268 @if STM32F328xx
1269 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1270 @endif
1271 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
1272 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
1273 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
1274 */
1275 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
1276 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
1277
1278 /** @brief Macro to get the USART1 clock source.
1279 * @retval The clock source can be one of the following values:
1280 @if STM32F302xC
1281 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1282 @endif
1283 @if STM32F303xC
1284 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1285 @endif
1286 @if STM32F358xx
1287 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1288 @endif
1289 @if STM32F302xE
1290 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1291 @endif
1292 @if STM32F303xE
1293 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1294 @endif
1295 @if STM32F398xx
1296 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1297 @endif
1298 @if STM32F373xC
1299 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1300 @endif
1301 @if STM32F378xx
1302 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
1303 @endif
1304 @if STM32F301x8
1305 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1306 @endif
1307 @if STM32F302x8
1308 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1309 @endif
1310 @if STM32F318xx
1311 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1312 @endif
1313 @if STM32F303x8
1314 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1315 @endif
1316 @if STM32F334x8
1317 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1318 @endif
1319 @if STM32F328xx
1320 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1321 @endif
1322 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
1323 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
1324 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
1325 */
1326 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
1327
1328 #if defined(RCC_CFGR3_USART2SW)
1329 /** @brief Macro to configure the USART2 clock (USART2CLK).
1330 * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
1331 * This parameter can be one of the following values:
1332 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
1333 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
1334 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
1335 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
1336 */
1337 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
1338 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
1339
1340 /** @brief Macro to get the USART2 clock source.
1341 * @retval The clock source can be one of the following values:
1342 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
1343 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
1344 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
1345 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
1346 */
1347 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
1348 #endif /* RCC_CFGR3_USART2SW */
1349
1350 #if defined(RCC_CFGR3_USART3SW)
1351 /** @brief Macro to configure the USART3 clock (USART3CLK).
1352 * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
1353 * This parameter can be one of the following values:
1354 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
1355 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
1356 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
1357 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
1358 */
1359 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
1360 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
1361
1362 /** @brief Macro to get the USART3 clock source.
1363 * @retval The clock source can be one of the following values:
1364 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
1365 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
1366 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
1367 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
1368 */
1369 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
1370 #endif /* RCC_CFGR3_USART2SW */
1371 /**
1372 * @}
1373 */
1374
1375 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
1376 * @{
1377 */
1378
1379 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
1380 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
1381 * This parameter can be one of the following values:
1382 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
1383 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
1384 */
1385 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
1386 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
1387
1388 /** @brief Macro to get the I2C1 clock source.
1389 * @retval The clock source can be one of the following values:
1390 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
1391 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
1392 */
1393 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
1394 /**
1395 * @}
1396 */
1397
1398 /** @defgroup RCC_PLL_Configuration PLL Configuration
1399 * @{
1400 */
1401
1402 /** @brief Macro to enable the main PLL.
1403 * @note After enabling the main PLL, the application software should wait on
1404 * PLLRDY flag to be set indicating that PLL clock is stable and can
1405 * be used as system clock source.
1406 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1407 */
1408 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1409
1410 /** @brief Macro to disable the main PLL.
1411 * @note The main PLL can not be disabled if it is used as system clock source
1412 */
1413 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1414
1415
1416 /** @brief Get oscillator clock selected as PLL input clock
1417 * @retval The clock source used for PLL entry. The returned value can be one
1418 * of the following:
1419 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
1420 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
1421 */
1422 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1423
1424 /**
1425 * @}
1426 */
1427
1428 /** @defgroup RCC_Get_Clock_source Get Clock source
1429 * @{
1430 */
1431
1432 /**
1433 * @brief Macro to configure the system clock source.
1434 * @param __SYSCLKSOURCE__ specifies the system clock source.
1435 * This parameter can be one of the following values:
1436 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
1437 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
1438 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
1439 */
1440 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
1441 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
1442
1443 /** @brief Macro to get the clock source used as system clock.
1444 * @retval The clock source used as system clock. The returned value can be one
1445 * of the following:
1446 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
1447 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
1448 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
1449 */
1450 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1451
1452 /**
1453 * @}
1454 */
1455
1456 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1457 * @{
1458 */
1459
1460 #if defined(RCC_CFGR_MCOPRE)
1461 /** @brief Macro to configure the MCO clock.
1462 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1463 * This parameter can be one of the following values:
1464 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
1465 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
1466 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
1467 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
1468 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
1469 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
1470 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
1471 * @param __MCODIV__ specifies the MCO clock prescaler.
1472 * This parameter can be one of the following values:
1473 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
1474 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
1475 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
1476 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
1477 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
1478 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
1479 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
1480 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
1481 */
1482 #else
1483 /** @brief Macro to configure the MCO clock.
1484 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1485 * This parameter can be one of the following values:
1486 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
1487 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
1488 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
1489 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
1490 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
1491 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
1492 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
1493 * @param __MCODIV__ specifies the MCO clock prescaler.
1494 * This parameter can be one of the following values:
1495 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
1496 */
1497 #endif
1498 #if defined(RCC_CFGR_MCOPRE)
1499 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1500 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1501 #else
1502
1503 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1504 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
1505
1506 #endif
1507
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
1513 * @{
1514 */
1515
1516 /** @brief Macro to configure the RTC clock (RTCCLK).
1517 * @note As the RTC clock configuration bits are in the Backup domain and write
1518 * access is denied to this domain after reset, you have to enable write
1519 * access using the Power Backup Access macro before to configure
1520 * the RTC clock source (to be done once after reset).
1521 * @note Once the RTC clock is configured it cannot be changed unless the
1522 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
1523 * a Power On Reset (POR).
1524 *
1525 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
1526 * This parameter can be one of the following values:
1527 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1528 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1529 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1530 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
1531 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
1532 * work in STOP and STANDBY modes, and can be used as wakeup source.
1533 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
1534 * the RTC cannot be used in STOP and STANDBY modes.
1535 * @note The system must always be configured so as to get a PCLK frequency greater than or
1536 * equal to the RTCCLK frequency for a proper operation of the RTC.
1537 */
1538 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
1539
1540 /** @brief Macro to get the RTC clock source.
1541 * @retval The clock source can be one of the following values:
1542 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1543 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1544 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1545 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
1546 */
1547 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1548
1549 /** @brief Macro to enable the the RTC clock.
1550 * @note These macros must be used only after the RTC clock source was selected.
1551 */
1552 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1553
1554 /** @brief Macro to disable the the RTC clock.
1555 * @note These macros must be used only after the RTC clock source was selected.
1556 */
1557 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1558
1559 /** @brief Macro to force the Backup domain reset.
1560 * @note This function resets the RTC peripheral (including the backup registers)
1561 * and the RTC clock source selection in RCC_BDCR register.
1562 */
1563 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1564
1565 /** @brief Macros to release the Backup domain reset.
1566 */
1567 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1568
1569 /**
1570 * @}
1571 */
1572
1573 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1574 * @brief macros to manage the specified RCC Flags and interrupts.
1575 * @{
1576 */
1577
1578 /** @brief Enable RCC interrupt.
1579 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1580 * This parameter can be any combination of the following values:
1581 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1582 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
1583 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1584 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
1585 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1586 */
1587 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1588
1589 /** @brief Disable RCC interrupt.
1590 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1591 * This parameter can be any combination of the following values:
1592 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1593 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
1594 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1595 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
1596 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1597 */
1598 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1599
1600 /** @brief Clear the RCC's interrupt pending bits.
1601 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1602 * This parameter can be any combination of the following values:
1603 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1604 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1605 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1606 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1607 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1608 * @arg @ref RCC_IT_CSS Clock Security System interrupt
1609 */
1610 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1611
1612 /** @brief Check the RCC's interrupt has occurred or not.
1613 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
1614 * This parameter can be one of the following values:
1615 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1616 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1617 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1618 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1619 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1620 * @arg @ref RCC_IT_CSS Clock Security System interrupt
1621 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1622 */
1623 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1624
1625 /** @brief Set RMVF bit to clear the reset flags.
1626 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1627 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1628 */
1629 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
1630
1631 /** @brief Check RCC flag is set or not.
1632 * @param __FLAG__ specifies the flag to check.
1633 * This parameter can be one of the following values:
1634 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
1635 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
1636 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
1637 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
1638 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
1639 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
1640 * @arg @ref RCC_FLAG_PINRST Pin reset.
1641 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
1642 * @arg @ref RCC_FLAG_SFTRST Software reset.
1643 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
1644 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
1645 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
1646 @if defined(STM32F301x8)
1647 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1648 @endif
1649 @if defined(STM32F302x8)
1650 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1651 @endif
1652 @if defined(STM32F302xC)
1653 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1654 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
1655 @endif
1656 @if defined(STM32F302xE)
1657 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1658 @endif
1659 @if defined(STM32F303x8)
1660 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1661 @endif
1662 @if defined(STM32F303xC)
1663 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1664 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
1665 @endif
1666 @if defined(STM32F303xE)
1667 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1668 @endif
1669 @if defined(STM32F334x8)
1670 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1671 @endif
1672 @if defined(STM32F358xx)
1673 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
1674 @endif
1675 @if defined(STM32F373xC)
1676 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1677 @endif
1678 * @retval The new state of __FLAG__ (TRUE or FALSE).
1679 */
1680 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
1681 (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
1682 (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
1683 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1684
1685 /**
1686 * @}
1687 */
1688
1689 /**
1690 * @}
1691 */
1692
1693 /* Include RCC HAL Extension module */
1694 #include "stm32f3xx_hal_rcc_ex.h"
1695
1696 /* Exported functions --------------------------------------------------------*/
1697 /** @addtogroup RCC_Exported_Functions
1698 * @{
1699 */
1700
1701 /** @addtogroup RCC_Exported_Functions_Group1
1702 * @{
1703 */
1704
1705 /* Initialization and de-initialization functions ******************************/
1706 void HAL_RCC_DeInit(void);
1707 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1708 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1709
1710 /**
1711 * @}
1712 */
1713
1714 /** @addtogroup RCC_Exported_Functions_Group2
1715 * @{
1716 */
1717
1718 /* Peripheral Control functions ************************************************/
1719 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1720 void HAL_RCC_EnableCSS(void);
1721 /* CSS NMI IRQ handler */
1722 void HAL_RCC_NMI_IRQHandler(void);
1723 /* User Callbacks in non blocking mode (IT mode) */
1724 void HAL_RCC_CSSCallback(void);
1725 void HAL_RCC_DisableCSS(void);
1726 uint32_t HAL_RCC_GetSysClockFreq(void);
1727 uint32_t HAL_RCC_GetHCLKFreq(void);
1728 uint32_t HAL_RCC_GetPCLK1Freq(void);
1729 uint32_t HAL_RCC_GetPCLK2Freq(void);
1730 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1731 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1732
1733 /**
1734 * @}
1735 */
1736
1737 /**
1738 * @}
1739 */
1740
1741 /**
1742 * @}
1743 */
1744
1745 /**
1746 * @}
1747 */
1748
1749 #ifdef __cplusplus
1750 }
1751 #endif
1752
1753 #endif /* __STM32F3xx_HAL_RCC_H */
1754
1755 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1756