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Updated and Validated
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal_tim.h
blob6cb103b1257ad085efa8734ce8edf7a11edd68a3
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_HAL_TIM_H
38 #define __STM32F3xx_HAL_TIM_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx_hal_def.h"
46
47 /** @addtogroup STM32F3xx_HAL_Driver
48 * @{
49 */
50
51 /** @addtogroup TIM
52 * @{
53 */
54
55 /* Exported types ------------------------------------------------------------*/
56 /** @defgroup TIM_Exported_Types TIM Exported Types
57 * @{
58 */
59 /**
60 * @brief TIM Time base Configuration Structure definition
61 */
62 typedef struct
63 {
64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
66
67 uint32_t CounterMode; /*!< Specifies the counter mode.
68 This parameter can be a value of @ref TIM_Counter_Mode */
69
70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
71 Auto-Reload Register at the next update event.
72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
73
74 uint32_t ClockDivision; /*!< Specifies the clock division.
75 This parameter can be a value of @ref TIM_ClockDivision */
76
77 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
78 reaches zero, an update event is generated and counting restarts
79 from the RCR value (N).
80 This means in PWM mode that (N+1U) corresponds to:
81 - the number of PWM periods in edge-aligned mode
82 - the number of half PWM period in center-aligned mode
83 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
84 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
85
86 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
87 This parameter can be a value of @ref TIM_AutoReloadPreload */
88 } TIM_Base_InitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Configuration Structure definition
92 */
93 typedef struct
94 {
95 uint32_t OCMode; /*!< Specifies the TIM mode.
96 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
97
98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
100
101 uint32_t OCPolarity; /*!< Specifies the output polarity.
102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
103
104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
106 @note This parameter is valid only for TIM1 and TIM8. */
107
108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
109 This parameter can be a value of @ref TIM_Output_Fast_State
110 @note This parameter is valid only in PWM1 and PWM2 mode. */
111
112
113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
115 @note This parameter is valid only for TIM1 and TIM8. */
116
117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
119 @note This parameter is valid only for TIM1 and TIM8. */
120 } TIM_OC_InitTypeDef;
121
122 /**
123 * @brief TIM One Pulse Mode Configuration Structure definition
124 */
125 typedef struct
126 {
127 uint32_t OCMode; /*!< Specifies the TIM mode.
128 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
129
130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
132
133 uint32_t OCPolarity; /*!< Specifies the output polarity.
134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
135
136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
138 @note This parameter is valid only for TIM1 and TIM8. */
139
140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
142 @note This parameter is valid only for TIM1 and TIM8. */
143
144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
146 @note This parameter is valid only for TIM1 and TIM8. */
147
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICFilter; /*!< Specifies the input capture filter.
155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
156 } TIM_OnePulse_InitTypeDef;
157
158
159 /**
160 * @brief TIM Input Capture Configuration Structure definition
161 */
162 typedef struct
163 {
164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166
167 uint32_t ICSelection; /*!< Specifies the input.
168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169
170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172
173 uint32_t ICFilter; /*!< Specifies the input capture filter.
174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
175 } TIM_IC_InitTypeDef;
176
177 /**
178 * @brief TIM Encoder Configuration Structure definition
179 */
180 typedef struct
181 {
182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Mode */
184
185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187
188 uint32_t IC1Selection; /*!< Specifies the input.
189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190
191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193
194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
196
197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199
200 uint32_t IC2Selection; /*!< Specifies the input.
201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202
203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205
206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
208 } TIM_Encoder_InitTypeDef;
209
210
211 /**
212 * @brief TIM Clock Configuration Handle Structure definition
213 */
214 typedef struct
215 {
216 uint32_t ClockSource; /*!< TIM clock sources
217 This parameter can be a value of @ref TIM_Clock_Source */
218 uint32_t ClockPolarity; /*!< TIM clock polarity
219 This parameter can be a value of @ref TIM_Clock_Polarity */
220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
221 This parameter can be a value of @ref TIM_Clock_Prescaler */
222 uint32_t ClockFilter; /*!< TIM clock filter
223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
224 }TIM_ClockConfigTypeDef;
225
226 /**
227 * @brief TIM Clear Input Configuration Handle Structure definition
228 */
229 typedef struct
230 {
231 uint32_t ClearInputState; /*!< TIM clear Input state
232 This parameter can be ENABLE or DISABLE */
233 uint32_t ClearInputSource; /*!< TIM clear Input sources
234 This parameter can be a value of @ref TIMEx_ClearInput_Source */
235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
241 }TIM_ClearInputConfigTypeDef;
242
243 /**
244 * @brief TIM Slave configuration Structure definition
245 */
246 typedef struct {
247 uint32_t SlaveMode; /*!< Slave mode selection
248 This parameter can be a value of @ref TIMEx_Slave_Mode */
249 uint32_t InputTrigger; /*!< Input Trigger source
250 This parameter can be a value of @ref TIM_Trigger_Selection */
251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
252 This parameter can be a value of @ref TIM_Trigger_Polarity */
253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
255 uint32_t TriggerFilter; /*!< Input trigger filter
256 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
257
258 }TIM_SlaveConfigTypeDef;
259
260 /**
261 * @brief HAL State structures definition
262 */
263 typedef enum
264 {
265 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
266 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
267 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
268 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
269 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
270 }HAL_TIM_StateTypeDef;
271
272 /**
273 * @brief HAL Active channel structures definition
274 */
275 typedef enum
276 {
277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
282 }HAL_TIM_ActiveChannel;
283
284 /**
285 * @brief TIM Time Base Handle Structure definition
286 */
287 typedef struct
288 {
289 TIM_TypeDef *Instance; /*!< Register base address */
290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
293 This array is accessed by a @ref TIM_DMA_Handle_index */
294 HAL_LockTypeDef Lock; /*!< Locking object */
295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
296 }TIM_HandleTypeDef;
297
298 /**
299 * @}
300 */
301 /* End of exported types -----------------------------------------------------*/
302
303 /* Exported constants --------------------------------------------------------*/
304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
305 * @{
306 */
307
308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
309 * @{
310 */
311 #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
314 /**
315 * @}
316 */
317
318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
319 * @{
320 */
321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
322 #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
323 /**
324 * @}
325 */
326
327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
328 * @{
329 */
330 #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */
332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */
333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */
334 /**
335 * @}
336 */
337
338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
339 * @{
340 */
341 #define TIM_COUNTERMODE_UP (0x0000U)
342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
346 /**
347 * @}
348 */
349
350 /** @defgroup TIM_ClockDivision TIM Clock Division
351 * @{
352 */
353 #define TIM_CLOCKDIVISION_DIV1 (0x0000U)
354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
356 /**
357 * @}
358 */
359
360 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
361 * @{
362 */
363 #define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
364 #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
365
366 /**
367 * @}
368 */
369
370 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
371 * @{
372 */
373 #define TIM_OCFAST_DISABLE (0x0000U)
374 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
375 /**
376 * @}
377 */
378
379 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
380 * @{
381 */
382 #define TIM_OCPOLARITY_HIGH (0x0000U)
383 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
384 /**
385 * @}
386 */
387
388 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
389 * @{
390 */
391 #define TIM_OCNPOLARITY_HIGH (0x0000U)
392 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
393 /**
394 * @}
395 */
396
397 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
398 * @{
399 */
400 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
401 #define TIM_OCIDLESTATE_RESET (0x0000U)
402 /**
403 * @}
404 */
405
406 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
407 * @{
408 */
409 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
410 #define TIM_OCNIDLESTATE_RESET (0x0000U)
411 /**
412 * @}
413 */
414
415 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
416 * @{
417 */
418 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
419 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
420 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
421 /**
422 * @}
423 */
424
425 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
426 * @{
427 */
428 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
429 connected to IC1, IC2, IC3 or IC4, respectively */
430 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
431 connected to IC2, IC1, IC4 or IC3, respectively */
432 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */
433 /**
434 * @}
435 */
436
437 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
438 * @{
439 */
440 #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
441 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
442 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
443 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
444 /**
445 * @}
446 */
447
448 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
449 * @{
450 */
451 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
452 #define TIM_OPMODE_REPETITIVE (0x0000U)
453 /**
454 * @}
455 */
456
457 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
458 * @{
459 */
460 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
461 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
462 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
463 /**
464 * @}
465 */
466
467 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
468 * @{
469 */
470 #define TIM_IT_UPDATE (TIM_DIER_UIE)
471 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
472 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
473 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
474 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
475 #define TIM_IT_COM (TIM_DIER_COMIE)
476 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
477 #define TIM_IT_BREAK (TIM_DIER_BIE)
478 /**
479 * @}
480 */
481
482 /** @defgroup TIM_Commutation_Source TIM Commutation Source
483 * @{
484 */
485 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
486 #define TIM_COMMUTATION_SOFTWARE (0x0000U)
487
488 /**
489 * @}
490 */
491
492 /** @defgroup TIM_DMA_sources TIM DMA Sources
493 * @{
494 */
495 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
496 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
497 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
498 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
499 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
500 #define TIM_DMA_COM (TIM_DIER_COMDE)
501 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
502 /**
503 * @}
504 */
505
506 /** @defgroup TIM_Flag_definition TIM Flag Definition
507 * @{
508 */
509 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
510 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
511 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
512 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
513 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
514 #define TIM_FLAG_COM (TIM_SR_COMIF)
515 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
516 #define TIM_FLAG_BREAK (TIM_SR_BIF)
517 #if defined(TIM_SR_B2IF)
518 #define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
519 #endif
520 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
521 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
522 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
523 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
524 /**
525 * @}
526 */
527
528 /** @defgroup TIM_Clock_Source TIM Clock Source
529 * @{
530 */
531 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
532 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
533 #define TIM_CLOCKSOURCE_ITR0 (0x0000U)
534 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
535 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
536 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
537 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
538 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
539 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
540 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
541 /**
542 * @}
543 */
544
545 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
546 * @{
547 */
548 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
549 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
550 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
551 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
552 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
553 /**
554 * @}
555 */
556
557 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
558 * @{
559 */
560 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
561 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
562 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
563 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
564 /**
565 * @}
566 */
567
568 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
569 * @{
570 */
571 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
572 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
573 /**
574 * @}
575 */
576
577 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
578 * @{
579 */
580 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
581 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
582 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
583 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
584 /**
585 * @}
586 */
587
588 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
589 * @{
590 */
591 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
592 #define TIM_OSSR_DISABLE (0x0000U)
593 /**
594 * @}
595 */
596
597 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
598 * @{
599 */
600 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
601 #define TIM_OSSI_DISABLE (0x0000U)
602 /**
603 * @}
604 */
605
606 /** @defgroup TIM_Lock_level TIM Lock level
607 * @{
608 */
609 #define TIM_LOCKLEVEL_OFF (0x0000U)
610 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
611 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
612 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
613 /**
614 * @}
615 */
616
617 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
618 * @{
619 */
620 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
621 #define TIM_BREAK_DISABLE (0x0000U)
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
627 * @{
628 */
629 #define TIM_BREAKPOLARITY_LOW (0x0000U)
630 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
631 /**
632 * @}
633 */
634 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
635 * @{
636 */
637 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
638 #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
644 * @{
645 */
646 #define TIM_TRGO_RESET (0x0000U)
647 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
648 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
649 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
650 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
651 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
652 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
653 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
654 /**
655 * @}
656 */
657
658 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
659 * @{
660 */
661 #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
662 #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
668 * @{
669 */
670 #define TIM_TS_ITR0 (0x0000U)
671 #define TIM_TS_ITR1 (0x0010U)
672 #define TIM_TS_ITR2 (0x0020U)
673 #define TIM_TS_ITR3 (0x0030U)
674 #define TIM_TS_TI1F_ED (0x0040U)
675 #define TIM_TS_TI1FP1 (0x0050U)
676 #define TIM_TS_TI2FP2 (0x0060U)
677 #define TIM_TS_ETRF (0x0070U)
678 #define TIM_TS_NONE (0xFFFFU)
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
684 * @{
685 */
686 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
687 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
688 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
689 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
690 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
696 * @{
697 */
698 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
699 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
700 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
701 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
702 /**
703 * @}
704 */
705
706 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
707 * @{
708 */
709 #define TIM_TI1SELECTION_CH1 (0x0000U)
710 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
716 * @{
717 */
718 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
719 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
720 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
721 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
722 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
723 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
724 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
725 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
726 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
727 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
728 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
729 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
730 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
731 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
732 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
733 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
734 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
735 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
736 /**
737 * @}
738 */
739
740 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
741 * @{
742 */
743 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
744 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
745 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
746 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
747 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
748 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
749 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
750 /**
751 * @}
752 */
753
754 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
755 * @{
756 */
757 #define TIM_CCx_ENABLE (0x0001U)
758 #define TIM_CCx_DISABLE (0x0000U)
759 #define TIM_CCxN_ENABLE (0x0004U)
760 #define TIM_CCxN_DISABLE (0x0000U)
761 /**
762 * @}
763 */
764
765 /**
766 * @}
767 */
768 /* End of exported constants -------------------------------------------------*/
769
770 /* Exported macros -----------------------------------------------------------*/
771 /** @defgroup TIM_Exported_Macros TIM Exported Macros
772 * @{
773 */
774
775 /** @brief Reset TIM handle state
776 * @param __HANDLE__ TIM handle.
777 * @retval None
778 */
779 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
780
781 /**
782 * @brief Enable the TIM peripheral.
783 * @param __HANDLE__ TIM handle
784 * @retval None
785 */
786 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
787
788 /**
789 * @brief Enable the TIM main Output.
790 * @param __HANDLE__ TIM handle
791 * @retval None
792 */
793 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
794
795 /**
796 * @brief Disable the TIM peripheral.
797 * @param __HANDLE__ TIM handle
798 * @retval None
799 */
800 #define __HAL_TIM_DISABLE(__HANDLE__) \
801 do { \
802 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
803 { \
804 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
805 { \
806 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
807 } \
808 } \
809 } while(0U)
810 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
811 channels have been disabled */
812 /**
813 * @brief Disable the TIM main Output.
814 * @param __HANDLE__ TIM handle
815 * @retval None
816 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
817 */
818 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
819 do { \
820 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
821 { \
822 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
823 { \
824 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
825 } \
826 } \
827 } while(0U)
828
829 /* The Main Output Enable of a timer instance is disabled unconditionally */
830 /**
831 * @brief Disable the TIM main Output.
832 * @param __HANDLE__ TIM handle
833 * @retval None
834 * @note The Main Output Enable of a timer instance is disabled uncondiotionally
835 */
836 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
837
838 /**
839 * @brief Enables the specified TIM interrupt.
840 * @param __HANDLE__ specifies the TIM Handle.
841 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
842 * This parameter can be one of the following values:
843 * @arg TIM_IT_UPDATE: Update interrupt
844 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
845 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
846 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
847 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
848 * @arg TIM_IT_COM: Commutation interrupt
849 * @arg TIM_IT_TRIGGER: Trigger interrupt
850 * @arg TIM_IT_BREAK: Break interrupt
851 * @retval None
852 */
853 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
854
855 /**
856 * @brief Disables the specified TIM interrupt.
857 * @param __HANDLE__ specifies the TIM Handle.
858 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
859 * This parameter can be one of the following values:
860 * @arg TIM_IT_UPDATE: Update interrupt
861 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
862 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
863 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
864 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
865 * @arg TIM_IT_COM: Commutation interrupt
866 * @arg TIM_IT_TRIGGER: Trigger interrupt
867 * @arg TIM_IT_BREAK: Break interrupt
868 * @retval None
869 */
870 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
871
872 /**
873 * @brief Enables the specified DMA request.
874 * @param __HANDLE__ specifies the TIM Handle.
875 * @param __DMA__ specifies the TIM DMA request to enable.
876 * This parameter can be one of the following values:
877 * @arg TIM_DMA_UPDATE: Update DMA request
878 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
879 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
880 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
881 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
882 * @arg TIM_DMA_COM: Commutation DMA request
883 * @arg TIM_DMA_TRIGGER: Trigger DMA request
884 * @retval None
885 */
886 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
887
888 /**
889 * @brief Disables the specified DMA request.
890 * @param __HANDLE__ specifies the TIM Handle.
891 * @param __DMA__ specifies the TIM DMA request to disable.
892 * This parameter can be one of the following values:
893 * @arg TIM_DMA_UPDATE: Update DMA request
894 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
895 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
896 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
897 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
898 * @arg TIM_DMA_COM: Commutation DMA request
899 * @arg TIM_DMA_TRIGGER: Trigger DMA request
900 * @retval None
901 */
902 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
903
904 /**
905 * @brief Checks whether the specified TIM interrupt flag is set or not.
906 * @param __HANDLE__ specifies the TIM Handle.
907 * @param __FLAG__ specifies the TIM interrupt flag to check.
908 * This parameter can be one of the following values:
909 * @arg TIM_FLAG_UPDATE: Update interrupt flag
910 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
911 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
912 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
913 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
914 * @arg TIM_FLAG_COM: Commutation interrupt flag
915 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
916 * @arg TIM_FLAG_BREAK: Break interrupt flag
917 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
918 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
919 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
920 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
921 * @retval The new state of __FLAG__ (TRUE or FALSE).
922 */
923 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
924
925 /**
926 * @brief Clears the specified TIM interrupt flag.
927 * @param __HANDLE__ specifies the TIM Handle.
928 * @param __FLAG__ specifies the TIM interrupt flag to clear.
929 * This parameter can be one of the following values:
930 * @arg TIM_FLAG_UPDATE: Update interrupt flag
931 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
932 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
933 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
934 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
935 * @arg TIM_FLAG_COM: Commutation interrupt flag
936 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
937 * @arg TIM_FLAG_BREAK: Break interrupt flag
938 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
939 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
940 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
941 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
942 * @retval The new state of __FLAG__ (TRUE or FALSE).
943 */
944 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
945
946 /**
947 * @brief Checks whether the specified TIM interrupt has occurred or not.
948 * @param __HANDLE__ TIM handle
949 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
950 * @retval The state of TIM_IT (SET or RESET).
951 */
952 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
953
954 /**
955 * @brief Clear the TIM interrupt pending bits
956 * @param __HANDLE__ TIM handle
957 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
958 * @retval None
959 */
960 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
961
962 /**
963 * @brief Indicates whether or not the TIM Counter is used as downcounter
964 * @param __HANDLE__ TIM handle.
965 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
966 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
967 */
968 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
969
970 /**
971 * @brief Sets the TIM active prescaler register value on update event.
972 * @param __HANDLE__ TIM handle.
973 * @param __PRESC__ specifies the active prescaler register new value.
974 * @retval None
975 */
976 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
977
978 /**
979 * @brief Sets the TIM Counter Register value on runtime.
980 * @param __HANDLE__ TIM handle.
981 * @param __COUNTER__ specifies the Counter register new value.
982 * @retval None
983 */
984 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
985
986 /**
987 * @brief Gets the TIM Counter Register value on runtime.
988 * @param __HANDLE__ TIM handle.
989 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
990 */
991 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
992 ((__HANDLE__)->Instance->CNT)
993
994 /**
995 * @brief Sets the TIM Autoreload Register value on runtime without calling
996 * another time any Init function.
997 * @param __HANDLE__ TIM handle.
998 * @param __AUTORELOAD__ specifies the Counter register new value.
999 * @retval None
1000 */
1001 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1002 do{ \
1003 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1004 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1005 } while(0U)
1006
1007 /**
1008 * @brief Gets the TIM Autoreload Register value on runtime
1009 * @param __HANDLE__ TIM handle.
1010 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1011 */
1012 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1013 ((__HANDLE__)->Instance->ARR)
1014
1015 /**
1016 * @brief Sets the TIM Clock Division value on runtime without calling
1017 * another time any Init function.
1018 * @param __HANDLE__ TIM handle.
1019 * @param __CKD__ specifies the clock division value.
1020 * This parameter can be one of the following value:
1021 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1022 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1023 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1024 * @retval None
1025 */
1026 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1027 do{ \
1028 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1029 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1030 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1031 } while(0U)
1032
1033 /**
1034 * @brief Gets the TIM Clock Division value on runtime
1035 * @param __HANDLE__ TIM handle.
1036 * @retval The clock division can be one of the following values:
1037 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1038 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1039 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1040 */
1041 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
1042 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1043
1044 /**
1045 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1046 * another time HAL_TIM_IC_ConfigChannel() function.
1047 * @param __HANDLE__ TIM handle.
1048 * @param __CHANNEL__ TIM Channels to be configured.
1049 * This parameter can be one of the following values:
1050 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1051 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1052 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1053 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1054 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1055 * This parameter can be one of the following values:
1056 * @arg TIM_ICPSC_DIV1: no prescaler
1057 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1058 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1059 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1060 * @retval None
1061 */
1062 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1063 do{ \
1064 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1065 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1066 } while(0U)
1067
1068 /**
1069 * @brief Gets the TIM Input Capture prescaler on runtime
1070 * @param __HANDLE__ TIM handle.
1071 * @param __CHANNEL__ TIM Channels to be configured.
1072 * This parameter can be one of the following values:
1073 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1074 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1075 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1076 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1077 * @retval The input capture prescaler can be one of the following values:
1078 * @arg TIM_ICPSC_DIV1: no prescaler
1079 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1080 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1081 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1082 */
1083 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1084 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1085 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1086 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1087 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1088
1089 /**
1090 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1091 * @param __HANDLE__ TIM handle.
1092 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1093 * overflow/underflow generates an update interrupt or DMA request (if
1094 * enabled)
1095 * @retval None
1096 */
1097 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1098 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1099
1100 /**
1101 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1102 * @param __HANDLE__ TIM handle.
1103 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1104 * following events generate an update interrupt or DMA request (if
1105 * enabled):
1106 * (+) Counter overflow/underflow
1107 * (+) Setting the UG bit
1108 * (+) Update generation through the slave mode controller
1109 * @retval None
1110 */
1111 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1112 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1113
1114 /**
1115 * @brief Sets the TIM Capture x input polarity on runtime.
1116 * @param __HANDLE__ TIM handle.
1117 * @param __CHANNEL__ TIM Channels to be configured.
1118 * This parameter can be one of the following values:
1119 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1120 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1121 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1122 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1123 * @param __POLARITY__ Polarity for TIx source
1124 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1125 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1126 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1127 * @retval None
1128 */
1129 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1130 do{ \
1131 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1132 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1133 }while(0U)
1134
1135 /**
1136 * @}
1137 */
1138 /* End of exported macros ----------------------------------------------------*/
1139
1140 /* Private Constants -----------------------------------------------------------*/
1141 /** @defgroup TIM_Private_Constants TIM Private Constants
1142 * @{
1143 */
1144
1145 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1146 channels have been disabled */
1147 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1148 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1149
1150 /**
1151 * @}
1152 */
1153 /* End of private constants --------------------------------------------------*/
1154
1155 /* Private Macros -----------------------------------------------------------*/
1156 /** @defgroup TIM_Private_Macros TIM Private Macros
1157 * @{
1158 */
1159
1160 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
1161 ((MODE) == TIM_COUNTERMODE_DOWN) || \
1162 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1163 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1164 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
1165
1166 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
1167 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
1168 ((DIV) == TIM_CLOCKDIVISION_DIV4))
1169
1170 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1171 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1172
1173 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
1174 ((STATE) == TIM_OCFAST_ENABLE))
1175
1176 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
1177 ((POLARITY) == TIM_OCPOLARITY_LOW))
1178
1179 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
1180 ((POLARITY) == TIM_OCNPOLARITY_LOW))
1181
1182 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
1183 ((STATE) == TIM_OCIDLESTATE_RESET))
1184
1185 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
1186 ((STATE) == TIM_OCNIDLESTATE_RESET))
1187
1188
1189 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
1190 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
1191 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
1192
1193 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
1194 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
1195 ((SELECTION) == TIM_ICSELECTION_TRC))
1196
1197 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
1198 ((PRESCALER) == TIM_ICPSC_DIV2) || \
1199 ((PRESCALER) == TIM_ICPSC_DIV4) || \
1200 ((PRESCALER) == TIM_ICPSC_DIV8))
1201
1202 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
1203 ((MODE) == TIM_OPMODE_REPETITIVE))
1204
1205 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
1206 ((MODE) == TIM_ENCODERMODE_TI2) || \
1207 ((MODE) == TIM_ENCODERMODE_TI12))
1208
1209 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
1210
1211
1212 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
1213 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
1214 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
1215 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
1216 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
1217 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
1218 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
1219 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
1220 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
1221 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
1222
1223 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
1224 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1225 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
1226 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
1227 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
1228
1229 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
1230 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
1231 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
1232 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
1233
1234 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
1235
1236 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1237 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1238
1239 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1240 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1241 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1242 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
1243
1244 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
1245
1246 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
1247 ((STATE) == TIM_OSSR_DISABLE))
1248
1249 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
1250 ((STATE) == TIM_OSSI_DISABLE))
1251
1252 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
1253 ((LEVEL) == TIM_LOCKLEVEL_1) || \
1254 ((LEVEL) == TIM_LOCKLEVEL_2) || \
1255 ((LEVEL) == TIM_LOCKLEVEL_3))
1256
1257 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
1258 ((STATE) == TIM_BREAK_DISABLE))
1259
1260 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
1261 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
1262
1263 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1264 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
1265
1266 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
1267 ((SOURCE) == TIM_TRGO_ENABLE) || \
1268 ((SOURCE) == TIM_TRGO_UPDATE) || \
1269 ((SOURCE) == TIM_TRGO_OC1) || \
1270 ((SOURCE) == TIM_TRGO_OC1REF) || \
1271 ((SOURCE) == TIM_TRGO_OC2REF) || \
1272 ((SOURCE) == TIM_TRGO_OC3REF) || \
1273 ((SOURCE) == TIM_TRGO_OC4REF))
1274
1275 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
1276 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
1277
1278 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1279 ((SELECTION) == TIM_TS_ITR1) || \
1280 ((SELECTION) == TIM_TS_ITR2) || \
1281 ((SELECTION) == TIM_TS_ITR3) || \
1282 ((SELECTION) == TIM_TS_TI1F_ED) || \
1283 ((SELECTION) == TIM_TS_TI1FP1) || \
1284 ((SELECTION) == TIM_TS_TI2FP2) || \
1285 ((SELECTION) == TIM_TS_ETRF))
1286
1287 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1288 ((SELECTION) == TIM_TS_ITR1) || \
1289 ((SELECTION) == TIM_TS_ITR2) || \
1290 ((SELECTION) == TIM_TS_ITR3) || \
1291 ((SELECTION) == TIM_TS_NONE))
1292
1293 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1294 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1295 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
1296 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
1297 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1298
1299 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
1300 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
1301 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
1302 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
1303
1304 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
1305
1306 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1307 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1308
1309 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1310 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1311 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1312 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1313 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1314 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1315 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1316 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1317 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1318 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1319 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1320 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1321 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1322 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1323 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1324 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1325 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1326 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
1327
1328 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
1329
1330 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
1331
1332 /** @brief Set TIM IC prescaler
1333 * @param __HANDLE__ TIM handle
1334 * @param __CHANNEL__ specifies TIM Channel
1335 * @param __ICPSC__ specifies the prescaler value.
1336 * @retval None
1337 */
1338 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1339 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1340 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1341 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1342 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1343
1344 /** @brief Reset TIM IC prescaler
1345 * @param __HANDLE__ TIM handle
1346 * @param __CHANNEL__ specifies TIM Channel
1347 * @retval None
1348 */
1349 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1350 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1351 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1352 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1353 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1354
1355 /** @brief Set TIM IC polarity
1356 * @param __HANDLE__ TIM handle
1357 * @param __CHANNEL__ specifies TIM Channel
1358 * @param __POLARITY__ specifies TIM Channel Polarity
1359 * @retval None
1360 */
1361 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1362 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1363 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1364 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1365 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1366
1367 /** @brief Reset TIM IC polarity
1368 * @param __HANDLE__ TIM handle
1369 * @param __CHANNEL__ specifies TIM Channel
1370 * @retval None
1371 */
1372 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1373 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1374 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1375 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1376 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1377 /**
1378 * @}
1379 */
1380 /* End of private macros -----------------------------------------------------*/
1381
1382 /* Include TIM HAL Extended module */
1383 #include "stm32f3xx_hal_tim_ex.h"
1384
1385 /* Exported functions --------------------------------------------------------*/
1386 /** @addtogroup TIM_Exported_Functions
1387 * @{
1388 */
1389
1390 /** @addtogroup TIM_Exported_Functions_Group1
1391 * @{
1392 */
1393 /* Time Base functions ********************************************************/
1394 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1395 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1396 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1397 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1398 /* Blocking mode: Polling */
1399 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1400 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1401 /* Non-Blocking mode: Interrupt */
1402 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1403 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1404 /* Non-Blocking mode: DMA */
1405 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1406 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1407 /**
1408 * @}
1409 */
1410
1411 /** @addtogroup TIM_Exported_Functions_Group2
1412 * @{
1413 */
1414 /* Timer Output Compare functions **********************************************/
1415 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1416 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1417 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1418 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1419 /* Blocking mode: Polling */
1420 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1421 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1422 /* Non-Blocking mode: Interrupt */
1423 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1424 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1425 /* Non-Blocking mode: DMA */
1426 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1427 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1428
1429 /**
1430 * @}
1431 */
1432
1433 /** @addtogroup TIM_Exported_Functions_Group3
1434 * @{
1435 */
1436 /* Timer PWM functions *********************************************************/
1437 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1438 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1439 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1440 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1441 /* Blocking mode: Polling */
1442 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1443 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1444 /* Non-Blocking mode: Interrupt */
1445 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1446 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1447 /* Non-Blocking mode: DMA */
1448 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1450 /**
1451 * @}
1452 */
1453
1454 /** @addtogroup TIM_Exported_Functions_Group4
1455 * @{
1456 */
1457 /* Timer Input Capture functions ***********************************************/
1458 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1459 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1460 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1461 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1462 /* Blocking mode: Polling */
1463 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1464 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1465 /* Non-Blocking mode: Interrupt */
1466 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1467 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1468 /* Non-Blocking mode: DMA */
1469 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1470 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1471 /**
1472 * @}
1473 */
1474
1475 /** @addtogroup TIM_Exported_Functions_Group5
1476 * @{
1477 */
1478 /* Timer One Pulse functions ***************************************************/
1479 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1480 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1481 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1482 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1483 /* Blocking mode: Polling */
1484 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1485 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1486 /* Non-Blocking mode: Interrupt */
1487 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1488 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1489 /**
1490 * @}
1491 */
1492
1493 /** @addtogroup TIM_Exported_Functions_Group6
1494 * @{
1495 */
1496 /* Timer Encoder functions *****************************************************/
1497 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1498 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1499 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1500 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1501 /* Blocking mode: Polling */
1502 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1503 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1504 /* Non-Blocking mode: Interrupt */
1505 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1506 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1507 /* Non-Blocking mode: DMA */
1508 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1509 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1510
1511 /**
1512 * @}
1513 */
1514
1515 /** @addtogroup TIM_Exported_Functions_Group7
1516 * @{
1517 */
1518 /* Interrupt Handler functions **********************************************/
1519 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1520 /**
1521 * @}
1522 */
1523
1524 /** @addtogroup TIM_Exported_Functions_Group8
1525 * @{
1526 */
1527 /* Control functions *********************************************************/
1528 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1529 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1530 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1531 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1532 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1533 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1534 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1535 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1536 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1537 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1538 uint32_t *BurstBuffer, uint32_t BurstLength);
1539 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1540 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
1541 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1542 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1543 uint32_t *BurstBuffer, uint32_t BurstLength);
1544 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1545 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
1546 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1547 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1548 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1549
1550 /**
1551 * @}
1552 */
1553
1554 /** @addtogroup TIM_Exported_Functions_Group9
1555 * @{
1556 */
1557 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1558 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1559 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1560 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1561 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1562 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1563 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1564 /**
1565 * @}
1566 */
1567
1568 /** @addtogroup TIM_Exported_Functions_Group10
1569 * @{
1570 */
1571 /* Peripheral State functions **************************************************/
1572 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1573 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1574 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1575 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1576 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1577 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1578
1579 /**
1580 * @}
1581 */
1582
1583 /**
1584 * @}
1585 */
1586 /* End of exported functions -------------------------------------------------*/
1587
1588 /* Private Functions --------------------------------------------------------*/
1589 /** @addtogroup TIM_Private_Functions
1590 * @{
1591 */
1592 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1593 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1594 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1595 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1596 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1597 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1598 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
1599 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
1600 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1601 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1602 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1603 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1604 /**
1605 * @}
1606 */
1607 /* End of private functions --------------------------------------------------*/
1608
1609 /**
1610 * @}
1611 */
1612
1613 /**
1614 * @}
1615 */
1616
1617 #ifdef __cplusplus
1618 }
1619 #endif
1620
1621 #endif /* __STM32F3xx_HAL_TIM_H */
1622
1623 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/