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Updated and Validated
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_bus.h
blobf3e5849bf585349b7cca010d137a106bf24b684b
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
27 *
28 * Redistribution and use in source and binary forms, with or without modification,
29 * are permitted provided that the following conditions are met:
30 * 1. Redistributions of source code must retain the above copyright notice,
31 * this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright notice,
33 * this list of conditions and the following disclaimer in the documentation
34 * and/or other materials provided with the distribution.
35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 ******************************************************************************
51 */
52
53 /* Define to prevent recursive inclusion -------------------------------------*/
54 #ifndef __STM32F3xx_LL_BUS_H
55 #define __STM32F3xx_LL_BUS_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 /* Includes ------------------------------------------------------------------*/
62 #include "stm32f3xx.h"
63
64 /** @addtogroup STM32F3xx_LL_Driver
65 * @{
66 */
67
68 #if defined(RCC)
69
70 /** @defgroup BUS_LL BUS
71 * @{
72 */
73
74 /* Private types -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76
77 /* Private constants ---------------------------------------------------------*/
78
79 /* Private macros ------------------------------------------------------------*/
80
81 /* Exported types ------------------------------------------------------------*/
82 /* Exported constants --------------------------------------------------------*/
83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
84 * @{
85 */
86
87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
88 * @{
89 */
90 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
91 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
92 #if defined(DMA2)
93 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
94 #endif /*DMA2*/
95 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
96 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
97 #if defined(FMC_Bank1)
98 #define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
99 #endif /*FMC_Bank1*/
100 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
101 #if defined(GPIOH)
102 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
103 #endif /*GPIOH*/
104 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
105 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
106 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
107 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
108 #if defined(GPIOE)
109 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
110 #endif /*GPIOE*/
111 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
112 #if defined(GPIOG)
113 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
114 #endif /*GPIOH*/
115 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
116 #if defined(RCC_AHBENR_ADC1EN)
117 #define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
118 #endif /*RCC_AHBENR_ADC1EN*/
119 #if defined(ADC1_2_COMMON)
120 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
121 #endif /*ADC1_2_COMMON*/
122 #if defined(ADC3_4_COMMON)
123 #define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
124 #endif /*ADC3_4_COMMON*/
125 /**
126 * @}
127 */
128
129 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
130 * @{
131 */
132 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
133 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
134 #if defined(TIM3)
135 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
136 #endif /*TIM3*/
137 #if defined(TIM4)
138 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
139 #endif /*TIM4*/
140 #if defined(TIM5)
141 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
142 #endif /*TIM5*/
143 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
144 #if defined(TIM7)
145 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
146 #endif /*TIM7*/
147 #if defined(TIM12)
148 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
149 #endif /*TIM12*/
150 #if defined(TIM13)
151 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
152 #endif /*TIM13*/
153 #if defined(TIM14)
154 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
155 #endif /*TIM14*/
156 #if defined(TIM18)
157 #define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
158 #endif /*TIM18*/
159 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
160 #if defined(SPI2)
161 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
162 #endif /*SPI2*/
163 #if defined(SPI3)
164 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
165 #endif /*SPI3*/
166 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
167 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
168 #if defined(UART4)
169 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
170 #endif /*UART4*/
171 #if defined(UART5)
172 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
173 #endif /*UART5*/
174 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
175 #if defined(I2C2)
176 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
177 #endif /*I2C2*/
178 #if defined(USB)
179 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
180 #endif /*USB*/
181 #if defined(CAN)
182 #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
183 #endif /*CAN*/
184 #if defined(DAC2)
185 #define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
186 #endif /*DAC2*/
187 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
188 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
189 #if defined(CEC)
190 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
191 #endif /*CEC*/
192 #if defined(I2C3)
193 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
194 #endif /*I2C3*/
195 /**
196 * @}
197 */
198
199 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
200 * @{
201 */
202 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
203 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
204 #if defined(RCC_APB2ENR_ADC1EN)
205 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
206 #endif /*RCC_APB2ENR_ADC1EN*/
207 #if defined(TIM1)
208 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
209 #endif /*TIM1*/
210 #if defined(SPI1)
211 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
212 #endif /*SPI1*/
213 #if defined(TIM8)
214 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
215 #endif /*TIM8*/
216 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
217 #if defined(SPI4)
218 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
219 #endif /*SPI4*/
220 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
221 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
222 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
223 #if defined(TIM19)
224 #define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
225 #endif /*TIM19*/
226 #if defined(TIM20)
227 #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
228 #endif /*TIM20*/
229 #if defined(HRTIM1)
230 #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
231 #endif /*HRTIM1*/
232 #if defined(SDADC1)
233 #define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
234 #endif /*SDADC1*/
235 #if defined(SDADC2)
236 #define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
237 #endif /*SDADC2*/
238 #if defined(SDADC3)
239 #define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
240 #endif /*SDADC3*/
241 /**
242 * @}
243 */
244
245 /**
246 * @}
247 */
248
249 /* Exported macro ------------------------------------------------------------*/
250
251 /* Exported functions --------------------------------------------------------*/
252 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
253 * @{
254 */
255
256 /** @defgroup BUS_LL_EF_AHB1 AHB1
257 * @{
258 */
259
260 /**
261 * @brief Enable AHB1 peripherals clock.
262 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
263 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
264 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
265 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
266 * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n
267 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
268 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
269 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
270 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
271 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
272 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
273 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
274 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
275 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
276 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
277 * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n
278 * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n
279 * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
280 * @param Periphs This parameter can be a combination of the following values:
281 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
282 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
283 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
284 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
285 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
286 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
287 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
288 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
289 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
290 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
292 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
293 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
294 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
296 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
297 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
298 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
299 *
300 * (*) value not defined in all devices.
301 * @retval None
302 */
303 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
304 {
305 __IO uint32_t tmpreg;
306 SET_BIT(RCC->AHBENR, Periphs);
307 /* Delay after an RCC peripheral clock enabling */
308 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
309 (void)tmpreg;
310 }
311
312 /**
313 * @brief Check if AHB1 peripheral clock is enabled or not
314 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
315 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
316 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
317 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
318 * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n
319 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
320 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
321 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
322 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
323 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
324 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
325 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
326 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
327 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
328 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
329 * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n
330 * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
331 * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
332 * @param Periphs This parameter can be a combination of the following values:
333 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
334 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
335 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
336 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
337 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
338 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
340 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
347 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
348 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
349 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
350 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
351 *
352 * (*) value not defined in all devices.
353 * @retval State of Periphs (1 or 0).
354 */
355 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
356 {
357 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
358 }
359
360 /**
361 * @brief Disable AHB1 peripherals clock.
362 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
363 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
364 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
365 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
366 * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n
367 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
368 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
369 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
370 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
371 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
372 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
373 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
374 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
375 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
376 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
377 * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n
378 * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n
379 * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
380 * @param Periphs This parameter can be a combination of the following values:
381 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
382 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
383 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
384 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
385 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
386 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
390 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
391 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
392 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
393 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
394 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
395 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
396 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
397 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
398 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
399 *
400 * (*) value not defined in all devices.
401 * @retval None
402 */
403 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
404 {
405 CLEAR_BIT(RCC->AHBENR, Periphs);
406 }
407
408 /**
409 * @brief Force AHB1 peripherals reset.
410 * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n
411 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
412 * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
413 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
414 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
415 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
416 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
417 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
418 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
419 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
420 * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n
421 * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
422 * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
423 * @param Periphs This parameter can be a combination of the following values:
424 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
425 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
429 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
430 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
431 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
432 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
433 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
434 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
435 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
436 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
437 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
438 *
439 * (*) value not defined in all devices.
440 * @retval None
441 */
442 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
443 {
444 SET_BIT(RCC->AHBRSTR, Periphs);
445 }
446
447 /**
448 * @brief Release AHB1 peripherals reset.
449 * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n
450 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
451 * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
452 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
453 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
454 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
455 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
456 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
457 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
458 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
459 * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n
460 * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
461 * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
462 * @param Periphs This parameter can be a combination of the following values:
463 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
464 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
473 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
474 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
475 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
476 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
477 *
478 * (*) value not defined in all devices.
479 * @retval None
480 */
481 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
482 {
483 CLEAR_BIT(RCC->AHBRSTR, Periphs);
484 }
485
486 /**
487 * @}
488 */
489
490 /** @defgroup BUS_LL_EF_APB1 APB1
491 * @{
492 */
493
494 /**
495 * @brief Enable APB1 peripherals clock.
496 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
497 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
498 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
499 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
500 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
501 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
502 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
503 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
504 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
505 * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n
506 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
507 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
508 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
509 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
510 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
511 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
512 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
513 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
514 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
515 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
516 * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
517 * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n
518 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
519 * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n
520 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
521 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
522 * @param Periphs This parameter can be a combination of the following values:
523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
529 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
530 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
531 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
532 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
533 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
534 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
535 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
536 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
537 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
538 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
539 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
540 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
541 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
542 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
543 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
544 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
545 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
546 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
547 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
548 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
549 *
550 * (*) value not defined in all devices.
551 * @retval None
552 */
553 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
554 {
555 __IO uint32_t tmpreg;
556 SET_BIT(RCC->APB1ENR, Periphs);
557 /* Delay after an RCC peripheral clock enabling */
558 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
559 (void)tmpreg;
560 }
561
562 /**
563 * @brief Check if APB1 peripheral clock is enabled or not
564 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
565 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
566 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
567 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
568 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
569 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
570 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
571 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
572 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
573 * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n
574 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
575 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
576 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
577 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
578 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
579 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
580 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
581 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
582 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
583 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
584 * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
585 * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n
586 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
587 * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n
588 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
589 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
590 * @param Periphs This parameter can be a combination of the following values:
591 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
592 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
593 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
594 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
595 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
596 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
597 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
598 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
599 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
600 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
601 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
602 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
603 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
604 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
605 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
606 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
607 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
608 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
609 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
610 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
611 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
612 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
613 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
614 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
615 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
616 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
617 *
618 * (*) value not defined in all devices.
619 * @retval State of Periphs (1 or 0).
620 */
621 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
622 {
623 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
624 }
625
626 /**
627 * @brief Disable APB1 peripherals clock.
628 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
629 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
630 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
631 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
632 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
633 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
634 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
635 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
636 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
637 * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n
638 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
639 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
640 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
641 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
642 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
643 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
644 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
645 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
646 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
647 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
648 * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
649 * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n
650 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
651 * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n
652 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
653 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
654 * @param Periphs This parameter can be a combination of the following values:
655 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
656 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
657 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
658 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
659 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
660 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
661 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
662 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
663 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
664 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
665 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
666 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
667 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
668 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
669 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
670 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
671 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
672 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
673 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
674 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
675 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
676 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
677 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
678 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
679 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
680 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
681 *
682 * (*) value not defined in all devices.
683 * @retval None
684 */
685 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
686 {
687 CLEAR_BIT(RCC->APB1ENR, Periphs);
688 }
689
690 /**
691 * @brief Force APB1 peripherals reset.
692 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
693 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
694 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
695 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
696 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
697 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
698 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
699 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
700 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
701 * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n
702 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
703 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
704 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
705 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
706 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
707 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
708 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
709 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
710 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
711 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
712 * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
713 * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n
714 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
715 * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n
716 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
717 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
718 * @param Periphs This parameter can be a combination of the following values:
719 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
720 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
721 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
722 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
723 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
724 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
725 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
726 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
727 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
728 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
729 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
730 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
731 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
732 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
733 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
734 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
735 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
736 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
737 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
738 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
739 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
740 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
741 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
742 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
743 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
744 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
745 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
746 *
747 * (*) value not defined in all devices.
748 * @retval None
749 */
750 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
751 {
752 SET_BIT(RCC->APB1RSTR, Periphs);
753 }
754
755 /**
756 * @brief Release APB1 peripherals reset.
757 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
758 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
759 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
760 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
761 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
762 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
763 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
764 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
765 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
766 * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n
767 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
768 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
769 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
770 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
771 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
772 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
773 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
774 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
775 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
776 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
777 * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
778 * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n
779 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
780 * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n
781 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
782 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
783 * @param Periphs This parameter can be a combination of the following values:
784 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
785 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
786 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
787 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
788 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
789 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
790 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
791 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
792 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
793 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
794 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
795 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
796 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
797 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
798 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
799 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
800 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
801 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
802 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
803 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
804 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
805 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
806 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
807 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
808 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
809 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
810 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
811 *
812 * (*) value not defined in all devices.
813 * @retval None
814 */
815 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
816 {
817 CLEAR_BIT(RCC->APB1RSTR, Periphs);
818 }
819
820 /**
821 * @}
822 */
823
824 /** @defgroup BUS_LL_EF_APB2 APB2
825 * @{
826 */
827
828 /**
829 * @brief Enable APB2 peripherals clock.
830 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
831 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
832 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
833 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
834 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
835 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
836 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
837 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
838 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
839 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
840 * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n
841 * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
842 * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n
843 * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n
844 * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n
845 * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
846 * @param Periphs This parameter can be a combination of the following values:
847 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
848 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
849 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
850 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
851 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
852 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
853 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
854 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
855 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
856 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
857 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
858 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
859 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
860 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
861 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
862 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
863 *
864 * (*) value not defined in all devices.
865 * @retval None
866 */
867 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
868 {
869 __IO uint32_t tmpreg;
870 SET_BIT(RCC->APB2ENR, Periphs);
871 /* Delay after an RCC peripheral clock enabling */
872 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
873 (void)tmpreg;
874 }
875
876 /**
877 * @brief Check if APB2 peripheral clock is enabled or not
878 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
879 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
880 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
881 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
882 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
883 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
884 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
885 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
886 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
887 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
888 * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n
889 * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
890 * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n
891 * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n
892 * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n
893 * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
894 * @param Periphs This parameter can be a combination of the following values:
895 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
896 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
897 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
898 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
899 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
900 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
901 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
903 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
904 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
905 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
906 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
907 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
908 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
909 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
910 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
911 *
912 * (*) value not defined in all devices.
913 * @retval State of Periphs (1 or 0).
914 */
915 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
916 {
917 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
918 }
919
920 /**
921 * @brief Disable APB2 peripherals clock.
922 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
923 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
924 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
925 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
926 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
927 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
928 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
929 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
930 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
931 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
932 * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n
933 * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
934 * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n
935 * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n
936 * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n
937 * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
938 * @param Periphs This parameter can be a combination of the following values:
939 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
940 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
941 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
942 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
943 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
944 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
945 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
946 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
947 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
948 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
949 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
950 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
951 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
952 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
953 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
954 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
955 *
956 * (*) value not defined in all devices.
957 * @retval None
958 */
959 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
960 {
961 CLEAR_BIT(RCC->APB2ENR, Periphs);
962 }
963
964 /**
965 * @brief Force APB2 peripherals reset.
966 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
967 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
968 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
969 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
970 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
971 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
972 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
973 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
974 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
975 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
976 * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n
977 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
978 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n
979 * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n
980 * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n
981 * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
982 * @param Periphs This parameter can be a combination of the following values:
983 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
984 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
985 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
986 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
987 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
988 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
989 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
990 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
992 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
993 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
994 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
995 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
996 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
997 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
998 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
999 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
1000 *
1001 * (*) value not defined in all devices.
1002 * @retval None
1003 */
1004 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1005 {
1006 SET_BIT(RCC->APB2RSTR, Periphs);
1007 }
1008
1009 /**
1010 * @brief Release APB2 peripherals reset.
1011 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1012 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
1013 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1014 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1015 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1016 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1017 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1018 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1019 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1020 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1021 * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n
1022 * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n
1023 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n
1024 * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n
1025 * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n
1026 * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
1027 * @param Periphs This parameter can be a combination of the following values:
1028 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1029 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1030 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
1031 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
1032 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1033 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1034 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1035 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1036 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1037 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1038 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1039 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
1040 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1041 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1042 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
1043 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
1044 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
1045 *
1046 * (*) value not defined in all devices.
1047 * @retval None
1048 */
1049 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1050 {
1051 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1052 }
1053
1054 /**
1055 * @}
1056 */
1057
1058
1059 /**
1060 * @}
1061 */
1062
1063 /**
1064 * @}
1065 */
1066
1067 #endif /* defined(RCC) */
1068
1069 /**
1070 * @}
1071 */
1072
1073 #ifdef __cplusplus
1074 }
1075 #endif
1076
1077 #endif /* __STM32F3xx_LL_BUS_H */
1078
1079 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/