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Updated and Validated
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_tim.h
blob61ad5cb80dad361d9115bc56281b3eb38d152f28
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_TIM_H
38 #define __STM32F3xx_LL_TIM_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx.h"
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
52
53 /** @defgroup TIM_LL TIM
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
60 * @{
61 */
62 static const uint8_t OFFSET_TAB_CCMRx[] =
63 {
64 0x00U, /* 0: TIMx_CH1 */
65 0x00U, /* 1: TIMx_CH1N */
66 0x00U, /* 2: TIMx_CH2 */
67 0x00U, /* 3: TIMx_CH2N */
68 0x04U, /* 4: TIMx_CH3 */
69 0x04U, /* 5: TIMx_CH3N */
70 0x04U, /* 6: TIMx_CH4 */
71 0x3CU, /* 7: TIMx_CH5 */
72 0x3CU /* 8: TIMx_CH6 */
73 };
74
75 static const uint8_t SHIFT_TAB_OCxx[] =
76 {
77 0U, /* 0: OC1M, OC1FE, OC1PE */
78 0U, /* 1: - NA */
79 8U, /* 2: OC2M, OC2FE, OC2PE */
80 0U, /* 3: - NA */
81 0U, /* 4: OC3M, OC3FE, OC3PE */
82 0U, /* 5: - NA */
83 8U, /* 6: OC4M, OC4FE, OC4PE */
84 0U, /* 7: OC5M, OC5FE, OC5PE */
85 8U /* 8: OC6M, OC6FE, OC6PE */
86 };
87
88 static const uint8_t SHIFT_TAB_ICxx[] =
89 {
90 0U, /* 0: CC1S, IC1PSC, IC1F */
91 0U, /* 1: - NA */
92 8U, /* 2: CC2S, IC2PSC, IC2F */
93 0U, /* 3: - NA */
94 0U, /* 4: CC3S, IC3PSC, IC3F */
95 0U, /* 5: - NA */
96 8U, /* 6: CC4S, IC4PSC, IC4F */
97 0U, /* 7: - NA */
98 0U /* 8: - NA */
99 };
100
101 static const uint8_t SHIFT_TAB_CCxP[] =
102 {
103 0U, /* 0: CC1P */
104 2U, /* 1: CC1NP */
105 4U, /* 2: CC2P */
106 6U, /* 3: CC2NP */
107 8U, /* 4: CC3P */
108 10U, /* 5: CC3NP */
109 12U, /* 6: CC4P */
110 16U, /* 7: CC5P */
111 20U /* 8: CC6P */
112 };
113
114 static const uint8_t SHIFT_TAB_OISx[] =
115 {
116 0U, /* 0: OIS1 */
117 1U, /* 1: OIS1N */
118 2U, /* 2: OIS2 */
119 3U, /* 3: OIS2N */
120 4U, /* 4: OIS3 */
121 5U, /* 5: OIS3N */
122 6U, /* 6: OIS4 */
123 8U, /* 7: OIS5 */
124 10U /* 8: OIS6 */
125 };
126 /**
127 * @}
128 */
129
130
131 /* Private constants ---------------------------------------------------------*/
132 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
133 * @{
134 */
135
136
137 #define TIMx_OR_RMP_SHIFT 16U
138 #define TIMx_OR_RMP_MASK 0x0000FFFFU
139 #if defined(TIM1)
140 #define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
141 #endif /* TIM1 */
142 #if defined (TIM8)
143 #define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
144 #endif /* TIM8 */
145 #if defined(TIM14)
146 #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
147 #endif /* TIM14 */
148 #if defined(TIM16)
149 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
150 #endif /* TIM16 */
151 #if defined(TIM20)
152 #define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
153 #endif /* TIM20 */
154
155 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
156 #define DT_DELAY_1 ((uint8_t)0x7FU)
157 #define DT_DELAY_2 ((uint8_t)0x3FU)
158 #define DT_DELAY_3 ((uint8_t)0x1FU)
159 #define DT_DELAY_4 ((uint8_t)0x1FU)
160
161 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
162 #define DT_RANGE_1 ((uint8_t)0x00U)
163 #define DT_RANGE_2 ((uint8_t)0x80U)
164 #define DT_RANGE_3 ((uint8_t)0xC0U)
165 #define DT_RANGE_4 ((uint8_t)0xE0U)
166
167
168 /**
169 * @}
170 */
171
172 /* Private macros ------------------------------------------------------------*/
173 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
174 * @{
175 */
176 /** @brief Convert channel id into channel index.
177 * @param __CHANNEL__ This parameter can be one of the following values:
178 * @arg @ref LL_TIM_CHANNEL_CH1
179 * @arg @ref LL_TIM_CHANNEL_CH1N
180 * @arg @ref LL_TIM_CHANNEL_CH2
181 * @arg @ref LL_TIM_CHANNEL_CH2N
182 * @arg @ref LL_TIM_CHANNEL_CH3
183 * @arg @ref LL_TIM_CHANNEL_CH3N
184 * @arg @ref LL_TIM_CHANNEL_CH4
185 * @arg @ref LL_TIM_CHANNEL_CH5
186 * @arg @ref LL_TIM_CHANNEL_CH6
187 * @note CH5 and CH6 channels are not available for all F3 devices
188 * @retval none
189 */
190 #if defined(TIM_CCR5_CCR5)
191 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
192 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
197 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
198 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
199 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
200 #else
201 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
202 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
203 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
204 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
205 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
206 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
207 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
208 #endif
209
210 /** @brief Calculate the deadtime sampling period(in ps).
211 * @param __TIMCLK__ timer input clock frequency (in Hz).
212 * @param __CKD__ This parameter can be one of the following values:
213 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
214 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
215 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
216 * @retval none
217 */
218 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
219 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
220 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
221 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
222 /**
223 * @}
224 */
225
226
227 /* Exported types ------------------------------------------------------------*/
228 #if defined(USE_FULL_LL_DRIVER)
229 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
230 * @{
231 */
232
233 /**
234 * @brief TIM Time Base configuration structure definition.
235 */
236 typedef struct
237 {
238 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
239 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240
241 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
242
243 uint32_t CounterMode; /*!< Specifies the counter mode.
244 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
245
246 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
247
248 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
249 Auto-Reload Register at the next update event.
250 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
251 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
252
253 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
254
255 uint32_t ClockDivision; /*!< Specifies the clock division.
256 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
257
258 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
259
260 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
261 reaches zero, an update event is generated and counting restarts
262 from the RCR value (N).
263 This means in PWM mode that (N+1) corresponds to:
264 - the number of PWM periods in edge-aligned mode
265 - the number of half PWM period in center-aligned mode
266 This parameter must be a number between 0x00 and 0xFF.
267
268 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
269 } LL_TIM_InitTypeDef;
270
271 /**
272 * @brief TIM Output Compare configuration structure definition.
273 */
274 typedef struct
275 {
276 uint32_t OCMode; /*!< Specifies the output mode.
277 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
278
279 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
280
281 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
282 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
283
284 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
285
286 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
287 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
288
289 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
290
291 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
292 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
293
294 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
295
296 uint32_t OCPolarity; /*!< Specifies the output polarity.
297 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
298
299 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
300
301 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
302 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
303
304 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
305
306
307 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
308 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
309
310 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
311
312 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
313 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
314
315 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
316 } LL_TIM_OC_InitTypeDef;
317
318 /**
319 * @brief TIM Input Capture configuration structure definition.
320 */
321
322 typedef struct
323 {
324
325 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
326 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
327
328 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
329
330 uint32_t ICActiveInput; /*!< Specifies the input.
331 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
332
333 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
334
335 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
336 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
337
338 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
339
340 uint32_t ICFilter; /*!< Specifies the input capture filter.
341 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
342
343 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
344 } LL_TIM_IC_InitTypeDef;
345
346
347 /**
348 * @brief TIM Encoder interface configuration structure definition.
349 */
350 typedef struct
351 {
352 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
353 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
354
355 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
356
357 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
358 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
359
360 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
361
362 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
363 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
364
365 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
366
367 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
368 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
369
370 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
371
372 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
373 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
374
375 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
376
377 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
378 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
379
380 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
381
382 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
383 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
384
385 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
386
387 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
388 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
389
390 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
391
392 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
393 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
394
395 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
396
397 } LL_TIM_ENCODER_InitTypeDef;
398
399 /**
400 * @brief TIM Hall sensor interface configuration structure definition.
401 */
402 typedef struct
403 {
404
405 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
406 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
407
408 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
409
410 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
411 Prescaler must be set to get a maximum counter period longer than the
412 time interval between 2 consecutive changes on the Hall inputs.
413 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
414
415 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
416
417 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
418 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
419
420 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
421
422 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
423 A positive pulse (TRGO event) is generated with a programmable delay every time
424 a change occurs on the Hall inputs.
425 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
426
427 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
428 } LL_TIM_HALLSENSOR_InitTypeDef;
429
430 /**
431 * @brief BDTR (Break and Dead Time) structure definition
432 */
433 typedef struct
434 {
435 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
436 This parameter can be a value of @ref TIM_LL_EC_OSSR
437
438 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
439
440 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
441
442 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
443 This parameter can be a value of @ref TIM_LL_EC_OSSI
444
445 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
446
447 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
448
449 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
450 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
451
452 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
453 has been written, their content is frozen until the next reset.*/
454
455 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
456 switching-on of the outputs.
457 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
458
459 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
460
461 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
462
463 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
464 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
465
466 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
467
468 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
469
470 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
471 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
472
473 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
474
475 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
476
477 #if defined(TIM_BDTR_BKF)
478 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
479 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
480
481 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
482
483 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
484
485 #endif /* TIM_BDTR_BKF */
486 #if defined(TIM_BDTR_BK2E)
487 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
488 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
489
490 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
491
492 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
493
494 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
495 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
496
497 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
498
499 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
500
501 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
502 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
503
504 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
505
506 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
507
508 #endif /* TIM_BDTR_BK2E */
509 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
510 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
511
512 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
513
514 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
515 } LL_TIM_BDTR_InitTypeDef;
516
517 /**
518 * @}
519 */
520 #endif /* USE_FULL_LL_DRIVER */
521
522 /* Exported constants --------------------------------------------------------*/
523 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
524 * @{
525 */
526
527 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
528 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
529 * @{
530 */
531 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
532 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
533 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
534 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
535 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
536 #if defined(TIM_CCMR1_OC1M_3)
537 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
538 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
539 #endif /* TIM_CCMR1_OC1M_3 */
540 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
541 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
542 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
543 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
544 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
545 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
546 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
547 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
548 /**
549 * @}
550 */
551
552 #if defined(USE_FULL_LL_DRIVER)
553 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
554 * @{
555 */
556 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
557 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
558 /**
559 * @}
560 */
561 #if defined(TIM_BDTR_BK2E)
562
563 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
564 * @{
565 */
566 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
567 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
568 /**
569 * @}
570 */
571 #endif /* TIM_BDTR_BK2E */
572
573 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
574 * @{
575 */
576 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
577 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
578 /**
579 * @}
580 */
581 #endif /* USE_FULL_LL_DRIVER */
582
583 /** @defgroup TIM_LL_EC_IT IT Defines
584 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
585 * @{
586 */
587 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
588 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
589 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
590 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
591 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
592 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
593 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
594 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
595 /**
596 * @}
597 */
598
599 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
600 * @{
601 */
602 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
603 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
604 /**
605 * @}
606 */
607
608 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
609 * @{
610 */
611 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
612 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
613 /**
614 * @}
615 */
616
617 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
618 * @{
619 */
620 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
621 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
622 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
623 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
624 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
625 /**
626 * @}
627 */
628
629 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
630 * @{
631 */
632 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
633 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
634 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
635 /**
636 * @}
637 */
638
639 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
640 * @{
641 */
642 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
643 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
644 /**
645 * @}
646 */
647
648 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
649 * @{
650 */
651 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
652 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
653 /**
654 * @}
655 */
656
657 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
658 * @{
659 */
660 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
661 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
662 /**
663 * @}
664 */
665
666 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
667 * @{
668 */
669 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
670 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
671 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
672 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_LL_EC_CHANNEL Channel
678 * @{
679 */
680 #if defined(TIM_CCMR1_OC1M_3)
681 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
682 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
683 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
684 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
685 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
686 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
687 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
688 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
689 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
690 #else
691 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
692 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
693 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
694 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
695 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
696 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
697 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
698 #endif
699 /**
700 * @}
701 */
702
703 #if defined(USE_FULL_LL_DRIVER)
704 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
705 * @{
706 */
707 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
708 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
709 /**
710 * @}
711 */
712 #endif /* USE_FULL_LL_DRIVER */
713
714 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
715 * @{
716 */
717 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
718 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
719 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
720 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
721 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
722 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
723 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
724 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
725 #if defined(TIM_CCMR1_OC1M_3)
726 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
727 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
728 #endif
729 #if defined(TIM_CCMR1_OC1M_3)
730 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
731 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
732 #endif
733 #if defined(TIM_CCMR1_OC1M_3)
734 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
735 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
736 #endif
737 /**
738 * @}
739 */
740
741 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
742 * @{
743 */
744 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
745 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
746 /**
747 * @}
748 */
749
750 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
751 * @{
752 */
753 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
754 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
755 /**
756 * @}
757 */
758
759 #if defined(TIM_CCR5_CCR5)
760 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
761 * @{
762 */
763 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
764 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
765 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
766 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
767 /**
768 * @}
769 */
770 #endif /* TIM_CCR5_CCR5 */
771
772 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
773 * @{
774 */
775 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
776 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
777 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
783 * @{
784 */
785 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
786 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
787 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
788 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
794 * @{
795 */
796 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
797 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
798 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
799 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
800 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
801 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
802 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
803 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
804 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
805 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
806 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
807 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
808 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
809 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
810 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
811 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
812 /**
813 * @}
814 */
815
816 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
817 * @{
818 */
819 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
820 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
821 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
822 /**
823 * @}
824 */
825
826 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
827 * @{
828 */
829 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
830 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
831 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
832 /**
833 * @}
834 */
835
836 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
837 * @{
838 */
839 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
840 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
841 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
842 /**
843 * @}
844 */
845
846 /** @defgroup TIM_LL_EC_TRGO Trigger Output
847 * @{
848 */
849 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
850 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
851 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
852 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
853 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
854 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
855 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
856 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
857 /**
858 * @}
859 */
860
861 #if defined(TIM_CR2_MMS2)
862 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
863 * @{
864 */
865 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
866 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
867 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
868 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
869 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
870 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
871 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
872 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
873 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
874 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
875 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
876 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
877 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
878 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
879 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
880 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
881 /**
882 * @}
883 */
884 #endif /* TIM_CR2_MMS2 */
885
886 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
887 * @{
888 */
889 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
890 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
891 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
892 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
893 #if defined (TIM_SMCR_SMS_3)
894 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
895 #endif /* TIM_SMCR_SMS_3 */
896 /**
897 * @}
898 */
899
900 /** @defgroup TIM_LL_EC_TS Trigger Selection
901 * @{
902 */
903 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
904 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
905 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
906 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
907 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
908 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
909 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
910 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
911 /**
912 * @}
913 */
914
915 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
916 * @{
917 */
918 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
919 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
920 /**
921 * @}
922 */
923
924 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
925 * @{
926 */
927 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
928 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
929 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
930 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
931 /**
932 * @}
933 */
934
935 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
936 * @{
937 */
938 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
939 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
940 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
941 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
942 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
943 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
944 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
945 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
946 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
947 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
948 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
949 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
950 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
951 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
952 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
953 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
954 /**
955 * @}
956 */
957
958
959 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
960 * @{
961 */
962 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
963 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
964 /**
965 * @}
966 */
967
968 #if defined(TIM_BDTR_BKF)
969 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
970 * @{
971 */
972 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
973 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
974 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
975 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
976 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
977 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
978 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
979 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
980 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
981 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
982 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
983 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
984 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
985 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
986 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
987 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
988 /**
989 * @}
990 */
991 #endif /* TIM_BDTR_BKF */
992
993 #if defined(TIM_BDTR_BK2P)
994 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
995 * @{
996 */
997 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
998 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
999 /**
1000 * @}
1001 */
1002 #endif /* TIM_BDTR_BK2P */
1003
1004 #if defined(TIM_BDTR_BK2F)
1005 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1006 * @{
1007 */
1008 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1009 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1010 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1011 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1012 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1013 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1014 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1015 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1016 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1017 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1018 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1019 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1020 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1021 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1022 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1023 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1024 /**
1025 * @}
1026 */
1027 #endif /* TIM_BDTR_BK2F */
1028
1029 /** @defgroup TIM_LL_EC_OSSI OSSI
1030 * @{
1031 */
1032 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1033 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1034 /**
1035 * @}
1036 */
1037
1038 /** @defgroup TIM_LL_EC_OSSR OSSR
1039 * @{
1040 */
1041 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1042 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1043 /**
1044 * @}
1045 */
1046
1047
1048 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1049 * @{
1050 */
1051 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1052 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1053 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1054 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1055 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1056 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1057 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1058 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1059 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1060 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1061 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1062 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1063 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1064 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1065 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1070 #if defined(TIM_CCR6_CCR6)
1071 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1073 #endif /* TIM_CCR6_CCR6 */
1074 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1080 * @{
1081 */
1082 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1083 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1084 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1085 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1086 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1087 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1088 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1089 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1090 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1091 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1092 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1093 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1094 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1095 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1096 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1097 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1098 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1099 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1100 /**
1101 * @}
1102 */
1103
1104 #if defined(TIM1)
1105 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1106 * @{
1107 */
1108 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1109 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1110 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1111 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1112 /**
1113 * @}
1114 */
1115 #if defined(ADC4)
1116 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP TIM1 External Trigger ADC4 Remap
1117 * @{
1118 */
1119 #define LL_TIM_TIM1_ETR_ADC4_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/
1120 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
1121 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
1122 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
1123 /**
1124 * @}
1125 */
1126 #else
1127 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
1128 * @{
1129 */
1130 #define LL_TIM_TIM1_ETR_ADC2_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/
1131 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
1132 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
1133 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
1134 /**
1135 * @}
1136 */
1137 #endif /* ADC4 */
1138 #endif /* TIM1 */
1139 #if defined(TIM8)
1140 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1141 * @{
1142 */
1143 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1144 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1145 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1146 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1152 * @{
1153 */
1154 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1155 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1156 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1157 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1158 /**
1159 * @}
1160 */
1161 #endif /* TIM8 */
1162 #if defined(TIM16)
1163 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1164 * @{
1165 */
1166 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */
1167 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1168 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */
1169 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1170 /**
1171 * @}
1172 */
1173 #endif /* TIM16 */
1174 #if defined(TIM20)
1175 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
1176 * @{
1177 */
1178 #define LL_TIM_TIM20_ETR_ADC3_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
1179 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */
1180 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
1181 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
1182 /**
1183 * @}
1184 */
1185
1186 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
1187 * @{
1188 */
1189 #define LL_TIM_TIM20_ETR_ADC4_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
1190 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
1191 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
1192 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
1193 /**
1194 * @}
1195 */
1196 #endif /* TIM20 */
1197 #if defined(TIM14)
1198 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
1199 * @{
1200 */
1201 #define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to GPIO */
1202 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */
1203 #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */
1204 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
1205 /**
1206 * @}
1207 */
1208 #endif /* TIM14 */
1209
1210 #if defined(TIM_SMCR_OCCS)
1211 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1212 * @{
1213 */
1214 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1215 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1216 /**
1217 * @}
1218 */
1219 #endif /* TIM_SMCR_OCCS*/
1220
1221 /**
1222 * @}
1223 */
1224
1225 /* Exported macro ------------------------------------------------------------*/
1226 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1227 * @{
1228 */
1229
1230 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1231 * @{
1232 */
1233 /**
1234 * @brief Write a value in TIM register.
1235 * @param __INSTANCE__ TIM Instance
1236 * @param __REG__ Register to be written
1237 * @param __VALUE__ Value to be written in the register
1238 * @retval None
1239 */
1240 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1241
1242 /**
1243 * @brief Read a value in TIM register.
1244 * @param __INSTANCE__ TIM Instance
1245 * @param __REG__ Register to be read
1246 * @retval Register value
1247 */
1248 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1254 * @{
1255 */
1256 /**
1257 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1258 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1259 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1260 * to TIMx_CNT register bit 31)
1261 * @param __CNT__ Counter value
1262 * @retval UIF status bit
1263 */
1264 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1265 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1266
1267 /**
1268 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1269 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1270 * @param __TIMCLK__ timer input clock frequency (in Hz)
1271 * @param __CKD__ This parameter can be one of the following values:
1272 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1273 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1274 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1275 * @param __DT__ deadtime duration (in ns)
1276 * @retval DTG[0:7]
1277 */
1278 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1279 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1280 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
1281 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
1282 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
1283 0U)
1284
1285 /**
1286 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1287 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1288 * @param __TIMCLK__ timer input clock frequency (in Hz)
1289 * @param __CNTCLK__ counter clock frequency (in Hz)
1290 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1291 */
1292 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1293 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
1294
1295 /**
1296 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1297 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1298 * @param __TIMCLK__ timer input clock frequency (in Hz)
1299 * @param __PSC__ prescaler
1300 * @param __FREQ__ output signal frequency (in Hz)
1301 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1302 */
1303 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1304 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
1305
1306 /**
1307 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1308 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1309 * @param __TIMCLK__ timer input clock frequency (in Hz)
1310 * @param __PSC__ prescaler
1311 * @param __DELAY__ timer output compare active/inactive delay (in us)
1312 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1313 */
1314 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1315 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1316 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1317
1318 /**
1319 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1320 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1321 * @param __TIMCLK__ timer input clock frequency (in Hz)
1322 * @param __PSC__ prescaler
1323 * @param __DELAY__ timer output compare active/inactive delay (in us)
1324 * @param __PULSE__ pulse duration (in us)
1325 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1326 */
1327 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1328 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1329 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1330
1331 /**
1332 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1333 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1334 * @param __ICPSC__ This parameter can be one of the following values:
1335 * @arg @ref LL_TIM_ICPSC_DIV1
1336 * @arg @ref LL_TIM_ICPSC_DIV2
1337 * @arg @ref LL_TIM_ICPSC_DIV4
1338 * @arg @ref LL_TIM_ICPSC_DIV8
1339 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1340 */
1341 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1342 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1343
1344
1345 /**
1346 * @}
1347 */
1348
1349
1350 /**
1351 * @}
1352 */
1353
1354 /* Exported functions --------------------------------------------------------*/
1355 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1356 * @{
1357 */
1358
1359 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1360 * @{
1361 */
1362 /**
1363 * @brief Enable timer counter.
1364 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1365 * @param TIMx Timer instance
1366 * @retval None
1367 */
1368 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1369 {
1370 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1371 }
1372
1373 /**
1374 * @brief Disable timer counter.
1375 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1376 * @param TIMx Timer instance
1377 * @retval None
1378 */
1379 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1380 {
1381 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1382 }
1383
1384 /**
1385 * @brief Indicates whether the timer counter is enabled.
1386 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1387 * @param TIMx Timer instance
1388 * @retval State of bit (1 or 0).
1389 */
1390 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1391 {
1392 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
1393 }
1394
1395 /**
1396 * @brief Enable update event generation.
1397 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1398 * @param TIMx Timer instance
1399 * @retval None
1400 */
1401 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1402 {
1403 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1404 }
1405
1406 /**
1407 * @brief Disable update event generation.
1408 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1409 * @param TIMx Timer instance
1410 * @retval None
1411 */
1412 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1413 {
1414 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1415 }
1416
1417 /**
1418 * @brief Indicates whether update event generation is enabled.
1419 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1420 * @param TIMx Timer instance
1421 * @retval State of bit (1 or 0).
1422 */
1423 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1424 {
1425 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
1426 }
1427
1428 /**
1429 * @brief Set update event source
1430 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1431 * generate an update interrupt or DMA request if enabled:
1432 * - Counter overflow/underflow
1433 * - Setting the UG bit
1434 * - Update generation through the slave mode controller
1435 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1436 * overflow/underflow generates an update interrupt or DMA request if enabled.
1437 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1438 * @param TIMx Timer instance
1439 * @param UpdateSource This parameter can be one of the following values:
1440 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1441 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1442 * @retval None
1443 */
1444 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1445 {
1446 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1447 }
1448
1449 /**
1450 * @brief Get actual event update source
1451 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1452 * @param TIMx Timer instance
1453 * @retval Returned value can be one of the following values:
1454 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1455 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1456 */
1457 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1458 {
1459 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1460 }
1461
1462 /**
1463 * @brief Set one pulse mode (one shot v.s. repetitive).
1464 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1465 * @param TIMx Timer instance
1466 * @param OnePulseMode This parameter can be one of the following values:
1467 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1468 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1469 * @retval None
1470 */
1471 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1472 {
1473 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1474 }
1475
1476 /**
1477 * @brief Get actual one pulse mode.
1478 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1479 * @param TIMx Timer instance
1480 * @retval Returned value can be one of the following values:
1481 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1482 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1483 */
1484 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1485 {
1486 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1487 }
1488
1489 /**
1490 * @brief Set the timer counter counting mode.
1491 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1492 * check whether or not the counter mode selection feature is supported
1493 * by a timer instance.
1494 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1495 * CR1 CMS LL_TIM_SetCounterMode
1496 * @param TIMx Timer instance
1497 * @param CounterMode This parameter can be one of the following values:
1498 * @arg @ref LL_TIM_COUNTERMODE_UP
1499 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1500 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1501 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1502 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1503 * @retval None
1504 */
1505 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1506 {
1507 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
1508 }
1509
1510 /**
1511 * @brief Get actual counter mode.
1512 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1513 * check whether or not the counter mode selection feature is supported
1514 * by a timer instance.
1515 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1516 * CR1 CMS LL_TIM_GetCounterMode
1517 * @param TIMx Timer instance
1518 * @retval Returned value can be one of the following values:
1519 * @arg @ref LL_TIM_COUNTERMODE_UP
1520 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1521 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1522 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1523 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1524 */
1525 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1526 {
1527 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1528 }
1529
1530 /**
1531 * @brief Enable auto-reload (ARR) preload.
1532 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1533 * @param TIMx Timer instance
1534 * @retval None
1535 */
1536 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1537 {
1538 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1539 }
1540
1541 /**
1542 * @brief Disable auto-reload (ARR) preload.
1543 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1544 * @param TIMx Timer instance
1545 * @retval None
1546 */
1547 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1548 {
1549 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1550 }
1551
1552 /**
1553 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1554 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1555 * @param TIMx Timer instance
1556 * @retval State of bit (1 or 0).
1557 */
1558 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1559 {
1560 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
1561 }
1562
1563 /**
1564 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1565 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1566 * whether or not the clock division feature is supported by the timer
1567 * instance.
1568 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1569 * @param TIMx Timer instance
1570 * @param ClockDivision This parameter can be one of the following values:
1571 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1572 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1573 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1574 * @retval None
1575 */
1576 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1577 {
1578 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1579 }
1580
1581 /**
1582 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1583 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1584 * whether or not the clock division feature is supported by the timer
1585 * instance.
1586 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1587 * @param TIMx Timer instance
1588 * @retval Returned value can be one of the following values:
1589 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1590 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1591 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1592 */
1593 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1594 {
1595 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1596 }
1597
1598 /**
1599 * @brief Set the counter value.
1600 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1601 * whether or not a timer instance supports a 32 bits counter.
1602 * @rmtoll CNT CNT LL_TIM_SetCounter
1603 * @param TIMx Timer instance
1604 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1605 * @retval None
1606 */
1607 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1608 {
1609 WRITE_REG(TIMx->CNT, Counter);
1610 }
1611
1612 /**
1613 * @brief Get the counter value.
1614 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1615 * whether or not a timer instance supports a 32 bits counter.
1616 * @rmtoll CNT CNT LL_TIM_GetCounter
1617 * @param TIMx Timer instance
1618 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1619 */
1620 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1621 {
1622 return (uint32_t)(READ_REG(TIMx->CNT));
1623 }
1624
1625 /**
1626 * @brief Get the current direction of the counter
1627 * @rmtoll CR1 DIR LL_TIM_GetDirection
1628 * @param TIMx Timer instance
1629 * @retval Returned value can be one of the following values:
1630 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1631 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1632 */
1633 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1634 {
1635 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1636 }
1637
1638 /**
1639 * @brief Set the prescaler value.
1640 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1641 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1642 * prescaler ratio is taken into account at the next update event.
1643 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1644 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1645 * @param TIMx Timer instance
1646 * @param Prescaler between Min_Data=0 and Max_Data=65535
1647 * @retval None
1648 */
1649 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1650 {
1651 WRITE_REG(TIMx->PSC, Prescaler);
1652 }
1653
1654 /**
1655 * @brief Get the prescaler value.
1656 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1657 * @param TIMx Timer instance
1658 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1659 */
1660 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1661 {
1662 return (uint32_t)(READ_REG(TIMx->PSC));
1663 }
1664
1665 /**
1666 * @brief Set the auto-reload value.
1667 * @note The counter is blocked while the auto-reload value is null.
1668 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1669 * whether or not a timer instance supports a 32 bits counter.
1670 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1671 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1672 * @param TIMx Timer instance
1673 * @param AutoReload between Min_Data=0 and Max_Data=65535
1674 * @retval None
1675 */
1676 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1677 {
1678 WRITE_REG(TIMx->ARR, AutoReload);
1679 }
1680
1681 /**
1682 * @brief Get the auto-reload value.
1683 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1684 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1685 * whether or not a timer instance supports a 32 bits counter.
1686 * @param TIMx Timer instance
1687 * @retval Auto-reload value
1688 */
1689 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1690 {
1691 return (uint32_t)(READ_REG(TIMx->ARR));
1692 }
1693
1694 /**
1695 * @brief Set the repetition counter value.
1696 * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
1697 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1698 * whether or not a timer instance supports a repetition counter.
1699 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1700 * @param TIMx Timer instance
1701 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1702 * @retval None
1703 */
1704 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1705 {
1706 WRITE_REG(TIMx->RCR, RepetitionCounter);
1707 }
1708
1709 /**
1710 * @brief Get the repetition counter value.
1711 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1712 * whether or not a timer instance supports a repetition counter.
1713 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1714 * @param TIMx Timer instance
1715 * @retval Repetition counter value
1716 */
1717 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1718 {
1719 return (uint32_t)(READ_REG(TIMx->RCR));
1720 }
1721
1722 #if defined(TIM_CR1_UIFREMAP)
1723 /**
1724 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1725 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1726 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1727 * @param TIMx Timer instance
1728 * @retval None
1729 */
1730 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1731 {
1732 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1733 }
1734
1735 /**
1736 * @brief Disable update interrupt flag (UIF) remapping.
1737 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1738 * @param TIMx Timer instance
1739 * @retval None
1740 */
1741 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1742 {
1743 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1744 }
1745
1746 #endif /* TIM_CR1_UIFREMAP */
1747 /**
1748 * @}
1749 */
1750
1751 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1752 * @{
1753 */
1754 /**
1755 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1756 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1757 * they are updated only when a commutation event (COM) occurs.
1758 * @note Only on channels that have a complementary output.
1759 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1760 * whether or not a timer instance is able to generate a commutation event.
1761 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1762 * @param TIMx Timer instance
1763 * @retval None
1764 */
1765 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1766 {
1767 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1768 }
1769
1770 /**
1771 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1772 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1773 * whether or not a timer instance is able to generate a commutation event.
1774 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1775 * @param TIMx Timer instance
1776 * @retval None
1777 */
1778 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1779 {
1780 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1781 }
1782
1783 /**
1784 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1785 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1786 * whether or not a timer instance is able to generate a commutation event.
1787 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1788 * @param TIMx Timer instance
1789 * @param CCUpdateSource This parameter can be one of the following values:
1790 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1791 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1792 * @retval None
1793 */
1794 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1795 {
1796 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1797 }
1798
1799 /**
1800 * @brief Set the trigger of the capture/compare DMA request.
1801 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1802 * @param TIMx Timer instance
1803 * @param DMAReqTrigger This parameter can be one of the following values:
1804 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1805 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1806 * @retval None
1807 */
1808 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1809 {
1810 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1811 }
1812
1813 /**
1814 * @brief Get actual trigger of the capture/compare DMA request.
1815 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1816 * @param TIMx Timer instance
1817 * @retval Returned value can be one of the following values:
1818 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1819 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1820 */
1821 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1822 {
1823 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1824 }
1825
1826 /**
1827 * @brief Set the lock level to freeze the
1828 * configuration of several capture/compare parameters.
1829 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1830 * the lock mechanism is supported by a timer instance.
1831 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1832 * @param TIMx Timer instance
1833 * @param LockLevel This parameter can be one of the following values:
1834 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1835 * @arg @ref LL_TIM_LOCKLEVEL_1
1836 * @arg @ref LL_TIM_LOCKLEVEL_2
1837 * @arg @ref LL_TIM_LOCKLEVEL_3
1838 * @retval None
1839 */
1840 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1841 {
1842 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1843 }
1844
1845 /**
1846 * @brief Enable capture/compare channels.
1847 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1848 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1849 * CCER CC2E LL_TIM_CC_EnableChannel\n
1850 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1851 * CCER CC3E LL_TIM_CC_EnableChannel\n
1852 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1853 * CCER CC4E LL_TIM_CC_EnableChannel\n
1854 * CCER CC5E LL_TIM_CC_EnableChannel\n
1855 * CCER CC6E LL_TIM_CC_EnableChannel
1856 * @param TIMx Timer instance
1857 * @param Channels This parameter can be a combination of the following values:
1858 * @arg @ref LL_TIM_CHANNEL_CH1
1859 * @arg @ref LL_TIM_CHANNEL_CH1N
1860 * @arg @ref LL_TIM_CHANNEL_CH2
1861 * @arg @ref LL_TIM_CHANNEL_CH2N
1862 * @arg @ref LL_TIM_CHANNEL_CH3
1863 * @arg @ref LL_TIM_CHANNEL_CH3N
1864 * @arg @ref LL_TIM_CHANNEL_CH4
1865 * @arg @ref LL_TIM_CHANNEL_CH5
1866 * @arg @ref LL_TIM_CHANNEL_CH6
1867 * @note CH5 and CH6 channels are not available for all F3 devices
1868 * @retval None
1869 */
1870 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1871 {
1872 SET_BIT(TIMx->CCER, Channels);
1873 }
1874
1875 /**
1876 * @brief Disable capture/compare channels.
1877 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1878 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1879 * CCER CC2E LL_TIM_CC_DisableChannel\n
1880 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1881 * CCER CC3E LL_TIM_CC_DisableChannel\n
1882 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1883 * CCER CC4E LL_TIM_CC_DisableChannel\n
1884 * CCER CC5E LL_TIM_CC_DisableChannel\n
1885 * CCER CC6E LL_TIM_CC_DisableChannel
1886 * @param TIMx Timer instance
1887 * @param Channels This parameter can be a combination of the following values:
1888 * @arg @ref LL_TIM_CHANNEL_CH1
1889 * @arg @ref LL_TIM_CHANNEL_CH1N
1890 * @arg @ref LL_TIM_CHANNEL_CH2
1891 * @arg @ref LL_TIM_CHANNEL_CH2N
1892 * @arg @ref LL_TIM_CHANNEL_CH3
1893 * @arg @ref LL_TIM_CHANNEL_CH3N
1894 * @arg @ref LL_TIM_CHANNEL_CH4
1895 * @arg @ref LL_TIM_CHANNEL_CH5
1896 * @arg @ref LL_TIM_CHANNEL_CH6
1897 * @note CH5 and CH6 channels are not available for all F3 devices
1898 * @retval None
1899 */
1900 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1901 {
1902 CLEAR_BIT(TIMx->CCER, Channels);
1903 }
1904
1905 /**
1906 * @brief Indicate whether channel(s) is(are) enabled.
1907 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1908 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1909 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1910 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1911 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1912 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1913 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1914 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1915 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1916 * @param TIMx Timer instance
1917 * @param Channels This parameter can be a combination of the following values:
1918 * @arg @ref LL_TIM_CHANNEL_CH1
1919 * @arg @ref LL_TIM_CHANNEL_CH1N
1920 * @arg @ref LL_TIM_CHANNEL_CH2
1921 * @arg @ref LL_TIM_CHANNEL_CH2N
1922 * @arg @ref LL_TIM_CHANNEL_CH3
1923 * @arg @ref LL_TIM_CHANNEL_CH3N
1924 * @arg @ref LL_TIM_CHANNEL_CH4
1925 * @arg @ref LL_TIM_CHANNEL_CH5
1926 * @arg @ref LL_TIM_CHANNEL_CH6
1927 * @note CH5 and CH6 channels are not available for all F3 devices
1928 * @retval State of bit (1 or 0).
1929 */
1930 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1931 {
1932 return (READ_BIT(TIMx->CCER, Channels) == (Channels));
1933 }
1934
1935 /**
1936 * @}
1937 */
1938
1939 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1940 * @{
1941 */
1942 /**
1943 * @brief Configure an output channel.
1944 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1945 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1946 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1947 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1948 * @if STM32F334x8
1949 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1950 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1951 * @elseif STM32F303xC
1952 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1953 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1954 * @elseif STM32F302x8
1955 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1956 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1957 * @endif
1958 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1959 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1960 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1961 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1962 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1963 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1964 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1965 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1966 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1967 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1968 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1969 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1970 * @param TIMx Timer instance
1971 * @param Channel This parameter can be one of the following values:
1972 * @arg @ref LL_TIM_CHANNEL_CH1
1973 * @arg @ref LL_TIM_CHANNEL_CH2
1974 * @arg @ref LL_TIM_CHANNEL_CH3
1975 * @arg @ref LL_TIM_CHANNEL_CH4
1976 * @arg @ref LL_TIM_CHANNEL_CH5
1977 * @arg @ref LL_TIM_CHANNEL_CH6
1978 * @param Configuration This parameter must be a combination of all the following values:
1979 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1980 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1981 * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
1982 * @retval None
1983 */
1984 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1985 {
1986 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1987 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1988 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1989 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1990 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1991 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1992 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1993 }
1994
1995 /**
1996 * @brief Define the behavior of the output reference signal OCxREF from which
1997 * OCx and OCxN (when relevant) are derived.
1998 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1999 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2000 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2001 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2002 * @if STM32F334x8
2003 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2004 * CCMR3 OC6M LL_TIM_OC_SetMode
2005 * @elseif STM32F303xC
2006 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2007 * CCMR3 OC6M LL_TIM_OC_SetMode
2008 * @elseif STM32F302x8
2009 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2010 * CCMR3 OC6M LL_TIM_OC_SetMode
2011 * @endif
2012 * @param TIMx Timer instance
2013 * @param Channel This parameter can be one of the following values:
2014 * @arg @ref LL_TIM_CHANNEL_CH1
2015 * @arg @ref LL_TIM_CHANNEL_CH2
2016 * @arg @ref LL_TIM_CHANNEL_CH3
2017 * @arg @ref LL_TIM_CHANNEL_CH4
2018 * @arg @ref LL_TIM_CHANNEL_CH5
2019 * @arg @ref LL_TIM_CHANNEL_CH6
2020 * @param Mode This parameter can be one of the following values:
2021 * @arg @ref LL_TIM_OCMODE_FROZEN
2022 * @arg @ref LL_TIM_OCMODE_ACTIVE
2023 * @arg @ref LL_TIM_OCMODE_INACTIVE
2024 * @arg @ref LL_TIM_OCMODE_TOGGLE
2025 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2026 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2027 * @arg @ref LL_TIM_OCMODE_PWM1
2028 * @arg @ref LL_TIM_OCMODE_PWM2
2029 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2030 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2031 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2032 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2033 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2034 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2035 * @note The following OC modes are not available on all F3 devices :
2036 * - LL_TIM_OCMODE_RETRIG_OPM1
2037 * - LL_TIM_OCMODE_RETRIG_OPM2
2038 * - LL_TIM_OCMODE_COMBINED_PWM1
2039 * - LL_TIM_OCMODE_COMBINED_PWM2
2040 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
2041 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
2042 * @note CH5 and CH6 channels are not available for all F3 devices
2043 * @retval None
2044 */
2045 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2046 {
2047 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2048 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2049 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2050 }
2051
2052 /**
2053 * @brief Get the output compare mode of an output channel.
2054 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2055 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2056 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2057 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2058 * @if STM32F334x8
2059 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2060 * CCMR3 OC6M LL_TIM_OC_GetMode
2061 * @elseif STM32F303xC
2062 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2063 * CCMR3 OC6M LL_TIM_OC_GetMode
2064 * @elseif STM32F302x8
2065 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2066 * CCMR3 OC6M LL_TIM_OC_GetMode
2067 * @endif
2068 * @param TIMx Timer instance
2069 * @param Channel This parameter can be one of the following values:
2070 * @arg @ref LL_TIM_CHANNEL_CH1
2071 * @arg @ref LL_TIM_CHANNEL_CH2
2072 * @arg @ref LL_TIM_CHANNEL_CH3
2073 * @arg @ref LL_TIM_CHANNEL_CH4
2074 * @arg @ref LL_TIM_CHANNEL_CH5
2075 * @arg @ref LL_TIM_CHANNEL_CH6
2076 * @note The following OC modes are not available on all F3 devices :
2077 * - LL_TIM_OCMODE_RETRIG_OPM1
2078 * - LL_TIM_OCMODE_RETRIG_OPM2
2079 * - LL_TIM_OCMODE_COMBINED_PWM1
2080 * - LL_TIM_OCMODE_COMBINED_PWM2
2081 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
2082 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
2083 * @note CH5 and CH6 channels are not available for all F3 devices
2084 * @retval Returned value can be one of the following values:
2085 * @arg @ref LL_TIM_OCMODE_FROZEN
2086 * @arg @ref LL_TIM_OCMODE_ACTIVE
2087 * @arg @ref LL_TIM_OCMODE_INACTIVE
2088 * @arg @ref LL_TIM_OCMODE_TOGGLE
2089 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2090 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2091 * @arg @ref LL_TIM_OCMODE_PWM1
2092 * @arg @ref LL_TIM_OCMODE_PWM2
2093 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2094 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2095 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2096 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2097 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2098 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2099 */
2100 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2101 {
2102 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2103 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2104 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2105 }
2106
2107 /**
2108 * @brief Set the polarity of an output channel.
2109 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2110 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2111 * CCER CC2P LL_TIM_OC_SetPolarity\n
2112 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2113 * CCER CC3P LL_TIM_OC_SetPolarity\n
2114 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2115 * CCER CC4P LL_TIM_OC_SetPolarity\n
2116 * CCER CC5P LL_TIM_OC_SetPolarity\n
2117 * CCER CC6P LL_TIM_OC_SetPolarity
2118 * @param TIMx Timer instance
2119 * @param Channel This parameter can be one of the following values:
2120 * @arg @ref LL_TIM_CHANNEL_CH1
2121 * @arg @ref LL_TIM_CHANNEL_CH1N
2122 * @arg @ref LL_TIM_CHANNEL_CH2
2123 * @arg @ref LL_TIM_CHANNEL_CH2N
2124 * @arg @ref LL_TIM_CHANNEL_CH3
2125 * @arg @ref LL_TIM_CHANNEL_CH3N
2126 * @arg @ref LL_TIM_CHANNEL_CH4
2127 * @arg @ref LL_TIM_CHANNEL_CH5
2128 * @arg @ref LL_TIM_CHANNEL_CH6
2129 * @param Polarity This parameter can be one of the following values:
2130 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2131 * @arg @ref LL_TIM_OCPOLARITY_LOW
2132 * @note CH5 and CH6 channels are not available for all F3 devices
2133 * @retval None
2134 */
2135 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2136 {
2137 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2138 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2139 }
2140
2141 /**
2142 * @brief Get the polarity of an output channel.
2143 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2144 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2145 * CCER CC2P LL_TIM_OC_GetPolarity\n
2146 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2147 * CCER CC3P LL_TIM_OC_GetPolarity\n
2148 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2149 * CCER CC4P LL_TIM_OC_GetPolarity\n
2150 * CCER CC5P LL_TIM_OC_GetPolarity\n
2151 * CCER CC6P LL_TIM_OC_GetPolarity
2152 * @param TIMx Timer instance
2153 * @param Channel This parameter can be one of the following values:
2154 * @arg @ref LL_TIM_CHANNEL_CH1
2155 * @arg @ref LL_TIM_CHANNEL_CH1N
2156 * @arg @ref LL_TIM_CHANNEL_CH2
2157 * @arg @ref LL_TIM_CHANNEL_CH2N
2158 * @arg @ref LL_TIM_CHANNEL_CH3
2159 * @arg @ref LL_TIM_CHANNEL_CH3N
2160 * @arg @ref LL_TIM_CHANNEL_CH4
2161 * @arg @ref LL_TIM_CHANNEL_CH5
2162 * @arg @ref LL_TIM_CHANNEL_CH6
2163 * @note CH5 and CH6 channels are not available for all F3 devices
2164 * @retval Returned value can be one of the following values:
2165 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2166 * @arg @ref LL_TIM_OCPOLARITY_LOW
2167 */
2168 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2169 {
2170 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2171 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2172 }
2173
2174 /**
2175 * @brief Set the IDLE state of an output channel
2176 * @note This function is significant only for the timer instances
2177 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
2178 * can be used to check whether or not a timer instance provides
2179 * a break input.
2180 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2181 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2182 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2183 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2184 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2185 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2186 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2187 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2188 * CR2 OIS6 LL_TIM_OC_SetIdleState
2189 * @param TIMx Timer instance
2190 * @param Channel This parameter can be one of the following values:
2191 * @arg @ref LL_TIM_CHANNEL_CH1
2192 * @arg @ref LL_TIM_CHANNEL_CH1N
2193 * @arg @ref LL_TIM_CHANNEL_CH2
2194 * @arg @ref LL_TIM_CHANNEL_CH2N
2195 * @arg @ref LL_TIM_CHANNEL_CH3
2196 * @arg @ref LL_TIM_CHANNEL_CH3N
2197 * @arg @ref LL_TIM_CHANNEL_CH4
2198 * @arg @ref LL_TIM_CHANNEL_CH5
2199 * @arg @ref LL_TIM_CHANNEL_CH6
2200 * @param IdleState This parameter can be one of the following values:
2201 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2202 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2203 * @note CH5 and CH6 channels are not available for all F3 devices
2204 * @retval None
2205 */
2206 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2207 {
2208 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2209 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2210 }
2211
2212 /**
2213 * @brief Get the IDLE state of an output channel
2214 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2215 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2216 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2217 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2218 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2219 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2220 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2221 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2222 * CR2 OIS6 LL_TIM_OC_GetIdleState
2223 * @param TIMx Timer instance
2224 * @param Channel This parameter can be one of the following values:
2225 * @arg @ref LL_TIM_CHANNEL_CH1
2226 * @arg @ref LL_TIM_CHANNEL_CH1N
2227 * @arg @ref LL_TIM_CHANNEL_CH2
2228 * @arg @ref LL_TIM_CHANNEL_CH2N
2229 * @arg @ref LL_TIM_CHANNEL_CH3
2230 * @arg @ref LL_TIM_CHANNEL_CH3N
2231 * @arg @ref LL_TIM_CHANNEL_CH4
2232 * @arg @ref LL_TIM_CHANNEL_CH5
2233 * @arg @ref LL_TIM_CHANNEL_CH6
2234 * @note CH5 and CH6 channels are not available for all F3 devices
2235 * @retval Returned value can be one of the following values:
2236 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2237 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2238 */
2239 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2240 {
2241 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2242 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2243 }
2244
2245 /**
2246 * @brief Enable fast mode for the output channel.
2247 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2248 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2249 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2250 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2251 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2252 * @if STM32F334x8
2253 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2254 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2255 * @elseif STM32F303xC
2256 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2257 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2258 * @elseif STM32F302x8
2259 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2260 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2261 * @endif
2262 * @param TIMx Timer instance
2263 * @param Channel This parameter can be one of the following values:
2264 * @arg @ref LL_TIM_CHANNEL_CH1
2265 * @arg @ref LL_TIM_CHANNEL_CH2
2266 * @arg @ref LL_TIM_CHANNEL_CH3
2267 * @arg @ref LL_TIM_CHANNEL_CH4
2268 * @arg @ref LL_TIM_CHANNEL_CH5
2269 * @arg @ref LL_TIM_CHANNEL_CH6
2270 * @note OC5FE and OC6FE are not available for all F3 devices
2271 * @note CH5 and CH6 channels are not available for all F3 devices
2272 * @retval None
2273 */
2274 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2275 {
2276 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2277 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2278 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2279
2280 }
2281
2282 /**
2283 * @brief Disable fast mode for the output channel.
2284 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2285 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2286 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2287 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2288 * @if STM32F334x8
2289 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2290 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2291 * @elseif STM32F303xC
2292 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2293 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2294 * @elseif STM32F302x8
2295 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2296 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2297 * @endif
2298 * @param TIMx Timer instance
2299 * @param Channel This parameter can be one of the following values:
2300 * @arg @ref LL_TIM_CHANNEL_CH1
2301 * @arg @ref LL_TIM_CHANNEL_CH2
2302 * @arg @ref LL_TIM_CHANNEL_CH3
2303 * @arg @ref LL_TIM_CHANNEL_CH4
2304 * @arg @ref LL_TIM_CHANNEL_CH5
2305 * @arg @ref LL_TIM_CHANNEL_CH6
2306 * @note OC5FE and OC6FE are not available for all F3 devices
2307 * @note CH5 and CH6 channels are not available for all F3 devices
2308 * @retval None
2309 */
2310 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2311 {
2312 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2313 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2314 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2315
2316 }
2317
2318 /**
2319 * @brief Indicates whether fast mode is enabled for the output channel.
2320 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2321 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2322 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2323 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2324 * @if STM32F334x8
2325 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2326 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2327 * @elseif STM32F303xC
2328 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2329 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2330 * @elseif STM32F302x8
2331 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2332 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2333 * @endif
2334 * @param TIMx Timer instance
2335 * @param Channel This parameter can be one of the following values:
2336 * @arg @ref LL_TIM_CHANNEL_CH1
2337 * @arg @ref LL_TIM_CHANNEL_CH2
2338 * @arg @ref LL_TIM_CHANNEL_CH3
2339 * @arg @ref LL_TIM_CHANNEL_CH4
2340 * @arg @ref LL_TIM_CHANNEL_CH5
2341 * @arg @ref LL_TIM_CHANNEL_CH6
2342 * @note OC5FE and OC6FE are not available for all F3 devices
2343 * @note CH5 and CH6 channels are not available for all F3 devices
2344 * @retval State of bit (1 or 0).
2345 */
2346 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2347 {
2348 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2349 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2350 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2351 return (READ_BIT(*pReg, bitfield) == bitfield);
2352 }
2353
2354 /**
2355 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2356 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2357 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2358 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2359 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2360 * @if STM32F334x8
2361 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2362 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2363 * @elseif STM32F303xC
2364 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2365 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2366 * @elseif STM32F302x8
2367 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2368 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2369 * @endif
2370 * @param TIMx Timer instance
2371 * @param Channel This parameter can be one of the following values:
2372 * @arg @ref LL_TIM_CHANNEL_CH1
2373 * @arg @ref LL_TIM_CHANNEL_CH2
2374 * @arg @ref LL_TIM_CHANNEL_CH3
2375 * @arg @ref LL_TIM_CHANNEL_CH4
2376 * @arg @ref LL_TIM_CHANNEL_CH5
2377 * @arg @ref LL_TIM_CHANNEL_CH6
2378 * @note OC5PE and OC6PE are not available for all F3 devices
2379 * @note CH5 and CH6 channels are not available for all F3 devices
2380 * @retval None
2381 */
2382 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2383 {
2384 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2385 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2386 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2387 }
2388
2389 /**
2390 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2391 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2392 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2393 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2394 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2395 * @if STM32F334x8
2396 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2397 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2398 * @elseif STM32F303xC
2399 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2400 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2401 * @elseif STM32F302x8
2402 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2403 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2404 * @endif
2405 * @param TIMx Timer instance
2406 * @param Channel This parameter can be one of the following values:
2407 * @arg @ref LL_TIM_CHANNEL_CH1
2408 * @arg @ref LL_TIM_CHANNEL_CH2
2409 * @arg @ref LL_TIM_CHANNEL_CH3
2410 * @arg @ref LL_TIM_CHANNEL_CH4
2411 * @arg @ref LL_TIM_CHANNEL_CH5
2412 * @arg @ref LL_TIM_CHANNEL_CH6
2413 * @note OC5PE and OC6PE are not available for all F3 devices
2414 * @note CH5 and CH6 channels are not available for all F3 devices
2415 * @retval None
2416 */
2417 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2418 {
2419 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2420 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2421 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2422 }
2423
2424 /**
2425 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2426 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2427 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2428 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2429 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2430 * @if STM32F334x8
2431 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2432 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2433 * @elseif STM32F303xC
2434 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2435 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2436 * @elseif STM32F302x8
2437 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2438 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2439 * @endif
2440 * @param TIMx Timer instance
2441 * @param Channel This parameter can be one of the following values:
2442 * @arg @ref LL_TIM_CHANNEL_CH1
2443 * @arg @ref LL_TIM_CHANNEL_CH2
2444 * @arg @ref LL_TIM_CHANNEL_CH3
2445 * @arg @ref LL_TIM_CHANNEL_CH4
2446 * @arg @ref LL_TIM_CHANNEL_CH5
2447 * @arg @ref LL_TIM_CHANNEL_CH6
2448 * @note OC5PE and OC6PE are not available for all F3 devices
2449 * @note CH5 and CH6 channels are not available for all F3 devices
2450 * @retval State of bit (1 or 0).
2451 */
2452 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2453 {
2454 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2455 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2456 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2457 return (READ_BIT(*pReg, bitfield) == bitfield);
2458 }
2459
2460 /**
2461 * @brief Enable clearing the output channel on an external event.
2462 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2463 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2464 * or not a timer instance can clear the OCxREF signal on an external event.
2465 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2466 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2467 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2468 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2469 * @if STM32F334x8
2470 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2471 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2472 * @elseif STM32F303xC
2473 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2474 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2475 * @elseif STM32F302x8
2476 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2477 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2478 * @endif
2479 * @param TIMx Timer instance
2480 * @param Channel This parameter can be one of the following values:
2481 * @arg @ref LL_TIM_CHANNEL_CH1
2482 * @arg @ref LL_TIM_CHANNEL_CH2
2483 * @arg @ref LL_TIM_CHANNEL_CH3
2484 * @arg @ref LL_TIM_CHANNEL_CH4
2485 * @arg @ref LL_TIM_CHANNEL_CH5
2486 * @arg @ref LL_TIM_CHANNEL_CH6
2487 * @note OC5CE and OC6CE are not available for all F3 devices
2488 * @note CH5 and CH6 channels are not available for all F3 devices
2489 * @retval None
2490 */
2491 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2492 {
2493 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2494 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2495 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2496 }
2497
2498 /**
2499 * @brief Disable clearing the output channel on an external event.
2500 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2501 * or not a timer instance can clear the OCxREF signal on an external event.
2502 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2503 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2504 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2505 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2506 * @if STM32F334x8
2507 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2508 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2509 * @elseif STM32F303xC
2510 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2511 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2512 * @elseif STM32F302x8
2513 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2514 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2515 * @endif
2516 * @param TIMx Timer instance
2517 * @param Channel This parameter can be one of the following values:
2518 * @arg @ref LL_TIM_CHANNEL_CH1
2519 * @arg @ref LL_TIM_CHANNEL_CH2
2520 * @arg @ref LL_TIM_CHANNEL_CH3
2521 * @arg @ref LL_TIM_CHANNEL_CH4
2522 * @arg @ref LL_TIM_CHANNEL_CH5
2523 * @arg @ref LL_TIM_CHANNEL_CH6
2524 * @note OC5CE and OC6CE are not available for all F3 devices
2525 * @note CH5 and CH6 channels are not available for all F3 devices
2526 * @retval None
2527 */
2528 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2529 {
2530 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2531 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2532 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2533 }
2534
2535 /**
2536 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2537 * @note This function enables clearing the output channel on an external event.
2538 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2539 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2540 * or not a timer instance can clear the OCxREF signal on an external event.
2541 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2542 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2543 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2544 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2545 * @if STM32F334x8
2546 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2547 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2548 * @elseif STM32F303xC
2549 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2550 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2551 * @elseif STM32F302x8
2552 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2553 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2554 * @endif
2555 * @param TIMx Timer instance
2556 * @param Channel This parameter can be one of the following values:
2557 * @arg @ref LL_TIM_CHANNEL_CH1
2558 * @arg @ref LL_TIM_CHANNEL_CH2
2559 * @arg @ref LL_TIM_CHANNEL_CH3
2560 * @arg @ref LL_TIM_CHANNEL_CH4
2561 * @arg @ref LL_TIM_CHANNEL_CH5
2562 * @arg @ref LL_TIM_CHANNEL_CH6
2563 * @note OC5CE and OC6CE are not available for all F3 devices
2564 * @note CH5 and CH6 channels are not available for all F3 devices
2565 * @retval State of bit (1 or 0).
2566 */
2567 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2568 {
2569 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2570 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2571 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2572 return (READ_BIT(*pReg, bitfield) == bitfield);
2573 }
2574
2575 /**
2576 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
2577 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2578 * dead-time insertion feature is supported by a timer instance.
2579 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2580 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2581 * @param TIMx Timer instance
2582 * @param DeadTime between Min_Data=0 and Max_Data=255
2583 * @retval None
2584 */
2585 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2586 {
2587 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2588 }
2589
2590 /**
2591 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2592 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2593 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2594 * whether or not a timer instance supports a 32 bits counter.
2595 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2596 * output channel 1 is supported by a timer instance.
2597 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2598 * @param TIMx Timer instance
2599 * @param CompareValue between Min_Data=0 and Max_Data=65535
2600 * @retval None
2601 */
2602 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2603 {
2604 WRITE_REG(TIMx->CCR1, CompareValue);
2605 }
2606
2607 /**
2608 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2609 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2610 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2611 * whether or not a timer instance supports a 32 bits counter.
2612 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2613 * output channel 2 is supported by a timer instance.
2614 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2615 * @param TIMx Timer instance
2616 * @param CompareValue between Min_Data=0 and Max_Data=65535
2617 * @retval None
2618 */
2619 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2620 {
2621 WRITE_REG(TIMx->CCR2, CompareValue);
2622 }
2623
2624 /**
2625 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2626 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2627 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2628 * whether or not a timer instance supports a 32 bits counter.
2629 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2630 * output channel is supported by a timer instance.
2631 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2632 * @param TIMx Timer instance
2633 * @param CompareValue between Min_Data=0 and Max_Data=65535
2634 * @retval None
2635 */
2636 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2637 {
2638 WRITE_REG(TIMx->CCR3, CompareValue);
2639 }
2640
2641 /**
2642 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2643 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2644 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2645 * whether or not a timer instance supports a 32 bits counter.
2646 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2647 * output channel 4 is supported by a timer instance.
2648 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2649 * @param TIMx Timer instance
2650 * @param CompareValue between Min_Data=0 and Max_Data=65535
2651 * @retval None
2652 */
2653 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2654 {
2655 WRITE_REG(TIMx->CCR4, CompareValue);
2656 }
2657
2658 #if defined(TIM_CCR5_CCR5)
2659 /**
2660 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2661 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2662 * output channel 5 is supported by a timer instance.
2663 * @if STM32F334x8
2664 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2665 * @elseif STM32F303xC
2666 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2667 * @elseif STM32F302x8
2668 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2669 * @endif
2670 * @param TIMx Timer instance
2671 * @param CompareValue between Min_Data=0 and Max_Data=65535
2672 * @note CH5 channel is not available for all F3 devices
2673 * @retval None
2674 */
2675 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2676 {
2677 WRITE_REG(TIMx->CCR5, CompareValue);
2678 }
2679
2680 #endif /* TIM_CCR5_CCR5 */
2681 #if defined(TIM_CCR6_CCR6)
2682 /**
2683 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2684 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2685 * output channel 6 is supported by a timer instance.
2686 * @if STM32F344x8
2687 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2688 * @elseif STM32F303xC
2689 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2690 * @elseif STM32F302x8
2691 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2692 * @endif
2693 * @param TIMx Timer instance
2694 * @param CompareValue between Min_Data=0 and Max_Data=65535
2695 * @note CH6 channel is not available for all F3 devices
2696 * @retval None
2697 */
2698 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2699 {
2700 WRITE_REG(TIMx->CCR6, CompareValue);
2701 }
2702
2703 #endif /* TIM_CCR6_CCR6 */
2704 /**
2705 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2706 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2707 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2708 * whether or not a timer instance supports a 32 bits counter.
2709 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2710 * output channel 1 is supported by a timer instance.
2711 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2712 * @param TIMx Timer instance
2713 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2714 */
2715 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2716 {
2717 return (uint32_t)(READ_REG(TIMx->CCR1));
2718 }
2719
2720 /**
2721 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2722 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2723 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2724 * whether or not a timer instance supports a 32 bits counter.
2725 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2726 * output channel 2 is supported by a timer instance.
2727 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2728 * @param TIMx Timer instance
2729 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2730 */
2731 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2732 {
2733 return (uint32_t)(READ_REG(TIMx->CCR2));
2734 }
2735
2736 /**
2737 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2738 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2739 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2740 * whether or not a timer instance supports a 32 bits counter.
2741 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2742 * output channel 3 is supported by a timer instance.
2743 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2744 * @param TIMx Timer instance
2745 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2746 */
2747 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2748 {
2749 return (uint32_t)(READ_REG(TIMx->CCR3));
2750 }
2751
2752 /**
2753 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2754 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2755 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2756 * whether or not a timer instance supports a 32 bits counter.
2757 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2758 * output channel 4 is supported by a timer instance.
2759 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2760 * @param TIMx Timer instance
2761 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2762 */
2763 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2764 {
2765 return (uint32_t)(READ_REG(TIMx->CCR4));
2766 }
2767
2768 #if defined(TIM_CCR5_CCR5)
2769 /**
2770 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2771 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2772 * output channel 5 is supported by a timer instance.
2773 * @if STM32F334x8
2774 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2775 * @elseif STM32F303xC
2776 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2777 * @elseif STM32F302x8
2778 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2779 * @endif
2780 * @param TIMx Timer instance
2781 * @note CH5 channel is not available for all F3 devices
2782 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2783 */
2784 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2785 {
2786 return (uint32_t)(READ_REG(TIMx->CCR5));
2787 }
2788
2789 #endif /* TIM_CCR5_CCR5 */
2790 #if defined(TIM_CCR6_CCR6)
2791 /**
2792 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2793 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2794 * output channel 6 is supported by a timer instance.
2795 * @if STM32F334x8
2796 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2797 * @elseif STM32F303xC
2798 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2799 * @elseif STM32F302x8
2800 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2801 * @endif
2802 * @param TIMx Timer instance
2803 * @note CH6 channel is not available for all F3 devices
2804 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2805 */
2806 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2807 {
2808 return (uint32_t)(READ_REG(TIMx->CCR6));
2809 }
2810
2811 #endif /* TIM_CCR6_CCR6 */
2812 #if defined(TIM_CCR5_CCR5)
2813 /**
2814 * @brief Select on which reference signal the OC5REF is combined to.
2815 * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2816 * whether or not a timer instance supports the combined 3-phase PWM mode.
2817 * @if STM32F334x8
2818 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2819 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2820 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2821 * @elseif STM32F303xC
2822 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2823 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2824 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2825 * @elseif STM32F302x8
2826 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2827 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2828 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2829 * @endif
2830 * @param TIMx Timer instance
2831 * @param GroupCH5 This parameter can be one of the following values:
2832 * @arg @ref LL_TIM_GROUPCH5_NONE
2833 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2834 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2835 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2836 * @note CH5 channel is not available for all F3 devices
2837 * @retval None
2838 */
2839 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2840 {
2841 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
2842 }
2843
2844 #endif /* TIM_CCR5_CCR5 */
2845 /**
2846 * @}
2847 */
2848
2849 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2850 * @{
2851 */
2852 /**
2853 * @brief Configure input channel.
2854 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2855 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2856 * CCMR1 IC1F LL_TIM_IC_Config\n
2857 * CCMR1 CC2S LL_TIM_IC_Config\n
2858 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2859 * CCMR1 IC2F LL_TIM_IC_Config\n
2860 * CCMR2 CC3S LL_TIM_IC_Config\n
2861 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2862 * CCMR2 IC3F LL_TIM_IC_Config\n
2863 * CCMR2 CC4S LL_TIM_IC_Config\n
2864 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2865 * CCMR2 IC4F LL_TIM_IC_Config\n
2866 * CCER CC1P LL_TIM_IC_Config\n
2867 * CCER CC1NP LL_TIM_IC_Config\n
2868 * CCER CC2P LL_TIM_IC_Config\n
2869 * CCER CC2NP LL_TIM_IC_Config\n
2870 * CCER CC3P LL_TIM_IC_Config\n
2871 * CCER CC3NP LL_TIM_IC_Config\n
2872 * CCER CC4P LL_TIM_IC_Config\n
2873 * CCER CC4NP LL_TIM_IC_Config
2874 * @param TIMx Timer instance
2875 * @param Channel This parameter can be one of the following values:
2876 * @arg @ref LL_TIM_CHANNEL_CH1
2877 * @arg @ref LL_TIM_CHANNEL_CH2
2878 * @arg @ref LL_TIM_CHANNEL_CH3
2879 * @arg @ref LL_TIM_CHANNEL_CH4
2880 * @param Configuration This parameter must be a combination of all the following values:
2881 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2882 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2883 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2884 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2885 * @retval None
2886 */
2887 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2888 {
2889 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2890 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2891 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2892 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2893 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2894 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2895 }
2896
2897 /**
2898 * @brief Set the active input.
2899 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2900 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2901 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2902 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2903 * @param TIMx Timer instance
2904 * @param Channel This parameter can be one of the following values:
2905 * @arg @ref LL_TIM_CHANNEL_CH1
2906 * @arg @ref LL_TIM_CHANNEL_CH2
2907 * @arg @ref LL_TIM_CHANNEL_CH3
2908 * @arg @ref LL_TIM_CHANNEL_CH4
2909 * @param ICActiveInput This parameter can be one of the following values:
2910 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2911 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2912 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2913 * @retval None
2914 */
2915 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2916 {
2917 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2918 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2919 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2920 }
2921
2922 /**
2923 * @brief Get the current active input.
2924 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2925 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2926 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2927 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2928 * @param TIMx Timer instance
2929 * @param Channel This parameter can be one of the following values:
2930 * @arg @ref LL_TIM_CHANNEL_CH1
2931 * @arg @ref LL_TIM_CHANNEL_CH2
2932 * @arg @ref LL_TIM_CHANNEL_CH3
2933 * @arg @ref LL_TIM_CHANNEL_CH4
2934 * @retval Returned value can be one of the following values:
2935 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2936 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2937 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2938 */
2939 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2940 {
2941 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2942 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2943 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2944 }
2945
2946 /**
2947 * @brief Set the prescaler of input channel.
2948 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2949 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2950 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2951 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2952 * @param TIMx Timer instance
2953 * @param Channel This parameter can be one of the following values:
2954 * @arg @ref LL_TIM_CHANNEL_CH1
2955 * @arg @ref LL_TIM_CHANNEL_CH2
2956 * @arg @ref LL_TIM_CHANNEL_CH3
2957 * @arg @ref LL_TIM_CHANNEL_CH4
2958 * @param ICPrescaler This parameter can be one of the following values:
2959 * @arg @ref LL_TIM_ICPSC_DIV1
2960 * @arg @ref LL_TIM_ICPSC_DIV2
2961 * @arg @ref LL_TIM_ICPSC_DIV4
2962 * @arg @ref LL_TIM_ICPSC_DIV8
2963 * @retval None
2964 */
2965 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2966 {
2967 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2968 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2969 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2970 }
2971
2972 /**
2973 * @brief Get the current prescaler value acting on an input channel.
2974 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2975 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2976 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2977 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2978 * @param TIMx Timer instance
2979 * @param Channel This parameter can be one of the following values:
2980 * @arg @ref LL_TIM_CHANNEL_CH1
2981 * @arg @ref LL_TIM_CHANNEL_CH2
2982 * @arg @ref LL_TIM_CHANNEL_CH3
2983 * @arg @ref LL_TIM_CHANNEL_CH4
2984 * @retval Returned value can be one of the following values:
2985 * @arg @ref LL_TIM_ICPSC_DIV1
2986 * @arg @ref LL_TIM_ICPSC_DIV2
2987 * @arg @ref LL_TIM_ICPSC_DIV4
2988 * @arg @ref LL_TIM_ICPSC_DIV8
2989 */
2990 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2991 {
2992 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2993 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2994 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2995 }
2996
2997 /**
2998 * @brief Set the input filter duration.
2999 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3000 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3001 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3002 * CCMR2 IC4F LL_TIM_IC_SetFilter
3003 * @param TIMx Timer instance
3004 * @param Channel This parameter can be one of the following values:
3005 * @arg @ref LL_TIM_CHANNEL_CH1
3006 * @arg @ref LL_TIM_CHANNEL_CH2
3007 * @arg @ref LL_TIM_CHANNEL_CH3
3008 * @arg @ref LL_TIM_CHANNEL_CH4
3009 * @param ICFilter This parameter can be one of the following values:
3010 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3011 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3012 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3013 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3014 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3015 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3016 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3017 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3018 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3019 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3020 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3021 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3022 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3023 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3024 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3025 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3026 * @retval None
3027 */
3028 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3029 {
3030 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3031 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3032 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3033 }
3034
3035 /**
3036 * @brief Get the input filter duration.
3037 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3038 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3039 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3040 * CCMR2 IC4F LL_TIM_IC_GetFilter
3041 * @param TIMx Timer instance
3042 * @param Channel This parameter can be one of the following values:
3043 * @arg @ref LL_TIM_CHANNEL_CH1
3044 * @arg @ref LL_TIM_CHANNEL_CH2
3045 * @arg @ref LL_TIM_CHANNEL_CH3
3046 * @arg @ref LL_TIM_CHANNEL_CH4
3047 * @retval Returned value can be one of the following values:
3048 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3049 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3050 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3051 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3052 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3053 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3054 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3055 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3056 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3057 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3058 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3059 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3060 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3061 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3062 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3063 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3064 */
3065 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
3066 {
3067 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3068 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3069 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3070 }
3071
3072 /**
3073 * @brief Set the input channel polarity.
3074 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3075 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3076 * CCER CC2P LL_TIM_IC_SetPolarity\n
3077 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3078 * CCER CC3P LL_TIM_IC_SetPolarity\n
3079 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3080 * CCER CC4P LL_TIM_IC_SetPolarity\n
3081 * CCER CC4NP LL_TIM_IC_SetPolarity
3082 * @param TIMx Timer instance
3083 * @param Channel This parameter can be one of the following values:
3084 * @arg @ref LL_TIM_CHANNEL_CH1
3085 * @arg @ref LL_TIM_CHANNEL_CH2
3086 * @arg @ref LL_TIM_CHANNEL_CH3
3087 * @arg @ref LL_TIM_CHANNEL_CH4
3088 * @param ICPolarity This parameter can be one of the following values:
3089 * @arg @ref LL_TIM_IC_POLARITY_RISING
3090 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3091 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3092 * @retval None
3093 */
3094 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3095 {
3096 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3097 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3098 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3099 }
3100
3101 /**
3102 * @brief Get the current input channel polarity.
3103 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3104 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3105 * CCER CC2P LL_TIM_IC_GetPolarity\n
3106 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3107 * CCER CC3P LL_TIM_IC_GetPolarity\n
3108 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3109 * CCER CC4P LL_TIM_IC_GetPolarity\n
3110 * CCER CC4NP LL_TIM_IC_GetPolarity
3111 * @param TIMx Timer instance
3112 * @param Channel This parameter can be one of the following values:
3113 * @arg @ref LL_TIM_CHANNEL_CH1
3114 * @arg @ref LL_TIM_CHANNEL_CH2
3115 * @arg @ref LL_TIM_CHANNEL_CH3
3116 * @arg @ref LL_TIM_CHANNEL_CH4
3117 * @retval Returned value can be one of the following values:
3118 * @arg @ref LL_TIM_IC_POLARITY_RISING
3119 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3120 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3121 */
3122 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
3123 {
3124 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3125 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3126 SHIFT_TAB_CCxP[iChannel]);
3127 }
3128
3129 /**
3130 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3131 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3132 * a timer instance provides an XOR input.
3133 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3134 * @param TIMx Timer instance
3135 * @retval None
3136 */
3137 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3138 {
3139 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3140 }
3141
3142 /**
3143 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3144 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3145 * a timer instance provides an XOR input.
3146 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3147 * @param TIMx Timer instance
3148 * @retval None
3149 */
3150 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3151 {
3152 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3153 }
3154
3155 /**
3156 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3157 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3158 * a timer instance provides an XOR input.
3159 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3160 * @param TIMx Timer instance
3161 * @retval State of bit (1 or 0).
3162 */
3163 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3164 {
3165 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
3166 }
3167
3168 /**
3169 * @brief Get captured value for input channel 1.
3170 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3171 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3172 * whether or not a timer instance supports a 32 bits counter.
3173 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3174 * input channel 1 is supported by a timer instance.
3175 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3176 * @param TIMx Timer instance
3177 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3178 */
3179 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3180 {
3181 return (uint32_t)(READ_REG(TIMx->CCR1));
3182 }
3183
3184 /**
3185 * @brief Get captured value for input channel 2.
3186 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3187 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3188 * whether or not a timer instance supports a 32 bits counter.
3189 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3190 * input channel 2 is supported by a timer instance.
3191 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3192 * @param TIMx Timer instance
3193 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3194 */
3195 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3196 {
3197 return (uint32_t)(READ_REG(TIMx->CCR2));
3198 }
3199
3200 /**
3201 * @brief Get captured value for input channel 3.
3202 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3203 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3204 * whether or not a timer instance supports a 32 bits counter.
3205 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3206 * input channel 3 is supported by a timer instance.
3207 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3208 * @param TIMx Timer instance
3209 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3210 */
3211 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3212 {
3213 return (uint32_t)(READ_REG(TIMx->CCR3));
3214 }
3215
3216 /**
3217 * @brief Get captured value for input channel 4.
3218 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3219 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3220 * whether or not a timer instance supports a 32 bits counter.
3221 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3222 * input channel 4 is supported by a timer instance.
3223 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3224 * @param TIMx Timer instance
3225 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3226 */
3227 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3228 {
3229 return (uint32_t)(READ_REG(TIMx->CCR4));
3230 }
3231
3232 /**
3233 * @}
3234 */
3235
3236 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3237 * @{
3238 */
3239 /**
3240 * @brief Enable external clock mode 2.
3241 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3242 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3243 * whether or not a timer instance supports external clock mode2.
3244 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3245 * @param TIMx Timer instance
3246 * @retval None
3247 */
3248 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3249 {
3250 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3251 }
3252
3253 /**
3254 * @brief Disable external clock mode 2.
3255 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3256 * whether or not a timer instance supports external clock mode2.
3257 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3258 * @param TIMx Timer instance
3259 * @retval None
3260 */
3261 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3262 {
3263 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3264 }
3265
3266 /**
3267 * @brief Indicate whether external clock mode 2 is enabled.
3268 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3269 * whether or not a timer instance supports external clock mode2.
3270 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3271 * @param TIMx Timer instance
3272 * @retval State of bit (1 or 0).
3273 */
3274 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3275 {
3276 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
3277 }
3278
3279 /**
3280 * @brief Set the clock source of the counter clock.
3281 * @note when selected clock source is external clock mode 1, the timer input
3282 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3283 * function. This timer input must be configured by calling
3284 * the @ref LL_TIM_IC_Config() function.
3285 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3286 * whether or not a timer instance supports external clock mode1.
3287 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3288 * whether or not a timer instance supports external clock mode2.
3289 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3290 * SMCR ECE LL_TIM_SetClockSource
3291 * @param TIMx Timer instance
3292 * @param ClockSource This parameter can be one of the following values:
3293 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3294 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3295 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3296 * @retval None
3297 */
3298 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3299 {
3300 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3301 }
3302
3303 /**
3304 * @brief Set the encoder interface mode.
3305 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3306 * whether or not a timer instance supports the encoder mode.
3307 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3308 * @param TIMx Timer instance
3309 * @param EncoderMode This parameter can be one of the following values:
3310 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3311 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3312 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3313 * @retval None
3314 */
3315 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3316 {
3317 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3318 }
3319
3320 /**
3321 * @}
3322 */
3323
3324 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3325 * @{
3326 */
3327 /**
3328 * @brief Set the trigger output (TRGO) used for timer synchronization .
3329 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3330 * whether or not a timer instance can operate as a master timer.
3331 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3332 * @param TIMx Timer instance
3333 * @param TimerSynchronization This parameter can be one of the following values:
3334 * @arg @ref LL_TIM_TRGO_RESET
3335 * @arg @ref LL_TIM_TRGO_ENABLE
3336 * @arg @ref LL_TIM_TRGO_UPDATE
3337 * @arg @ref LL_TIM_TRGO_CC1IF
3338 * @arg @ref LL_TIM_TRGO_OC1REF
3339 * @arg @ref LL_TIM_TRGO_OC2REF
3340 * @arg @ref LL_TIM_TRGO_OC3REF
3341 * @arg @ref LL_TIM_TRGO_OC4REF
3342 * @retval None
3343 */
3344 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3345 {
3346 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3347 }
3348
3349 #if defined(TIM_CR2_MMS2)
3350 /**
3351 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3352 * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3353 * whether or not a timer instance can be used for ADC synchronization.
3354 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3355 * @param TIMx Timer Instance
3356 * @param ADCSynchronization This parameter can be one of the following values:
3357 * @arg @ref LL_TIM_TRGO2_RESET
3358 * @arg @ref LL_TIM_TRGO2_ENABLE
3359 * @arg @ref LL_TIM_TRGO2_UPDATE
3360 * @arg @ref LL_TIM_TRGO2_CC1F
3361 * @arg @ref LL_TIM_TRGO2_OC1
3362 * @arg @ref LL_TIM_TRGO2_OC2
3363 * @arg @ref LL_TIM_TRGO2_OC3
3364 * @arg @ref LL_TIM_TRGO2_OC4
3365 * @arg @ref LL_TIM_TRGO2_OC5
3366 * @arg @ref LL_TIM_TRGO2_OC6
3367 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3368 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3369 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3370 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3371 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3372 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3373 * @note OC5 and OC6 are not available for all F3 devices
3374 * @retval None
3375 */
3376 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3377 {
3378 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3379 }
3380
3381 #endif /* TIM_CR2_MMS2 */
3382 /**
3383 * @brief Set the synchronization mode of a slave timer.
3384 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3385 * a timer instance can operate as a slave timer.
3386 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3387 * @param TIMx Timer instance
3388 * @param SlaveMode This parameter can be one of the following values:
3389 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3390 * @arg @ref LL_TIM_SLAVEMODE_RESET
3391 * @arg @ref LL_TIM_SLAVEMODE_GATED
3392 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3393 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3394 * @retval None
3395 */
3396 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3397 {
3398 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3399 }
3400
3401 /**
3402 * @brief Set the selects the trigger input to be used to synchronize the counter.
3403 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3404 * a timer instance can operate as a slave timer.
3405 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3406 * @param TIMx Timer instance
3407 * @param TriggerInput This parameter can be one of the following values:
3408 * @arg @ref LL_TIM_TS_ITR0
3409 * @arg @ref LL_TIM_TS_ITR1
3410 * @arg @ref LL_TIM_TS_ITR2
3411 * @arg @ref LL_TIM_TS_ITR3
3412 * @arg @ref LL_TIM_TS_TI1F_ED
3413 * @arg @ref LL_TIM_TS_TI1FP1
3414 * @arg @ref LL_TIM_TS_TI2FP2
3415 * @arg @ref LL_TIM_TS_ETRF
3416 * @retval None
3417 */
3418 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3419 {
3420 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3421 }
3422
3423 /**
3424 * @brief Enable the Master/Slave mode.
3425 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3426 * a timer instance can operate as a slave timer.
3427 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3428 * @param TIMx Timer instance
3429 * @retval None
3430 */
3431 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3432 {
3433 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3434 }
3435
3436 /**
3437 * @brief Disable the Master/Slave mode.
3438 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3439 * a timer instance can operate as a slave timer.
3440 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3441 * @param TIMx Timer instance
3442 * @retval None
3443 */
3444 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3445 {
3446 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3447 }
3448
3449 /**
3450 * @brief Indicates whether the Master/Slave mode is enabled.
3451 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3452 * a timer instance can operate as a slave timer.
3453 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3454 * @param TIMx Timer instance
3455 * @retval State of bit (1 or 0).
3456 */
3457 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3458 {
3459 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
3460 }
3461
3462 /**
3463 * @brief Configure the external trigger (ETR) input.
3464 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3465 * a timer instance provides an external trigger input.
3466 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3467 * SMCR ETPS LL_TIM_ConfigETR\n
3468 * SMCR ETF LL_TIM_ConfigETR
3469 * @param TIMx Timer instance
3470 * @param ETRPolarity This parameter can be one of the following values:
3471 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3472 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3473 * @param ETRPrescaler This parameter can be one of the following values:
3474 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3475 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3476 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3477 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3478 * @param ETRFilter This parameter can be one of the following values:
3479 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3480 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3481 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3482 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3483 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3484 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3485 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3486 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3487 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3488 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3489 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3490 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3491 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3492 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3493 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3494 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3495 * @retval None
3496 */
3497 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3498 uint32_t ETRFilter)
3499 {
3500 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3501 }
3502
3503 /**
3504 * @}
3505 */
3506
3507 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3508 * @{
3509 */
3510 /**
3511 * @brief Enable the break function.
3512 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3513 * a timer instance provides a break input.
3514 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3515 * @param TIMx Timer instance
3516 * @retval None
3517 */
3518 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3519 {
3520 __IO uint32_t tmpreg;
3521
3522 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3523
3524 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3525 tmpreg = READ_REG(TIMx->BDTR);
3526 (void)(tmpreg);
3527 }
3528
3529 /**
3530 * @brief Disable the break function.
3531 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3532 * @param TIMx Timer instance
3533 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3534 * a timer instance provides a break input.
3535 * @retval None
3536 */
3537 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3538 {
3539 __IO uint32_t tmpreg;
3540
3541 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3542
3543 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3544 tmpreg = READ_REG(TIMx->BDTR);
3545 (void)(tmpreg);
3546 }
3547
3548 #if defined(TIM_BDTR_BKF)
3549 /**
3550 * @brief Configure the break input.
3551 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3552 * a timer instance provides a break input.
3553 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3554 * BDTR BKF LL_TIM_ConfigBRK
3555 * @param TIMx Timer instance
3556 * @param BreakPolarity This parameter can be one of the following values:
3557 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3558 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3559 * @param BreakFilter This parameter can be one of the following values:
3560 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3561 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3562 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3563 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3564 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3565 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3566 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3567 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3568 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3569 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3570 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3571 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3572 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3573 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3574 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3575 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3576 * @retval None
3577 */
3578 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
3579 {
3580 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3581 }
3582
3583 #else
3584 /**
3585 * @brief Configure the break input.
3586 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3587 * a timer instance provides a break input.
3588 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
3589 * @param TIMx Timer instance
3590 * @param BreakPolarity This parameter can be one of the following values:
3591 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3592 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3593 * @retval None
3594 */
3595 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
3596 {
3597 __IO uint32_t tmpreg;
3598
3599 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
3600
3601 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3602 tmpreg = READ_REG(TIMx->BDTR);
3603 (void)(tmpreg);
3604 }
3605
3606 #endif /* TIM_BDTR_BKF */
3607 #if defined(TIM_BDTR_BK2E)
3608 /**
3609 * @brief Enable the break 2 function.
3610 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3611 * a timer instance provides a second break input.
3612 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3613 * @param TIMx Timer instance
3614 * @retval None
3615 */
3616 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3617 {
3618 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3619 }
3620
3621 /**
3622 * @brief Disable the break 2 function.
3623 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3624 * a timer instance provides a second break input.
3625 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3626 * @param TIMx Timer instance
3627 * @retval None
3628 */
3629 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3630 {
3631 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3632 }
3633
3634 /**
3635 * @brief Configure the break 2 input.
3636 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3637 * a timer instance provides a second break input.
3638 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3639 * BDTR BK2F LL_TIM_ConfigBRK2
3640 * @param TIMx Timer instance
3641 * @param Break2Polarity This parameter can be one of the following values:
3642 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3643 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3644 * @param Break2Filter This parameter can be one of the following values:
3645 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3646 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3647 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3648 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3649 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3650 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3651 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3652 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3653 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3654 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3655 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3656 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3657 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3658 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3659 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3660 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3661 * @retval None
3662 */
3663 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3664 {
3665 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3666 }
3667
3668 #endif /* TIM_BDTR_BK2E */
3669 /**
3670 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3671 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3672 * a timer instance provides a break input.
3673 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3674 * BDTR OSSR LL_TIM_SetOffStates
3675 * @param TIMx Timer instance
3676 * @param OffStateIdle This parameter can be one of the following values:
3677 * @arg @ref LL_TIM_OSSI_DISABLE
3678 * @arg @ref LL_TIM_OSSI_ENABLE
3679 * @param OffStateRun This parameter can be one of the following values:
3680 * @arg @ref LL_TIM_OSSR_DISABLE
3681 * @arg @ref LL_TIM_OSSR_ENABLE
3682 * @retval None
3683 */
3684 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3685 {
3686 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3687 }
3688
3689 /**
3690 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3691 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3692 * a timer instance provides a break input.
3693 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3694 * @param TIMx Timer instance
3695 * @retval None
3696 */
3697 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3698 {
3699 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3700 }
3701
3702 /**
3703 * @brief Disable automatic output (MOE can be set only by software).
3704 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3705 * a timer instance provides a break input.
3706 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3707 * @param TIMx Timer instance
3708 * @retval None
3709 */
3710 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3711 {
3712 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3713 }
3714
3715 /**
3716 * @brief Indicate whether automatic output is enabled.
3717 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3718 * a timer instance provides a break input.
3719 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3720 * @param TIMx Timer instance
3721 * @retval State of bit (1 or 0).
3722 */
3723 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3724 {
3725 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
3726 }
3727
3728 /**
3729 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3730 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3731 * software and is reset in case of break or break2 event
3732 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3733 * a timer instance provides a break input.
3734 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3735 * @param TIMx Timer instance
3736 * @retval None
3737 */
3738 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3739 {
3740 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3741 }
3742
3743 /**
3744 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3745 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3746 * software and is reset in case of break or break2 event.
3747 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3748 * a timer instance provides a break input.
3749 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3750 * @param TIMx Timer instance
3751 * @retval None
3752 */
3753 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3754 {
3755 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3756 }
3757
3758 /**
3759 * @brief Indicates whether outputs are enabled.
3760 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3761 * a timer instance provides a break input.
3762 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3763 * @param TIMx Timer instance
3764 * @retval State of bit (1 or 0).
3765 */
3766 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3767 {
3768 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
3769 }
3770
3771 /**
3772 * @}
3773 */
3774
3775 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3776 * @{
3777 */
3778 /**
3779 * @brief Configures the timer DMA burst feature.
3780 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3781 * not a timer instance supports the DMA burst mode.
3782 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3783 * DCR DBA LL_TIM_ConfigDMABurst
3784 * @param TIMx Timer instance
3785 * @param DMABurstBaseAddress This parameter can be one of the following values:
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3787 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3788 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3789 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3790 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3791 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3792 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3793 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3794 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3795 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3796 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3797 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3798 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3799 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3800 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3801 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3802 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3803 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3804 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
3805 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
3806 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
3807 * (*) value not defined in all devices
3808 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3809 * @param DMABurstLength This parameter can be one of the following values:
3810 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3811 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3812 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3813 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3814 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3815 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3816 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3817 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3818 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3819 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3820 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3821 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3822 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3823 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3824 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3825 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3826 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3827 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3828 * @retval None
3829 */
3830 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3831 {
3832 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
3833 }
3834
3835 /**
3836 * @}
3837 */
3838
3839 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3840 * @{
3841 */
3842 /**
3843 * @brief Remap TIM inputs (input channel, internal/external triggers).
3844 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3845 * a some timer inputs can be remapped.
3846 * @if STM32F334x8
3847 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3848 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3849 * @elseif STM32F302x8
3850 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3851 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3852 * @elseif STM32F303xC
3853 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3854 * TIM8_OR ETR_RMP LL_TIM_SetRemap\n
3855 * TIM20_OR ETR_RMP LL_TIM_SetRemap\n
3856 * @elseif STM32F373xC
3857 * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
3858 * @endif
3859 * @param TIMx Timer instance
3860 * @param Remap Remap params depends on the TIMx. Description available only
3861 * in CHM version of the User Manual (not in .pdf).
3862 * Otherwise see Reference Manual description of OR registers.
3863 *
3864 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3865 *
3866 * TIM1: any combination of ETR_RMP where (**)
3867 *
3868 * . . ETR_RMP can be one of the following values
3869 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3870 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
3871 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
3872 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
3873 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
3874 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
3875 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
3876 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
3877 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
3878 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
3879 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
3880 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
3881 *
3882 * TIM8: any combination of ETR_RMP where (**)
3883 *
3884 * . . ETR_RMP can be one of the following values
3885 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
3886 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
3887 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
3888 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
3889 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
3890 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
3891 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
3892 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
3893 *
3894 * TIM14: any combination of TI1_RMP where (**)
3895 *
3896 * . . TI1_RMP can be one of the following values
3897 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
3898 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
3899 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
3900 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
3901 *
3902 * TIM16: any combination of TI1_RMP where (**)
3903 *
3904 * . . TI1_RMP can be one of the following values
3905 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
3906 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
3907 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
3908 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
3909 *
3910 * TIM20: any combination of ETR_RMP where (**)
3911 *
3912 * . . ETR_RMP can be one of the following values
3913 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
3914 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
3915 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
3916 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
3917 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
3918 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
3919 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
3920 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
3921 *
3922 * (*) Value not defined in all devices. \n
3923 * (**) Register not available in all devices.
3924 * @retval None
3925 */
3926 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3927 {
3928 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3929 }
3930
3931 /**
3932 * @}
3933 */
3934
3935 #if defined(TIM_SMCR_OCCS)
3936 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3937 * @{
3938 */
3939 /**
3940 * @brief Set the OCREF clear input source
3941 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3942 * @note This function can only be used in Output compare and PWM modes.
3943 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3944 * @param TIMx Timer instance
3945 * @param OCRefClearInputSource This parameter can be one of the following values:
3946 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3947 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3948 * @retval None
3949 */
3950 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3951 {
3952 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3953 }
3954 /**
3955 * @}
3956 */
3957 #endif /* TIM_SMCR_OCCS */
3958
3959 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3960 * @{
3961 */
3962 /**
3963 * @brief Clear the update interrupt flag (UIF).
3964 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3965 * @param TIMx Timer instance
3966 * @retval None
3967 */
3968 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3969 {
3970 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3971 }
3972
3973 /**
3974 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3975 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3976 * @param TIMx Timer instance
3977 * @retval State of bit (1 or 0).
3978 */
3979 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3980 {
3981 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
3982 }
3983
3984 /**
3985 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3986 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3987 * @param TIMx Timer instance
3988 * @retval None
3989 */
3990 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3991 {
3992 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3993 }
3994
3995 /**
3996 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3997 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3998 * @param TIMx Timer instance
3999 * @retval State of bit (1 or 0).
4000 */
4001 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
4002 {
4003 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
4004 }
4005
4006 /**
4007 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4008 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4009 * @param TIMx Timer instance
4010 * @retval None
4011 */
4012 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4013 {
4014 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4015 }
4016
4017 /**
4018 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4019 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4020 * @param TIMx Timer instance
4021 * @retval State of bit (1 or 0).
4022 */
4023 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
4024 {
4025 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
4026 }
4027
4028 /**
4029 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4030 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4031 * @param TIMx Timer instance
4032 * @retval None
4033 */
4034 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4035 {
4036 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4037 }
4038
4039 /**
4040 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4041 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4042 * @param TIMx Timer instance
4043 * @retval State of bit (1 or 0).
4044 */
4045 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4046 {
4047 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
4048 }
4049
4050 /**
4051 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4052 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4053 * @param TIMx Timer instance
4054 * @retval None
4055 */
4056 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4057 {
4058 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4059 }
4060
4061 /**
4062 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4063 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4064 * @param TIMx Timer instance
4065 * @retval State of bit (1 or 0).
4066 */
4067 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4068 {
4069 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
4070 }
4071
4072 #if defined (TIM_SR_CC5IF)
4073 /**
4074 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4075 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4076 * @param TIMx Timer instance
4077 * @retval None
4078 */
4079 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4080 {
4081 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4082 }
4083
4084 /**
4085 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4086 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4087 * @param TIMx Timer instance
4088 * @retval State of bit (1 or 0).
4089 */
4090 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4091 {
4092 return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
4093 }
4094
4095 #endif /* TIM_SR_CC5IF */
4096 #if defined (TIM_SR_CC6IF)
4097 /**
4098 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4099 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4100 * @param TIMx Timer instance
4101 * @retval None
4102 */
4103 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4104 {
4105 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4106 }
4107
4108 /**
4109 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4110 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4111 * @param TIMx Timer instance
4112 * @retval State of bit (1 or 0).
4113 */
4114 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4115 {
4116 return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
4117 }
4118
4119 #endif /* TIM_SR_CC6IF */
4120 /**
4121 * @brief Clear the commutation interrupt flag (COMIF).
4122 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4123 * @param TIMx Timer instance
4124 * @retval None
4125 */
4126 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4127 {
4128 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4129 }
4130
4131 /**
4132 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4133 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4134 * @param TIMx Timer instance
4135 * @retval State of bit (1 or 0).
4136 */
4137 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4138 {
4139 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
4140 }
4141
4142 /**
4143 * @brief Clear the trigger interrupt flag (TIF).
4144 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4145 * @param TIMx Timer instance
4146 * @retval None
4147 */
4148 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4149 {
4150 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4151 }
4152
4153 /**
4154 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4155 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4156 * @param TIMx Timer instance
4157 * @retval State of bit (1 or 0).
4158 */
4159 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4160 {
4161 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
4162 }
4163
4164 /**
4165 * @brief Clear the break interrupt flag (BIF).
4166 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4167 * @param TIMx Timer instance
4168 * @retval None
4169 */
4170 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4171 {
4172 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4173 }
4174
4175 /**
4176 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4177 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4178 * @param TIMx Timer instance
4179 * @retval State of bit (1 or 0).
4180 */
4181 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4182 {
4183 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
4184 }
4185
4186 #if defined(TIM_SR_B2IF)
4187 /**
4188 * @brief Clear the break 2 interrupt flag (B2IF).
4189 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4190 * @param TIMx Timer instance
4191 * @retval None
4192 */
4193 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4194 {
4195 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4196 }
4197
4198 /**
4199 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4200 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4201 * @param TIMx Timer instance
4202 * @retval State of bit (1 or 0).
4203 */
4204 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4205 {
4206 return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
4207 }
4208
4209 #endif /* TIM_SR_B2IF */
4210 /**
4211 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4212 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4213 * @param TIMx Timer instance
4214 * @retval None
4215 */
4216 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4217 {
4218 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4219 }
4220
4221 /**
4222 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4223 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4224 * @param TIMx Timer instance
4225 * @retval State of bit (1 or 0).
4226 */
4227 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4228 {
4229 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
4230 }
4231
4232 /**
4233 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4234 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4235 * @param TIMx Timer instance
4236 * @retval None
4237 */
4238 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4239 {
4240 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4241 }
4242
4243 /**
4244 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4245 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4246 * @param TIMx Timer instance
4247 * @retval State of bit (1 or 0).
4248 */
4249 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4250 {
4251 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
4252 }
4253
4254 /**
4255 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4256 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4257 * @param TIMx Timer instance
4258 * @retval None
4259 */
4260 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4261 {
4262 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4263 }
4264
4265 /**
4266 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4267 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4268 * @param TIMx Timer instance
4269 * @retval State of bit (1 or 0).
4270 */
4271 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4272 {
4273 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
4274 }
4275
4276 /**
4277 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4278 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4279 * @param TIMx Timer instance
4280 * @retval None
4281 */
4282 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4283 {
4284 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4285 }
4286
4287 /**
4288 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4289 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4290 * @param TIMx Timer instance
4291 * @retval State of bit (1 or 0).
4292 */
4293 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4294 {
4295 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
4296 }
4297
4298 /**
4299 * @}
4300 */
4301
4302 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4303 * @{
4304 */
4305 /**
4306 * @brief Enable update interrupt (UIE).
4307 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4308 * @param TIMx Timer instance
4309 * @retval None
4310 */
4311 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4312 {
4313 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4314 }
4315
4316 /**
4317 * @brief Disable update interrupt (UIE).
4318 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4319 * @param TIMx Timer instance
4320 * @retval None
4321 */
4322 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4323 {
4324 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4325 }
4326
4327 /**
4328 * @brief Indicates whether the update interrupt (UIE) is enabled.
4329 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4330 * @param TIMx Timer instance
4331 * @retval State of bit (1 or 0).
4332 */
4333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4334 {
4335 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
4336 }
4337
4338 /**
4339 * @brief Enable capture/compare 1 interrupt (CC1IE).
4340 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4341 * @param TIMx Timer instance
4342 * @retval None
4343 */
4344 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4345 {
4346 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4347 }
4348
4349 /**
4350 * @brief Disable capture/compare 1 interrupt (CC1IE).
4351 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4352 * @param TIMx Timer instance
4353 * @retval None
4354 */
4355 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4356 {
4357 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4358 }
4359
4360 /**
4361 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4362 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4363 * @param TIMx Timer instance
4364 * @retval State of bit (1 or 0).
4365 */
4366 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4367 {
4368 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
4369 }
4370
4371 /**
4372 * @brief Enable capture/compare 2 interrupt (CC2IE).
4373 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4374 * @param TIMx Timer instance
4375 * @retval None
4376 */
4377 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4378 {
4379 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4380 }
4381
4382 /**
4383 * @brief Disable capture/compare 2 interrupt (CC2IE).
4384 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4385 * @param TIMx Timer instance
4386 * @retval None
4387 */
4388 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4389 {
4390 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4391 }
4392
4393 /**
4394 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4395 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4396 * @param TIMx Timer instance
4397 * @retval State of bit (1 or 0).
4398 */
4399 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4400 {
4401 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
4402 }
4403
4404 /**
4405 * @brief Enable capture/compare 3 interrupt (CC3IE).
4406 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4407 * @param TIMx Timer instance
4408 * @retval None
4409 */
4410 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4411 {
4412 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4413 }
4414
4415 /**
4416 * @brief Disable capture/compare 3 interrupt (CC3IE).
4417 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4418 * @param TIMx Timer instance
4419 * @retval None
4420 */
4421 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4422 {
4423 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4424 }
4425
4426 /**
4427 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4428 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4429 * @param TIMx Timer instance
4430 * @retval State of bit (1 or 0).
4431 */
4432 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4433 {
4434 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
4435 }
4436
4437 /**
4438 * @brief Enable capture/compare 4 interrupt (CC4IE).
4439 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4440 * @param TIMx Timer instance
4441 * @retval None
4442 */
4443 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4444 {
4445 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4446 }
4447
4448 /**
4449 * @brief Disable capture/compare 4 interrupt (CC4IE).
4450 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4451 * @param TIMx Timer instance
4452 * @retval None
4453 */
4454 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4455 {
4456 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4457 }
4458
4459 /**
4460 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4461 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4462 * @param TIMx Timer instance
4463 * @retval State of bit (1 or 0).
4464 */
4465 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4466 {
4467 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
4468 }
4469
4470 /**
4471 * @brief Enable commutation interrupt (COMIE).
4472 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4473 * @param TIMx Timer instance
4474 * @retval None
4475 */
4476 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4477 {
4478 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4479 }
4480
4481 /**
4482 * @brief Disable commutation interrupt (COMIE).
4483 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4484 * @param TIMx Timer instance
4485 * @retval None
4486 */
4487 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4488 {
4489 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4490 }
4491
4492 /**
4493 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4494 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4495 * @param TIMx Timer instance
4496 * @retval State of bit (1 or 0).
4497 */
4498 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4499 {
4500 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
4501 }
4502
4503 /**
4504 * @brief Enable trigger interrupt (TIE).
4505 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4506 * @param TIMx Timer instance
4507 * @retval None
4508 */
4509 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4510 {
4511 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4512 }
4513
4514 /**
4515 * @brief Disable trigger interrupt (TIE).
4516 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4517 * @param TIMx Timer instance
4518 * @retval None
4519 */
4520 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4521 {
4522 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4523 }
4524
4525 /**
4526 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4527 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4528 * @param TIMx Timer instance
4529 * @retval State of bit (1 or 0).
4530 */
4531 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4532 {
4533 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
4534 }
4535
4536 /**
4537 * @brief Enable break interrupt (BIE).
4538 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4539 * @param TIMx Timer instance
4540 * @retval None
4541 */
4542 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4543 {
4544 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4545 }
4546
4547 /**
4548 * @brief Disable break interrupt (BIE).
4549 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4550 * @param TIMx Timer instance
4551 * @retval None
4552 */
4553 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4554 {
4555 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4556 }
4557
4558 /**
4559 * @brief Indicates whether the break interrupt (BIE) is enabled.
4560 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4561 * @param TIMx Timer instance
4562 * @retval State of bit (1 or 0).
4563 */
4564 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4565 {
4566 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
4567 }
4568
4569 /**
4570 * @}
4571 */
4572
4573 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4574 * @{
4575 */
4576 /**
4577 * @brief Enable update DMA request (UDE).
4578 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4579 * @param TIMx Timer instance
4580 * @retval None
4581 */
4582 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4583 {
4584 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4585 }
4586
4587 /**
4588 * @brief Disable update DMA request (UDE).
4589 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4590 * @param TIMx Timer instance
4591 * @retval None
4592 */
4593 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4594 {
4595 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4596 }
4597
4598 /**
4599 * @brief Indicates whether the update DMA request (UDE) is enabled.
4600 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4601 * @param TIMx Timer instance
4602 * @retval State of bit (1 or 0).
4603 */
4604 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4605 {
4606 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
4607 }
4608
4609 /**
4610 * @brief Enable capture/compare 1 DMA request (CC1DE).
4611 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4612 * @param TIMx Timer instance
4613 * @retval None
4614 */
4615 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4616 {
4617 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4618 }
4619
4620 /**
4621 * @brief Disable capture/compare 1 DMA request (CC1DE).
4622 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4623 * @param TIMx Timer instance
4624 * @retval None
4625 */
4626 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4627 {
4628 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4629 }
4630
4631 /**
4632 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4633 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4634 * @param TIMx Timer instance
4635 * @retval State of bit (1 or 0).
4636 */
4637 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4638 {
4639 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
4640 }
4641
4642 /**
4643 * @brief Enable capture/compare 2 DMA request (CC2DE).
4644 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4645 * @param TIMx Timer instance
4646 * @retval None
4647 */
4648 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4649 {
4650 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4651 }
4652
4653 /**
4654 * @brief Disable capture/compare 2 DMA request (CC2DE).
4655 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4656 * @param TIMx Timer instance
4657 * @retval None
4658 */
4659 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4660 {
4661 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4662 }
4663
4664 /**
4665 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4666 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4667 * @param TIMx Timer instance
4668 * @retval State of bit (1 or 0).
4669 */
4670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4671 {
4672 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
4673 }
4674
4675 /**
4676 * @brief Enable capture/compare 3 DMA request (CC3DE).
4677 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4678 * @param TIMx Timer instance
4679 * @retval None
4680 */
4681 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4682 {
4683 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4684 }
4685
4686 /**
4687 * @brief Disable capture/compare 3 DMA request (CC3DE).
4688 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4689 * @param TIMx Timer instance
4690 * @retval None
4691 */
4692 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4693 {
4694 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4695 }
4696
4697 /**
4698 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4699 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4700 * @param TIMx Timer instance
4701 * @retval State of bit (1 or 0).
4702 */
4703 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4704 {
4705 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
4706 }
4707
4708 /**
4709 * @brief Enable capture/compare 4 DMA request (CC4DE).
4710 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4711 * @param TIMx Timer instance
4712 * @retval None
4713 */
4714 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4715 {
4716 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4717 }
4718
4719 /**
4720 * @brief Disable capture/compare 4 DMA request (CC4DE).
4721 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4722 * @param TIMx Timer instance
4723 * @retval None
4724 */
4725 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4726 {
4727 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4728 }
4729
4730 /**
4731 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4732 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4733 * @param TIMx Timer instance
4734 * @retval State of bit (1 or 0).
4735 */
4736 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4737 {
4738 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
4739 }
4740
4741 /**
4742 * @brief Enable commutation DMA request (COMDE).
4743 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4744 * @param TIMx Timer instance
4745 * @retval None
4746 */
4747 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4748 {
4749 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4750 }
4751
4752 /**
4753 * @brief Disable commutation DMA request (COMDE).
4754 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4755 * @param TIMx Timer instance
4756 * @retval None
4757 */
4758 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4759 {
4760 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4761 }
4762
4763 /**
4764 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4765 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4766 * @param TIMx Timer instance
4767 * @retval State of bit (1 or 0).
4768 */
4769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4770 {
4771 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
4772 }
4773
4774 /**
4775 * @brief Enable trigger interrupt (TDE).
4776 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4777 * @param TIMx Timer instance
4778 * @retval None
4779 */
4780 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4781 {
4782 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4783 }
4784
4785 /**
4786 * @brief Disable trigger interrupt (TDE).
4787 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4788 * @param TIMx Timer instance
4789 * @retval None
4790 */
4791 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4792 {
4793 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4794 }
4795
4796 /**
4797 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4798 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4799 * @param TIMx Timer instance
4800 * @retval State of bit (1 or 0).
4801 */
4802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4803 {
4804 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
4805 }
4806
4807 /**
4808 * @}
4809 */
4810
4811 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4812 * @{
4813 */
4814 /**
4815 * @brief Generate an update event.
4816 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4817 * @param TIMx Timer instance
4818 * @retval None
4819 */
4820 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4821 {
4822 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4823 }
4824
4825 /**
4826 * @brief Generate Capture/Compare 1 event.
4827 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4828 * @param TIMx Timer instance
4829 * @retval None
4830 */
4831 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4832 {
4833 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4834 }
4835
4836 /**
4837 * @brief Generate Capture/Compare 2 event.
4838 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4839 * @param TIMx Timer instance
4840 * @retval None
4841 */
4842 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4843 {
4844 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4845 }
4846
4847 /**
4848 * @brief Generate Capture/Compare 3 event.
4849 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4850 * @param TIMx Timer instance
4851 * @retval None
4852 */
4853 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4854 {
4855 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4856 }
4857
4858 /**
4859 * @brief Generate Capture/Compare 4 event.
4860 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4861 * @param TIMx Timer instance
4862 * @retval None
4863 */
4864 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4865 {
4866 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4867 }
4868
4869 /**
4870 * @brief Generate commutation event.
4871 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4872 * @param TIMx Timer instance
4873 * @retval None
4874 */
4875 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4876 {
4877 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4878 }
4879
4880 /**
4881 * @brief Generate trigger event.
4882 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4883 * @param TIMx Timer instance
4884 * @retval None
4885 */
4886 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4887 {
4888 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4889 }
4890
4891 /**
4892 * @brief Generate break event.
4893 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4894 * @param TIMx Timer instance
4895 * @retval None
4896 */
4897 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4898 {
4899 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4900 }
4901
4902 #if defined(TIM_EGR_B2G)
4903 /**
4904 * @brief Generate break 2 event.
4905 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4906 * @param TIMx Timer instance
4907 * @retval None
4908 */
4909 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4910 {
4911 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4912 }
4913
4914 #endif /* TIM_EGR_B2G */
4915 /**
4916 * @}
4917 */
4918
4919 #if defined(USE_FULL_LL_DRIVER)
4920 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4921 * @{
4922 */
4923
4924 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4925 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4926 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4927 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4928 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4929 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4930 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4931 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4932 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4933 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4934 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4935 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4936 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4937 /**
4938 * @}
4939 */
4940 #endif /* USE_FULL_LL_DRIVER */
4941
4942 /**
4943 * @}
4944 */
4945
4946 /**
4947 * @}
4948 */
4949
4950 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
4951
4952 /**
4953 * @}
4954 */
4955
4956 #ifdef __cplusplus
4957 }
4958 #endif
4959
4960 #endif /* __STM32F3xx_LL_TIM_H */
4961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/