lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of DMA HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32F7xx_HAL_DMA_H
  22 #define __STM32F7xx_HAL_DMA_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32f7xx_hal_def.h"
  30
  31 /** @addtogroup STM32F7xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup DMA
  36   * @{
  37   */
  38
  39 /* Exported types ------------------------------------------------------------*/
  40
  41 /** @defgroup DMA_Exported_Types DMA Exported Types
  42   * @brief    DMA Exported Types
  43   * @{
  44   */
  45
  46 /**
  47   * @brief  DMA Configuration Structure definition
  48   */
  49 typedef struct
  50 {
  51   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
  52                                       This parameter can be a value of @ref DMAEx_Channel_selection                  */
  53
  54   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
  55                                       from memory to memory or from peripheral to memory.
  56                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
  57
  58   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
  59                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  60
  61   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
  62                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  63
  64   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
  65                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  66
  67   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
  68                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
  69
  70   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
  71                                       This parameter can be a value of @ref DMA_mode
  72                                       @note The circular buffer mode cannot be used if the memory-to-memory
  73                                             data transfer is configured on the selected Stream                        */
  74
  75   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
  76                                       This parameter can be a value of @ref DMA_Priority_level                       */
  77
  78   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  79                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
  80                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
  81                                             memory-to-memory data transfer is configured on the selected stream       */
  82
  83   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
  84                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
  85
  86   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
  87                                       It specifies the amount of data to be transferred in a single non interruptible
  88                                       transaction.
  89                                       This parameter can be a value of @ref DMA_Memory_burst
  90                                       @note The burst mode is possible only if the address Increment mode is enabled. */
  91
  92   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
  93                                       It specifies the amount of data to be transferred in a single non interruptible
  94                                       transaction.
  95                                       This parameter can be a value of @ref DMA_Peripheral_burst
  96                                       @note The burst mode is possible only if the address Increment mode is enabled. */
  97 }DMA_InitTypeDef;
  98
  99 /**
 100   * @brief  HAL DMA State structures definition
 101   */
 102 typedef enum
 103 {
 104   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
 105   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
 106   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
 107   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
 108   HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
 109   HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
 110 }HAL_DMA_StateTypeDef;
 111
 112 /**
 113   * @brief  HAL DMA Error Code structure definition
 114   */
 115 typedef enum
 116 {
 117   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
 118   HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
 119 }HAL_DMA_LevelCompleteTypeDef;
 120
 121 /**
 122   * @brief  HAL DMA Error Code structure definition
 123   */
 124 typedef enum
 125 {
 126   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 127   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
 128   HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
 129   HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
 130   HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
 131   HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
 132   HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
 133 }HAL_DMA_CallbackIDTypeDef;
 134
 135 /**
 136   * @brief  DMA handle Structure definition
 137   */
 138 typedef struct __DMA_HandleTypeDef
 139 {
 140   DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
 141
 142   DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
 143
 144   HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
 145
 146   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 147
 148   void                       *Parent;                                                      /*!< Parent object state                    */
 149
 150   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 151
 152   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 153
 154   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
 155
 156   void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
 157
 158   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 159
 160   void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */
 161
 162  __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
 163
 164  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
 165
 166  uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
 167
 168 }DMA_HandleTypeDef;
 169
 170 /**
 171   * @}
 172   */
 173
 174
 175 /* Exported constants --------------------------------------------------------*/
 176
 177 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 178   * @brief    DMA Exported constants
 179   * @{
 180   */
 181
 182 /** @defgroup DMA_Error_Code DMA Error Code
 183   * @brief    DMA Error Code
 184   * @{
 185   */
 186 #define HAL_DMA_ERROR_NONE                       0x00000000U    /*!< No error                               */
 187 #define HAL_DMA_ERROR_TE                         0x00000001U    /*!< Transfer error                         */
 188 #define HAL_DMA_ERROR_FE                         0x00000002U    /*!< FIFO error                             */
 189 #define HAL_DMA_ERROR_DME                        0x00000004U    /*!< Direct Mode error                      */
 190 #define HAL_DMA_ERROR_TIMEOUT                    0x00000020U    /*!< Timeout error                          */
 191 #define HAL_DMA_ERROR_PARAM                      0x00000040U    /*!< Parameter error                        */
 192 #define HAL_DMA_ERROR_NO_XFER                    0x00000080U    /*!< Abort requested with no Xfer ongoing   */
 193 #define HAL_DMA_ERROR_NOT_SUPPORTED              0x00000100U    /*!< Not supported mode                     */
 194 /**
 195   * @}
 196   */
 197
 198 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 199   * @brief    DMA data transfer direction
 200   * @{
 201   */
 202 #define DMA_PERIPH_TO_MEMORY                     0x00000000U      /*!< Peripheral to memory direction */
 203 #define DMA_MEMORY_TO_PERIPH                     DMA_SxCR_DIR_0   /*!< Memory to peripheral direction */
 204 #define DMA_MEMORY_TO_MEMORY                     DMA_SxCR_DIR_1   /*!< Memory to memory direction     */
 205 /**
 206   * @}
 207   */
 208
 209 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 210   * @brief    DMA peripheral incremented mode
 211   * @{
 212   */
 213 #define DMA_PINC_ENABLE                          DMA_SxCR_PINC    /*!< Peripheral increment mode enable  */
 214 #define DMA_PINC_DISABLE                         0x00000000U      /*!< Peripheral increment mode disable */
 215 /**
 216   * @}
 217   */
 218
 219 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 220   * @brief    DMA memory incremented mode
 221   * @{
 222   */
 223 #define DMA_MINC_ENABLE                          DMA_SxCR_MINC    /*!< Memory increment mode enable  */
 224 #define DMA_MINC_DISABLE                         0x00000000U      /*!< Memory increment mode disable */
 225 /**
 226   * @}
 227   */
 228
 229 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 230   * @brief    DMA peripheral data size
 231   * @{
 232   */
 233 #define DMA_PDATAALIGN_BYTE                      0x00000000U        /*!< Peripheral data alignment: Byte     */
 234 #define DMA_PDATAALIGN_HALFWORD                  DMA_SxCR_PSIZE_0   /*!< Peripheral data alignment: HalfWord */
 235 #define DMA_PDATAALIGN_WORD                      DMA_SxCR_PSIZE_1   /*!< Peripheral data alignment: Word     */
 236 /**
 237   * @}
 238   */
 239
 240 /** @defgroup DMA_Memory_data_size DMA Memory data size
 241   * @brief    DMA memory data size
 242   * @{
 243   */
 244 #define DMA_MDATAALIGN_BYTE                      0x00000000U        /*!< Memory data alignment: Byte     */
 245 #define DMA_MDATAALIGN_HALFWORD                  DMA_SxCR_MSIZE_0   /*!< Memory data alignment: HalfWord */
 246 #define DMA_MDATAALIGN_WORD                      DMA_SxCR_MSIZE_1   /*!< Memory data alignment: Word     */
 247 /**
 248   * @}
 249   */
 250
 251 /** @defgroup DMA_mode DMA mode
 252   * @brief    DMA mode
 253   * @{
 254   */
 255 #define DMA_NORMAL                               0x00000000U       /*!< Normal mode                  */
 256 #define DMA_CIRCULAR                             DMA_SxCR_CIRC     /*!< Circular mode                */
 257 #define DMA_PFCTRL                               DMA_SxCR_PFCTRL   /*!< Peripheral flow control mode */
 258 /**
 259   * @}
 260   */
 261
 262 /** @defgroup DMA_Priority_level DMA Priority level
 263   * @brief    DMA priority levels
 264   * @{
 265   */
 266 #define DMA_PRIORITY_LOW                         0x00000000U    /*!< Priority level: Low       */
 267 #define DMA_PRIORITY_MEDIUM                      DMA_SxCR_PL_0  /*!< Priority level: Medium    */
 268 #define DMA_PRIORITY_HIGH                        DMA_SxCR_PL_1  /*!< Priority level: High      */
 269 #define DMA_PRIORITY_VERY_HIGH                   DMA_SxCR_PL    /*!< Priority level: Very High */
 270 /**
 271   * @}
 272   */
 273
 274 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
 275   * @brief    DMA FIFO direct mode
 276   * @{
 277   */
 278 #define DMA_FIFOMODE_DISABLE                     0x00000000U       /*!< FIFO mode disable */
 279 #define DMA_FIFOMODE_ENABLE                      DMA_SxFCR_DMDIS   /*!< FIFO mode enable  */
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
 285   * @brief    DMA FIFO level
 286   * @{
 287   */
 288 #define DMA_FIFO_THRESHOLD_1QUARTERFULL          0x00000000U       /*!< FIFO threshold 1 quart full configuration  */
 289 #define DMA_FIFO_THRESHOLD_HALFFULL              DMA_SxFCR_FTH_0   /*!< FIFO threshold half full configuration     */
 290 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL         DMA_SxFCR_FTH_1   /*!< FIFO threshold 3 quarts full configuration */
 291 #define DMA_FIFO_THRESHOLD_FULL                  DMA_SxFCR_FTH     /*!< FIFO threshold full configuration          */
 292 /**
 293   * @}
 294   */
 295
 296 /** @defgroup DMA_Memory_burst DMA Memory burst
 297   * @brief    DMA memory burst
 298   * @{
 299   */
 300 #define DMA_MBURST_SINGLE                        0x00000000U
 301 #define DMA_MBURST_INC4                          DMA_SxCR_MBURST_0
 302 #define DMA_MBURST_INC8                          DMA_SxCR_MBURST_1
 303 #define DMA_MBURST_INC16                         DMA_SxCR_MBURST
 304 /**
 305   * @}
 306   */
 307
 308 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
 309   * @brief    DMA peripheral burst
 310   * @{
 311   */
 312 #define DMA_PBURST_SINGLE                        0x00000000U
 313 #define DMA_PBURST_INC4                          DMA_SxCR_PBURST_0
 314 #define DMA_PBURST_INC8                          DMA_SxCR_PBURST_1
 315 #define DMA_PBURST_INC16                         DMA_SxCR_PBURST
 316 /**
 317   * @}
 318   */
 319
 320 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 321   * @brief    DMA interrupts definition
 322   * @{
 323   */
 324 #define DMA_IT_TC                                DMA_SxCR_TCIE
 325 #define DMA_IT_HT                                DMA_SxCR_HTIE
 326 #define DMA_IT_TE                                DMA_SxCR_TEIE
 327 #define DMA_IT_DME                               DMA_SxCR_DMEIE
 328 #define DMA_IT_FE                                0x00000080U
 329 /**
 330   * @}
 331   */
 332
 333 /** @defgroup DMA_flag_definitions DMA flag definitions
 334   * @brief    DMA flag definitions
 335   * @{
 336   */
 337 #define DMA_FLAG_FEIF0_4                         0x00000001U
 338 #define DMA_FLAG_DMEIF0_4                        0x00000004U
 339 #define DMA_FLAG_TEIF0_4                         0x00000008U
 340 #define DMA_FLAG_HTIF0_4                         0x00000010U
 341 #define DMA_FLAG_TCIF0_4                         0x00000020U
 342 #define DMA_FLAG_FEIF1_5                         0x00000040U
 343 #define DMA_FLAG_DMEIF1_5                        0x00000100U
 344 #define DMA_FLAG_TEIF1_5                         0x00000200U
 345 #define DMA_FLAG_HTIF1_5                         0x00000400U
 346 #define DMA_FLAG_TCIF1_5                         0x00000800U
 347 #define DMA_FLAG_FEIF2_6                         0x00010000U
 348 #define DMA_FLAG_DMEIF2_6                        0x00040000U
 349 #define DMA_FLAG_TEIF2_6                         0x00080000U
 350 #define DMA_FLAG_HTIF2_6                         0x00100000U
 351 #define DMA_FLAG_TCIF2_6                         0x00200000U
 352 #define DMA_FLAG_FEIF3_7                         0x00400000U
 353 #define DMA_FLAG_DMEIF3_7                        0x01000000U
 354 #define DMA_FLAG_TEIF3_7                         0x02000000U
 355 #define DMA_FLAG_HTIF3_7                         0x04000000U
 356 #define DMA_FLAG_TCIF3_7                         0x08000000U
 357 /**
 358   * @}
 359   */
 360
 361 /**
 362   * @}
 363   */
 364
 365 /* Exported macro ------------------------------------------------------------*/
 366
 367 /** @brief Reset DMA handle state
 368   * @param  __HANDLE__ specifies the DMA handle.
 369   * @retval None
 370   */
 371 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 372
 373 /**
 374   * @brief  Return the current DMA Stream FIFO filled level.
 375   * @param  __HANDLE__ DMA handle
 376   * @retval The FIFO filling state.
 377   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
 378   *                                              and not empty.
 379   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 380   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 381   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 382   *           - DMA_FIFOStatus_Empty: when FIFO is empty
 383   *           - DMA_FIFOStatus_Full: when FIFO is full
 384   */
 385 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
 386
 387 /**
 388   * @brief  Enable the specified DMA Stream.
 389   * @param  __HANDLE__ DMA handle
 390   * @retval None
 391   */
 392 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 393
 394 /**
 395   * @brief  Disable the specified DMA Stream.
 396   * @param  __HANDLE__ DMA handle
 397   * @retval None
 398   */
 399 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
 400
 401 /* Interrupt & Flag management */
 402
 403 /**
 404   * @brief  Return the current DMA Stream transfer complete flag.
 405   * @param  __HANDLE__ DMA handle
 406   * @retval The specified transfer complete flag index.
 407   */
 408 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 409 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 410  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 411  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 412  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 413  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 414  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 415  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 416  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 417  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 418  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 419  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 420  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 421    DMA_FLAG_TCIF3_7)
 422
 423 /**
 424   * @brief  Return the current DMA Stream half transfer complete flag.
 425   * @param  __HANDLE__ DMA handle
 426   * @retval The specified half transfer complete flag index.
 427   */
 428 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 429 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 430  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 431  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 432  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 439  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 440  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 441    DMA_FLAG_HTIF3_7)
 442
 443 /**
 444   * @brief  Return the current DMA Stream transfer error flag.
 445   * @param  __HANDLE__ DMA handle
 446   * @retval The specified transfer error flag index.
 447   */
 448 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 459  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 461    DMA_FLAG_TEIF3_7)
 462
 463 /**
 464   * @brief  Return the current DMA Stream FIFO error flag.
 465   * @param  __HANDLE__ DMA handle
 466   * @retval The specified FIFO error flag index.
 467   */
 468 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
 469 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 481    DMA_FLAG_FEIF3_7)
 482
 483 /**
 484   * @brief  Return the current DMA Stream direct mode error flag.
 485   * @param  __HANDLE__ DMA handle
 486   * @retval The specified direct mode error flag index.
 487   */
 488 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
 489 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 501    DMA_FLAG_DMEIF3_7)
 502
 503 /**
 504   * @brief  Get the DMA Stream pending flags.
 505   * @param  __HANDLE__ DMA handle
 506   * @param  __FLAG__ Get the specified flag.
 507   *          This parameter can be any combination of the following values:
 508   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 509   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 510   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 511   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 512   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 513   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 514   * @retval The state of FLAG (SET or RESET).
 515   */
 516 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
 517 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 518  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 519  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
 520
 521 /**
 522   * @brief  Clear the DMA Stream pending flags.
 523   * @param  __HANDLE__ DMA handle
 524   * @param  __FLAG__ specifies the flag to clear.
 525   *          This parameter can be any combination of the following values:
 526   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 527   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 528   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 529   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 530   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 531   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 532   * @retval None
 533   */
 534 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 535 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 536  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 537  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
 538
 539 /**
 540   * @brief  Enable the specified DMA Stream interrupts.
 541   * @param  __HANDLE__ DMA handle
 542   * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 543   *        This parameter can be one of the following values:
 544   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
 545   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
 546   *           @arg DMA_IT_TE: Transfer error interrupt mask.
 547   *           @arg DMA_IT_FE: FIFO error interrupt mask.
 548   *           @arg DMA_IT_DME: Direct mode error interrupt.
 549   * @retval None
 550   */
 551 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
 552 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
 553
 554 /**
 555   * @brief  Disable the specified DMA Stream interrupts.
 556   * @param  __HANDLE__ DMA handle
 557   * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 558   *         This parameter can be one of the following values:
 559   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 560   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 561   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 562   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 563   *            @arg DMA_IT_DME: Direct mode error interrupt.
 564   * @retval None
 565   */
 566 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 567 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
 568
 569 /**
 570   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
 571   * @param  __HANDLE__ DMA handle
 572   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
 573   *         This parameter can be one of the following values:
 574   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 575   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 576   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 577   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 578   *            @arg DMA_IT_DME: Direct mode error interrupt.
 579   * @retval The state of DMA_IT.
 580   */
 581 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 582                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
 583                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
 584
 585 /**
 586   * @brief  Writes the number of data units to be transferred on the DMA Stream.
 587   * @param  __HANDLE__ DMA handle
 588   * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535)
 589   *          Number of data items depends only on the Peripheral data format.
 590   *
 591   * @note   If Peripheral data format is Bytes: number of data units is equal
 592   *         to total number of bytes to be transferred.
 593   *
 594   * @note   If Peripheral data format is Half-Word: number of data units is
 595   *         equal to total number of bytes to be transferred / 2.
 596   *
 597   * @note   If Peripheral data format is Word: number of data units is equal
 598   *         to total  number of bytes to be transferred / 4.
 599   *
 600   * @retval The number of remaining data units in the current DMAy Streamx transfer.
 601   */
 602 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
 603
 604 /**
 605   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
 606   * @param  __HANDLE__ DMA handle
 607   *
 608   * @retval The number of remaining data units in the current DMA Stream transfer.
 609   */
 610 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
 611
 612
 613 /* Include DMA HAL Extension module */
 614 #include "stm32f7xx_hal_dma_ex.h"
 615
 616 /* Exported functions --------------------------------------------------------*/
 617
 618 /** @defgroup DMA_Exported_Functions DMA Exported Functions
 619   * @brief    DMA Exported functions
 620   * @{
 621   */
 622
 623 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 624   * @brief   Initialization and de-initialization functions
 625   * @{
 626   */
 627 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 628 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 629 /**
 630   * @}
 631   */
 632
 633 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
 634   * @brief   I/O operation functions
 635   * @{
 636   */
 637 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 638 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 639 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 640 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 641 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 642 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 643 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
 644 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 645
 646 /**
 647   * @}
 648   */
 649
 650 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
 651   * @brief    Peripheral State functions
 652   * @{
 653   */
 654 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 655 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 656 /**
 657   * @}
 658   */
 659 /**
 660   * @}
 661   */
 662 /* Private Constants -------------------------------------------------------------*/
 663 /** @defgroup DMA_Private_Constants DMA Private Constants
 664   * @brief    DMA private defines and constants
 665   * @{
 666   */
 667 /**
 668   * @}
 669   */
 670
 671 /* Private macros ------------------------------------------------------------*/
 672 /** @defgroup DMA_Private_Macros DMA Private Macros
 673   * @brief    DMA private macros
 674   * @{
 675   */
 676 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 677                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 678                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 679
 680 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
 681
 682 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 683                                             ((STATE) == DMA_PINC_DISABLE))
 684
 685 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 686                                         ((STATE) == DMA_MINC_DISABLE))
 687
 688 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 689                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 690                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 691
 692 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 693                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 694                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 695
 696 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 697                            ((MODE) == DMA_CIRCULAR) || \
 698                            ((MODE) == DMA_PFCTRL))
 699
 700 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 701                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 702                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 703                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 704
 705 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
 706                                        ((STATE) == DMA_FIFOMODE_ENABLE))
 707
 708 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
 709                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
 710                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
 711                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
 712
 713 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
 714                                     ((BURST) == DMA_MBURST_INC4)   || \
 715                                     ((BURST) == DMA_MBURST_INC8)   || \
 716                                     ((BURST) == DMA_MBURST_INC16))
 717
 718 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
 719                                         ((BURST) == DMA_PBURST_INC4)   || \
 720                                         ((BURST) == DMA_PBURST_INC8)   || \
 721                                         ((BURST) == DMA_PBURST_INC16))
 722 /**
 723   * @}
 724   */
 725
 726 /* Private functions ---------------------------------------------------------*/
 727 /** @defgroup DMA_Private_Functions DMA Private Functions
 728   * @brief    DMA private  functions
 729   * @{
 730   */
 731 /**
 732   * @}
 733   */
 734
 735 /**
 736   * @}
 737   */
 738
 739 /**
 740   * @}
 741   */
 742
 743 #ifdef __cplusplus
 744 }
 745 #endif
 746
 747 #endif /* __STM32F7xx_HAL_DMA_H */
 748
 749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/