lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_dma2d.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of DMA2D HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32F7xx_HAL_DMA2D_H
  22 #define STM32F7xx_HAL_DMA2D_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif
  27
  28 #if defined (DMA2D)
  29
  30 /* Includes ------------------------------------------------------------------*/
  31 #include "stm32f7xx_hal_def.h"
  32
  33 /** @addtogroup STM32F7xx_HAL_Driver
  34   * @{
  35   */
  36
  37 /** @addtogroup DMA2D DMA2D
  38   * @brief DMA2D HAL module driver
  39   * @{
  40   */
  41
  42 /* Exported types ------------------------------------------------------------*/
  43 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
  44   * @{
  45   */
  46 #define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
  47
  48 /**
  49   * @brief DMA2D CLUT Structure definition
  50   */
  51 typedef struct
  52 {
  53   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
  54
  55   uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
  56                                          This parameter can be one value of @ref DMA2D_CLUT_CM. */
  57
  58   uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
  59                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
  60 } DMA2D_CLUTCfgTypeDef;
  61
  62 /**
  63   * @brief DMA2D Init structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
  68                                                 This parameter can be one value of @ref DMA2D_Mode. */
  69
  70   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
  71                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
  72
  73   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
  74                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
  75 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
  76   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
  77                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
  78
  79   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
  80                                                for the output pixel format converter.
  81                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
  82
  83 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
  84
  85
  86
  87
  88 } DMA2D_InitTypeDef;
  89
  90
  91 /**
  92   * @brief DMA2D Layer structure definition
  93   */
  94 typedef struct
  95 {
  96   uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
  97                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
  98
  99   uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
 100                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
 101
 102   uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
 103                                                This parameter can be one value of @ref DMA2D_Alpha_Mode. */
 104
 105   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
 106                                                This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
 107                                                @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
 108                                                Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
 109                                                - InputAlpha[24:31] is the alpha value ALPHA[0:7]
 110                                                - InputAlpha[16:23] is the red value RED[0:7]
 111                                                - InputAlpha[8:15] is the green value GREEN[0:7]
 112                                                - InputAlpha[0:7] is the blue value BLUE[0:7]. */
 113 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
 114   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
 115                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
 116
 117   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
 118                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
 119 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT  */
 120
 121
 122 } DMA2D_LayerCfgTypeDef;
 123
 124 /**
 125   * @brief  HAL DMA2D State structures definition
 126   */
 127 typedef enum
 128 {
 129   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
 130   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
 131   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
 132   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
 133   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
 134   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
 135 }HAL_DMA2D_StateTypeDef;
 136
 137 /**
 138   * @brief  DMA2D handle Structure definition
 139   */
 140 typedef struct __DMA2D_HandleTypeDef
 141 {
 142   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
 143
 144   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
 145
 146   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
 147
 148   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
 149
 150 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 151   void                        (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D line event callback.      */
 152
 153   void                        (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
 154
 155   void                        (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D Msp Init callback.          */
 156
 157   void                        (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback.        */
 158
 159 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
 160
 161   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
 162
 163   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
 164
 165   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
 166
 167   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
 168 } DMA2D_HandleTypeDef;
 169
 170 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 171 /**
 172   * @brief  HAL DMA2D Callback pointer definition
 173   */
 174 typedef  void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
 175 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
 176 /**
 177   * @}
 178   */
 179
 180 /* Exported constants --------------------------------------------------------*/
 181 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
 182   * @{
 183   */
 184
 185 /** @defgroup DMA2D_Error_Code DMA2D Error Code
 186   * @{
 187   */
 188 #define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */
 189 #define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */
 190 #define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */
 191 #define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */
 192 #define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */
 193 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 194 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */
 195 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 196
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup DMA2D_Mode DMA2D Mode
 202   * @{
 203   */
 204 #define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
 205 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
 206 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
 207 #define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
 208 /**
 209   * @}
 210   */
 211
 212 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
 213   * @{
 214   */
 215 #define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
 216 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
 217 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
 218 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
 219 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
 220 /**
 221   * @}
 222   */
 223
 224 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
 225   * @{
 226   */
 227 #define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */
 228 #define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */
 229 #define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */
 230 #define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */
 231 #define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */
 232 #define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */
 233 #define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */
 234 #define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */
 235 #define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */
 236 #define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */
 237 #define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */
 238 /**
 239   * @}
 240   */
 241
 242 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
 243   * @{
 244   */
 245 #define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value */
 246 #define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */
 247 #define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value
 248                                                                 with original alpha channel value                              */
 249 /**
 250   * @}
 251   */
 252
 253 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
 254 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
 255   * @{
 256   */
 257 #define DMA2D_REGULAR_ALPHA         0x00000000U  /*!< No modification of the alpha channel value */
 258 #define DMA2D_INVERTED_ALPHA        0x00000001U  /*!< Invert the alpha channel value */
 259 /**
 260   * @}
 261   */
 262
 263 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
 264   * @{
 265   */
 266 #define DMA2D_RB_REGULAR            0x00000000U  /*!< Select regular mode (RGB or ARGB) */
 267 #define DMA2D_RB_SWAP               0x00000001U  /*!< Select swap mode (BGR or ABGR) */
 268 /**
 269   * @}
 270   */
 271 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
 272
 273
 274
 275
 276
 277 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
 278   * @{
 279   */
 280 #define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */
 281 #define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */
 282 /**
 283   * @}
 284   */
 285
 286 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
 287   * @{
 288   */
 289 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
 290 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
 291 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
 292 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
 293 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
 294 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
 295 /**
 296   * @}
 297   */
 298
 299 /** @defgroup DMA2D_Flags DMA2D Flags
 300   * @{
 301   */
 302 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
 303 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
 304 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
 305 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
 306 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
 307 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
 308 /**
 309   * @}
 310   */
 311
 312 /** @defgroup DMA2D_Aliases DMA2D API Aliases
 313   * @{
 314   */
 315 #define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
 316 /**
 317   * @}
 318   */
 319
 320 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 321 /**
 322   * @brief  HAL DMA2D common Callback ID enumeration definition
 323   */
 324 typedef enum
 325 {
 326   HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */
 327   HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */
 328   HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */
 329   HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */
 330   HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */
 331   HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */
 332 }HAL_DMA2D_CallbackIDTypeDef;
 333 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
 334
 335
 336 /**
 337   * @}
 338   */
 339 /* Exported macros ------------------------------------------------------------*/
 340 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
 341   * @{
 342   */
 343
 344 /** @brief Reset DMA2D handle state
 345   * @param  __HANDLE__ specifies the DMA2D handle.
 346   * @retval None
 347   */
 348 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 349 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
 350                                                       (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
 351                                                       (__HANDLE__)->MspInitCallback = NULL;       \
 352                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
 353                                                      }while(0)
 354 #else
 355 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
 356 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
 357
 358
 359 /**
 360   * @brief  Enable the DMA2D.
 361   * @param  __HANDLE__ DMA2D handle
 362   * @retval None.
 363   */
 364 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
 365
 366
 367 /* Interrupt & Flag management */
 368 /**
 369   * @brief  Get the DMA2D pending flags.
 370   * @param  __HANDLE__ DMA2D handle
 371   * @param  __FLAG__ flag to check.
 372   *          This parameter can be any combination of the following values:
 373   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 374   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 375   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 376   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 377   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 378   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 379   * @retval The state of FLAG.
 380   */
 381 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
 382
 383 /**
 384   * @brief  Clear the DMA2D pending flags.
 385   * @param  __HANDLE__ DMA2D handle
 386   * @param  __FLAG__ specifies the flag to clear.
 387   *          This parameter can be any combination of the following values:
 388   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 389   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 390   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 391   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 392   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 393   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 394   * @retval None
 395   */
 396 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
 397
 398 /**
 399   * @brief  Enable the specified DMA2D interrupts.
 400   * @param  __HANDLE__ DMA2D handle
 401   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
 402   *          This parameter can be any combination of the following values:
 403   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 404   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 405   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 406   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 407   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 408   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 409   * @retval None
 410   */
 411 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 412
 413 /**
 414   * @brief  Disable the specified DMA2D interrupts.
 415   * @param  __HANDLE__ DMA2D handle
 416   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
 417   *          This parameter can be any combination of the following values:
 418   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 419   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 420   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 421   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 422   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 423   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 424   * @retval None
 425   */
 426 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 427
 428 /**
 429   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
 430   * @param  __HANDLE__ DMA2D handle
 431   * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.
 432   *          This parameter can be one of the following values:
 433   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 434   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 435   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 436   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 437   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 438   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 439   * @retval The state of INTERRUPT source.
 440   */
 441 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
 442
 443 /**
 444   * @}
 445   */
 446
 447 /* Exported functions --------------------------------------------------------*/
 448 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
 449   * @{
 450   */
 451
 452 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
 453   * @{
 454   */
 455
 456 /* Initialization and de-initialization functions *******************************/
 457 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
 458 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
 459 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
 460 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
 461 /* Callbacks Register/UnRegister functions  ***********************************/
 462 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 463 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
 464 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
 465 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
 466
 467 /**
 468   * @}
 469   */
 470
 471
 472 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
 473   * @{
 474   */
 475
 476 /* IO operation functions *******************************************************/
 477 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 478 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
 479 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 480 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 481 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
 482 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
 483 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
 484 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 485 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 486 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 487 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 488 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 489 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 490 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
 491 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
 492 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
 493 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
 494
 495 /**
 496   * @}
 497   */
 498
 499 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
 500   * @{
 501   */
 502
 503 /* Peripheral Control functions *************************************************/
 504 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 505 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 506 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
 507 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 508 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 509 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
 510
 511 /**
 512   * @}
 513   */
 514
 515 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
 516   * @{
 517   */
 518
 519 /* Peripheral State functions ***************************************************/
 520 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
 521 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 522
 523 /**
 524   * @}
 525   */
 526
 527 /**
 528   * @}
 529   */
 530
 531 /* Private constants ---------------------------------------------------------*/
 532
 533 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
 534   * @{
 535   */
 536
 537 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
 538   * @{
 539   */
 540 #define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
 541 /**
 542   * @}
 543   */
 544
 545 /** @defgroup DMA2D_Color_Value DMA2D Color Value
 546   * @{
 547   */
 548 #define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */
 549 /**
 550   * @}
 551   */
 552
 553 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
 554   * @{
 555   */
 556 #define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
 557 /**
 558   * @}
 559   */
 560
 561 /** @defgroup DMA2D_Layers DMA2D Layers
 562   * @{
 563   */
 564 #define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */
 565 #define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */
 566 /**
 567   * @}
 568   */
 569
 570 /** @defgroup DMA2D_Offset DMA2D Offset
 571   * @{
 572   */
 573 #define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
 574 /**
 575   * @}
 576   */
 577
 578 /** @defgroup DMA2D_Size DMA2D Size
 579   * @{
 580   */
 581 #define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
 582 #define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
 583 /**
 584   * @}
 585   */
 586
 587 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
 588   * @{
 589   */
 590 #define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */
 591 /**
 592   * @}
 593   */
 594
 595 /**
 596   * @}
 597   */
 598
 599
 600 /* Private macros ------------------------------------------------------------*/
 601 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
 602   * @{
 603   */
 604 #define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
 605
 606 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
 607                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
 608
 609 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
 610                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
 611                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
 612
 613 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
 614 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
 615 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
 616 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
 617
 618 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
 619                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
 620                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
 621                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
 622                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
 623                                                ((INPUT_CM) == DMA2D_INPUT_A4))
 624
 625 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
 626                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
 627                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
 628
 629 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
 630 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
 631                                                  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
 632
 633 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
 634                                    ((RB_Swap) == DMA2D_RB_SWAP))
 635 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
 636
 637
 638
 639
 640 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
 641 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
 642 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
 643 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
 644                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
 645                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
 646 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
 647                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
 648                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
 649 /**
 650   * @}
 651   */
 652
 653 /**
 654   * @}
 655   */
 656
 657 /**
 658   * @}
 659   */
 660
 661 #endif /* defined (DMA2D) */
 662
 663 #ifdef __cplusplus
 664 }
 665 #endif
 666
 667 #endif /* STM32F7xx_HAL_DMA2D_H */
 668
 669
 670 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/