?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_dsi.h
blob38cb0e5718b422e097ef15ad582bba5a709d53c1
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dsi.h
4 * @author MCD Application Team
5 * @brief Header file of DSI HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_DSI_H
22 #define STM32F7xx_HAL_DSI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 #if defined(DSI)
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32f7xx_hal_def.h"
31
32 /** @addtogroup STM32F7xx_HAL_Driver
33 * @{
34 */
35
36 /** @defgroup DSI DSI
37 * @brief DSI HAL module driver
38 * @{
39 */
40
41 /* Exported types ------------------------------------------------------------*/
42 /**
43 * @brief DSI Init Structure definition
44 */
45 typedef struct
46 {
47 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
48 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
49
50 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
51 The values 0 and 1 stop the TX_ESC clock generation */
52
53 uint32_t NumberOfLanes; /*!< Number of lanes
54 This parameter can be any value of @ref DSI_Number_Of_Lanes */
55
56 } DSI_InitTypeDef;
57
58 /**
59 * @brief DSI PLL Clock structure definition
60 */
61 typedef struct
62 {
63 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
64 This parameter must be a value between 10 and 125 */
65
66 uint32_t PLLIDF; /*!< PLL Input Division Factor
67 This parameter can be any value of @ref DSI_PLL_IDF */
68
69 uint32_t PLLODF; /*!< PLL Output Division Factor
70 This parameter can be any value of @ref DSI_PLL_ODF */
71
72 } DSI_PLLInitTypeDef;
73
74 /**
75 * @brief DSI Video mode configuration
76 */
77 typedef struct
78 {
79 uint32_t VirtualChannelID; /*!< Virtual channel ID */
80
81 uint32_t ColorCoding; /*!< Color coding for LTDC interface
82 This parameter can be any value of @ref DSI_Color_Coding */
83
84 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
85 18-bit configuration).
86 This parameter can be any value of @ref DSI_LooselyPacked */
87
88 uint32_t Mode; /*!< Video mode type
89 This parameter can be any value of @ref DSI_Video_Mode_Type */
90
91 uint32_t PacketSize; /*!< Video packet size */
92
93 uint32_t NumberOfChunks; /*!< Number of chunks */
94
95 uint32_t NullPacketSize; /*!< Null packet size */
96
97 uint32_t HSPolarity; /*!< HSYNC pin polarity
98 This parameter can be any value of @ref DSI_HSYNC_Polarity */
99
100 uint32_t VSPolarity; /*!< VSYNC pin polarity
101 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
102
103 uint32_t DEPolarity; /*!< Data Enable pin polarity
104 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
105
106 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
107
108 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
109
110 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
111
112 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
113
114 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
115
116 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
117
118 uint32_t VerticalActive; /*!< Vertical active duration */
119
120 uint32_t LPCommandEnable; /*!< Low-power command enable
121 This parameter can be any value of @ref DSI_LP_Command */
122
123 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
124 can fit in a line during VSA, VBP and VFP regions */
125
126 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
127 can fit in a line during VACT region */
128
129 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
130 This parameter can be any value of @ref DSI_LP_HFP */
131
132 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
133 This parameter can be any value of @ref DSI_LP_HBP */
134
135 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
136 This parameter can be any value of @ref DSI_LP_VACT */
137
138 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
139 This parameter can be any value of @ref DSI_LP_VFP */
140
141 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
142 This parameter can be any value of @ref DSI_LP_VBP */
143
144 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
145 This parameter can be any value of @ref DSI_LP_VSYNC */
146
147 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
148 This parameter can be any value of @ref DSI_FBTA_acknowledge */
149
150 } DSI_VidCfgTypeDef;
151
152 /**
153 * @brief DSI Adapted command mode configuration
154 */
155 typedef struct
156 {
157 uint32_t VirtualChannelID; /*!< Virtual channel ID */
158
159 uint32_t ColorCoding; /*!< Color coding for LTDC interface
160 This parameter can be any value of @ref DSI_Color_Coding */
161
162 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
163 pixels. This parameter can be any value between 0x00 and 0xFFFFU */
164
165 uint32_t TearingEffectSource; /*!< Tearing effect source
166 This parameter can be any value of @ref DSI_TearingEffectSource */
167
168 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
169 This parameter can be any value of @ref DSI_TearingEffectPolarity */
170
171 uint32_t HSPolarity; /*!< HSYNC pin polarity
172 This parameter can be any value of @ref DSI_HSYNC_Polarity */
173
174 uint32_t VSPolarity; /*!< VSYNC pin polarity
175 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
176
177 uint32_t DEPolarity; /*!< Data Enable pin polarity
178 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
179
180 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
181 This parameter can be any value of @ref DSI_Vsync_Polarity */
182
183 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
184 This parameter can be any value of @ref DSI_AutomaticRefresh */
185
186 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
187 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
188
189 } DSI_CmdCfgTypeDef;
190
191 /**
192 * @brief DSI command transmission mode configuration
193 */
194 typedef struct
195 {
196 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
197 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
198
199 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
200 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
201
202 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
203 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
204
205 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
206 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
207
208 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
209 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
210
211 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
212 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
213
214 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
215 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
216
217 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
218 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
219
220 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
221 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
222
223 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
224 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
225
226 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
227 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
228
229 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
230 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
231
232 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
233 This parameter can be any value of @ref DSI_AcknowledgeRequest */
234
235 } DSI_LPCmdTypeDef;
236
237 /**
238 * @brief DSI PHY Timings definition
239 */
240 typedef struct
241 {
242 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
243 to low-power transmission */
244
245 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
246 to high-speed transmission */
247
248 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
249 to low-power transmission */
250
251 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
252 to high-speed transmission */
253
254 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
255
256 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
257 Stop state */
258
259 } DSI_PHY_TimerTypeDef;
260
261 /**
262 * @brief DSI HOST Timeouts definition
263 */
264 typedef struct
265 {
266 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
267
268 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
269
270 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
271
272 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
273
274 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
275
276 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
277
278 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
279 This parameter can be any value of @ref DSI_HS_PrespMode */
280
281 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
282
283 uint32_t BTATimeout; /*!< BTA time-out */
284
285 } DSI_HOST_TimeoutTypeDef;
286
287 /**
288 * @brief DSI States Structure definition
289 */
290 typedef enum
291 {
292 HAL_DSI_STATE_RESET = 0x00U,
293 HAL_DSI_STATE_READY = 0x01U,
294 HAL_DSI_STATE_ERROR = 0x02U,
295 HAL_DSI_STATE_BUSY = 0x03U,
296 HAL_DSI_STATE_TIMEOUT = 0x04U
297 } HAL_DSI_StateTypeDef;
298
299 /**
300 * @brief DSI Handle Structure definition
301 */
302 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
303 typedef struct __DSI_HandleTypeDef
304 #else
305 typedef struct
306 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
307 {
308 DSI_TypeDef *Instance; /*!< Register base address */
309 DSI_InitTypeDef Init; /*!< DSI required parameters */
310 HAL_LockTypeDef Lock; /*!< DSI peripheral status */
311 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
312 __IO uint32_t ErrorCode; /*!< DSI Error code */
313 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
314
315 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
316 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */
317 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */
318 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */
319
320 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */
321 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */
322
323 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
324
325 } DSI_HandleTypeDef;
326
327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
328 /**
329 * @brief HAL DSI Callback ID enumeration definition
330 */
331 typedef enum
332 {
333 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */
334 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */
335
336 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */
337 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */
338 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */
339
340 } HAL_DSI_CallbackIDTypeDef;
341
342 /**
343 * @brief HAL DSI Callback pointer definition
344 */
345 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
346
347 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
348
349 /* Exported constants --------------------------------------------------------*/
350 /** @defgroup DSI_DCS_Command DSI DCS Command
351 * @{
352 */
353 #define DSI_ENTER_IDLE_MODE 0x39U
354 #define DSI_ENTER_INVERT_MODE 0x21U
355 #define DSI_ENTER_NORMAL_MODE 0x13U
356 #define DSI_ENTER_PARTIAL_MODE 0x12U
357 #define DSI_ENTER_SLEEP_MODE 0x10U
358 #define DSI_EXIT_IDLE_MODE 0x38U
359 #define DSI_EXIT_INVERT_MODE 0x20U
360 #define DSI_EXIT_SLEEP_MODE 0x11U
361 #define DSI_GET_3D_CONTROL 0x3FU
362 #define DSI_GET_ADDRESS_MODE 0x0BU
363 #define DSI_GET_BLUE_CHANNEL 0x08U
364 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
365 #define DSI_GET_DISPLAY_MODE 0x0DU
366 #define DSI_GET_GREEN_CHANNEL 0x07U
367 #define DSI_GET_PIXEL_FORMAT 0x0CU
368 #define DSI_GET_POWER_MODE 0x0AU
369 #define DSI_GET_RED_CHANNEL 0x06U
370 #define DSI_GET_SCANLINE 0x45U
371 #define DSI_GET_SIGNAL_MODE 0x0EU
372 #define DSI_NOP 0x00U
373 #define DSI_READ_DDB_CONTINUE 0xA8U
374 #define DSI_READ_DDB_START 0xA1U
375 #define DSI_READ_MEMORY_CONTINUE 0x3EU
376 #define DSI_READ_MEMORY_START 0x2EU
377 #define DSI_SET_3D_CONTROL 0x3DU
378 #define DSI_SET_ADDRESS_MODE 0x36U
379 #define DSI_SET_COLUMN_ADDRESS 0x2AU
380 #define DSI_SET_DISPLAY_OFF 0x28U
381 #define DSI_SET_DISPLAY_ON 0x29U
382 #define DSI_SET_GAMMA_CURVE 0x26U
383 #define DSI_SET_PAGE_ADDRESS 0x2BU
384 #define DSI_SET_PARTIAL_COLUMNS 0x31U
385 #define DSI_SET_PARTIAL_ROWS 0x30U
386 #define DSI_SET_PIXEL_FORMAT 0x3AU
387 #define DSI_SET_SCROLL_AREA 0x33U
388 #define DSI_SET_SCROLL_START 0x37U
389 #define DSI_SET_TEAR_OFF 0x34U
390 #define DSI_SET_TEAR_ON 0x35U
391 #define DSI_SET_TEAR_SCANLINE 0x44U
392 #define DSI_SET_VSYNC_TIMING 0x40U
393 #define DSI_SOFT_RESET 0x01U
394 #define DSI_WRITE_LUT 0x2DU
395 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
396 #define DSI_WRITE_MEMORY_START 0x2CU
397 /**
398 * @}
399 */
400
401 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
402 * @{
403 */
404 #define DSI_VID_MODE_NB_PULSES 0U
405 #define DSI_VID_MODE_NB_EVENTS 1U
406 #define DSI_VID_MODE_BURST 2U
407 /**
408 * @}
409 */
410
411 /** @defgroup DSI_Color_Mode DSI Color Mode
412 * @{
413 */
414 #define DSI_COLOR_MODE_FULL 0x00000000U
415 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
416 /**
417 * @}
418 */
419
420 /** @defgroup DSI_ShutDown DSI ShutDown
421 * @{
422 */
423 #define DSI_DISPLAY_ON 0x00000000U
424 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
425 /**
426 * @}
427 */
428
429 /** @defgroup DSI_LP_Command DSI LP Command
430 * @{
431 */
432 #define DSI_LP_COMMAND_DISABLE 0x00000000U
433 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
434 /**
435 * @}
436 */
437
438 /** @defgroup DSI_LP_HFP DSI LP HFP
439 * @{
440 */
441 #define DSI_LP_HFP_DISABLE 0x00000000U
442 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
443 /**
444 * @}
445 */
446
447 /** @defgroup DSI_LP_HBP DSI LP HBP
448 * @{
449 */
450 #define DSI_LP_HBP_DISABLE 0x00000000U
451 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
452 /**
453 * @}
454 */
455
456 /** @defgroup DSI_LP_VACT DSI LP VACT
457 * @{
458 */
459 #define DSI_LP_VACT_DISABLE 0x00000000U
460 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
461 /**
462 * @}
463 */
464
465 /** @defgroup DSI_LP_VFP DSI LP VFP
466 * @{
467 */
468 #define DSI_LP_VFP_DISABLE 0x00000000U
469 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
470 /**
471 * @}
472 */
473
474 /** @defgroup DSI_LP_VBP DSI LP VBP
475 * @{
476 */
477 #define DSI_LP_VBP_DISABLE 0x00000000U
478 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
479 /**
480 * @}
481 */
482
483 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
484 * @{
485 */
486 #define DSI_LP_VSYNC_DISABLE 0x00000000U
487 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
488 /**
489 * @}
490 */
491
492 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
493 * @{
494 */
495 #define DSI_FBTAA_DISABLE 0x00000000U
496 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
497 /**
498 * @}
499 */
500
501 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
502 * @{
503 */
504 #define DSI_TE_DSILINK 0x00000000U
505 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
506 /**
507 * @}
508 */
509
510 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
511 * @{
512 */
513 #define DSI_TE_RISING_EDGE 0x00000000U
514 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
515 /**
516 * @}
517 */
518
519 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
520 * @{
521 */
522 #define DSI_VSYNC_FALLING 0x00000000U
523 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
524 /**
525 * @}
526 */
527
528 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
529 * @{
530 */
531 #define DSI_AR_DISABLE 0x00000000U
532 #define DSI_AR_ENABLE DSI_WCFGR_AR
533 /**
534 * @}
535 */
536
537 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
538 * @{
539 */
540 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
541 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
542 /**
543 * @}
544 */
545
546 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
547 * @{
548 */
549 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
550 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
551 /**
552 * @}
553 */
554
555 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
556 * @{
557 */
558 #define DSI_LP_GSW0P_DISABLE 0x00000000U
559 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
560 /**
561 * @}
562 */
563
564 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
565 * @{
566 */
567 #define DSI_LP_GSW1P_DISABLE 0x00000000U
568 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
569 /**
570 * @}
571 */
572
573 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
574 * @{
575 */
576 #define DSI_LP_GSW2P_DISABLE 0x00000000U
577 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
578 /**
579 * @}
580 */
581
582 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
583 * @{
584 */
585 #define DSI_LP_GSR0P_DISABLE 0x00000000U
586 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
587 /**
588 * @}
589 */
590
591 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
592 * @{
593 */
594 #define DSI_LP_GSR1P_DISABLE 0x00000000U
595 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
596 /**
597 * @}
598 */
599
600 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
601 * @{
602 */
603 #define DSI_LP_GSR2P_DISABLE 0x00000000U
604 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
605 /**
606 * @}
607 */
608
609 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
610 * @{
611 */
612 #define DSI_LP_GLW_DISABLE 0x00000000U
613 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
614 /**
615 * @}
616 */
617
618 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
619 * @{
620 */
621 #define DSI_LP_DSW0P_DISABLE 0x00000000U
622 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
623 /**
624 * @}
625 */
626
627 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
628 * @{
629 */
630 #define DSI_LP_DSW1P_DISABLE 0x00000000U
631 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
632 /**
633 * @}
634 */
635
636 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
637 * @{
638 */
639 #define DSI_LP_DSR0P_DISABLE 0x00000000U
640 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
641 /**
642 * @}
643 */
644
645 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
646 * @{
647 */
648 #define DSI_LP_DLW_DISABLE 0x00000000U
649 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
650 /**
651 * @}
652 */
653
654 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
655 * @{
656 */
657 #define DSI_LP_MRDP_DISABLE 0x00000000U
658 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
659 /**
660 * @}
661 */
662
663 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
664 * @{
665 */
666 #define DSI_HS_PM_DISABLE 0x00000000U
667 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
668 /**
669 * @}
670 */
671
672
673 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
674 * @{
675 */
676 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
677 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
678 /**
679 * @}
680 */
681
682 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
683 * @{
684 */
685 #define DSI_ONE_DATA_LANE 0U
686 #define DSI_TWO_DATA_LANES 1U
687 /**
688 * @}
689 */
690
691 /** @defgroup DSI_FlowControl DSI Flow Control
692 * @{
693 */
694 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
695 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
696 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
697 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
698 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
699 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
700 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
701 DSI_FLOW_CONTROL_EOTP_TX)
702 /**
703 * @}
704 */
705
706 /** @defgroup DSI_Color_Coding DSI Color Coding
707 * @{
708 */
709 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
710 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
711 #define DSI_RGB888 0x00000005U
712 /**
713 * @}
714 */
715
716 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
717 * @{
718 */
719 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
720 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
721 /**
722 * @}
723 */
724
725 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
726 * @{
727 */
728 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
729 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
730 /**
731 * @}
732 */
733
734 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
735 * @{
736 */
737 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
738 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
739 /**
740 * @}
741 */
742
743 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
744 * @{
745 */
746 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
747 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
748 /**
749 * @}
750 */
751
752 /** @defgroup DSI_PLL_IDF DSI PLL IDF
753 * @{
754 */
755 #define DSI_PLL_IN_DIV1 0x00000001U
756 #define DSI_PLL_IN_DIV2 0x00000002U
757 #define DSI_PLL_IN_DIV3 0x00000003U
758 #define DSI_PLL_IN_DIV4 0x00000004U
759 #define DSI_PLL_IN_DIV5 0x00000005U
760 #define DSI_PLL_IN_DIV6 0x00000006U
761 #define DSI_PLL_IN_DIV7 0x00000007U
762 /**
763 * @}
764 */
765
766 /** @defgroup DSI_PLL_ODF DSI PLL ODF
767 * @{
768 */
769 #define DSI_PLL_OUT_DIV1 0x00000000U
770 #define DSI_PLL_OUT_DIV2 0x00000001U
771 #define DSI_PLL_OUT_DIV4 0x00000002U
772 #define DSI_PLL_OUT_DIV8 0x00000003U
773 /**
774 * @}
775 */
776
777 /** @defgroup DSI_Flags DSI Flags
778 * @{
779 */
780 #define DSI_FLAG_TE DSI_WISR_TEIF
781 #define DSI_FLAG_ER DSI_WISR_ERIF
782 #define DSI_FLAG_BUSY DSI_WISR_BUSY
783 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
784 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
785 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
786 #define DSI_FLAG_RRS DSI_WISR_RRS
787 #define DSI_FLAG_RR DSI_WISR_RRIF
788 /**
789 * @}
790 */
791
792 /** @defgroup DSI_Interrupts DSI Interrupts
793 * @{
794 */
795 #define DSI_IT_TE DSI_WIER_TEIE
796 #define DSI_IT_ER DSI_WIER_ERIE
797 #define DSI_IT_PLLL DSI_WIER_PLLLIE
798 #define DSI_IT_PLLU DSI_WIER_PLLUIE
799 #define DSI_IT_RR DSI_WIER_RRIE
800 /**
801 * @}
802 */
803
804 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
805 * @{
806 */
807 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
808 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
809 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
810 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
811 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
812 /**
813 * @}
814 */
815
816 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
817 * @{
818 */
819 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
820 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
821 /**
822 * @}
823 */
824
825 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
826 * @{
827 */
828 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
829 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
830 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
831 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
832 /**
833 * @}
834 */
835
836 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
837 * @{
838 */
839 #define HAL_DSI_ERROR_NONE 0U
840 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
841 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
842 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
843 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
844 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
845 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
846 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
847 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
848 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
849 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
850 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
851 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
852 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
853 /**
854 * @}
855 */
856
857 /** @defgroup DSI_Lane_Group DSI Lane Group
858 * @{
859 */
860 #define DSI_CLOCK_LANE 0x00000000U
861 #define DSI_DATA_LANES 0x00000001U
862 /**
863 * @}
864 */
865
866 /** @defgroup DSI_Communication_Delay DSI Communication Delay
867 * @{
868 */
869 #define DSI_SLEW_RATE_HSTX 0x00000000U
870 #define DSI_SLEW_RATE_LPTX 0x00000001U
871 #define DSI_HS_DELAY 0x00000002U
872 /**
873 * @}
874 */
875
876 /** @defgroup DSI_CustomLane DSI CustomLane
877 * @{
878 */
879 #define DSI_SWAP_LANE_PINS 0x00000000U
880 #define DSI_INVERT_HS_SIGNAL 0x00000001U
881 /**
882 * @}
883 */
884
885 /** @defgroup DSI_Lane_Select DSI Lane Select
886 * @{
887 */
888 #define DSI_CLK_LANE 0x00000000U
889 #define DSI_DATA_LANE0 0x00000001U
890 #define DSI_DATA_LANE1 0x00000002U
891 /**
892 * @}
893 */
894
895 /** @defgroup DSI_PHY_Timing DSI PHY Timing
896 * @{
897 */
898 #define DSI_TCLK_POST 0x00000000U
899 #define DSI_TLPX_CLK 0x00000001U
900 #define DSI_THS_EXIT 0x00000002U
901 #define DSI_TLPX_DATA 0x00000003U
902 #define DSI_THS_ZERO 0x00000004U
903 #define DSI_THS_TRAIL 0x00000005U
904 #define DSI_THS_PREPARE 0x00000006U
905 #define DSI_TCLK_ZERO 0x00000007U
906 #define DSI_TCLK_PREPARE 0x00000008U
907 /**
908 * @}
909 */
910
911 /* Exported macros -----------------------------------------------------------*/
912 /**
913 * @brief Reset DSI handle state.
914 * @param __HANDLE__: DSI handle
915 * @retval None
916 */
917 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
918 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
919 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
920 (__HANDLE__)->MspInitCallback = NULL; \
921 (__HANDLE__)->MspDeInitCallback = NULL; \
922 } while(0)
923 #else
924 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
925 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
926
927 /**
928 * @brief Enables the DSI host.
929 * @param __HANDLE__ DSI handle
930 * @retval None.
931 */
932 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
933 __IO uint32_t tmpreg = 0x00U; \
934 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
935 /* Delay after an DSI Host enabling */ \
936 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
937 UNUSED(tmpreg); \
938 } while(0U)
939
940 /**
941 * @brief Disables the DSI host.
942 * @param __HANDLE__ DSI handle
943 * @retval None.
944 */
945 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
946 __IO uint32_t tmpreg = 0x00U; \
947 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
948 /* Delay after an DSI Host disabling */ \
949 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
950 UNUSED(tmpreg); \
951 } while(0U)
952
953 /**
954 * @brief Enables the DSI wrapper.
955 * @param __HANDLE__ DSI handle
956 * @retval None.
957 */
958 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
959 __IO uint32_t tmpreg = 0x00U; \
960 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
961 /* Delay after an DSI warpper enabling */ \
962 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
963 UNUSED(tmpreg); \
964 } while(0U)
965
966 /**
967 * @brief Disable the DSI wrapper.
968 * @param __HANDLE__ DSI handle
969 * @retval None.
970 */
971 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
972 __IO uint32_t tmpreg = 0x00U; \
973 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
974 /* Delay after an DSI warpper disabling*/ \
975 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
976 UNUSED(tmpreg); \
977 } while(0U)
978
979 /**
980 * @brief Enables the DSI PLL.
981 * @param __HANDLE__ DSI handle
982 * @retval None.
983 */
984 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
985 __IO uint32_t tmpreg = 0x00U; \
986 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
987 /* Delay after an DSI PLL enabling */ \
988 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
989 UNUSED(tmpreg); \
990 } while(0U)
991
992 /**
993 * @brief Disables the DSI PLL.
994 * @param __HANDLE__ DSI handle
995 * @retval None.
996 */
997 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
998 __IO uint32_t tmpreg = 0x00U; \
999 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1000 /* Delay after an DSI PLL disabling */ \
1001 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1002 UNUSED(tmpreg); \
1003 } while(0U)
1004
1005 /**
1006 * @brief Enables the DSI regulator.
1007 * @param __HANDLE__ DSI handle
1008 * @retval None.
1009 */
1010 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1011 __IO uint32_t tmpreg = 0x00U; \
1012 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1013 /* Delay after an DSI regulator enabling */ \
1014 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1015 UNUSED(tmpreg); \
1016 } while(0U)
1017
1018 /**
1019 * @brief Disables the DSI regulator.
1020 * @param __HANDLE__ DSI handle
1021 * @retval None.
1022 */
1023 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1024 __IO uint32_t tmpreg = 0x00U; \
1025 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1026 /* Delay after an DSI regulator disabling */ \
1027 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1028 UNUSED(tmpreg); \
1029 } while(0U)
1030
1031 /**
1032 * @brief Get the DSI pending flags.
1033 * @param __HANDLE__ DSI handle.
1034 * @param __FLAG__ Get the specified flag.
1035 * This parameter can be any combination of the following values:
1036 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1037 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1038 * @arg DSI_FLAG_BUSY : Busy Flag
1039 * @arg DSI_FLAG_PLLLS: PLL Lock Status
1040 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1041 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1042 * @arg DSI_FLAG_RRS : Regulator Ready Flag
1043 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1044 * @retval The state of FLAG (SET or RESET).
1045 */
1046 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1047
1048 /**
1049 * @brief Clears the DSI pending flags.
1050 * @param __HANDLE__ DSI handle.
1051 * @param __FLAG__ specifies the flag to clear.
1052 * This parameter can be any combination of the following values:
1053 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1054 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1055 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1056 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1057 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1058 * @retval None
1059 */
1060 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1061
1062 /**
1063 * @brief Enables the specified DSI interrupts.
1064 * @param __HANDLE__ DSI handle.
1065 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
1066 * This parameter can be any combination of the following values:
1067 * @arg DSI_IT_TE : Tearing Effect Interrupt
1068 * @arg DSI_IT_ER : End of Refresh Interrupt
1069 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1070 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1071 * @arg DSI_IT_RR : Regulator Ready Interrupt
1072 * @retval None
1073 */
1074 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1075
1076 /**
1077 * @brief Disables the specified DSI interrupts.
1078 * @param __HANDLE__ DSI handle
1079 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
1080 * This parameter can be any combination of the following values:
1081 * @arg DSI_IT_TE : Tearing Effect Interrupt
1082 * @arg DSI_IT_ER : End of Refresh Interrupt
1083 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1084 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1085 * @arg DSI_IT_RR : Regulator Ready Interrupt
1086 * @retval None
1087 */
1088 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1089
1090 /**
1091 * @brief Checks whether the specified DSI interrupt source is enabled or not.
1092 * @param __HANDLE__ DSI handle
1093 * @param __INTERRUPT__ specifies the DSI interrupt source to check.
1094 * This parameter can be one of the following values:
1095 * @arg DSI_IT_TE : Tearing Effect Interrupt
1096 * @arg DSI_IT_ER : End of Refresh Interrupt
1097 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1098 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1099 * @arg DSI_IT_RR : Regulator Ready Interrupt
1100 * @retval The state of INTERRUPT (SET or RESET).
1101 */
1102 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1103
1104 /* Exported functions --------------------------------------------------------*/
1105 /** @defgroup DSI_Exported_Functions DSI Exported Functions
1106 * @{
1107 */
1108 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1109 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1110 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1111 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1112
1113 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1114 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1115 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1116 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1117
1118 /* Callbacks Register/UnRegister functions ***********************************/
1119 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1120 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1121 pDSI_CallbackTypeDef pCallback);
1122 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1123 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1124
1125 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1126 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1127 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1128 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1129 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1130 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1131 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1132 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1133 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1134 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1135 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1136 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1137 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1138 uint32_t ChannelID,
1139 uint32_t Mode,
1140 uint32_t Param1,
1141 uint32_t Param2);
1142 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1143 uint32_t ChannelID,
1144 uint32_t Mode,
1145 uint32_t NbParams,
1146 uint32_t Param1,
1147 uint8_t *ParametersTable);
1148 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1149 uint32_t ChannelNbr,
1150 uint8_t *Array,
1151 uint32_t Size,
1152 uint32_t Mode,
1153 uint32_t DCSCmd,
1154 uint8_t *ParametersTable);
1155 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1156 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1157 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1158 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1159
1160 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1161 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1162
1163 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1164 uint32_t Value);
1165 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1166 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1167 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1168 FunctionalState State);
1169 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1170 uint32_t Value);
1171 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1172 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1173 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1174 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1175 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1176
1177 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1178 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1179 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1180 /**
1181 * @}
1182 */
1183
1184 /* Private types -------------------------------------------------------------*/
1185 /** @defgroup DSI_Private_Types DSI Private Types
1186 * @{
1187 */
1188
1189 /**
1190 * @}
1191 */
1192
1193 /* Private defines -----------------------------------------------------------*/
1194 /** @defgroup DSI_Private_Defines DSI Private Defines
1195 * @{
1196 */
1197
1198 /**
1199 * @}
1200 */
1201
1202 /* Private variables ---------------------------------------------------------*/
1203 /** @defgroup DSI_Private_Variables DSI Private Variables
1204 * @{
1205 */
1206
1207 /**
1208 * @}
1209 */
1210
1211 /* Private constants ---------------------------------------------------------*/
1212 /** @defgroup DSI_Private_Constants DSI Private Constants
1213 * @{
1214 */
1215 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
1216 /**
1217 * @}
1218 */
1219
1220 /* Private macros ------------------------------------------------------------*/
1221 /** @defgroup DSI_Private_Macros DSI Private Macros
1222 * @{
1223 */
1224 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1225 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1226 ((IDF) == DSI_PLL_IN_DIV2) || \
1227 ((IDF) == DSI_PLL_IN_DIV3) || \
1228 ((IDF) == DSI_PLL_IN_DIV4) || \
1229 ((IDF) == DSI_PLL_IN_DIV5) || \
1230 ((IDF) == DSI_PLL_IN_DIV6) || \
1231 ((IDF) == DSI_PLL_IN_DIV7))
1232 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1233 ((ODF) == DSI_PLL_OUT_DIV2) || \
1234 ((ODF) == DSI_PLL_OUT_DIV4) || \
1235 ((ODF) == DSI_PLL_OUT_DIV8))
1236 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1237 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1238 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1239 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1240 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1241 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1242 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1243 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1244 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1245 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1246 ((VideoModeType) == DSI_VID_MODE_BURST))
1247 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1248 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1249 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1250 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1251 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1252 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1253 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1254 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1255 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1256 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1257 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1258 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1259 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1260 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1261 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1262 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1263 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1264 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1265 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1266 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1267 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1268 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1269 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1270 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1271 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1272 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1273 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1274 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1275 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1276 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1277 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1278 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1279 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1280 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1281 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1282 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1283 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1284 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1285 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1286 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1287 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1288 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1289 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1290 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1291 ((Timing) == DSI_TLPX_CLK ) || \
1292 ((Timing) == DSI_THS_EXIT ) || \
1293 ((Timing) == DSI_TLPX_DATA ) || \
1294 ((Timing) == DSI_THS_ZERO ) || \
1295 ((Timing) == DSI_THS_TRAIL ) || \
1296 ((Timing) == DSI_THS_PREPARE ) || \
1297 ((Timing) == DSI_TCLK_ZERO ) || \
1298 ((Timing) == DSI_TCLK_PREPARE))
1299
1300 /**
1301 * @}
1302 */
1303
1304 /* Private functions prototypes ----------------------------------------------*/
1305 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
1306 * @{
1307 */
1308
1309 /**
1310 * @}
1311 */
1312
1313 /* Private functions ---------------------------------------------------------*/
1314 /** @defgroup DSI_Private_Functions DSI Private Functions
1315 * @{
1316 */
1317
1318 /**
1319 * @}
1320 */
1321
1322 /**
1323 * @}
1324 */
1325
1326 /**
1327 * @}
1328 */
1329 #endif /* DSI */
1330
1331 #ifdef __cplusplus
1332 }
1333 #endif
1334
1335 #endif /* STM32F7xx_HAL_DSI_H */
1336
1337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/