lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of NAND HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32F7xx_HAL_NAND_H
  22 #define __STM32F7xx_HAL_NAND_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32f7xx_ll_fmc.h"
  30
  31 /** @addtogroup STM32F7xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup NAND
  36   * @{
  37   */
  38
  39 /* Exported typedef ----------------------------------------------------------*/
  40 /* Exported types ------------------------------------------------------------*/
  41 /** @defgroup NAND_Exported_Types NAND Exported Types
  42   * @{
  43   */
  44
  45 /**
  46   * @brief  HAL NAND State structures definition
  47   */
  48 typedef enum
  49 {
  50   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  51   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  52   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  53   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  54 }HAL_NAND_StateTypeDef;
  55
  56 /**
  57   * @brief  NAND Memory electronic signature Structure definition
  58   */
  59 typedef struct
  60 {
  61   /*<! NAND memory electronic signature maker and device IDs */
  62
  63   uint8_t Maker_Id;
  64
  65   uint8_t Device_Id;
  66
  67   uint8_t Third_Id;
  68
  69   uint8_t Fourth_Id;
  70 }NAND_IDTypeDef;
  71
  72 /**
  73   * @brief  NAND Memory address Structure definition
  74   */
  75 typedef struct
  76 {
  77   uint16_t Page;   /*!< NAND memory Page address  */
  78
  79   uint16_t Plane;   /*!< NAND memory Zone address  */
  80
  81   uint16_t Block;  /*!< NAND memory Block address */
  82
  83 }NAND_AddressTypeDef;
  84
  85 /**
  86   * @brief  NAND Memory info Structure definition
  87   */
  88 typedef struct
  89 {
  90   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
  91                                               for 8 bits adressing or words for 16 bits addressing             */
  92
  93   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
  94                                               for 8 bits adressing or words for 16 bits addressing             */
  95
  96   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
  97
  98   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
  99
 100   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 101
 102   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
 103
 104   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 105                                               parameter is mandatory for some NAND parts after the read
 106                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 107                                               Example: Toshiba THTH58BYG3S0HBAI6.
 108                                               This parameter could be ENABLE or DISABLE
 109                                               Please check the Read Mode sequnece in the NAND device datasheet */
 110 }NAND_DeviceConfigTypeDef;
 111
 112 /**
 113   * @brief  NAND handle Structure definition
 114   */
 115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 116 typedef struct __NAND_HandleTypeDef
 117 #else
 118 typedef struct
 119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
 120 {
 121   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 122
 123   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 124
 125   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 126
 127   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 128
 129   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 130
 131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 132   void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */
 133   void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */
 134   void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */
 135 #endif
 136 } NAND_HandleTypeDef;
 137
 138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 139 /**
 140   * @brief  HAL NAND Callback ID enumeration definition
 141   */
 142 typedef enum
 143 {
 144   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
 145   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
 146   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
 147 }HAL_NAND_CallbackIDTypeDef;
 148
 149 /**
 150   * @brief  HAL NAND Callback pointer definition
 151   */
 152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
 153 #endif
 154
 155 /**
 156   * @}
 157   */
 158
 159 /* Exported constants --------------------------------------------------------*/
 160 /* Exported macro ------------------------------------------------------------*/
 161 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 162  * @{
 163  */
 164
 165 /** @brief Reset NAND handle state
 166   * @param  __HANDLE__ specifies the NAND handle.
 167   * @retval None
 168   */
 169 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
 171                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
 172                                                                (__HANDLE__)->MspInitCallback = NULL;       \
 173                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
 174                                                              } while(0)
 175 #else
 176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 177 #endif
 178
 179 /**
 180   * @}
 181   */
 182
 183 /* Exported functions --------------------------------------------------------*/
 184 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 185   * @{
 186   */
 187
 188 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 189   * @{
 190   */
 191
 192 /* Initialization/de-initialization functions  ********************************/
 193 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 194 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 195
 196 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 197
 198 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 199
 200 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 201 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 202 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 203 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 204
 205 /**
 206   * @}
 207   */
 208
 209 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 210   * @{
 211   */
 212
 213 /* IO operation functions  ****************************************************/
 214
 215 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 216
 217 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 218 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 219 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 220 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 221
 222 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 223 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 224 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 225 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 226
 227 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 228
 229 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 230
 231 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 232 /* NAND callback registering/unregistering */
 233 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
 234 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
 235 #endif
 236
 237 /**
 238   * @}
 239   */
 240
 241 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 242   * @{
 243   */
 244
 245 /* NAND Control functions  ****************************************************/
 246 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 247 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 248 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 249
 250 /**
 251   * @}
 252   */
 253
 254 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 255   * @{
 256   */
 257 /* NAND State functions *******************************************************/
 258 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 259 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 260 /**
 261   * @}
 262   */
 263
 264 /**
 265   * @}
 266   */
 267 /* Private types -------------------------------------------------------------*/
 268 /* Private variables ---------------------------------------------------------*/
 269 /* Private constants ---------------------------------------------------------*/
 270 /** @defgroup NAND_Private_Constants NAND Private Constants
 271   * @{
 272   */
 273 #define NAND_DEVICE                ((uint32_t)0x80000000U)
 274 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
 275
 276 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
 277 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
 278
 279 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
 280 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
 281 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
 282 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
 283
 284 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
 285 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
 286 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
 287 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
 288 #define NAND_CMD_READID            ((uint8_t)0x90U)
 289 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
 290 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
 291 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
 292
 293 /* NAND memory status */
 294 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
 295 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
 296 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
 297 #define NAND_BUSY                  ((uint32_t)0x00000000U)
 298 #define NAND_ERROR                 ((uint32_t)0x00000001U)
 299 #define NAND_READY                 ((uint32_t)0x00000040U)
 300 /**
 301   * @}
 302   */
 303
 304 /* Private macros ------------------------------------------------------------*/
 305 /** @defgroup NAND_Private_Macros NAND Private Macros
 306   * @{
 307   */
 308
 309 /**
 310   * @brief  NAND memory address computation.
 311   * @param  __ADDRESS__ NAND memory address.
 312   * @param  __HANDLE__  NAND handle.
 313   * @retval NAND Raw address value
 314   */
 315 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 316                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 317
 318 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 319
 320 /**
 321   * @brief  NAND memory address cycling.
 322   * @param  __ADDRESS__ NAND memory address.
 323   * @retval NAND address cycling value.
 324   */
 325 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 326 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 327 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 328 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 329
 330 /**
 331   * @brief  NAND memory Columns cycling.
 332   * @param  __ADDRESS__ NAND memory address.
 333   * @retval NAND Column address cycling value.
 334   */
 335 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
 336 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 337
 338 /**
 339   * @}
 340   */
 341
 342 /**
 343   * @}
 344   */
 345 /**
 346   * @}
 347   */
 348
 349 /**
 350   * @}
 351   */
 352
 353 #ifdef __cplusplus
 354 }
 355 #endif
 356
 357 #endif /* __STM32F7xx_HAL_NAND_H */
 358
 359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/