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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_qspi.h
blob78de574323cb2239d99fb5e1e342be2a770e8a94
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_qspi.h
4 * @author MCD Application Team
5 * @brief Header file of QSPI HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_HAL_QSPI_H
22 #define __STM32F7xx_HAL_QSPI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30
31 /** @addtogroup STM32F7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup QSPI
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup QSPI_Exported_Types QSPI Exported Types
41 * @{
42 */
43
44 /**
45 * @brief QSPI Init structure definition
46 */
47
48 typedef struct
49 {
50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
51 This parameter can be a number between 0 and 255 */
52
53 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
54 This parameter can be a value between 1 and 32 */
55
56 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
57 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
58 This parameter can be a value of @ref QSPI_SampleShifting */
59
60 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
61 required to address the flash memory. The flash capacity can be up to 4GB
62 (addressed using 32 bits) in indirect mode, but the addressable space in
63 memory-mapped mode is limited to 256MB
64 This parameter can be a number between 0 and 31 */
65
66 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
67 of clock cycles which the chip select must remain high between commands.
68 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
69
70 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
71 This parameter can be a value of @ref QSPI_ClockMode */
72
73 uint32_t FlashID; /* Specifies the Flash which will be used,
74 This parameter can be a value of @ref QSPI_Flash_Select */
75
76 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
77 This parameter can be a value of @ref QSPI_DualFlash_Mode */
78 }QSPI_InitTypeDef;
79
80 /**
81 * @brief HAL QSPI State structures definition
82 */
83 typedef enum
84 {
85 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
86 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
87 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
88 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
89 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
90 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
91 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
92 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
93 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
94 }HAL_QSPI_StateTypeDef;
95
96 /**
97 * @brief QSPI Handle Structure definition
98 */
99 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
100 typedef struct __QSPI_HandleTypeDef
101 #else
102 typedef struct
103 #endif
104 {
105 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
106 QSPI_InitTypeDef Init; /* QSPI communication parameters */
107 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
108 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
109 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
110 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
111 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
112 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
113 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
114 __IO HAL_LockTypeDef Lock; /* Locking object */
115 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
116 __IO uint32_t ErrorCode; /* QSPI Error code */
117 uint32_t Timeout; /* Timeout for the QSPI memory access */
118 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
119 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
120 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
121 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
122 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
123 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
124 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
125 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
126 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
127 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
128 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
129
130 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
131 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
132 #endif
133 }QSPI_HandleTypeDef;
134
135 /**
136 * @brief QSPI Command structure definition
137 */
138 typedef struct
139 {
140 uint32_t Instruction; /* Specifies the Instruction to be sent
141 This parameter can be a value (8-bit) between 0x00 and 0xFF */
142 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
143 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
144 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
145 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
146 uint32_t AddressSize; /* Specifies the Address Size
147 This parameter can be a value of @ref QSPI_AddressSize */
148 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
149 This parameter can be a value of @ref QSPI_AlternateBytesSize */
150 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
151 This parameter can be a number between 0 and 31 */
152 uint32_t InstructionMode; /* Specifies the Instruction Mode
153 This parameter can be a value of @ref QSPI_InstructionMode */
154 uint32_t AddressMode; /* Specifies the Address Mode
155 This parameter can be a value of @ref QSPI_AddressMode */
156 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
157 This parameter can be a value of @ref QSPI_AlternateBytesMode */
158 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
159 This parameter can be a value of @ref QSPI_DataMode */
160 uint32_t NbData; /* Specifies the number of data to transfer.
161 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
162 until end of memory)*/
163 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
164 This parameter can be a value of @ref QSPI_DdrMode */
165 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
166 system clock in DDR mode.
167 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
168 uint32_t SIOOMode; /* Specifies the send instruction only once mode
169 This parameter can be a value of @ref QSPI_SIOOMode */
170 }QSPI_CommandTypeDef;
171
172 /**
173 * @brief QSPI Auto Polling mode configuration structure definition
174 */
175 typedef struct
176 {
177 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
178 This parameter can be any value between 0 and 0xFFFFFFFF */
179 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
180 This parameter can be any value between 0 and 0xFFFFFFFF */
181 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
182 This parameter can be any value between 0 and 0xFFFF */
183 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
184 This parameter can be any value between 1 and 4 */
185 uint32_t MatchMode; /* Specifies the method used for determining a match.
186 This parameter can be a value of @ref QSPI_MatchMode */
187 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
188 This parameter can be a value of @ref QSPI_AutomaticStop */
189 }QSPI_AutoPollingTypeDef;
190
191 /**
192 * @brief QSPI Memory Mapped mode configuration structure definition
193 */
194 typedef struct
195 {
196 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
197 This parameter can be any value between 0 and 0xFFFF */
198 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
199 This parameter can be a value of @ref QSPI_TimeOutActivation */
200 }QSPI_MemoryMappedTypeDef;
201
202 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
203 /**
204 * @brief HAL QSPI Callback ID enumeration definition
205 */
206 typedef enum
207 {
208 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
209 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
210 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
211 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
212 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
213 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
214 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
215 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
216 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
217 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
218
219 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
220 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
221 }HAL_QSPI_CallbackIDTypeDef;
222
223 /**
224 * @brief HAL QSPI Callback pointer definition
225 */
226 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
227 #endif
228 /**
229 * @}
230 */
231
232 /* Exported constants --------------------------------------------------------*/
233 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
234 * @{
235 */
236 /** @defgroup QSPI_ErrorCode QSPI Error Code
237 * @{
238 */
239 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
240 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
241 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
242 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
243 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
244 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
245 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
246 #endif
247 /**
248 * @}
249 */
250
251 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
252 * @{
253 */
254 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
255 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
256 /**
257 * @}
258 */
259
260 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
261 * @{
262 */
263 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
264 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
265 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
266 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
267 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
268 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
269 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
270 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
271 /**
272 * @}
273 */
274
275 /** @defgroup QSPI_ClockMode QSPI Clock Mode
276 * @{
277 */
278 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
279 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
280 /**
281 * @}
282 */
283
284 /** @defgroup QSPI_Flash_Select QSPI Flash Select
285 * @{
286 */
287 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
288 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
289 /**
290 * @}
291 */
292
293 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
294 * @{
295 */
296 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
297 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
298 /**
299 * @}
300 */
301
302 /** @defgroup QSPI_AddressSize QSPI Address Size
303 * @{
304 */
305 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
306 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
307 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
308 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
309 /**
310 * @}
311 */
312
313 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
314 * @{
315 */
316 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
317 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
318 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
319 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
320 /**
321 * @}
322 */
323
324 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
325 * @{
326 */
327 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
328 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
329 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
330 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
331 /**
332 * @}
333 */
334
335 /** @defgroup QSPI_AddressMode QSPI Address Mode
336 * @{
337 */
338 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
339 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
340 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
341 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
342 /**
343 * @}
344 */
345
346 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
347 * @{
348 */
349 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
350 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
351 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
352 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
353 /**
354 * @}
355 */
356
357 /** @defgroup QSPI_DataMode QSPI Data Mode
358 * @{
359 */
360 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
361 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
362 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
363 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
364 /**
365 * @}
366 */
367
368 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
369 * @{
370 */
371 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
372 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
373 /**
374 * @}
375 */
376
377 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
378 * @{
379 */
380 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
381 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
382 /**
383 * @}
384 */
385
386 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
387 * @{
388 */
389 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
390 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
391 /**
392 * @}
393 */
394
395 /** @defgroup QSPI_MatchMode QSPI Match Mode
396 * @{
397 */
398 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
399 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
400 /**
401 * @}
402 */
403
404 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
405 * @{
406 */
407 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
408 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
409 /**
410 * @}
411 */
412
413 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
414 * @{
415 */
416 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
417 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
418 /**
419 * @}
420 */
421
422 /** @defgroup QSPI_Flags QSPI Flags
423 * @{
424 */
425 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
426 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
427 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
428 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
429 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
430 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
431 /**
432 * @}
433 */
434
435 /** @defgroup QSPI_Interrupts QSPI Interrupts
436 * @{
437 */
438 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
439 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
440 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
441 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
442 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
443 /**
444 * @}
445 */
446
447 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
448 * @{
449 */
450 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
451 /**
452 * @}
453 */
454
455 /**
456 * @}
457 */
458
459 /* Exported macros -----------------------------------------------------------*/
460 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
461 * @{
462 */
463
464 /** @brief Reset QSPI handle state
465 * @param __HANDLE__ QSPI handle.
466 * @retval None
467 */
468 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
469 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
470 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
471 (__HANDLE__)->MspInitCallback = NULL; \
472 (__HANDLE__)->MspDeInitCallback = NULL; \
473 } while(0)
474 #else
475 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
476 #endif
477
478 /** @brief Enable QSPI
479 * @param __HANDLE__ specifies the QSPI Handle.
480 * @retval None
481 */
482 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
483
484 /** @brief Disable QSPI
485 * @param __HANDLE__ specifies the QSPI Handle.
486 * @retval None
487 */
488 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
489
490 /** @brief Enables the specified QSPI interrupt.
491 * @param __HANDLE__ specifies the QSPI Handle.
492 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
493 * This parameter can be one of the following values:
494 * @arg QSPI_IT_TO: QSPI Time out interrupt
495 * @arg QSPI_IT_SM: QSPI Status match interrupt
496 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
497 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
498 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
499 * @retval None
500 */
501 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
502
503
504 /** @brief Disables the specified QSPI interrupt.
505 * @param __HANDLE__ specifies the QSPI Handle.
506 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
507 * This parameter can be one of the following values:
508 * @arg QSPI_IT_TO: QSPI Timeout interrupt
509 * @arg QSPI_IT_SM: QSPI Status match interrupt
510 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
511 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
512 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
513 * @retval None
514 */
515 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
516
517 /** @brief Checks whether the specified QSPI interrupt source is enabled.
518 * @param __HANDLE__ specifies the QSPI Handle.
519 * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
520 * This parameter can be one of the following values:
521 * @arg QSPI_IT_TO: QSPI Time out interrupt
522 * @arg QSPI_IT_SM: QSPI Status match interrupt
523 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
524 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
525 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
526 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
527 */
528 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
529
530 /**
531 * @brief Get the selected QSPI's flag status.
532 * @param __HANDLE__ specifies the QSPI Handle.
533 * @param __FLAG__ specifies the QSPI flag to check.
534 * This parameter can be one of the following values:
535 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
536 * @arg QSPI_FLAG_TO: QSPI Time out flag
537 * @arg QSPI_FLAG_SM: QSPI Status match flag
538 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
539 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
540 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
541 * @retval None
542 */
543 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
544
545 /** @brief Clears the specified QSPI's flag status.
546 * @param __HANDLE__ specifies the QSPI Handle.
547 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
548 * This parameter can be one of the following values:
549 * @arg QSPI_FLAG_TO: QSPI Time out flag
550 * @arg QSPI_FLAG_SM: QSPI Status match flag
551 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
552 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
553 * @retval None
554 */
555 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
556 /**
557 * @}
558 */
559
560 /* Exported functions --------------------------------------------------------*/
561 /** @addtogroup QSPI_Exported_Functions
562 * @{
563 */
564
565 /** @addtogroup QSPI_Exported_Functions_Group1
566 * @{
567 */
568 /* Initialization/de-initialization functions ********************************/
569 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
570 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
571 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
572 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
573 /**
574 * @}
575 */
576
577 /** @addtogroup QSPI_Exported_Functions_Group2
578 * @{
579 */
580 /* IO operation functions *****************************************************/
581 /* QSPI IRQ handler method */
582 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
583
584 /* QSPI indirect mode */
585 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
586 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
587 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
588 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
589 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
590 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
591 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
592 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
593
594 /* QSPI status flag polling mode */
595 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
596 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
597
598 /* QSPI memory-mapped mode */
599 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
600 /**
601 * @}
602 */
603
604 /** @addtogroup QSPI_Exported_Functions_Group3
605 * @{
606 */
607 /* Callback functions in non-blocking modes ***********************************/
608 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
609 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
610 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
611
612 /* QSPI indirect mode */
613 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
614 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
615 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
616 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
617 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
618
619 /* QSPI status flag polling mode */
620 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
621
622 /* QSPI memory-mapped mode */
623 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
624
625 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
626 /* QSPI callback registering/unregistering */
627 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
628 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
629 #endif
630 /**
631 * @}
632 */
633
634 /** @addtogroup QSPI_Exported_Functions_Group4
635 * @{
636 */
637 /* Peripheral Control and State functions ************************************/
638 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
639 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
640 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
641 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
642 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
643 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
644 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
645 /**
646 * @}
647 */
648
649 /**
650 * @}
651 */
652
653 /* Private macros ------------------------------------------------------------*/
654 /** @defgroup QSPI_Private_Macros QSPI Private Macros
655 * @{
656 */
657 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
658 * @{
659 */
660 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
661 /**
662 * @}
663 */
664
665 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
666 * @{
667 */
668 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
669 /**
670 * @}
671 */
672
673 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
674 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
675
676 /** @defgroup QSPI_FlashSize QSPI Flash Size
677 * @{
678 */
679 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
680 /**
681 * @}
682 */
683
684 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
685 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
686 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
687 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
688 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
689 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
690 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
691 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
692
693 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
694 ((CLKMODE) == QSPI_CLOCK_MODE_3))
695
696 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
697 ((FLA) == QSPI_FLASH_ID_2))
698
699 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
700 ((MODE) == QSPI_DUALFLASH_DISABLE))
701
702
703 /** @defgroup QSPI_Instruction QSPI Instruction
704 * @{
705 */
706 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
707 /**
708 * @}
709 */
710
711 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
712 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
713 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
714 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
715
716 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
717 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
718 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
719 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
720
721
722 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
723 * @{
724 */
725 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
726 /**
727 * @}
728 */
729
730 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
731 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
732 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
733 ((MODE) == QSPI_INSTRUCTION_4_LINES))
734
735 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
736 ((MODE) == QSPI_ADDRESS_1_LINE) || \
737 ((MODE) == QSPI_ADDRESS_2_LINES) || \
738 ((MODE) == QSPI_ADDRESS_4_LINES))
739
740 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
741 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
742 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
743 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
744
745 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
746 ((MODE) == QSPI_DATA_1_LINE) || \
747 ((MODE) == QSPI_DATA_2_LINES) || \
748 ((MODE) == QSPI_DATA_4_LINES))
749
750 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
751 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
752
753 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
754 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
755
756 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
757 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
758
759 /** @defgroup QSPI_Interval QSPI Interval
760 * @{
761 */
762 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
763 /**
764 * @}
765 */
766
767 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
768 * @{
769 */
770 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
771 /**
772 * @}
773 */
774 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
775 ((MODE) == QSPI_MATCH_MODE_OR))
776
777 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
778 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
779
780 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
781 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
782
783 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
784 * @{
785 */
786 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
787 /**
788 * @}
789 */
790
791 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
792 ((FLAG) == QSPI_FLAG_TO) || \
793 ((FLAG) == QSPI_FLAG_SM) || \
794 ((FLAG) == QSPI_FLAG_FT) || \
795 ((FLAG) == QSPI_FLAG_TC) || \
796 ((FLAG) == QSPI_FLAG_TE))
797
798 #define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
799 /**
800 * @}
801 */
802
803 /* Private functions ---------------------------------------------------------*/
804 /** @defgroup QSPI_Private_Functions QSPI Private Functions
805 * @{
806 */
807
808 /**
809 * @}
810 */
811
812 /**
813 * @}
814 */
815
816 /**
817 * @}
818 */
819
820 #ifdef __cplusplus
821 }
822 #endif
823
824 #endif /* __STM32F7xx_HAL_QSPI_H */
825
826 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/