?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_rcc.h
blob1681d79b27225de7f2cf74c8b2fff48b298f4159
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_HAL_RCC_H
22 #define __STM32F7xx_HAL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30
31 /* Include RCC HAL Extended module */
32 /* (include on top of file since RCC structures are defined in extended file) */
33 #include "stm32f7xx_hal_rcc_ex.h"
34
35 /** @addtogroup STM32F7xx_HAL_Driver
36 * @{
37 */
38
39 /** @addtogroup RCC
40 * @{
41 */
42
43 /* Exported types ------------------------------------------------------------*/
44
45 /** @defgroup RCC_Exported_Types RCC Exported Types
46 * @{
47 */
48
49 /**
50 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
51 */
52 typedef struct
53 {
54 uint32_t OscillatorType; /*!< The oscillators to be configured.
55 This parameter can be a value of @ref RCC_Oscillator_Type */
56
57 uint32_t HSEState; /*!< The new state of the HSE.
58 This parameter can be a value of @ref RCC_HSE_Config */
59
60 uint32_t LSEState; /*!< The new state of the LSE.
61 This parameter can be a value of @ref RCC_LSE_Config */
62
63 uint32_t HSIState; /*!< The new state of the HSI.
64 This parameter can be a value of @ref RCC_HSI_Config */
65
66 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
67 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
68
69 uint32_t LSIState; /*!< The new state of the LSI.
70 This parameter can be a value of @ref RCC_LSI_Config */
71
72 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
73
74 }RCC_OscInitTypeDef;
75
76 /**
77 * @brief RCC System, AHB and APB busses clock configuration structure definition
78 */
79 typedef struct
80 {
81 uint32_t ClockType; /*!< The clock to be configured.
82 This parameter can be a value of @ref RCC_System_Clock_Type */
83
84 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
85 This parameter can be a value of @ref RCC_System_Clock_Source */
86
87 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
88 This parameter can be a value of @ref RCC_AHB_Clock_Source */
89
90 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
91 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
92
93 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
94 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
95
96 }RCC_ClkInitTypeDef;
97
98 /**
99 * @}
100 */
101
102 /* Exported constants --------------------------------------------------------*/
103 /** @defgroup RCC_Exported_Constants RCC Exported Constants
104 * @{
105 */
106
107 /** @defgroup RCC_Oscillator_Type Oscillator Type
108 * @{
109 */
110 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
111 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
112 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
113 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
114 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
115 /**
116 * @}
117 */
118
119 /** @defgroup RCC_HSE_Config RCC HSE Config
120 * @{
121 */
122 #define RCC_HSE_OFF ((uint32_t)0x00000000U)
123 #define RCC_HSE_ON RCC_CR_HSEON
124 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
125 /**
126 * @}
127 */
128
129 /** @defgroup RCC_LSE_Config RCC LSE Config
130 * @{
131 */
132 #define RCC_LSE_OFF ((uint32_t)0x00000000U)
133 #define RCC_LSE_ON RCC_BDCR_LSEON
134 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
135 /**
136 * @}
137 */
138
139 /** @defgroup RCC_HSI_Config RCC HSI Config
140 * @{
141 */
142 #define RCC_HSI_OFF ((uint32_t)0x00000000U)
143 #define RCC_HSI_ON RCC_CR_HSION
144
145 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
146 /**
147 * @}
148 */
149
150 /** @defgroup RCC_LSI_Config RCC LSI Config
151 * @{
152 */
153 #define RCC_LSI_OFF ((uint32_t)0x00000000U)
154 #define RCC_LSI_ON RCC_CSR_LSION
155 /**
156 * @}
157 */
158
159 /** @defgroup RCC_PLL_Config RCC PLL Config
160 * @{
161 */
162 #define RCC_PLL_NONE ((uint32_t)0x00000000U)
163 #define RCC_PLL_OFF ((uint32_t)0x00000001U)
164 #define RCC_PLL_ON ((uint32_t)0x00000002U)
165 /**
166 * @}
167 */
168
169 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
170 * @{
171 */
172 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
173 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
174 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
175 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
181 * @{
182 */
183 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
184 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
185 /**
186 * @}
187 */
188
189 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
190 * @{
191 */
192 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
193 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
194 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
195 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
196 /**
197 * @}
198 */
199
200 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
201 * @{
202 */
203 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
204 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
205 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
206 /**
207 * @}
208 */
209
210
211 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
212 * @{
213 */
214 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
215 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
216 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
217 /**
218 * @}
219 */
220
221 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
222 * @{
223 */
224 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
225 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
226 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
227 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
228 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
229 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
230 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
231 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
232 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
233 /**
234 * @}
235 */
236
237 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
238 * @{
239 */
240 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
241 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
242 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
243 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
244 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
245 /**
246 * @}
247 */
248
249 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
250 * @{
251 */
252 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
253 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
254 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
255 #define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U)
256 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
257 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
258 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
259 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
260 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
261 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
262 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
263 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
264 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
265 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
266 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
267 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
268 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
269 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
270 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
271 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
272 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
273 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
274 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
275 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
276 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
277 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
278 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
279 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
280 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
281 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
282 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
283 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
284 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
285 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
286 /**
287 * @}
288 */
289
290
291
292 /** @defgroup RCC_MCO_Index RCC MCO Index
293 * @{
294 */
295 #define RCC_MCO1 ((uint32_t)0x00000000U)
296 #define RCC_MCO2 ((uint32_t)0x00000001U)
297 /**
298 * @}
299 */
300
301 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
302 * @{
303 */
304 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
305 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
306 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
307 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
308 /**
309 * @}
310 */
311
312 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
313 * @{
314 */
315 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
316 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
317 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
318 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
319 /**
320 * @}
321 */
322
323 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
324 * @{
325 */
326 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
327 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
328 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
329 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
330 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
331 /**
332 * @}
333 */
334
335 /** @defgroup RCC_Interrupt RCC Interrupt
336 * @{
337 */
338 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
339 #define RCC_IT_LSERDY ((uint8_t)0x02U)
340 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
341 #define RCC_IT_HSERDY ((uint8_t)0x08U)
342 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
343 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
344 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
345 #define RCC_IT_CSS ((uint8_t)0x80U)
346 /**
347 * @}
348 */
349
350 /** @defgroup RCC_Flag RCC Flags
351 * Elements values convention: 0XXYYYYYb
352 * - YYYYY : Flag position in the register
353 * - 0XX : Register index
354 * - 01: CR register
355 * - 10: BDCR register
356 * - 11: CSR register
357 * @{
358 */
359 /* Flags in the CR register */
360 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
361 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
362 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
363 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
364 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
365
366 /* Flags in the BDCR register */
367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
368
369 /* Flags in the CSR register */
370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
378 /**
379 * @}
380 */
381
382 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
383 * @{
384 */
385 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
386 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
387 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
388 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
389 /**
390 * @}
391 */
392
393 /**
394 * @}
395 */
396
397 /* Exported macro ------------------------------------------------------------*/
398 /** @defgroup RCC_Exported_Macros RCC Exported Macros
399 * @{
400 */
401
402 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
403 * @brief Enable or disable the AHB1 peripheral clock.
404 * @note After reset, the peripheral clock (used for registers read/write access)
405 * is disabled and the application software has to enable this clock before
406 * using it.
407 * @{
408 */
409 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
410 __IO uint32_t tmpreg; \
411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
412 /* Delay after an RCC peripheral clock enabling */ \
413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
414 UNUSED(tmpreg); \
415 } while(0)
416
417 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
418 __IO uint32_t tmpreg; \
419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
420 /* Delay after an RCC peripheral clock enabling */ \
421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
422 UNUSED(tmpreg); \
423 } while(0)
424
425 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
426 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
427
428 /**
429 * @}
430 */
431
432 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
433 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
434 * @note After reset, the peripheral clock (used for registers read/write access)
435 * is disabled and the application software has to enable this clock before
436 * using it.
437 * @{
438 */
439 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
440 __IO uint32_t tmpreg; \
441 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
442 /* Delay after an RCC peripheral clock enabling */ \
443 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
444 UNUSED(tmpreg); \
445 } while(0)
446
447 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
448 __IO uint32_t tmpreg; \
449 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
450 /* Delay after an RCC peripheral clock enabling */ \
451 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
452 UNUSED(tmpreg); \
453 } while(0)
454
455 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
456 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
457 /**
458 * @}
459 */
460
461 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
462 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
463 * @note After reset, the peripheral clock (used for registers read/write access)
464 * is disabled and the application software has to enable this clock before
465 * using it.
466 * @{
467 */
468 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
469 __IO uint32_t tmpreg; \
470 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
471 /* Delay after an RCC peripheral clock enabling */ \
472 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
473 UNUSED(tmpreg); \
474 } while(0)
475
476 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
477
478 /**
479 * @}
480 */
481
482 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
483 * @brief Get the enable or disable status of the AHB1 peripheral clock.
484 * @note After reset, the peripheral clock (used for registers read/write access)
485 * is disabled and the application software has to enable this clock before
486 * using it.
487 * @{
488 */
489 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
490 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
491
492 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
493 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
494 /**
495 * @}
496 */
497
498 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
499 * @brief Get the enable or disable status of the APB1 peripheral clock.
500 * @note After reset, the peripheral clock (used for registers read/write access)
501 * is disabled and the application software has to enable this clock before
502 * using it.
503 * @{
504 */
505 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
506 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
507
508 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
509 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
510 /**
511 * @}
512 */
513
514 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
515 * @brief EGet the enable or disable status of the APB2 peripheral clock.
516 * @note After reset, the peripheral clock (used for registers read/write access)
517 * is disabled and the application software has to enable this clock before
518 * using it.
519 * @{
520 */
521 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
522 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
523 /**
524 * @}
525 */
526
527 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
528 * @brief Force or release AHB peripheral reset.
529 * @{
530 */
531 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
532 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
533 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
534
535 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
536 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
537 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
538 /**
539 * @}
540 */
541
542 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
543 * @brief Force or release APB1 peripheral reset.
544 * @{
545 */
546 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
547 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
548 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
549
550 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
551 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
552 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
553 /**
554 * @}
555 */
556
557 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
558 * @brief Force or release APB2 peripheral reset.
559 * @{
560 */
561 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
562 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
563
564 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
565 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
566
567 /**
568 * @}
569 */
570
571 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
572 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
573 * power consumption.
574 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
575 * @note By default, all peripheral clocks are enabled during SLEEP mode.
576 * @{
577 */
578 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
579 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
580
581 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
582 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
583
584 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
585 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
586 * power consumption.
587 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
588 * @note By default, all peripheral clocks are enabled during SLEEP mode.
589 */
590 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
591 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
592
593 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
594 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
595
596 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
597 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
598 * power consumption.
599 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
600 * @note By default, all peripheral clocks are enabled during SLEEP mode.
601 */
602 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
603 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
604
605 /**
606 * @}
607 */
608
609 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
610 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
611 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
612 * power consumption.
613 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
614 * @note By default, all peripheral clocks are enabled during SLEEP mode.
615 * @{
616 */
617 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
618 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
619
620 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
621 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
622 /**
623 * @}
624 */
625
626 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
627 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
628 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
629 * power consumption.
630 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
631 * @note By default, all peripheral clocks are enabled during SLEEP mode.
632 * @{
633 */
634 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
635 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
636
637 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
638 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
639 /**
640 * @}
641 */
642
643 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
644 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
645 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
646 * power consumption.
647 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
648 * @note By default, all peripheral clocks are enabled during SLEEP mode.
649 * @{
650 */
651 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
652 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
653 /**
654 * @}
655 */
656
657 /** @defgroup RCC_HSI_Configuration HSI Configuration
658 * @{
659 */
660
661 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
662 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
663 * It is used (enabled by hardware) as system clock source after startup
664 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
665 * of the HSE used directly or indirectly as system clock (if the Clock
666 * Security System CSS is enabled).
667 * @note HSI can not be stopped if it is used as system clock source. In this case,
668 * you have to select another source of the system clock then stop the HSI.
669 * @note After enabling the HSI, the application software should wait on HSIRDY
670 * flag to be set indicating that HSI clock is stable and can be used as
671 * system clock source.
672 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
673 * clock cycles.
674 */
675 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
676 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
677
678 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
679 * @note The calibration is used to compensate for the variations in voltage
680 * and temperature that influence the frequency of the internal HSI RC.
681 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value.
682 * (default is RCC_HSICALIBRATION_DEFAULT).
683 */
684 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
685 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))
686 /**
687 * @}
688 */
689
690 /** @defgroup RCC_LSI_Configuration LSI Configuration
691 * @{
692 */
693
694 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
695 * @note After enabling the LSI, the application software should wait on
696 * LSIRDY flag to be set indicating that LSI clock is stable and can
697 * be used to clock the IWDG and/or the RTC.
698 * @note LSI can not be disabled if the IWDG is running.
699 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
700 * clock cycles.
701 */
702 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
703 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
704 /**
705 * @}
706 */
707
708 /** @defgroup RCC_HSE_Configuration HSE Configuration
709 * @{
710 */
711 /**
712 * @brief Macro to configure the External High Speed oscillator (HSE).
713 * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
714 * supported by this macro. User should request a transition to HSE Off
715 * first and then HSE On or HSE Bypass.
716 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
717 * software should wait on HSERDY flag to be set indicating that HSE clock
718 * is stable and can be used to clock the PLL and/or system clock.
719 * @note HSE state can not be changed if it is used directly or through the
720 * PLL as system clock. In this case, you have to select another source
721 * of the system clock then change the HSE state (ex. disable it).
722 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
723 * @note This function reset the CSSON bit, so if the clock security system(CSS)
724 * was previously enabled you have to enable it again after calling this
725 * function.
726 * @param __STATE__ specifies the new state of the HSE.
727 * This parameter can be one of the following values:
728 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
729 * 6 HSE oscillator clock cycles.
730 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
731 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
732 */
733 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
734 do { \
735 if ((__STATE__) == RCC_HSE_ON) \
736 { \
737 SET_BIT(RCC->CR, RCC_CR_HSEON); \
738 } \
739 else if ((__STATE__) == RCC_HSE_OFF) \
740 { \
741 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
742 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
743 } \
744 else if ((__STATE__) == RCC_HSE_BYPASS) \
745 { \
746 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
747 SET_BIT(RCC->CR, RCC_CR_HSEON); \
748 } \
749 else \
750 { \
751 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
752 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
753 } \
754 } while(0)
755 /**
756 * @}
757 */
758
759 /** @defgroup RCC_LSE_Configuration LSE Configuration
760 * @{
761 */
762
763 /**
764 * @brief Macro to configure the External Low Speed oscillator (LSE).
765 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
766 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
767 * @note As the LSE is in the Backup domain and write access is denied to
768 * this domain after reset, you have to enable write access using
769 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
770 * (to be done once after reset).
771 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
772 * software should wait on LSERDY flag to be set indicating that LSE clock
773 * is stable and can be used to clock the RTC.
774 * @param __STATE__ specifies the new state of the LSE.
775 * This parameter can be one of the following values:
776 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
777 * 6 LSE oscillator clock cycles.
778 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
779 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
780 */
781 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
782 do { \
783 if((__STATE__) == RCC_LSE_ON) \
784 { \
785 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
786 } \
787 else if((__STATE__) == RCC_LSE_OFF) \
788 { \
789 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
790 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
791 } \
792 else if((__STATE__) == RCC_LSE_BYPASS) \
793 { \
794 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
795 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
796 } \
797 else \
798 { \
799 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
800 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
801 } \
802 } while(0)
803 /**
804 * @}
805 */
806
807 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
808 * @{
809 */
810
811 /** @brief Macros to enable or disable the RTC clock.
812 * @note These macros must be used only after the RTC clock source was selected.
813 */
814 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
815 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
816
817 /** @brief Macros to configure the RTC clock (RTCCLK).
818 * @note As the RTC clock configuration bits are in the Backup domain and write
819 * access is denied to this domain after reset, you have to enable write
820 * access using the Power Backup Access macro before to configure
821 * the RTC clock source (to be done once after reset).
822 * @note Once the RTC clock is configured it can't be changed unless the
823 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
824 * a Power On Reset (POR).
825 * @param __RTCCLKSource__ specifies the RTC clock source.
826 * This parameter can be one of the following values:
827 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
828 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
829 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
830 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
831 * as RTC clock, where x:[2,31]
832 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
833 * work in STOP and STANDBY modes, and can be used as wakeup source.
834 * However, when the HSE clock is used as RTC clock source, the RTC
835 * cannot be used in STOP and STANDBY modes.
836 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
837 * RTC clock source).
838 */
839 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
840 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
841
842 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
843 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
844 } while (0)
845
846 /** @brief Macro to get the RTC clock source.
847 * @retval The clock source can be one of the following values:
848 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
849 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
850 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
851 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
852 */
853 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
854
855 /**
856 * @brief Get the RTC and HSE clock divider (RTCPRE).
857 * @retval Returned value can be one of the following values:
858 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
859 * as RTC clock, where x:[2,31]
860 */
861 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
862
863 /** @brief Macros to force or release the Backup domain reset.
864 * @note This function resets the RTC peripheral (including the backup registers)
865 * and the RTC clock source selection in RCC_CSR register.
866 * @note The BKPSRAM is not affected by this reset.
867 */
868 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
869 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
870 /**
871 * @}
872 */
873
874 /** @defgroup RCC_PLL_Configuration PLL Configuration
875 * @{
876 */
877
878 /** @brief Macros to enable or disable the main PLL.
879 * @note After enabling the main PLL, the application software should wait on
880 * PLLRDY flag to be set indicating that PLL clock is stable and can
881 * be used as system clock source.
882 * @note The main PLL can not be disabled if it is used as system clock source
883 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
884 */
885 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
886 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
887
888 /** @brief Macro to configure the PLL clock source.
889 * @note This function must be used only when the main PLL is disabled.
890 * @param __PLLSOURCE__ specifies the PLL entry clock source.
891 * This parameter can be one of the following values:
892 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
893 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
894 *
895 */
896 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
897
898 /** @brief Macro to configure the PLL multiplication factor.
899 * @note This function must be used only when the main PLL is disabled.
900 * @param __PLLM__ specifies the division factor for PLL VCO input clock
901 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
902 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
903 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
904 * of 2 MHz to limit PLL jitter.
905 *
906 */
907 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
908 /**
909 * @}
910 */
911
912 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
913 * @{
914 */
915
916 /** @brief Macro to configure the I2S clock source (I2SCLK).
917 * @note This function must be called before enabling the I2S APB clock.
918 * @param __SOURCE__ specifies the I2S clock source.
919 * This parameter can be one of the following values:
920 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
921 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
922 * used as I2S clock source.
923 */
924 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
925 RCC->CFGR |= (__SOURCE__); \
926 }while(0)
927
928 /** @brief Macros to enable or disable the PLLI2S.
929 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
930 */
931 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
932 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
933 /**
934 * @}
935 */
936
937 /** @defgroup RCC_Get_Clock_source Get Clock source
938 * @{
939 */
940 /**
941 * @brief Macro to configure the system clock source.
942 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
943 * This parameter can be one of the following values:
944 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
945 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
946 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
947 */
948 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
949
950 /** @brief Macro to get the clock source used as system clock.
951 * @retval The clock source used as system clock. The returned value can be one
952 * of the following:
953 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
954 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
955 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
956 */
957 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
958
959 /**
960 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
961 * @note As the LSE is in the Backup domain and write access is denied to
962 * this domain after reset, you have to enable write access using
963 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
964 * (to be done once after reset).
965 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
966 * This parameter can be one of the following values:
967 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
968 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
969 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
970 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
971 * @retval None
972 */
973 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
974 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
975
976 /** @brief Macro to get the oscillator used as PLL clock source.
977 * @retval The oscillator used as PLL clock source. The returned value can be one
978 * of the following:
979 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
980 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
981 */
982 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
983 /**
984 * @}
985 */
986
987 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
988 * @{
989 */
990
991 /** @brief Macro to configure the MCO1 clock.
992 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
993 * This parameter can be one of the following values:
994 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
995 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
996 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
997 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
998 * @param __MCODIV__ specifies the MCO clock prescaler.
999 * This parameter can be one of the following values:
1000 * @arg RCC_MCODIV_1: no division applied to MCOx clock
1001 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1002 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1003 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1004 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1005 */
1006
1007 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1008 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1009
1010 /** @brief Macro to configure the MCO2 clock.
1011 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1012 * This parameter can be one of the following values:
1013 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1014 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
1015 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1016 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
1017 * @param __MCODIV__ specifies the MCO clock prescaler.
1018 * This parameter can be one of the following values:
1019 * @arg RCC_MCODIV_1: no division applied to MCOx clock
1020 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1021 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1022 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1023 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1024 */
1025
1026 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1027 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1033 * @brief macros to manage the specified RCC Flags and interrupts.
1034 * @{
1035 */
1036
1037 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1038 * the selected interrupts).
1039 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1040 * This parameter can be any combination of the following values:
1041 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1042 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1043 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1044 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1045 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1046 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1047 */
1048 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1049
1050 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1051 * the selected interrupts).
1052 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1053 * This parameter can be any combination of the following values:
1054 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1055 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1056 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1057 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1058 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1059 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1060 */
1061 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1062
1063 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
1064 * bits to clear the selected interrupt pending bits.
1065 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1066 * This parameter can be any combination of the following values:
1067 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1068 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1069 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1070 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1071 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1072 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1073 * @arg RCC_IT_CSS: Clock Security System interrupt
1074 */
1075 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1076
1077 /** @brief Check the RCC's interrupt has occurred or not.
1078 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
1079 * This parameter can be one of the following values:
1080 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1081 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1082 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1083 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1084 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1085 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1086 * @arg RCC_IT_CSS: Clock Security System interrupt
1087 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1088 */
1089 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1090
1091 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1092 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
1093 */
1094 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1095
1096 /** @brief Check RCC flag is set or not.
1097 * @param __FLAG__ specifies the flag to check.
1098 * This parameter can be one of the following values:
1099 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1100 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1101 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1102 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
1103 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1104 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1105 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
1106 * @arg RCC_FLAG_PINRST: Pin reset.
1107 * @arg RCC_FLAG_PORRST: POR/PDR reset.
1108 * @arg RCC_FLAG_SFTRST: Software reset.
1109 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1110 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1111 * @arg RCC_FLAG_LPWRRST: Low Power reset.
1112 * @retval The new state of __FLAG__ (TRUE or FALSE).
1113 */
1114 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1115 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
1116
1117 /**
1118 * @}
1119 */
1120
1121 /**
1122 * @}
1123 */
1124
1125 /* Include RCC HAL Extension module */
1126 #include "stm32f7xx_hal_rcc_ex.h"
1127
1128 /* Exported functions --------------------------------------------------------*/
1129 /** @addtogroup RCC_Exported_Functions
1130 * @{
1131 */
1132
1133 /** @addtogroup RCC_Exported_Functions_Group1
1134 * @{
1135 */
1136 /* Initialization and de-initialization functions ******************************/
1137 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1138 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1139 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1140 /**
1141 * @}
1142 */
1143
1144 /** @addtogroup RCC_Exported_Functions_Group2
1145 * @{
1146 */
1147 /* Peripheral Control functions ************************************************/
1148 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1149 void HAL_RCC_EnableCSS(void);
1150 void HAL_RCC_DisableCSS(void);
1151 uint32_t HAL_RCC_GetSysClockFreq(void);
1152 uint32_t HAL_RCC_GetHCLKFreq(void);
1153 uint32_t HAL_RCC_GetPCLK1Freq(void);
1154 uint32_t HAL_RCC_GetPCLK2Freq(void);
1155 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1156 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1157
1158 /* CSS NMI IRQ handler */
1159 void HAL_RCC_NMI_IRQHandler(void);
1160
1161 /* User Callbacks in non blocking mode (IT mode) */
1162 void HAL_RCC_CSSCallback(void);
1163 /**
1164 * @}
1165 */
1166
1167 /**
1168 * @}
1169 */
1170
1171 /* Private types -------------------------------------------------------------*/
1172 /* Private variables ---------------------------------------------------------*/
1173 /* Private constants ---------------------------------------------------------*/
1174 /** @defgroup RCC_Private_Constants RCC Private Constants
1175 * @{
1176 */
1177 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1178 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1179 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1180 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1181 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
1182 #define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
1183 #define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
1184
1185 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
1186 * @brief RCC registers bit address alias
1187 * @{
1188 */
1189 /* CIR register byte 2 (Bits[15:8]) base address */
1190 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
1191
1192 /* CIR register byte 3 (Bits[23:16]) base address */
1193 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
1194
1195 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
1196 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1197 /**
1198 * @}
1199 */
1200 /**
1201 * @}
1202 */
1203
1204 /* Private macros ------------------------------------------------------------*/
1205 /** @addtogroup RCC_Private_Macros RCC Private Macros
1206 * @{
1207 */
1208
1209 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
1210 * @{
1211 */
1212 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
1213
1214 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1215 ((HSE) == RCC_HSE_BYPASS))
1216
1217 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1218 ((LSE) == RCC_LSE_BYPASS))
1219
1220 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1221
1222 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1223
1224 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1225
1226 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1227 ((SOURCE) == RCC_PLLSOURCE_HSE))
1228
1229 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1230 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1231 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
1232 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
1233
1234 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
1235
1236 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
1237 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
1238 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1239
1240 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1241 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1242 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1243 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1244 ((HCLK) == RCC_SYSCLK_DIV512))
1245
1246 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
1247
1248 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1249 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1250 ((PCLK) == RCC_HCLK_DIV16))
1251
1252 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
1253
1254
1255 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1256 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1257
1258 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
1259 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
1260
1261 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1262 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1263 ((DIV) == RCC_MCODIV_5))
1264 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
1265
1266 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
1267 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1268 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1269 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1270 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1271 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1272 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1273 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1274 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1275 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1276 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1277 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1278 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1279 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1280 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1281 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
1282
1283
1284 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
1285 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
1286 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
1287 ((DRIVE) == RCC_LSEDRIVE_HIGH))
1288 /**
1289 * @}
1290 */
1291
1292 /**
1293 * @}
1294 */
1295
1296 /**
1297 * @}
1298 */
1299
1300 /**
1301 * @}
1302 */
1303
1304 #ifdef __cplusplus
1305 }
1306 #endif
1307
1308 #endif /* __STM32F7xx_HAL_RCC_H */
1309
1310 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/