lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_sram.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of SRAM HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32F7xx_HAL_SRAM_H
  22 #define __STM32F7xx_HAL_SRAM_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32f7xx_ll_fmc.h"
  30
  31 /** @addtogroup STM32F7xx_HAL_Driver
  32   * @{
  33   */
  34 /** @addtogroup SRAM
  35   * @{
  36   */
  37
  38 /* Exported typedef ----------------------------------------------------------*/
  39
  40 /** @defgroup SRAM_Exported_Types SRAM Exported Types
  41   * @{
  42   */
  43 /**
  44   * @brief  HAL SRAM State structures definition
  45   */
  46 typedef enum
  47 {
  48   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
  49   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
  50   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
  51   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
  52   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
  53
  54 } HAL_SRAM_StateTypeDef;
  55
  56 /**
  57   * @brief  SRAM handle Structure definition
  58   */
  59 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  60 typedef struct __SRAM_HandleTypeDef
  61 #else
  62 typedef struct
  63 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
  64 {
  65   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
  66
  67   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
  68
  69   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
  70
  71   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
  72
  73   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
  74
  75   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
  76
  77 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  78   void  (* MspInitCallback)        ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp Init callback              */
  79   void  (* MspDeInitCallback)      ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp DeInit callback            */
  80   void  (* DmaXferCpltCallback)    ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Complete callback     */
  81   void  (* DmaXferErrorCallback)   ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Error callback        */
  82 #endif
  83 } SRAM_HandleTypeDef;
  84
  85 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  86 /**
  87   * @brief  HAL SRAM Callback ID enumeration definition
  88   */
  89 typedef enum
  90 {
  91   HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
  92   HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
  93   HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
  94   HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
  95 }HAL_SRAM_CallbackIDTypeDef;
  96
  97 /**
  98   * @brief  HAL SRAM Callback pointer definition
  99   */
 100 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
 101 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
 102 #endif
 103 /**
 104   * @}
 105   */
 106
 107 /* Exported constants --------------------------------------------------------*/
 108 /* Exported macro ------------------------------------------------------------*/
 109
 110 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
 111  * @{
 112  */
 113
 114 /** @brief Reset SRAM handle state
 115   * @param  __HANDLE__ SRAM handle
 116   * @retval None
 117   */
 118 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 119 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
 120                                                                (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
 121                                                                (__HANDLE__)->MspInitCallback = NULL;       \
 122                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
 123                                                              } while(0)
 124 #else
 125 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
 126 #endif
 127
 128 /**
 129   * @}
 130   */
 131
 132 /* Exported functions --------------------------------------------------------*/
 133 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
 134   * @{
 135   */
 136
 137 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 138  * @{
 139  */
 140
 141 /* Initialization/de-initialization functions  ********************************/
 142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
 143 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
 144 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
 145 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 146
 147 /**
 148   * @}
 149   */
 150
 151 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
 152  * @{
 153  */
 154
 155 /* I/O operation functions  ***************************************************/
 156 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
 157 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
 158 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
 159 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
 160 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 161 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 162 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 163 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 164
 165 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
 166 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 167
 168 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 169 /* SRAM callback registering/unregistering */
 170 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
 171 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
 172 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
 173 #endif
 174
 175 /**
 176   * @}
 177   */
 178
 179 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
 180  * @{
 181  */
 182
 183 /* SRAM Control functions  ****************************************************/
 184 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 185 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
 186
 187 /**
 188   * @}
 189   */
 190
 191 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
 192  * @{
 193  */
 194
 195 /* SRAM  State functions ******************************************************/
 196 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
 197
 198 /**
 199   * @}
 200   */
 201
 202 /**
 203   * @}
 204   */
 205
 206 /**
 207   * @}
 208   */
 209
 210 /**
 211   * @}
 212   */
 213
 214 #ifdef __cplusplus
 215 }
 216 #endif
 217
 218 #endif /* __STM32F7xx_HAL_SRAM_H */
 219
 220 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/