?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_tim.h
blob1a3b50aebc2d1a3e5120100f9043860a4b4bf8b1
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_TIM_H
22 #define STM32F7xx_HAL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30
31 /** @addtogroup STM32F7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup TIM
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup TIM_Exported_Types TIM Exported Types
41 * @{
42 */
43
44 /**
45 * @brief TIM Time base Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
51
52 uint32_t CounterMode; /*!< Specifies the counter mode.
53 This parameter can be a value of @ref TIM_Counter_Mode */
54
55 uint32_t Period; /*!< Specifies the period value to be loaded into the active
56 Auto-Reload Register at the next update event.
57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
58
59 uint32_t ClockDivision; /*!< Specifies the clock division.
60 This parameter can be a value of @ref TIM_ClockDivision */
61
62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
63 reaches zero, an update event is generated and counting restarts
64 from the RCR value (N).
65 This means in PWM mode that (N+1) corresponds to:
66 - the number of PWM periods in edge-aligned mode
67 - the number of half PWM period in center-aligned mode
68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
70
71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
72 This parameter can be a value of @ref TIM_AutoReloadPreload */
73 } TIM_Base_InitTypeDef;
74
75 /**
76 * @brief TIM Output Compare Configuration Structure definition
77 */
78 typedef struct
79 {
80 uint32_t OCMode; /*!< Specifies the TIM mode.
81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
82
83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
85
86 uint32_t OCPolarity; /*!< Specifies the output polarity.
87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
88
89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
91 @note This parameter is valid only for timer instances supporting break feature. */
92
93 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
94 This parameter can be a value of @ref TIM_Output_Fast_State
95 @note This parameter is valid only in PWM1 and PWM2 mode. */
96
97
98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
100 @note This parameter is valid only for timer instances supporting break feature. */
101
102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
104 @note This parameter is valid only for timer instances supporting break feature. */
105 } TIM_OC_InitTypeDef;
106
107 /**
108 * @brief TIM One Pulse Mode Configuration Structure definition
109 */
110 typedef struct
111 {
112 uint32_t OCMode; /*!< Specifies the TIM mode.
113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
114
115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
117
118 uint32_t OCPolarity; /*!< Specifies the output polarity.
119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
120
121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
123 @note This parameter is valid only for timer instances supporting break feature. */
124
125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
127 @note This parameter is valid only for timer instances supporting break feature. */
128
129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
131 @note This parameter is valid only for timer instances supporting break feature. */
132
133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
135
136 uint32_t ICSelection; /*!< Specifies the input.
137 This parameter can be a value of @ref TIM_Input_Capture_Selection */
138
139 uint32_t ICFilter; /*!< Specifies the input capture filter.
140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
141 } TIM_OnePulse_InitTypeDef;
142
143 /**
144 * @brief TIM Input Capture Configuration Structure definition
145 */
146 typedef struct
147 {
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
156
157 uint32_t ICFilter; /*!< Specifies the input capture filter.
158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
159 } TIM_IC_InitTypeDef;
160
161 /**
162 * @brief TIM Encoder Configuration Structure definition
163 */
164 typedef struct
165 {
166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
167 This parameter can be a value of @ref TIM_Encoder_Mode */
168
169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
170 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
171
172 uint32_t IC1Selection; /*!< Specifies the input.
173 This parameter can be a value of @ref TIM_Input_Capture_Selection */
174
175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
177
178 uint32_t IC1Filter; /*!< Specifies the input capture filter.
179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
180
181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
182 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
183
184 uint32_t IC2Selection; /*!< Specifies the input.
185 This parameter can be a value of @ref TIM_Input_Capture_Selection */
186
187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
189
190 uint32_t IC2Filter; /*!< Specifies the input capture filter.
191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
192 } TIM_Encoder_InitTypeDef;
193
194 /**
195 * @brief Clock Configuration Handle Structure definition
196 */
197 typedef struct
198 {
199 uint32_t ClockSource; /*!< TIM clock sources
200 This parameter can be a value of @ref TIM_Clock_Source */
201 uint32_t ClockPolarity; /*!< TIM clock polarity
202 This parameter can be a value of @ref TIM_Clock_Polarity */
203 uint32_t ClockPrescaler; /*!< TIM clock prescaler
204 This parameter can be a value of @ref TIM_Clock_Prescaler */
205 uint32_t ClockFilter; /*!< TIM clock filter
206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
207 } TIM_ClockConfigTypeDef;
208
209 /**
210 * @brief TIM Clear Input Configuration Handle Structure definition
211 */
212 typedef struct
213 {
214 uint32_t ClearInputState; /*!< TIM clear Input state
215 This parameter can be ENABLE or DISABLE */
216 uint32_t ClearInputSource; /*!< TIM clear Input sources
217 This parameter can be a value of @ref TIM_ClearInput_Source */
218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
219 This parameter can be a value of @ref TIM_ClearInput_Polarity */
220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
224 } TIM_ClearInputConfigTypeDef;
225
226 /**
227 * @brief TIM Master configuration Structure definition
228 * @note Advanced timers provide TRGO2 internal line which is redirected
229 * to the ADC
230 */
231 typedef struct
232 {
233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
234 This parameter can be a value of @ref TIM_Master_Mode_Selection */
235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
238 This parameter can be a value of @ref TIM_Master_Slave_Mode */
239 } TIM_MasterConfigTypeDef;
240
241 /**
242 * @brief TIM Slave configuration Structure definition
243 */
244 typedef struct
245 {
246 uint32_t SlaveMode; /*!< Slave mode selection
247 This parameter can be a value of @ref TIM_Slave_Mode */
248 uint32_t InputTrigger; /*!< Input Trigger source
249 This parameter can be a value of @ref TIM_Trigger_Selection */
250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
251 This parameter can be a value of @ref TIM_Trigger_Polarity */
252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
254 uint32_t TriggerFilter; /*!< Input trigger filter
255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
256
257 } TIM_SlaveConfigTypeDef;
258
259 /**
260 * @brief TIM Break input(s) and Dead time configuration Structure definition
261 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
262 * filter and polarity.
263 */
264 typedef struct
265 {
266 uint32_t OffStateRunMode; /*!< TIM off state in run mode
267 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
268 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
269 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
270 uint32_t LockLevel; /*!< TIM Lock level
271 This parameter can be a value of @ref TIM_Lock_level */
272 uint32_t DeadTime; /*!< TIM dead Time
273 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
274 uint32_t BreakState; /*!< TIM Break State
275 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
276 uint32_t BreakPolarity; /*!< TIM Break input polarity
277 This parameter can be a value of @ref TIM_Break_Polarity */
278 uint32_t BreakFilter; /*!< Specifies the break input filter.
279 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
280 uint32_t Break2State; /*!< TIM Break2 State
281 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
282 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
283 This parameter can be a value of @ref TIM_Break2_Polarity */
284 uint32_t Break2Filter; /*!< TIM break2 input filter.
285 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
286 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
287 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
288 } TIM_BreakDeadTimeConfigTypeDef;
289
290 /**
291 * @brief HAL State structures definition
292 */
293 typedef enum
294 {
295 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
296 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
297 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
298 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
299 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
300 } HAL_TIM_StateTypeDef;
301
302 /**
303 * @brief HAL Active channel structures definition
304 */
305 typedef enum
306 {
307 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
308 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
309 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
310 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
311 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
312 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
313 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
314 } HAL_TIM_ActiveChannel;
315
316 /**
317 * @brief TIM Time Base Handle Structure definition
318 */
319 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
320 typedef struct __TIM_HandleTypeDef
321 #else
322 typedef struct
323 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
324 {
325 TIM_TypeDef *Instance; /*!< Register base address */
326 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
327 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
328 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
329 This array is accessed by a @ref DMA_Handle_index */
330 HAL_LockTypeDef Lock; /*!< Locking object */
331 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
332
333 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
334 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
335 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
336 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
337 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
338 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
339 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
340 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
341 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
342 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
343 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
344 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
345 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
346 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
347 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
348 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
349 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
350 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
351 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
352 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
353 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
354 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
355 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
356 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
357 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
358 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
359 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
360 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
361 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
362 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
363 } TIM_HandleTypeDef;
364
365 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
366 /**
367 * @brief HAL TIM Callback ID enumeration definition
368 */
369 typedef enum
370 {
371 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
372 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
373 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
374 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
375 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
376 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
377 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
378 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
379 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
380 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
381 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
382 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
383 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
384 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
385 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
386 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
387 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
388 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
389
390 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
391 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
392 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
393 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
394 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
395 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
396 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
397 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
398 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
399 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
400 } HAL_TIM_CallbackIDTypeDef;
401
402 /**
403 * @brief HAL TIM Callback pointer definition
404 */
405 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
406
407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
408
409 /**
410 * @}
411 */
412 /* End of exported types -----------------------------------------------------*/
413
414 /* Exported constants --------------------------------------------------------*/
415 /** @defgroup TIM_Exported_Constants TIM Exported Constants
416 * @{
417 */
418
419 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
420 * @{
421 */
422 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
423 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
424 /**
425 * @}
426 */
427
428 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
429 * @{
430 */
431 #define TIM_DMABASE_CR1 0x00000000U
432 #define TIM_DMABASE_CR2 0x00000001U
433 #define TIM_DMABASE_SMCR 0x00000002U
434 #define TIM_DMABASE_DIER 0x00000003U
435 #define TIM_DMABASE_SR 0x00000004U
436 #define TIM_DMABASE_EGR 0x00000005U
437 #define TIM_DMABASE_CCMR1 0x00000006U
438 #define TIM_DMABASE_CCMR2 0x00000007U
439 #define TIM_DMABASE_CCER 0x00000008U
440 #define TIM_DMABASE_CNT 0x00000009U
441 #define TIM_DMABASE_PSC 0x0000000AU
442 #define TIM_DMABASE_ARR 0x0000000BU
443 #define TIM_DMABASE_RCR 0x0000000CU
444 #define TIM_DMABASE_CCR1 0x0000000DU
445 #define TIM_DMABASE_CCR2 0x0000000EU
446 #define TIM_DMABASE_CCR3 0x0000000FU
447 #define TIM_DMABASE_CCR4 0x00000010U
448 #define TIM_DMABASE_BDTR 0x00000011U
449 #define TIM_DMABASE_DCR 0x00000012U
450 #define TIM_DMABASE_DMAR 0x00000013U
451 #define TIM_DMABASE_OR 0x00000014U
452 #define TIM_DMABASE_CCMR3 0x00000015U
453 #define TIM_DMABASE_CCR5 0x00000016U
454 #define TIM_DMABASE_CCR6 0x00000017U
455 #if defined(TIM_BREAK_INPUT_SUPPORT)
456 #define TIM_DMABASE_AF1 0x00000018U
457 #define TIM_DMABASE_AF2 0x00000019U
458 #endif /* TIM_BREAK_INPUT_SUPPORT */
459 /**
460 * @}
461 */
462
463 /** @defgroup TIM_Event_Source TIM Event Source
464 * @{
465 */
466 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
467 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
468 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
469 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
470 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
471 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
472 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
473 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
474 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
475 /**
476 * @}
477 */
478
479 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
480 * @{
481 */
482 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
483 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
484 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
485 /**
486 * @}
487 */
488
489 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
490 * @{
491 */
492 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
493 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
494 /**
495 * @}
496 */
497
498 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
499 * @{
500 */
501 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
502 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
503 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
504 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
505 /**
506 * @}
507 */
508
509 /** @defgroup TIM_Counter_Mode TIM Counter Mode
510 * @{
511 */
512 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
513 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
514 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
515 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
516 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
517 /**
518 * @}
519 */
520
521 /** @defgroup TIM_ClockDivision TIM Clock Division
522 * @{
523 */
524 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
525 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
526 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
527 /**
528 * @}
529 */
530
531 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
532 * @{
533 */
534 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
535 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
536 /**
537 * @}
538 */
539
540 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
541 * @{
542 */
543 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
544 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
545
546 /**
547 * @}
548 */
549
550 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
551 * @{
552 */
553 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
554 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
555 /**
556 * @}
557 */
558
559 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
560 * @{
561 */
562 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
563 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
564 /**
565 * @}
566 */
567
568 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
569 * @{
570 */
571 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
572 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
573 /**
574 * @}
575 */
576
577 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
578 * @{
579 */
580 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
581 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
582 /**
583 * @}
584 */
585
586 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
587 * @{
588 */
589 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
590 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
591 /**
592 * @}
593 */
594
595 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
596 * @{
597 */
598 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
599 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
600 /**
601 * @}
602 */
603
604 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
605 * @{
606 */
607 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
608 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
609 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
615 * @{
616 */
617 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
618 connected to IC1, IC2, IC3 or IC4, respectively */
619 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
620 connected to IC2, IC1, IC4 or IC3, respectively */
621 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
627 * @{
628 */
629 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
630 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
631 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
632 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
633 /**
634 * @}
635 */
636
637 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
638 * @{
639 */
640 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
641 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
647 * @{
648 */
649 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
650 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
651 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
657 * @{
658 */
659 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
660 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
661 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
662 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
663 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
664 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
665 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
666 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_Commutation_Source TIM Commutation Source
672 * @{
673 */
674 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
675 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
676 /**
677 * @}
678 */
679
680 /** @defgroup TIM_DMA_sources TIM DMA Sources
681 * @{
682 */
683 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
684 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
685 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
686 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
687 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
688 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
689 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_Flag_definition TIM Flag Definition
695 * @{
696 */
697 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
698 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
699 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
700 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
701 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
702 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
703 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
704 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
705 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
706 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
707 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
708 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
709 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
710 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
711 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
712 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
713 /**
714 * @}
715 */
716
717 /** @defgroup TIM_Channel TIM Channel
718 * @{
719 */
720 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
721 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
722 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
723 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
724 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
725 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
726 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_Clock_Source TIM Clock Source
732 * @{
733 */
734 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
735 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
736 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
737 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
738 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
739 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
740 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
741 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
742 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
743 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
744 /**
745 * @}
746 */
747
748 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
749 * @{
750 */
751 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
752 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
753 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
754 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
755 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
756 /**
757 * @}
758 */
759
760 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
761 * @{
762 */
763 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
764 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
765 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
766 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
767 /**
768 * @}
769 */
770
771 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
772 * @{
773 */
774 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
775 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
776 /**
777 * @}
778 */
779
780 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
781 * @{
782 */
783 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
784 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
785 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
786 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
792 * @{
793 */
794 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
795 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
801 * @{
802 */
803 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
804 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
805 /**
806 * @}
807 */
808 /** @defgroup TIM_Lock_level TIM Lock level
809 * @{
810 */
811 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
812 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
813 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
814 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
815 /**
816 * @}
817 */
818
819 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
820 * @{
821 */
822 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
823 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
824 /**
825 * @}
826 */
827
828 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
829 * @{
830 */
831 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
832 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
833 /**
834 * @}
835 */
836
837 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
838 * @{
839 */
840 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
841 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
842 /**
843 * @}
844 */
845
846 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
847 * @{
848 */
849 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
850 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
856 * @{
857 */
858 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
859 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
860 (if none of the break inputs BRK and BRK2 is active) */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
866 * @{
867 */
868 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
869 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
870 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
871 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
872 /**
873 * @}
874 */
875
876 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
877 * @{
878 */
879 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
880 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
881 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
882 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
883 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
884 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
885 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
886 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
887 /**
888 * @}
889 */
890
891 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
892 * @{
893 */
894 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
895 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
896 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
897 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
898 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
899 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
900 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
901 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
902 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
903 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
904 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
905 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
906 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
907 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
908 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
909 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
910 /**
911 * @}
912 */
913
914 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
915 * @{
916 */
917 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
918 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
919 /**
920 * @}
921 */
922
923 /** @defgroup TIM_Slave_Mode TIM Slave mode
924 * @{
925 */
926 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
927 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
928 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
929 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
930 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
931 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
932 /**
933 * @}
934 */
935
936 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
937 * @{
938 */
939 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
940 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
941 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
942 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
943 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
944 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
945 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
946 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
947 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
948 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
949 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
950 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
951 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
952 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
953 /**
954 * @}
955 */
956
957 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
958 * @{
959 */
960 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
961 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
962 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
963 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
964 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
965 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
966 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
967 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
968 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
969 /**
970 * @}
971 */
972
973 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
974 * @{
975 */
976 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
977 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
978 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
979 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
980 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
981 /**
982 * @}
983 */
984
985 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
986 * @{
987 */
988 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
989 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
990 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
991 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
992 /**
993 * @}
994 */
995
996 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
997 * @{
998 */
999 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
1000 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1006 * @{
1007 */
1008 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
1009 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1010 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1011 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1012 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1013 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1014 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1015 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1016 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1017 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1018 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1019 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1020 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1021 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1022 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1023 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1024 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1025 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1026 /**
1027 * @}
1028 */
1029
1030 /** @defgroup DMA_Handle_index TIM DMA Handle Index
1031 * @{
1032 */
1033 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
1034 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1035 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1036 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1037 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1038 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
1039 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1045 * @{
1046 */
1047 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
1048 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
1049 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
1050 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup TIM_Break_System TIM Break System
1056 * @{
1057 */
1058 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
1059 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1060 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
1061 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
1062 /**
1063 * @}
1064 */
1065
1066 /**
1067 * @}
1068 */
1069 /* End of exported constants -------------------------------------------------*/
1070
1071 /* Exported macros -----------------------------------------------------------*/
1072 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1073 * @{
1074 */
1075
1076 /** @brief Reset TIM handle state.
1077 * @param __HANDLE__ TIM handle.
1078 * @retval None
1079 */
1080 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1081 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1082 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1083 (__HANDLE__)->Base_MspInitCallback = NULL; \
1084 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1085 (__HANDLE__)->IC_MspInitCallback = NULL; \
1086 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1087 (__HANDLE__)->OC_MspInitCallback = NULL; \
1088 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1089 (__HANDLE__)->PWM_MspInitCallback = NULL; \
1090 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1091 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1092 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1093 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1094 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1095 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1096 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1097 } while(0)
1098 #else
1099 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1100 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1101
1102 /**
1103 * @brief Enable the TIM peripheral.
1104 * @param __HANDLE__ TIM handle
1105 * @retval None
1106 */
1107 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1108
1109 /**
1110 * @brief Enable the TIM main Output.
1111 * @param __HANDLE__ TIM handle
1112 * @retval None
1113 */
1114 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1115
1116 /**
1117 * @brief Disable the TIM peripheral.
1118 * @param __HANDLE__ TIM handle
1119 * @retval None
1120 */
1121 #define __HAL_TIM_DISABLE(__HANDLE__) \
1122 do { \
1123 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1124 { \
1125 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1126 { \
1127 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1128 } \
1129 } \
1130 } while(0)
1131
1132 /**
1133 * @brief Disable the TIM main Output.
1134 * @param __HANDLE__ TIM handle
1135 * @retval None
1136 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1137 */
1138 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1139 do { \
1140 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1141 { \
1142 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1143 { \
1144 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1145 } \
1146 } \
1147 } while(0)
1148
1149 /**
1150 * @brief Disable the TIM main Output.
1151 * @param __HANDLE__ TIM handle
1152 * @retval None
1153 * @note The Main Output Enable of a timer instance is disabled unconditionally
1154 */
1155 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1156
1157 /** @brief Enable the specified TIM interrupt.
1158 * @param __HANDLE__ specifies the TIM Handle.
1159 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
1160 * This parameter can be one of the following values:
1161 * @arg TIM_IT_UPDATE: Update interrupt
1162 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1163 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1164 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1165 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1166 * @arg TIM_IT_COM: Commutation interrupt
1167 * @arg TIM_IT_TRIGGER: Trigger interrupt
1168 * @arg TIM_IT_BREAK: Break interrupt
1169 * @retval None
1170 */
1171 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1172
1173 /** @brief Disable the specified TIM interrupt.
1174 * @param __HANDLE__ specifies the TIM Handle.
1175 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
1176 * This parameter can be one of the following values:
1177 * @arg TIM_IT_UPDATE: Update interrupt
1178 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1179 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1180 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1181 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1182 * @arg TIM_IT_COM: Commutation interrupt
1183 * @arg TIM_IT_TRIGGER: Trigger interrupt
1184 * @arg TIM_IT_BREAK: Break interrupt
1185 * @retval None
1186 */
1187 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1188
1189 /** @brief Enable the specified DMA request.
1190 * @param __HANDLE__ specifies the TIM Handle.
1191 * @param __DMA__ specifies the TIM DMA request to enable.
1192 * This parameter can be one of the following values:
1193 * @arg TIM_DMA_UPDATE: Update DMA request
1194 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1195 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1196 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1197 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1198 * @arg TIM_DMA_COM: Commutation DMA request
1199 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1200 * @retval None
1201 */
1202 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1203
1204 /** @brief Disable the specified DMA request.
1205 * @param __HANDLE__ specifies the TIM Handle.
1206 * @param __DMA__ specifies the TIM DMA request to disable.
1207 * This parameter can be one of the following values:
1208 * @arg TIM_DMA_UPDATE: Update DMA request
1209 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1210 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1211 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1212 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1213 * @arg TIM_DMA_COM: Commutation DMA request
1214 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1215 * @retval None
1216 */
1217 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1218
1219 /** @brief Check whether the specified TIM interrupt flag is set or not.
1220 * @param __HANDLE__ specifies the TIM Handle.
1221 * @param __FLAG__ specifies the TIM interrupt flag to check.
1222 * This parameter can be one of the following values:
1223 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1224 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1225 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1226 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1227 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1228 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1229 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1230 * @arg TIM_FLAG_COM: Commutation interrupt flag
1231 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1232 * @arg TIM_FLAG_BREAK: Break interrupt flag
1233 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1234 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1235 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1236 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1237 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1238 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1239 * @retval The new state of __FLAG__ (TRUE or FALSE).
1240 */
1241 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1242
1243 /** @brief Clear the specified TIM interrupt flag.
1244 * @param __HANDLE__ specifies the TIM Handle.
1245 * @param __FLAG__ specifies the TIM interrupt flag to clear.
1246 * This parameter can be one of the following values:
1247 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1248 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1249 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1250 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1251 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1252 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1253 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1254 * @arg TIM_FLAG_COM: Commutation interrupt flag
1255 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1256 * @arg TIM_FLAG_BREAK: Break interrupt flag
1257 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1258 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1259 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1260 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1261 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1262 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1263 * @retval The new state of __FLAG__ (TRUE or FALSE).
1264 */
1265 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1266
1267 /**
1268 * @brief Check whether the specified TIM interrupt source is enabled or not.
1269 * @param __HANDLE__ TIM handle
1270 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
1271 * This parameter can be one of the following values:
1272 * @arg TIM_IT_UPDATE: Update interrupt
1273 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1274 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1275 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1276 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1277 * @arg TIM_IT_COM: Commutation interrupt
1278 * @arg TIM_IT_TRIGGER: Trigger interrupt
1279 * @arg TIM_IT_BREAK: Break interrupt
1280 * @retval The state of TIM_IT (SET or RESET).
1281 */
1282 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1283
1284 /** @brief Clear the TIM interrupt pending bits.
1285 * @param __HANDLE__ TIM handle
1286 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1287 * This parameter can be one of the following values:
1288 * @arg TIM_IT_UPDATE: Update interrupt
1289 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1290 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1291 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1292 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1293 * @arg TIM_IT_COM: Commutation interrupt
1294 * @arg TIM_IT_TRIGGER: Trigger interrupt
1295 * @arg TIM_IT_BREAK: Break interrupt
1296 * @retval None
1297 */
1298 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1299
1300 /**
1301 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1302 * @param __HANDLE__ TIM handle.
1303 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1304 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
1305 mode.
1306 */
1307 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1308
1309 /**
1310 * @brief Set the TIM Prescaler on runtime.
1311 * @param __HANDLE__ TIM handle.
1312 * @param __PRESC__ specifies the Prescaler new value.
1313 * @retval None
1314 */
1315 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1316
1317 /**
1318 * @brief Set the TIM Counter Register value on runtime.
1319 * @param __HANDLE__ TIM handle.
1320 * @param __COUNTER__ specifies the Counter register new value.
1321 * @retval None
1322 */
1323 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1324
1325 /**
1326 * @brief Get the TIM Counter Register value on runtime.
1327 * @param __HANDLE__ TIM handle.
1328 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1329 */
1330 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
1331 ((__HANDLE__)->Instance->CNT)
1332
1333 /**
1334 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1335 * @param __HANDLE__ TIM handle.
1336 * @param __AUTORELOAD__ specifies the Counter register new value.
1337 * @retval None
1338 */
1339 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1340 do{ \
1341 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1342 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1343 } while(0)
1344
1345 /**
1346 * @brief Get the TIM Autoreload Register value on runtime.
1347 * @param __HANDLE__ TIM handle.
1348 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1349 */
1350 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1351 ((__HANDLE__)->Instance->ARR)
1352
1353 /**
1354 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1355 * @param __HANDLE__ TIM handle.
1356 * @param __CKD__ specifies the clock division value.
1357 * This parameter can be one of the following value:
1358 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1359 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1360 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1361 * @retval None
1362 */
1363 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1364 do{ \
1365 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1366 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1367 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1368 } while(0)
1369
1370 /**
1371 * @brief Get the TIM Clock Division value on runtime.
1372 * @param __HANDLE__ TIM handle.
1373 * @retval The clock division can be one of the following values:
1374 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1375 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1376 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1377 */
1378 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
1379 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1380
1381 /**
1382 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
1383 * @param __HANDLE__ TIM handle.
1384 * @param __CHANNEL__ TIM Channels to be configured.
1385 * This parameter can be one of the following values:
1386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1388 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1389 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1390 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1391 * This parameter can be one of the following values:
1392 * @arg TIM_ICPSC_DIV1: no prescaler
1393 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1394 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1395 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1396 * @retval None
1397 */
1398 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1399 do{ \
1400 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1401 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1402 } while(0)
1403
1404 /**
1405 * @brief Get the TIM Input Capture prescaler on runtime.
1406 * @param __HANDLE__ TIM handle.
1407 * @param __CHANNEL__ TIM Channels to be configured.
1408 * This parameter can be one of the following values:
1409 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1410 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1411 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1412 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1413 * @retval The input capture prescaler can be one of the following values:
1414 * @arg TIM_ICPSC_DIV1: no prescaler
1415 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1416 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1417 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1418 */
1419 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1420 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1421 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1422 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1423 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1424
1425 /**
1426 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1427 * @param __HANDLE__ TIM handle.
1428 * @param __CHANNEL__ TIM Channels to be configured.
1429 * This parameter can be one of the following values:
1430 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1431 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1432 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1433 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1434 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1435 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1436 * @param __COMPARE__ specifies the Capture Compare register new value.
1437 * @retval None
1438 */
1439 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1440 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1441 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1442 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1443 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1444 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1445 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1446
1447 /**
1448 * @brief Get the TIM Capture Compare Register value on runtime.
1449 * @param __HANDLE__ TIM handle.
1450 * @param __CHANNEL__ TIM Channel associated with the capture compare register
1451 * This parameter can be one of the following values:
1452 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1453 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1454 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1455 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1456 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1457 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1458 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1459 */
1460 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1461 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1462 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1463 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1464 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1465 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1466 ((__HANDLE__)->Instance->CCR6))
1467
1468 /**
1469 * @brief Set the TIM Output compare preload.
1470 * @param __HANDLE__ TIM handle.
1471 * @param __CHANNEL__ TIM Channels to be configured.
1472 * This parameter can be one of the following values:
1473 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1474 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1475 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1476 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1477 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1478 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1479 * @retval None
1480 */
1481 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1482 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1483 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1484 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1485 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1486 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1487 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1488
1489 /**
1490 * @brief Reset the TIM Output compare preload.
1491 * @param __HANDLE__ TIM handle.
1492 * @param __CHANNEL__ TIM Channels to be configured.
1493 * This parameter can be one of the following values:
1494 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1495 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1496 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1497 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1498 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1499 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1500 * @retval None
1501 */
1502 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1503 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
1504 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
1505 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
1506 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
1507 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
1508 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
1509
1510 /**
1511 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1512 * @param __HANDLE__ TIM handle.
1513 * @note When the URS bit of the TIMx_CR1 register is set, only counter
1514 * overflow/underflow generates an update interrupt or DMA request (if
1515 * enabled)
1516 * @retval None
1517 */
1518 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1519 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1520
1521 /**
1522 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1523 * @param __HANDLE__ TIM handle.
1524 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
1525 * following events generate an update interrupt or DMA request (if
1526 * enabled):
1527 * _ Counter overflow underflow
1528 * _ Setting the UG bit
1529 * _ Update generation through the slave mode controller
1530 * @retval None
1531 */
1532 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1533 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1534
1535 /**
1536 * @brief Set the TIM Capture x input polarity on runtime.
1537 * @param __HANDLE__ TIM handle.
1538 * @param __CHANNEL__ TIM Channels to be configured.
1539 * This parameter can be one of the following values:
1540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1542 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1543 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1544 * @param __POLARITY__ Polarity for TIx source
1545 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1546 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1547 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1548 * @retval None
1549 */
1550 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1551 do{ \
1552 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1553 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1554 }while(0)
1555
1556 /**
1557 * @}
1558 */
1559 /* End of exported macros ----------------------------------------------------*/
1560
1561 /* Private constants ---------------------------------------------------------*/
1562 /** @defgroup TIM_Private_Constants TIM Private Constants
1563 * @{
1564 */
1565 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1566 channels have been disabled */
1567 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1568 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1569 /**
1570 * @}
1571 */
1572 /* End of private constants --------------------------------------------------*/
1573
1574 /* Private macros ------------------------------------------------------------*/
1575 /** @defgroup TIM_Private_Macros TIM Private Macros
1576 * @{
1577 */
1578 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1579 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1580
1581 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
1582 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1583 ((__BASE__) == TIM_DMABASE_CR2) || \
1584 ((__BASE__) == TIM_DMABASE_SMCR) || \
1585 ((__BASE__) == TIM_DMABASE_DIER) || \
1586 ((__BASE__) == TIM_DMABASE_SR) || \
1587 ((__BASE__) == TIM_DMABASE_EGR) || \
1588 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1589 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1590 ((__BASE__) == TIM_DMABASE_CCER) || \
1591 ((__BASE__) == TIM_DMABASE_CNT) || \
1592 ((__BASE__) == TIM_DMABASE_PSC) || \
1593 ((__BASE__) == TIM_DMABASE_ARR) || \
1594 ((__BASE__) == TIM_DMABASE_RCR) || \
1595 ((__BASE__) == TIM_DMABASE_CCR1) || \
1596 ((__BASE__) == TIM_DMABASE_CCR2) || \
1597 ((__BASE__) == TIM_DMABASE_CCR3) || \
1598 ((__BASE__) == TIM_DMABASE_CCR4) || \
1599 ((__BASE__) == TIM_DMABASE_BDTR) || \
1600 ((__BASE__) == TIM_DMABASE_OR) || \
1601 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1602 ((__BASE__) == TIM_DMABASE_CCR5) || \
1603 ((__BASE__) == TIM_DMABASE_CCR6) || \
1604 ((__BASE__) == TIM_DMABASE_AF1) || \
1605 ((__BASE__) == TIM_DMABASE_AF2))
1606 #else
1607 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1608 ((__BASE__) == TIM_DMABASE_CR2) || \
1609 ((__BASE__) == TIM_DMABASE_SMCR) || \
1610 ((__BASE__) == TIM_DMABASE_DIER) || \
1611 ((__BASE__) == TIM_DMABASE_SR) || \
1612 ((__BASE__) == TIM_DMABASE_EGR) || \
1613 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1614 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1615 ((__BASE__) == TIM_DMABASE_CCER) || \
1616 ((__BASE__) == TIM_DMABASE_CNT) || \
1617 ((__BASE__) == TIM_DMABASE_PSC) || \
1618 ((__BASE__) == TIM_DMABASE_ARR) || \
1619 ((__BASE__) == TIM_DMABASE_RCR) || \
1620 ((__BASE__) == TIM_DMABASE_CCR1) || \
1621 ((__BASE__) == TIM_DMABASE_CCR2) || \
1622 ((__BASE__) == TIM_DMABASE_CCR3) || \
1623 ((__BASE__) == TIM_DMABASE_CCR4) || \
1624 ((__BASE__) == TIM_DMABASE_BDTR) || \
1625 ((__BASE__) == TIM_DMABASE_OR) || \
1626 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1627 ((__BASE__) == TIM_DMABASE_CCR5) || \
1628 ((__BASE__) == TIM_DMABASE_CCR6))
1629 #endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */
1630
1631 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1632
1633 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1634 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1635 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1636 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1637 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1638
1639 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1640 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1641 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1642
1643 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1644 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1645
1646 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1647 ((__STATE__) == TIM_OCFAST_ENABLE))
1648
1649 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1650 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1651
1652 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1653 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1654
1655 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1656 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1657
1658 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1659 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1660
1661 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1662 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1663 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1664
1665 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1666 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1667 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1668
1669 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1670 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1671 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1672 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1673
1674 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1675 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1676
1677 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1678 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1679 ((__MODE__) == TIM_ENCODERMODE_TI12))
1680
1681 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1682
1683 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1684 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1685 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1686 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1687 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1688 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1689 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1690
1691 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1692 ((__CHANNEL__) == TIM_CHANNEL_2))
1693
1694 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1695 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1696 ((__CHANNEL__) == TIM_CHANNEL_3))
1697
1698 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1699 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1700 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1701 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1702 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1703 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1704 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1705 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1706 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1707 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1708
1709 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1710 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1711 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1712 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1713 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1714
1715 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1716 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1717 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1718 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1719
1720 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1721
1722 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1723 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1724
1725 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1726 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1727 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1728 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1729
1730 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1731
1732 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1733 ((__STATE__) == TIM_OSSR_DISABLE))
1734
1735 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1736 ((__STATE__) == TIM_OSSI_DISABLE))
1737
1738 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1739 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1740 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1741 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1742
1743 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1744
1745
1746 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1747 ((__STATE__) == TIM_BREAK_DISABLE))
1748
1749 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1750 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1751
1752 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1753 ((__STATE__) == TIM_BREAK2_DISABLE))
1754
1755 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1756 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1757
1758 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1759 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1760
1761 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1762
1763 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1764 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1765 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1766 ((__SOURCE__) == TIM_TRGO_OC1) || \
1767 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1768 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1769 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1770 ((__SOURCE__) == TIM_TRGO_OC4REF))
1771
1772 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1773 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1774 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1775 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1776 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1777 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1778 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1779 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1780 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1781 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1782 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1783 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1784 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1785 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1786 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1787 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1788 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1789
1790 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1791 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1792
1793 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1794 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1795 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1796 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1797 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1798 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1799
1800 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1801 ((__MODE__) == TIM_OCMODE_PWM2) || \
1802 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1803 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1804 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1805 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1806
1807 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1808 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1809 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1810 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1811 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1812 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1813 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1814 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1815
1816 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1817 ((__SELECTION__) == TIM_TS_ITR1) || \
1818 ((__SELECTION__) == TIM_TS_ITR2) || \
1819 ((__SELECTION__) == TIM_TS_ITR3) || \
1820 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1821 ((__SELECTION__) == TIM_TS_TI1FP1) || \
1822 ((__SELECTION__) == TIM_TS_TI2FP2) || \
1823 ((__SELECTION__) == TIM_TS_ETRF))
1824
1825 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1826 ((__SELECTION__) == TIM_TS_ITR1) || \
1827 ((__SELECTION__) == TIM_TS_ITR2) || \
1828 ((__SELECTION__) == TIM_TS_ITR3) || \
1829 ((__SELECTION__) == TIM_TS_NONE))
1830
1831 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1832 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1833 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1834 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1835 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1836
1837 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1838 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1839 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1840 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1841
1842 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1843
1844 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1845 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1846
1847 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1848 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1849 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1850 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1851 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1852 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1853 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1854 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1855 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1856 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1857 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1858 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1859 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1860 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1861 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1862 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1863 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1864 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1865
1866 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1867
1868 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1869
1870 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
1871 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
1872 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
1873 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
1874
1875 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
1876 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1877
1878 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1879 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1880 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1881 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1882 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1883
1884 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1885 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1886 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1887 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1888 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1889
1890 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1891 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1892 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1893 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1894 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1895
1896 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1897 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1898 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1899 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1900 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1901
1902 /**
1903 * @}
1904 */
1905 /* End of private macros -----------------------------------------------------*/
1906
1907 /* Include TIM HAL Extended module */
1908 #include "stm32f7xx_hal_tim_ex.h"
1909
1910 /* Exported functions --------------------------------------------------------*/
1911 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
1912 * @{
1913 */
1914
1915 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
1916 * @brief Time Base functions
1917 * @{
1918 */
1919 /* Time Base functions ********************************************************/
1920 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1921 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1922 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1923 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1924 /* Blocking mode: Polling */
1925 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1926 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1927 /* Non-Blocking mode: Interrupt */
1928 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1929 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1930 /* Non-Blocking mode: DMA */
1931 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1932 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1933 /**
1934 * @}
1935 */
1936
1937 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
1938 * @brief TIM Output Compare functions
1939 * @{
1940 */
1941 /* Timer Output Compare functions *********************************************/
1942 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1943 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1944 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1945 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1946 /* Blocking mode: Polling */
1947 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1948 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1949 /* Non-Blocking mode: Interrupt */
1950 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1951 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1952 /* Non-Blocking mode: DMA */
1953 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1954 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1955 /**
1956 * @}
1957 */
1958
1959 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
1960 * @brief TIM PWM functions
1961 * @{
1962 */
1963 /* Timer PWM functions ********************************************************/
1964 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1965 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1966 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1967 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1968 /* Blocking mode: Polling */
1969 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1970 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1971 /* Non-Blocking mode: Interrupt */
1972 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1973 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1974 /* Non-Blocking mode: DMA */
1975 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1976 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1977 /**
1978 * @}
1979 */
1980
1981 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1982 * @brief TIM Input Capture functions
1983 * @{
1984 */
1985 /* Timer Input Capture functions **********************************************/
1986 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1987 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1988 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1989 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1990 /* Blocking mode: Polling */
1991 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1992 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1993 /* Non-Blocking mode: Interrupt */
1994 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1995 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1996 /* Non-Blocking mode: DMA */
1997 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1998 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1999 /**
2000 * @}
2001 */
2002
2003 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2004 * @brief TIM One Pulse functions
2005 * @{
2006 */
2007 /* Timer One Pulse functions **************************************************/
2008 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2009 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2010 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2011 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2012 /* Blocking mode: Polling */
2013 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2014 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2015 /* Non-Blocking mode: Interrupt */
2016 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2017 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2018 /**
2019 * @}
2020 */
2021
2022 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2023 * @brief TIM Encoder functions
2024 * @{
2025 */
2026 /* Timer Encoder functions ****************************************************/
2027 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
2028 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2029 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2030 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2031 /* Blocking mode: Polling */
2032 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2033 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2034 /* Non-Blocking mode: Interrupt */
2035 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2036 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2037 /* Non-Blocking mode: DMA */
2038 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
2039 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2040 /**
2041 * @}
2042 */
2043
2044 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2045 * @brief IRQ handler management
2046 * @{
2047 */
2048 /* Interrupt Handler functions ***********************************************/
2049 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2050 /**
2051 * @}
2052 */
2053
2054 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2055 * @brief Peripheral Control functions
2056 * @{
2057 */
2058 /* Control functions *********************************************************/
2059 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2060 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2061 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2062 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
2063 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
2064 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2065 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2066 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2067 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2068 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
2069 uint32_t *BurstBuffer, uint32_t BurstLength);
2070 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2071 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
2072 uint32_t *BurstBuffer, uint32_t BurstLength);
2073 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2074 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2075 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2076 /**
2077 * @}
2078 */
2079
2080 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2081 * @brief TIM Callbacks functions
2082 * @{
2083 */
2084 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2085 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2086 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2087 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2088 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2089 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2090 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2091 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2092 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2093 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2094 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2095
2096 /* Callbacks Register/UnRegister functions ***********************************/
2097 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2098 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
2099 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2100 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2101
2102 /**
2103 * @}
2104 */
2105
2106 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2107 * @brief Peripheral State functions
2108 * @{
2109 */
2110 /* Peripheral State functions ************************************************/
2111 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2112 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2113 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2114 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2115 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2116 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2117 /**
2118 * @}
2119 */
2120
2121 /**
2122 * @}
2123 */
2124 /* End of exported functions -------------------------------------------------*/
2125
2126 /* Private functions----------------------------------------------------------*/
2127 /** @defgroup TIM_Private_Functions TIM Private Functions
2128 * @{
2129 */
2130 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2131 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2132 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2133 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2134 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2135
2136 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2137 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2138 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2139 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2140 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2141 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2142
2143 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2144 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2145 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2146
2147 /**
2148 * @}
2149 */
2150 /* End of private functions --------------------------------------------------*/
2151
2152 /**
2153 * @}
2154 */
2155
2156 /**
2157 * @}
2158 */
2159
2160 #ifdef __cplusplus
2161 }
2162 #endif
2163
2164 #endif /* STM32F7xx_HAL_TIM_H */
2165
2166 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/