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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_adc.h
blobe857b561a890878f7689df2618713258d1605d88
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_ADC_H
22 #define __STM32F7xx_LL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @defgroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46 * @{
47 */
48
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET 0x00000000U
57 #define ADC_SQR2_REGOFFSET 0x00000100U
58 #define ADC_SQR3_REGOFFSET 0x00000200U
59 #define ADC_SQR4_REGOFFSET 0x00000300U
60
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
63
64 /* Definition of ADC group regular sequencer bits information to be inserted */
65 /* into ADC group regular sequencer ranks literals definition. */
66 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
67 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
68 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
69 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
70 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
71 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
72 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
73 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
74 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
75 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
76 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
77 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
78 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
79 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
80 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
81 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
82
83 /* Internal mask for ADC group injected sequencer: */
84 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
85 /* - data register offset */
86 /* - offset register offset */
87 /* - sequencer rank bits position into the selected register */
88
89 /* Internal register offset for ADC group injected data register */
90 /* (offset placed into a spare area of literal definition) */
91 #define ADC_JDR1_REGOFFSET 0x00000000U
92 #define ADC_JDR2_REGOFFSET 0x00000100U
93 #define ADC_JDR3_REGOFFSET 0x00000200U
94 #define ADC_JDR4_REGOFFSET 0x00000300U
95
96 /* Internal register offset for ADC group injected offset configuration */
97 /* (offset placed into a spare area of literal definition) */
98 #define ADC_JOFR1_REGOFFSET 0x00000000U
99 #define ADC_JOFR2_REGOFFSET 0x00001000U
100 #define ADC_JOFR3_REGOFFSET 0x00002000U
101 #define ADC_JOFR4_REGOFFSET 0x00003000U
102
103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
106
107 /* Internal mask for ADC group regular trigger: */
108 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
109 /* - regular trigger source */
110 /* - regular trigger edge */
111 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
112
113 /* Mask containing trigger source masks for each of possible */
114 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
115 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
116 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
117 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
118 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
119 ((ADC_CR2_EXTSEL) >> (4U * 3U)))
120
121 /* Mask containing trigger edge masks for each of possible */
122 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
123 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
124 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
127 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
128
129 /* Definition of ADC group regular trigger bits information. */
130 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
131 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
132
133
134
135 /* Internal mask for ADC group injected trigger: */
136 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
137 /* - injected trigger source */
138 /* - injected trigger edge */
139 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
140
141 /* Mask containing trigger source masks for each of possible */
142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
145 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
146 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
147 ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
148
149 /* Mask containing trigger edge masks for each of possible */
150 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
151 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
152 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
155 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
156
157 /* Definition of ADC group injected trigger bits information. */
158 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
159 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
160
161 /* Internal mask for ADC channel: */
162 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
163 /* - channel identifier defined by number */
164 /* - channel differentiation between external channels (connected to */
165 /* GPIO pins) and internal channels (connected to internal paths) */
166 /* - channel sampling time defined by SMPRx register offset */
167 /* and SMPx bits positions into SMPRx register */
168 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
169 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
170 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
171 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
172 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
173
174 /* Channel differentiation between external and internal channels */
175 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
176 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
177 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
178 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
179
180 /* Internal register offset for ADC channel sampling time configuration */
181 /* (offset placed into a spare area of literal definition) */
182 #define ADC_SMPR1_REGOFFSET 0x00000000U
183 #define ADC_SMPR2_REGOFFSET 0x02000000U
184 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
185
186 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
187 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
188
189 /* Definition of channels ID number information to be inserted into */
190 /* channels literals definition. */
191 #define ADC_CHANNEL_0_NUMBER 0x00000000U
192 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
193 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
194 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
195 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
196 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
197 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
198 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
199 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
200 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
201 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
202 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
203 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
204 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
205 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
206 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
207 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
208 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
209 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
210
211 /* Definition of channels sampling time information to be inserted into */
212 /* channels literals definition. */
213 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
214 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
215 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
216 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
217 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
218 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
219 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
220 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
221 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
222 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
223 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
224 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
225 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
226 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
227 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
228 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
229 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
230 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
231 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
232
233 /* Internal mask for ADC analog watchdog: */
234 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
235 /* (concatenation of multiple bits used in different analog watchdogs, */
236 /* (feature of several watchdogs not available on all STM32 families)). */
237 /* - analog watchdog 1: monitored channel defined by number, */
238 /* selection of ADC group (ADC groups regular and-or injected). */
239
240 /* Internal register offset for ADC analog watchdog channel configuration */
241 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
242
243 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
244
245 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
246 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
247
248 /* Internal register offset for ADC analog watchdog threshold configuration */
249 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
250 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
251 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
252
253 /* ADC registers bits positions */
254 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
255 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
256 /* ADC internal channels related definitions */
257 /* Internal voltage reference VrefInt */
258 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
259 #define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
260 /* Temperature sensor */
261 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
262 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
263 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
264 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
265 #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
266 /**
267 * @}
268 */
269
270
271 /* Private macros ------------------------------------------------------------*/
272 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
273 * @{
274 */
275
276 /**
277 * @brief Driver macro reserved for internal use: isolate bits with the
278 * selected mask and shift them to the register LSB
279 * (shift mask on register position bit 0).
280 * @param __BITS__ Bits in register 32 bits
281 * @param __MASK__ Mask in register 32 bits
282 * @retval Bits in register 32 bits
283 */
284 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
285 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
286
287 /**
288 * @brief Driver macro reserved for internal use: set a pointer to
289 * a register from a register basis from which an offset
290 * is applied.
291 * @param __REG__ Register basis from which the offset is applied.
292 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
293 * @retval Pointer to register address
294 */
295 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
296 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
297
298 /**
299 * @}
300 */
301
302
303 /* Exported types ------------------------------------------------------------*/
304 #if defined(USE_FULL_LL_DRIVER)
305 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
306 * @{
307 */
308
309 /**
310 * @brief Structure definition of some features of ADC common parameters
311 * and multimode
312 * (all ADC instances belonging to the same ADC common instance).
313 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
314 * is conditioned to ADC instances state (all ADC instances
315 * sharing the same ADC common instance):
316 * All ADC instances sharing the same ADC common instance must be
317 * disabled.
318 */
319 typedef struct
320 {
321 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
322 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
323
324 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
325
326 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
327 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
328
329 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
330
331 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
332 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
333
334 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
335
336 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
337 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
338
339 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
340
341 } LL_ADC_CommonInitTypeDef;
342
343 /**
344 * @brief Structure definition of some features of ADC instance.
345 * @note These parameters have an impact on ADC scope: ADC instance.
346 * Affects both group regular and group injected (availability
347 * of ADC group injected depends on STM32 families).
348 * Refer to corresponding unitary functions into
349 * @ref ADC_LL_EF_Configuration_ADC_Instance .
350 * @note The setting of these parameters by function @ref LL_ADC_Init()
351 * is conditioned to ADC state:
352 * ADC instance must be disabled.
353 * This condition is applied to all ADC features, for efficiency
354 * and compatibility over all STM32 families. However, the different
355 * features can be set under different ADC state conditions
356 * (setting possible with ADC enabled without conversion on going,
357 * ADC enabled with conversion on going, ...)
358 * Each feature can be updated afterwards with a unitary function
359 * and potentially with ADC in a different state than disabled,
360 * refer to description of each function for setting
361 * conditioned to ADC state.
362 */
363 typedef struct
364 {
365 uint32_t Resolution; /*!< Set ADC resolution.
366 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
367
368 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
369
370 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
371 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
372
373 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
374
375 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
376 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
377
378 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
379
380 } LL_ADC_InitTypeDef;
381
382 /**
383 * @brief Structure definition of some features of ADC group regular.
384 * @note These parameters have an impact on ADC scope: ADC group regular.
385 * Refer to corresponding unitary functions into
386 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
387 * (functions with prefix "REG").
388 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
389 * is conditioned to ADC state:
390 * ADC instance must be disabled.
391 * This condition is applied to all ADC features, for efficiency
392 * and compatibility over all STM32 families. However, the different
393 * features can be set under different ADC state conditions
394 * (setting possible with ADC enabled without conversion on going,
395 * ADC enabled with conversion on going, ...)
396 * Each feature can be updated afterwards with a unitary function
397 * and potentially with ADC in a different state than disabled,
398 * refer to description of each function for setting
399 * conditioned to ADC state.
400 */
401 typedef struct
402 {
403 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
404 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
405 @note On this STM32 serie, setting of external trigger edge is performed
406 using function @ref LL_ADC_REG_StartConversionExtTrig().
407
408 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
409
410 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
411 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
412 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
413
414 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
415
416 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
417 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
418 @note This parameter has an effect only if group regular sequencer is enabled
419 (scan length of 2 ranks or more).
420
421 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
422
423 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
424 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
425 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
426
427 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
428
429 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
430 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
431
432 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
433
434 } LL_ADC_REG_InitTypeDef;
435
436 /**
437 * @brief Structure definition of some features of ADC group injected.
438 * @note These parameters have an impact on ADC scope: ADC group injected.
439 * Refer to corresponding unitary functions into
440 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
441 * (functions with prefix "INJ").
442 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
443 * is conditioned to ADC state:
444 * ADC instance must be disabled.
445 * This condition is applied to all ADC features, for efficiency
446 * and compatibility over all STM32 families. However, the different
447 * features can be set under different ADC state conditions
448 * (setting possible with ADC enabled without conversion on going,
449 * ADC enabled with conversion on going, ...)
450 * Each feature can be updated afterwards with a unitary function
451 * and potentially with ADC in a different state than disabled,
452 * refer to description of each function for setting
453 * conditioned to ADC state.
454 */
455 typedef struct
456 {
457 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
458 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
459 @note On this STM32 serie, setting of external trigger edge is performed
460 using function @ref LL_ADC_INJ_StartConversionExtTrig().
461
462 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
463
464 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
465 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
466 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
467
468 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
469
470 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
471 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
472 @note This parameter has an effect only if group injected sequencer is enabled
473 (scan length of 2 ranks or more).
474
475 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
476
477 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
478 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
479 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
480
481 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
482
483 } LL_ADC_INJ_InitTypeDef;
484
485 /**
486 * @}
487 */
488 #endif /* USE_FULL_LL_DRIVER */
489
490 /* Exported constants --------------------------------------------------------*/
491 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
492 * @{
493 */
494
495 /** @defgroup ADC_LL_EC_FLAG ADC flags
496 * @brief Flags defines which can be used with LL_ADC_ReadReg function
497 * @{
498 */
499 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
500 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
501 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
502 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
503 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
504 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
505 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
506 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
507 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
508 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
509 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
510 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
511 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
512 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
513 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
514 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
515 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
516 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
517 /**
518 * @}
519 */
520
521 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
522 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
523 * @{
524 */
525 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
526 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
527 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
528 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
529 /**
530 * @}
531 */
532
533 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
534 * @{
535 */
536 /* List of ADC registers intended to be used (most commonly) with */
537 /* DMA transfer. */
538 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
539 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
540 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
541 /**
542 * @}
543 */
544
545 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
546 * @{
547 */
548 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
549 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
550 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
551 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
552 /**
553 * @}
554 */
555
556 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
557 * @{
558 */
559 /* Note: Other measurement paths to internal channels may be available */
560 /* (connections to other peripherals). */
561 /* If they are not listed below, they do not require any specific */
562 /* path enable. In this case, Access to measurement path is done */
563 /* only by selecting the corresponding ADC internal channel. */
564 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
565 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
566 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
567 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
568 /**
569 * @}
570 */
571
572 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
573 * @{
574 */
575 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
576 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
577 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
578 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
579 /**
580 * @}
581 */
582
583 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
584 * @{
585 */
586 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
587 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
588 /**
589 * @}
590 */
591
592 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
593 * @{
594 */
595 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
596 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
597 /**
598 * @}
599 */
600
601 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
602 * @{
603 */
604 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
605 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
606 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
607 /**
608 * @}
609 */
610
611 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
612 * @{
613 */
614 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
615 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
616 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
617 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
618 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
619 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
620 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
621 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
622 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
623 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
624 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
625 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
626 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
627 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
628 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
629 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
630 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
631 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
632 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
633 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */
634 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */
635 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */
636
637 /**
638 * @}
639 */
640
641 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
642 * @{
643 */
644 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
645 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
646 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
647 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
648 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
649 #define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
650 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
651 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
652 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
653 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
654 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
655 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
656 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
657 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
659 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
660
661 /**
662 * @}
663 */
664
665 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
666 * @{
667 */
668 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
669 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
670 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
671 /**
672 * @}
673 */
674
675 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
676 * @{
677 */
678 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
679 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
680 /**
681 * @}
682 */
683
684 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
685 * @{
686 */
687 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
688 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
689 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
690 /**
691 * @}
692 */
693
694 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
695 * @{
696 */
697 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
698 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
699 /**
700 * @}
701 */
702
703 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
704 * @{
705 */
706 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
707 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
708 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
709 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
710 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
711 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
712 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
713 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
714 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
715 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
716 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
717 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
718 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
722 /**
723 * @}
724 */
725
726 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
727 * @{
728 */
729 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
730 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
731 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
732 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
733 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
734 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
735 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
736 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
737 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
738 /**
739 * @}
740 */
741
742 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
743 * @{
744 */
745 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
746 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
747 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
748 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
749 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
750 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
751 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
752 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
753 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
754 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
755 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
756 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
757 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
758 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
759 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
760 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
761 /**
762 * @}
763 */
764
765 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
766 * @{
767 */
768 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
769 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
770 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
771 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
772 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
773 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
774 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
775 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
776 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
777 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
778 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
779 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
780 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
781 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
782 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
783
784 /**
785 * @}
786 */
787
788 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
789 * @{
790 */
791 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
792 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
793 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
794 /**
795 * @}
796 */
797
798 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
799 * @{
800 */
801 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
802 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
803 /**
804 * @}
805 */
806
807
808 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
809 * @{
810 */
811 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
812 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
813 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
814 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
815 /**
816 * @}
817 */
818
819 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
820 * @{
821 */
822 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
823 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
824 /**
825 * @}
826 */
827
828 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
829 * @{
830 */
831 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
832 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
833 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
834 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
835 /**
836 * @}
837 */
838
839 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
840 * @{
841 */
842 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
843 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
844 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
845 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
846 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
847 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
848 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
849 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
850 /**
851 * @}
852 */
853
854 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
855 * @{
856 */
857 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
858 /**
859 * @}
860 */
861
862 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
863 * @{
864 */
865 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
866 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
867 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
868 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
869 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
870 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
871 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
872 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
873 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
874 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
875 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
876 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
877 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
878 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
879 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
880 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
881 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
882 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
883 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
884 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
885 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
886 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
887 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
888 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
889 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
890 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
891 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
892 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
893 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
894 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
895 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
896 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
897 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
898 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
899 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
900 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
901 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
902 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
903 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
904 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
905 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
906 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
907 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
908 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
909 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
910 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
911 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
912 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
913 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
914 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
915 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
916 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
917 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
918 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
919 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
920 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
921 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
922 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
923 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
924 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
925 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
926 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
927 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
928 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
929 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
930 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
931 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
932 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
933 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
934 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
935 /**
936 * @}
937 */
938
939 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
940 * @{
941 */
942 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
943 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
944 /**
945 * @}
946 */
947
948 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
949 * @{
950 */
951 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
952 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
953 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
954 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
955 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
956 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
957 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
958 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
959 #if defined(ADC3)
960 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
961 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
962 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
963 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
964 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
965 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
966 #endif
967 /**
968 * @}
969 */
970
971 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
972 * @{
973 */
974 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
975 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
976 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
977 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
978 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
979 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
980 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
981 /**
982 * @}
983 */
984
985 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
986 * @{
987 */
988 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
989 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
990 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
991 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
992 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
993 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
994 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
995 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
996 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
997 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
998 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
999 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1000 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1001 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1002 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1003 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1009 * @{
1010 */
1011 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1012 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1013 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1014 /**
1015 * @}
1016 */
1017
1018
1019
1020 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1021 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1022 * not timeout values.
1023 * For details on delays values, refer to descriptions in source code
1024 * above each literal definition.
1025 * @{
1026 */
1027
1028 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1029 /* not timeout values. */
1030 /* Timeout values for ADC operations are dependent to device clock */
1031 /* configuration (system clock versus ADC clock), */
1032 /* and therefore must be defined in user application. */
1033 /* Indications for estimation of ADC timeout delays, for this */
1034 /* STM32 serie: */
1035 /* - ADC enable time: maximum delay is 2us */
1036 /* (refer to device datasheet, parameter "tSTAB") */
1037 /* - ADC conversion time: duration depending on ADC clock and ADC */
1038 /* configuration. */
1039 /* (refer to device reference manual, section "Timing") */
1040
1041 /* Delay for internal voltage reference stabilization time. */
1042 /* Delay set to maximum value (refer to device datasheet, */
1043 /* parameter "tSTART"). */
1044 /* Unit: us */
1045 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1046
1047 /* Delay for temperature sensor stabilization time. */
1048 /* Literal set to maximum value (refer to device datasheet, */
1049 /* parameter "tSTART"). */
1050 /* Unit: us */
1051 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1052
1053 /**
1054 * @}
1055 */
1056
1057 /**
1058 * @}
1059 */
1060
1061
1062 /* Exported macro ------------------------------------------------------------*/
1063 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1064 * @{
1065 */
1066
1067 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1068 * @{
1069 */
1070
1071 /**
1072 * @brief Write a value in ADC register
1073 * @param __INSTANCE__ ADC Instance
1074 * @param __REG__ Register to be written
1075 * @param __VALUE__ Value to be written in the register
1076 * @retval None
1077 */
1078 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1079
1080 /**
1081 * @brief Read a value in ADC register
1082 * @param __INSTANCE__ ADC Instance
1083 * @param __REG__ Register to be read
1084 * @retval Register value
1085 */
1086 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1087 /**
1088 * @}
1089 */
1090
1091 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1092 * @{
1093 */
1094
1095 /**
1096 * @brief Helper macro to get ADC channel number in decimal format
1097 * from literals LL_ADC_CHANNEL_x.
1098 * @note Example:
1099 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1100 * will return decimal number "4".
1101 * @note The input can be a value from functions where a channel
1102 * number is returned, either defined with number
1103 * or with bitfield (only one bit must be set).
1104 * @param __CHANNEL__ This parameter can be one of the following values:
1105 * @arg @ref LL_ADC_CHANNEL_0
1106 * @arg @ref LL_ADC_CHANNEL_1
1107 * @arg @ref LL_ADC_CHANNEL_2
1108 * @arg @ref LL_ADC_CHANNEL_3
1109 * @arg @ref LL_ADC_CHANNEL_4
1110 * @arg @ref LL_ADC_CHANNEL_5
1111 * @arg @ref LL_ADC_CHANNEL_6
1112 * @arg @ref LL_ADC_CHANNEL_7
1113 * @arg @ref LL_ADC_CHANNEL_8
1114 * @arg @ref LL_ADC_CHANNEL_9
1115 * @arg @ref LL_ADC_CHANNEL_10
1116 * @arg @ref LL_ADC_CHANNEL_11
1117 * @arg @ref LL_ADC_CHANNEL_12
1118 * @arg @ref LL_ADC_CHANNEL_13
1119 * @arg @ref LL_ADC_CHANNEL_14
1120 * @arg @ref LL_ADC_CHANNEL_15
1121 * @arg @ref LL_ADC_CHANNEL_16
1122 * @arg @ref LL_ADC_CHANNEL_17
1123 * @arg @ref LL_ADC_CHANNEL_18
1124 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1125 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1126 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1127 *
1128 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1129 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1130 * @retval Value between Min_Data=0 and Max_Data=18
1131 */
1132 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1133 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1134
1135 /**
1136 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1137 * from number in decimal format.
1138 * @note Example:
1139 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1140 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1141 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1142 * @retval Returned value can be one of the following values:
1143 * @arg @ref LL_ADC_CHANNEL_0
1144 * @arg @ref LL_ADC_CHANNEL_1
1145 * @arg @ref LL_ADC_CHANNEL_2
1146 * @arg @ref LL_ADC_CHANNEL_3
1147 * @arg @ref LL_ADC_CHANNEL_4
1148 * @arg @ref LL_ADC_CHANNEL_5
1149 * @arg @ref LL_ADC_CHANNEL_6
1150 * @arg @ref LL_ADC_CHANNEL_7
1151 * @arg @ref LL_ADC_CHANNEL_8
1152 * @arg @ref LL_ADC_CHANNEL_9
1153 * @arg @ref LL_ADC_CHANNEL_10
1154 * @arg @ref LL_ADC_CHANNEL_11
1155 * @arg @ref LL_ADC_CHANNEL_12
1156 * @arg @ref LL_ADC_CHANNEL_13
1157 * @arg @ref LL_ADC_CHANNEL_14
1158 * @arg @ref LL_ADC_CHANNEL_15
1159 * @arg @ref LL_ADC_CHANNEL_16
1160 * @arg @ref LL_ADC_CHANNEL_17
1161 * @arg @ref LL_ADC_CHANNEL_18
1162 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1163 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1164 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1165 *
1166 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1167 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1168 * (1) For ADC channel read back from ADC register,
1169 * comparison with internal channel parameter to be done
1170 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1171 */
1172 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1173 (((__DECIMAL_NB__) <= 9U) \
1174 ? ( \
1175 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1176 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1177 ) \
1178 : \
1179 ( \
1180 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1181 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1182 ) \
1183 )
1184
1185 /**
1186 * @brief Helper macro to determine whether the selected channel
1187 * corresponds to literal definitions of driver.
1188 * @note The different literal definitions of ADC channels are:
1189 * - ADC internal channel:
1190 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1191 * - ADC external channel (channel connected to a GPIO pin):
1192 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1193 * @note The channel parameter must be a value defined from literal
1194 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1195 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1196 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1197 * must not be a value from functions where a channel number is
1198 * returned from ADC registers,
1199 * because internal and external channels share the same channel
1200 * number in ADC registers. The differentiation is made only with
1201 * parameters definitions of driver.
1202 * @param __CHANNEL__ This parameter can be one of the following values:
1203 * @arg @ref LL_ADC_CHANNEL_0
1204 * @arg @ref LL_ADC_CHANNEL_1
1205 * @arg @ref LL_ADC_CHANNEL_2
1206 * @arg @ref LL_ADC_CHANNEL_3
1207 * @arg @ref LL_ADC_CHANNEL_4
1208 * @arg @ref LL_ADC_CHANNEL_5
1209 * @arg @ref LL_ADC_CHANNEL_6
1210 * @arg @ref LL_ADC_CHANNEL_7
1211 * @arg @ref LL_ADC_CHANNEL_8
1212 * @arg @ref LL_ADC_CHANNEL_9
1213 * @arg @ref LL_ADC_CHANNEL_10
1214 * @arg @ref LL_ADC_CHANNEL_11
1215 * @arg @ref LL_ADC_CHANNEL_12
1216 * @arg @ref LL_ADC_CHANNEL_13
1217 * @arg @ref LL_ADC_CHANNEL_14
1218 * @arg @ref LL_ADC_CHANNEL_15
1219 * @arg @ref LL_ADC_CHANNEL_16
1220 * @arg @ref LL_ADC_CHANNEL_17
1221 * @arg @ref LL_ADC_CHANNEL_18
1222 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1223 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1224 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1225 *
1226 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1227 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1228 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1229 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1230 */
1231 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1232 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1233
1234 /**
1235 * @brief Helper macro to convert a channel defined from parameter
1236 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1237 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1238 * to its equivalent parameter definition of a ADC external channel
1239 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1240 * @note The channel parameter can be, additionally to a value
1241 * defined from parameter definition of a ADC internal channel
1242 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1243 * a value defined from parameter definition of
1244 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1245 * or a value from functions where a channel number is returned
1246 * from ADC registers.
1247 * @param __CHANNEL__ This parameter can be one of the following values:
1248 * @arg @ref LL_ADC_CHANNEL_0
1249 * @arg @ref LL_ADC_CHANNEL_1
1250 * @arg @ref LL_ADC_CHANNEL_2
1251 * @arg @ref LL_ADC_CHANNEL_3
1252 * @arg @ref LL_ADC_CHANNEL_4
1253 * @arg @ref LL_ADC_CHANNEL_5
1254 * @arg @ref LL_ADC_CHANNEL_6
1255 * @arg @ref LL_ADC_CHANNEL_7
1256 * @arg @ref LL_ADC_CHANNEL_8
1257 * @arg @ref LL_ADC_CHANNEL_9
1258 * @arg @ref LL_ADC_CHANNEL_10
1259 * @arg @ref LL_ADC_CHANNEL_11
1260 * @arg @ref LL_ADC_CHANNEL_12
1261 * @arg @ref LL_ADC_CHANNEL_13
1262 * @arg @ref LL_ADC_CHANNEL_14
1263 * @arg @ref LL_ADC_CHANNEL_15
1264 * @arg @ref LL_ADC_CHANNEL_16
1265 * @arg @ref LL_ADC_CHANNEL_17
1266 * @arg @ref LL_ADC_CHANNEL_18
1267 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1268 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1269 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1270 *
1271 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1272 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1273 * @retval Returned value can be one of the following values:
1274 * @arg @ref LL_ADC_CHANNEL_0
1275 * @arg @ref LL_ADC_CHANNEL_1
1276 * @arg @ref LL_ADC_CHANNEL_2
1277 * @arg @ref LL_ADC_CHANNEL_3
1278 * @arg @ref LL_ADC_CHANNEL_4
1279 * @arg @ref LL_ADC_CHANNEL_5
1280 * @arg @ref LL_ADC_CHANNEL_6
1281 * @arg @ref LL_ADC_CHANNEL_7
1282 * @arg @ref LL_ADC_CHANNEL_8
1283 * @arg @ref LL_ADC_CHANNEL_9
1284 * @arg @ref LL_ADC_CHANNEL_10
1285 * @arg @ref LL_ADC_CHANNEL_11
1286 * @arg @ref LL_ADC_CHANNEL_12
1287 * @arg @ref LL_ADC_CHANNEL_13
1288 * @arg @ref LL_ADC_CHANNEL_14
1289 * @arg @ref LL_ADC_CHANNEL_15
1290 * @arg @ref LL_ADC_CHANNEL_16
1291 * @arg @ref LL_ADC_CHANNEL_17
1292 * @arg @ref LL_ADC_CHANNEL_18
1293 */
1294 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1295 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1296
1297 /**
1298 * @brief Helper macro to determine whether the internal channel
1299 * selected is available on the ADC instance selected.
1300 * @note The channel parameter must be a value defined from parameter
1301 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1302 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1303 * must not be a value defined from parameter definition of
1304 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1305 * or a value from functions where a channel number is
1306 * returned from ADC registers,
1307 * because internal and external channels share the same channel
1308 * number in ADC registers. The differentiation is made only with
1309 * parameters definitions of driver.
1310 * @param __ADC_INSTANCE__ ADC instance
1311 * @param __CHANNEL__ This parameter can be one of the following values:
1312 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1313 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1314 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1315 *
1316 * (1) On STM32F7, parameter available only on ADC instance: ADC1.
1317 * (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1318 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1319 * Value "1" if the internal channel selected is available on the ADC instance selected.
1320 */
1321 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1322 ( \
1323 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1324 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1325 )
1326 /**
1327 * @brief Helper macro to define ADC analog watchdog parameter:
1328 * define a single channel to monitor with analog watchdog
1329 * from sequencer channel and groups definition.
1330 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1331 * Example:
1332 * LL_ADC_SetAnalogWDMonitChannels(
1333 * ADC1, LL_ADC_AWD1,
1334 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1335 * @param __CHANNEL__ This parameter can be one of the following values:
1336 * @arg @ref LL_ADC_CHANNEL_0
1337 * @arg @ref LL_ADC_CHANNEL_1
1338 * @arg @ref LL_ADC_CHANNEL_2
1339 * @arg @ref LL_ADC_CHANNEL_3
1340 * @arg @ref LL_ADC_CHANNEL_4
1341 * @arg @ref LL_ADC_CHANNEL_5
1342 * @arg @ref LL_ADC_CHANNEL_6
1343 * @arg @ref LL_ADC_CHANNEL_7
1344 * @arg @ref LL_ADC_CHANNEL_8
1345 * @arg @ref LL_ADC_CHANNEL_9
1346 * @arg @ref LL_ADC_CHANNEL_10
1347 * @arg @ref LL_ADC_CHANNEL_11
1348 * @arg @ref LL_ADC_CHANNEL_12
1349 * @arg @ref LL_ADC_CHANNEL_13
1350 * @arg @ref LL_ADC_CHANNEL_14
1351 * @arg @ref LL_ADC_CHANNEL_15
1352 * @arg @ref LL_ADC_CHANNEL_16
1353 * @arg @ref LL_ADC_CHANNEL_17
1354 * @arg @ref LL_ADC_CHANNEL_18
1355 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1356 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1357 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1358 *
1359 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1360 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1361 * (1) For ADC channel read back from ADC register,
1362 * comparison with internal channel parameter to be done
1363 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1364 * @param __GROUP__ This parameter can be one of the following values:
1365 * @arg @ref LL_ADC_GROUP_REGULAR
1366 * @arg @ref LL_ADC_GROUP_INJECTED
1367 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1368 * @retval Returned value can be one of the following values:
1369 * @arg @ref LL_ADC_AWD_DISABLE
1370 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1371 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1372 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1373 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1374 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1375 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1376 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1377 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1378 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1379 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1380 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1381 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1382 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1383 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1384 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1385 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1386 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1387 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1388 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1389 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1390 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1391 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1392 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1393 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1394 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1395 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1396 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1397 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1398 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1399 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1400 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1401 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1403 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1404 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1406 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1407 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1409 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1410 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1412 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1413 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1414 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1415 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1416 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1417 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1418 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1419 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1420 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1421 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1422 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1423 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1424 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1425 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1426 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1427 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1428 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1429 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1430 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1431 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1432 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1433 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1434 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1435 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1436 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1437 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1438 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1439 *
1440 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1441 * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1442 */
1443 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1444 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1445 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1446 : \
1447 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1448 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1449 : \
1450 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1451 )
1452
1453 /**
1454 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1455 * or low in function of ADC resolution, when ADC resolution is
1456 * different of 12 bits.
1457 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1458 * Example, with a ADC resolution of 8 bits, to set the value of
1459 * analog watchdog threshold high (on 8 bits):
1460 * LL_ADC_SetAnalogWDThresholds
1461 * (< ADCx param >,
1462 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1463 * );
1464 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1465 * @arg @ref LL_ADC_RESOLUTION_12B
1466 * @arg @ref LL_ADC_RESOLUTION_10B
1467 * @arg @ref LL_ADC_RESOLUTION_8B
1468 * @arg @ref LL_ADC_RESOLUTION_6B
1469 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1470 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1471 */
1472 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1473 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1474
1475 /**
1476 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1477 * or low in function of ADC resolution, when ADC resolution is
1478 * different of 12 bits.
1479 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1480 * Example, with a ADC resolution of 8 bits, to get the value of
1481 * analog watchdog threshold high (on 8 bits):
1482 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1483 * (LL_ADC_RESOLUTION_8B,
1484 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1485 * );
1486 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1487 * @arg @ref LL_ADC_RESOLUTION_12B
1488 * @arg @ref LL_ADC_RESOLUTION_10B
1489 * @arg @ref LL_ADC_RESOLUTION_8B
1490 * @arg @ref LL_ADC_RESOLUTION_6B
1491 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1492 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1493 */
1494 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1495 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1496
1497 /**
1498 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1499 * or ADC slave from raw value with both ADC conversion data concatenated.
1500 * @note This macro is intended to be used when multimode transfer by DMA
1501 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1502 * In this case the transferred data need to processed with this macro
1503 * to separate the conversion data of ADC master and ADC slave.
1504 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1505 * @arg @ref LL_ADC_MULTI_MASTER
1506 * @arg @ref LL_ADC_MULTI_SLAVE
1507 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1508 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1509 */
1510 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1511 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1512
1513 /**
1514 * @brief Helper macro to select the ADC common instance
1515 * to which is belonging the selected ADC instance.
1516 * @note ADC common register instance can be used for:
1517 * - Set parameters common to several ADC instances
1518 * - Multimode (for devices with several ADC instances)
1519 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1520 * @param __ADCx__ ADC instance
1521 * @retval ADC common register instance
1522 */
1523 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1524 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1525 (ADC123_COMMON)
1526 #elif defined(ADC1) && defined(ADC2)
1527 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1528 (ADC12_COMMON)
1529 #else
1530 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1531 (ADC1_COMMON)
1532 #endif
1533
1534 /**
1535 * @brief Helper macro to check if all ADC instances sharing the same
1536 * ADC common instance are disabled.
1537 * @note This check is required by functions with setting conditioned to
1538 * ADC state:
1539 * All ADC instances of the ADC common group must be disabled.
1540 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1541 * @note On devices with only 1 ADC common instance, parameter of this macro
1542 * is useless and can be ignored (parameter kept for compatibility
1543 * with devices featuring several ADC common instances).
1544 * @param __ADCXY_COMMON__ ADC common instance
1545 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1546 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1547 * are disabled.
1548 * Value "1" if at least one ADC instance sharing the same ADC common instance
1549 * is enabled.
1550 */
1551 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1552 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1553 (LL_ADC_IsEnabled(ADC1) | \
1554 LL_ADC_IsEnabled(ADC2) | \
1555 LL_ADC_IsEnabled(ADC3) )
1556 #elif defined(ADC1) && defined(ADC2)
1557 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1558 (LL_ADC_IsEnabled(ADC1) | \
1559 LL_ADC_IsEnabled(ADC2) )
1560 #else
1561 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1562 (LL_ADC_IsEnabled(ADC1))
1563 #endif
1564
1565 /**
1566 * @brief Helper macro to define the ADC conversion data full-scale digital
1567 * value corresponding to the selected ADC resolution.
1568 * @note ADC conversion data full-scale corresponds to voltage range
1569 * determined by analog voltage references Vref+ and Vref-
1570 * (refer to reference manual).
1571 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1572 * @arg @ref LL_ADC_RESOLUTION_12B
1573 * @arg @ref LL_ADC_RESOLUTION_10B
1574 * @arg @ref LL_ADC_RESOLUTION_8B
1575 * @arg @ref LL_ADC_RESOLUTION_6B
1576 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1577 */
1578 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1579 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1580
1581 /**
1582 * @brief Helper macro to convert the ADC conversion data from
1583 * a resolution to another resolution.
1584 * @param __DATA__ ADC conversion data to be converted
1585 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1586 * This parameter can be one of the following values:
1587 * @arg @ref LL_ADC_RESOLUTION_12B
1588 * @arg @ref LL_ADC_RESOLUTION_10B
1589 * @arg @ref LL_ADC_RESOLUTION_8B
1590 * @arg @ref LL_ADC_RESOLUTION_6B
1591 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1592 * This parameter can be one of the following values:
1593 * @arg @ref LL_ADC_RESOLUTION_12B
1594 * @arg @ref LL_ADC_RESOLUTION_10B
1595 * @arg @ref LL_ADC_RESOLUTION_8B
1596 * @arg @ref LL_ADC_RESOLUTION_6B
1597 * @retval ADC conversion data to the requested resolution
1598 */
1599 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1600 (((__DATA__) \
1601 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1602 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1603 )
1604
1605 /**
1606 * @brief Helper macro to calculate the voltage (unit: mVolt)
1607 * corresponding to a ADC conversion data (unit: digital value).
1608 * @note Analog reference voltage (Vref+) must be either known from
1609 * user board environment or can be calculated using ADC measurement
1610 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1611 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1612 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1613 * (unit: digital value).
1614 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1615 * @arg @ref LL_ADC_RESOLUTION_12B
1616 * @arg @ref LL_ADC_RESOLUTION_10B
1617 * @arg @ref LL_ADC_RESOLUTION_8B
1618 * @arg @ref LL_ADC_RESOLUTION_6B
1619 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1620 */
1621 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1622 __ADC_DATA__,\
1623 __ADC_RESOLUTION__) \
1624 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1625 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1626 )
1627
1628 /**
1629 * @brief Helper macro to calculate analog reference voltage (Vref+)
1630 * (unit: mVolt) from ADC conversion data of internal voltage
1631 * reference VrefInt.
1632 * @note Computation is using VrefInt calibration value
1633 * stored in system memory for each device during production.
1634 * @note This voltage depends on user board environment: voltage level
1635 * connected to pin Vref+.
1636 * On devices with small package, the pin Vref+ is not present
1637 * and internally bonded to pin Vdda.
1638 * @note On this STM32 serie, calibration data of internal voltage reference
1639 * VrefInt corresponds to a resolution of 12 bits,
1640 * this is the recommended ADC resolution to convert voltage of
1641 * internal voltage reference VrefInt.
1642 * Otherwise, this macro performs the processing to scale
1643 * ADC conversion data to 12 bits.
1644 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1645 * of internal voltage reference VrefInt (unit: digital value).
1646 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1647 * @arg @ref LL_ADC_RESOLUTION_12B
1648 * @arg @ref LL_ADC_RESOLUTION_10B
1649 * @arg @ref LL_ADC_RESOLUTION_8B
1650 * @arg @ref LL_ADC_RESOLUTION_6B
1651 * @retval Analog reference voltage (unit: mV)
1652 */
1653 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1654 __ADC_RESOLUTION__) \
1655 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1656 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1657 (__ADC_RESOLUTION__), \
1658 LL_ADC_RESOLUTION_12B) \
1659 )
1660
1661 /**
1662 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1663 * from ADC conversion data of internal temperature sensor.
1664 * @note Computation is using temperature sensor calibration values
1665 * stored in system memory for each device during production.
1666 * @note Calculation formula:
1667 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1668 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1669 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1670 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1671 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1672 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1673 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1674 * TEMP_DEGC_CAL1 (calibrated in factory)
1675 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1676 * TEMP_DEGC_CAL2 (calibrated in factory)
1677 * Caution: Calculation relevancy under reserve that calibration
1678 * parameters are correct (address and data).
1679 * To calculate temperature using temperature sensor
1680 * datasheet typical values (generic values less, therefore
1681 * less accurate than calibrated values),
1682 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1683 * @note As calculation input, the analog reference voltage (Vref+) must be
1684 * defined as it impacts the ADC LSB equivalent voltage.
1685 * @note Analog reference voltage (Vref+) must be either known from
1686 * user board environment or can be calculated using ADC measurement
1687 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1688 * @note On this STM32 serie, calibration data of temperature sensor
1689 * corresponds to a resolution of 12 bits,
1690 * this is the recommended ADC resolution to convert voltage of
1691 * temperature sensor.
1692 * Otherwise, this macro performs the processing to scale
1693 * ADC conversion data to 12 bits.
1694 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1695 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1696 * temperature sensor (unit: digital value).
1697 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1698 * sensor voltage has been measured.
1699 * This parameter can be one of the following values:
1700 * @arg @ref LL_ADC_RESOLUTION_12B
1701 * @arg @ref LL_ADC_RESOLUTION_10B
1702 * @arg @ref LL_ADC_RESOLUTION_8B
1703 * @arg @ref LL_ADC_RESOLUTION_6B
1704 * @retval Temperature (unit: degree Celsius)
1705 */
1706 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1707 __TEMPSENSOR_ADC_DATA__,\
1708 __ADC_RESOLUTION__) \
1709 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1710 (__ADC_RESOLUTION__), \
1711 LL_ADC_RESOLUTION_12B) \
1712 * (__VREFANALOG_VOLTAGE__)) \
1713 / TEMPSENSOR_CAL_VREFANALOG) \
1714 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1715 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1716 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1717 ) + TEMPSENSOR_CAL1_TEMP \
1718 )
1719
1720 /**
1721 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1722 * from ADC conversion data of internal temperature sensor.
1723 * @note Computation is using temperature sensor typical values
1724 * (refer to device datasheet).
1725 * @note Calculation formula:
1726 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1727 * / Avg_Slope + CALx_TEMP
1728 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1729 * (unit: digital value)
1730 * Avg_Slope = temperature sensor slope
1731 * (unit: uV/Degree Celsius)
1732 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1733 * temperature CALx_TEMP (unit: mV)
1734 * Caution: Calculation relevancy under reserve the temperature sensor
1735 * of the current device has characteristics in line with
1736 * datasheet typical values.
1737 * If temperature sensor calibration values are available on
1738 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1739 * temperature calculation will be more accurate using
1740 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1741 * @note As calculation input, the analog reference voltage (Vref+) must be
1742 * defined as it impacts the ADC LSB equivalent voltage.
1743 * @note Analog reference voltage (Vref+) must be either known from
1744 * user board environment or can be calculated using ADC measurement
1745 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1746 * @note ADC measurement data must correspond to a resolution of 12bits
1747 * (full scale digital value 4095). If not the case, the data must be
1748 * preliminarily rescaled to an equivalent resolution of 12 bits.
1749 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1750 * On STM32F7, refer to device datasheet parameter "Avg_Slope".
1751 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1752 * On STM32F4, refer to device datasheet parameter "V25".
1753 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1754 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1755 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1756 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1757 * This parameter can be one of the following values:
1758 * @arg @ref LL_ADC_RESOLUTION_12B
1759 * @arg @ref LL_ADC_RESOLUTION_10B
1760 * @arg @ref LL_ADC_RESOLUTION_8B
1761 * @arg @ref LL_ADC_RESOLUTION_6B
1762 * @retval Temperature (unit: degree Celsius)
1763 */
1764 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1765 __TEMPSENSOR_TYP_CALX_V__,\
1766 __TEMPSENSOR_CALX_TEMP__,\
1767 __VREFANALOG_VOLTAGE__,\
1768 __TEMPSENSOR_ADC_DATA__,\
1769 __ADC_RESOLUTION__) \
1770 ((( ( \
1771 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1772 * 1000) \
1773 - \
1774 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1775 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1776 * 1000) \
1777 ) \
1778 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1779 ) + (__TEMPSENSOR_CALX_TEMP__) \
1780 )
1781
1782 /**
1783 * @}
1784 */
1785
1786 /**
1787 * @}
1788 */
1789
1790
1791 /* Exported functions --------------------------------------------------------*/
1792 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1793 * @{
1794 */
1795
1796 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1797 * @{
1798 */
1799 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1800 /* configuration of ADC instance, groups and multimode (if available): */
1801 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1802
1803 /**
1804 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1805 * ADC register address from ADC instance and a list of ADC registers
1806 * intended to be used (most commonly) with DMA transfer.
1807 * @note These ADC registers are data registers:
1808 * when ADC conversion data is available in ADC data registers,
1809 * ADC generates a DMA transfer request.
1810 * @note This macro is intended to be used with LL DMA driver, refer to
1811 * function "LL_DMA_ConfigAddresses()".
1812 * Example:
1813 * LL_DMA_ConfigAddresses(DMA1,
1814 * LL_DMA_CHANNEL_1,
1815 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1816 * (uint32_t)&< array or variable >,
1817 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1818 * @note For devices with several ADC: in multimode, some devices
1819 * use a different data register outside of ADC instance scope
1820 * (common data register). This macro manages this register difference,
1821 * only ADC instance has to be set as parameter.
1822 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1823 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1824 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1825 * @param ADCx ADC instance
1826 * @param Register This parameter can be one of the following values:
1827 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1828 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1829 *
1830 * (1) Available on devices with several ADC instances.
1831 * @retval ADC register address
1832 */
1833 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1834 {
1835 register uint32_t data_reg_addr = 0U;
1836
1837 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1838 {
1839 /* Retrieve address of register DR */
1840 data_reg_addr = (uint32_t)&(ADCx->DR);
1841 }
1842 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1843 {
1844 /* Retrieve address of register CDR */
1845 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1846 }
1847
1848 return data_reg_addr;
1849 }
1850
1851 /**
1852 * @}
1853 */
1854
1855 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1856 * @{
1857 */
1858
1859 /**
1860 * @brief Set parameter common to several ADC: Clock source and prescaler.
1861 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1862 * @param ADCxy_COMMON ADC common instance
1863 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1864 * @param CommonClock This parameter can be one of the following values:
1865 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1866 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1867 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1868 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1869 * @retval None
1870 */
1871 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1872 {
1873 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1874 }
1875
1876 /**
1877 * @brief Get parameter common to several ADC: Clock source and prescaler.
1878 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1879 * @param ADCxy_COMMON ADC common instance
1880 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1881 * @retval Returned value can be one of the following values:
1882 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1883 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1884 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1885 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1886 */
1887 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1888 {
1889 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1890 }
1891
1892 /**
1893 * @brief Set parameter common to several ADC: measurement path to internal
1894 * channels (VrefInt, temperature sensor, ...).
1895 * @note One or several values can be selected.
1896 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1897 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1898 * @note Stabilization time of measurement path to internal channel:
1899 * After enabling internal paths, before starting ADC conversion,
1900 * a delay is required for internal voltage reference and
1901 * temperature sensor stabilization time.
1902 * Refer to device datasheet.
1903 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1904 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1905 * @note ADC internal channel sampling time constraint:
1906 * For ADC conversion of internal channels,
1907 * a sampling time minimum value is required.
1908 * Refer to device datasheet.
1909 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1910 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1911 * @param ADCxy_COMMON ADC common instance
1912 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1913 * @param PathInternal This parameter can be a combination of the following values:
1914 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1915 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1916 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1917 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1918 * @retval None
1919 */
1920 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1921 {
1922 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1923 }
1924
1925 /**
1926 * @brief Get parameter common to several ADC: measurement path to internal
1927 * channels (VrefInt, temperature sensor, ...).
1928 * @note One or several values can be selected.
1929 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1930 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1931 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1932 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1933 * @param ADCxy_COMMON ADC common instance
1934 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1935 * @retval Returned value can be a combination of the following values:
1936 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1937 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1938 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1939 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1940 */
1941 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1942 {
1943 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1944 }
1945
1946 /**
1947 * @}
1948 */
1949
1950 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1951 * @{
1952 */
1953
1954 /**
1955 * @brief Set ADC resolution.
1956 * Refer to reference manual for alignments formats
1957 * dependencies to ADC resolutions.
1958 * @rmtoll CR1 RES LL_ADC_SetResolution
1959 * @param ADCx ADC instance
1960 * @param Resolution This parameter can be one of the following values:
1961 * @arg @ref LL_ADC_RESOLUTION_12B
1962 * @arg @ref LL_ADC_RESOLUTION_10B
1963 * @arg @ref LL_ADC_RESOLUTION_8B
1964 * @arg @ref LL_ADC_RESOLUTION_6B
1965 * @retval None
1966 */
1967 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1968 {
1969 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
1970 }
1971
1972 /**
1973 * @brief Get ADC resolution.
1974 * Refer to reference manual for alignments formats
1975 * dependencies to ADC resolutions.
1976 * @rmtoll CR1 RES LL_ADC_GetResolution
1977 * @param ADCx ADC instance
1978 * @retval Returned value can be one of the following values:
1979 * @arg @ref LL_ADC_RESOLUTION_12B
1980 * @arg @ref LL_ADC_RESOLUTION_10B
1981 * @arg @ref LL_ADC_RESOLUTION_8B
1982 * @arg @ref LL_ADC_RESOLUTION_6B
1983 */
1984 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1985 {
1986 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
1987 }
1988
1989 /**
1990 * @brief Set ADC conversion data alignment.
1991 * @note Refer to reference manual for alignments formats
1992 * dependencies to ADC resolutions.
1993 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1994 * @param ADCx ADC instance
1995 * @param DataAlignment This parameter can be one of the following values:
1996 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1997 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1998 * @retval None
1999 */
2000 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2001 {
2002 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2003 }
2004
2005 /**
2006 * @brief Get ADC conversion data alignment.
2007 * @note Refer to reference manual for alignments formats
2008 * dependencies to ADC resolutions.
2009 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2010 * @param ADCx ADC instance
2011 * @retval Returned value can be one of the following values:
2012 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2013 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2014 */
2015 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2016 {
2017 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2018 }
2019
2020 /**
2021 * @brief Set ADC sequencers scan mode, for all ADC groups
2022 * (group regular, group injected).
2023 * @note According to sequencers scan mode :
2024 * - If disabled: ADC conversion is performed in unitary conversion
2025 * mode (one channel converted, that defined in rank 1).
2026 * Configuration of sequencers of all ADC groups
2027 * (sequencer scan length, ...) is discarded: equivalent to
2028 * scan length of 1 rank.
2029 * - If enabled: ADC conversions are performed in sequence conversions
2030 * mode, according to configuration of sequencers of
2031 * each ADC group (sequencer scan length, ...).
2032 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2033 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2034 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2035 * @param ADCx ADC instance
2036 * @param ScanMode This parameter can be one of the following values:
2037 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2038 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2039 * @retval None
2040 */
2041 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2042 {
2043 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2044 }
2045
2046 /**
2047 * @brief Get ADC sequencers scan mode, for all ADC groups
2048 * (group regular, group injected).
2049 * @note According to sequencers scan mode :
2050 * - If disabled: ADC conversion is performed in unitary conversion
2051 * mode (one channel converted, that defined in rank 1).
2052 * Configuration of sequencers of all ADC groups
2053 * (sequencer scan length, ...) is discarded: equivalent to
2054 * scan length of 1 rank.
2055 * - If enabled: ADC conversions are performed in sequence conversions
2056 * mode, according to configuration of sequencers of
2057 * each ADC group (sequencer scan length, ...).
2058 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2059 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2060 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2061 * @param ADCx ADC instance
2062 * @retval Returned value can be one of the following values:
2063 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2064 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2065 */
2066 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2067 {
2068 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2069 }
2070
2071 /**
2072 * @}
2073 */
2074
2075 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2076 * @{
2077 */
2078
2079 /**
2080 * @brief Set ADC group regular conversion trigger source:
2081 * internal (SW start) or from external IP (timer event,
2082 * external interrupt line).
2083 * @note On this STM32 serie, setting of external trigger edge is performed
2084 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2085 * @note Availability of parameters of trigger sources from timer
2086 * depends on timers availability on the selected device.
2087 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2088 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2089 * @param ADCx ADC instance
2090 * @param TriggerSource This parameter can be one of the following values:
2091 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
2097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2098 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
2099 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2100 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
2101 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
2102 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2103 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2104 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2105 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2106 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2107 * @retval None
2108 */
2109 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2110 {
2111 /* Note: On this STM32 serie, ADC group regular external trigger edge */
2112 /* is used to perform a ADC conversion start. */
2113 /* This function does not set external trigger edge. */
2114 /* This feature is set using function */
2115 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2116 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2117 }
2118
2119 /**
2120 * @brief Get ADC group regular conversion trigger source:
2121 * internal (SW start) or from external IP (timer event,
2122 * external interrupt line).
2123 * @note To determine whether group regular trigger source is
2124 * internal (SW start) or external, without detail
2125 * of which peripheral is selected as external trigger,
2126 * (equivalent to
2127 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2128 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2129 * @note Availability of parameters of trigger sources from timer
2130 * depends on timers availability on the selected device.
2131 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2132 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2133 * @param ADCx ADC instance
2134 * @retval Returned value can be one of the following values:
2135 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2144 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
2145 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
2146 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2147 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2148 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2149 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2150 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2151 */
2152 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2153 {
2154 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2155
2156 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2157 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2158 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2159
2160 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2161 /* to match with triggers literals definition. */
2162 return ((TriggerSource
2163 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2164 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2165 );
2166 }
2167
2168 /**
2169 * @brief Get ADC group regular conversion trigger source internal (SW start)
2170 or external.
2171 * @note In case of group regular trigger source set to external trigger,
2172 * to determine which peripheral is selected as external trigger,
2173 * use function @ref LL_ADC_REG_GetTriggerSource().
2174 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2175 * @param ADCx ADC instance
2176 * @retval Value "0" if trigger source external trigger
2177 * Value "1" if trigger source SW start.
2178 */
2179 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2180 {
2181 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2182 }
2183
2184 /**
2185 * @brief Get ADC group regular conversion trigger polarity.
2186 * @note Applicable only for trigger source set to external trigger.
2187 * @note On this STM32 serie, setting of external trigger edge is performed
2188 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2189 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2190 * @param ADCx ADC instance
2191 * @retval Returned value can be one of the following values:
2192 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2193 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2194 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2195 */
2196 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2197 {
2198 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2199 }
2200
2201
2202 /**
2203 * @brief Set ADC group regular sequencer length and scan direction.
2204 * @note Description of ADC group regular sequencer features:
2205 * - For devices with sequencer fully configurable
2206 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2207 * sequencer length and each rank affectation to a channel
2208 * are configurable.
2209 * This function performs configuration of:
2210 * - Sequence length: Number of ranks in the scan sequence.
2211 * - Sequence direction: Unless specified in parameters, sequencer
2212 * scan direction is forward (from rank 1 to rank n).
2213 * Sequencer ranks are selected using
2214 * function "LL_ADC_REG_SetSequencerRanks()".
2215 * - For devices with sequencer not fully configurable
2216 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2217 * sequencer length and each rank affectation to a channel
2218 * are defined by channel number.
2219 * This function performs configuration of:
2220 * - Sequence length: Number of ranks in the scan sequence is
2221 * defined by number of channels set in the sequence,
2222 * rank of each channel is fixed by channel HW number.
2223 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2224 * - Sequence direction: Unless specified in parameters, sequencer
2225 * scan direction is forward (from lowest channel number to
2226 * highest channel number).
2227 * Sequencer ranks are selected using
2228 * function "LL_ADC_REG_SetSequencerChannels()".
2229 * @note On this STM32 serie, group regular sequencer configuration
2230 * is conditioned to ADC instance sequencer mode.
2231 * If ADC instance sequencer mode is disabled, sequencers of
2232 * all groups (group regular, group injected) can be configured
2233 * but their execution is disabled (limited to rank 1).
2234 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2235 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2236 * ADC conversion on only 1 channel.
2237 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2238 * @param ADCx ADC instance
2239 * @param SequencerNbRanks This parameter can be one of the following values:
2240 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2241 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2242 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2243 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2244 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2245 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2246 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2247 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2248 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2249 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2256 * @retval None
2257 */
2258 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2259 {
2260 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2261 }
2262
2263 /**
2264 * @brief Get ADC group regular sequencer length and scan direction.
2265 * @note Description of ADC group regular sequencer features:
2266 * - For devices with sequencer fully configurable
2267 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2268 * sequencer length and each rank affectation to a channel
2269 * are configurable.
2270 * This function retrieves:
2271 * - Sequence length: Number of ranks in the scan sequence.
2272 * - Sequence direction: Unless specified in parameters, sequencer
2273 * scan direction is forward (from rank 1 to rank n).
2274 * Sequencer ranks are selected using
2275 * function "LL_ADC_REG_SetSequencerRanks()".
2276 * - For devices with sequencer not fully configurable
2277 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2278 * sequencer length and each rank affectation to a channel
2279 * are defined by channel number.
2280 * This function retrieves:
2281 * - Sequence length: Number of ranks in the scan sequence is
2282 * defined by number of channels set in the sequence,
2283 * rank of each channel is fixed by channel HW number.
2284 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2285 * - Sequence direction: Unless specified in parameters, sequencer
2286 * scan direction is forward (from lowest channel number to
2287 * highest channel number).
2288 * Sequencer ranks are selected using
2289 * function "LL_ADC_REG_SetSequencerChannels()".
2290 * @note On this STM32 serie, group regular sequencer configuration
2291 * is conditioned to ADC instance sequencer mode.
2292 * If ADC instance sequencer mode is disabled, sequencers of
2293 * all groups (group regular, group injected) can be configured
2294 * but their execution is disabled (limited to rank 1).
2295 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2296 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2297 * ADC conversion on only 1 channel.
2298 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2299 * @param ADCx ADC instance
2300 * @retval Returned value can be one of the following values:
2301 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2302 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2303 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2304 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2305 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2306 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2307 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2308 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2309 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2310 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2311 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2312 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2313 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2314 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2315 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2316 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2317 */
2318 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2319 {
2320 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2321 }
2322
2323 /**
2324 * @brief Set ADC group regular sequencer discontinuous mode:
2325 * sequence subdivided and scan conversions interrupted every selected
2326 * number of ranks.
2327 * @note It is not possible to enable both ADC group regular
2328 * continuous mode and sequencer discontinuous mode.
2329 * @note It is not possible to enable both ADC auto-injected mode
2330 * and ADC group regular sequencer discontinuous mode.
2331 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2332 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2333 * @param ADCx ADC instance
2334 * @param SeqDiscont This parameter can be one of the following values:
2335 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2336 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2337 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2338 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2339 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2340 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2341 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2342 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2343 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2344 * @retval None
2345 */
2346 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2347 {
2348 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2349 }
2350
2351 /**
2352 * @brief Get ADC group regular sequencer discontinuous mode:
2353 * sequence subdivided and scan conversions interrupted every selected
2354 * number of ranks.
2355 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2356 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2357 * @param ADCx ADC instance
2358 * @retval Returned value can be one of the following values:
2359 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2360 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2361 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2362 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2363 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2364 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2365 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2366 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2367 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2368 */
2369 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2370 {
2371 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2372 }
2373
2374 /**
2375 * @brief Set ADC group regular sequence: channel on the selected
2376 * scan sequence rank.
2377 * @note This function performs configuration of:
2378 * - Channels ordering into each rank of scan sequence:
2379 * whatever channel can be placed into whatever rank.
2380 * @note On this STM32 serie, ADC group regular sequencer is
2381 * fully configurable: sequencer length and each rank
2382 * affectation to a channel are configurable.
2383 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2384 * @note Depending on devices and packages, some channels may not be available.
2385 * Refer to device datasheet for channels availability.
2386 * @note On this STM32 serie, to measure internal channels (VrefInt,
2387 * TempSensor, ...), measurement paths to internal channels must be
2388 * enabled separately.
2389 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2390 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2391 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2392 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2393 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2394 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2395 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2396 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2397 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2398 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2399 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2400 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2401 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2402 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2403 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2404 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2405 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2406 * @param ADCx ADC instance
2407 * @param Rank This parameter can be one of the following values:
2408 * @arg @ref LL_ADC_REG_RANK_1
2409 * @arg @ref LL_ADC_REG_RANK_2
2410 * @arg @ref LL_ADC_REG_RANK_3
2411 * @arg @ref LL_ADC_REG_RANK_4
2412 * @arg @ref LL_ADC_REG_RANK_5
2413 * @arg @ref LL_ADC_REG_RANK_6
2414 * @arg @ref LL_ADC_REG_RANK_7
2415 * @arg @ref LL_ADC_REG_RANK_8
2416 * @arg @ref LL_ADC_REG_RANK_9
2417 * @arg @ref LL_ADC_REG_RANK_10
2418 * @arg @ref LL_ADC_REG_RANK_11
2419 * @arg @ref LL_ADC_REG_RANK_12
2420 * @arg @ref LL_ADC_REG_RANK_13
2421 * @arg @ref LL_ADC_REG_RANK_14
2422 * @arg @ref LL_ADC_REG_RANK_15
2423 * @arg @ref LL_ADC_REG_RANK_16
2424 * @param Channel This parameter can be one of the following values:
2425 * @arg @ref LL_ADC_CHANNEL_0
2426 * @arg @ref LL_ADC_CHANNEL_1
2427 * @arg @ref LL_ADC_CHANNEL_2
2428 * @arg @ref LL_ADC_CHANNEL_3
2429 * @arg @ref LL_ADC_CHANNEL_4
2430 * @arg @ref LL_ADC_CHANNEL_5
2431 * @arg @ref LL_ADC_CHANNEL_6
2432 * @arg @ref LL_ADC_CHANNEL_7
2433 * @arg @ref LL_ADC_CHANNEL_8
2434 * @arg @ref LL_ADC_CHANNEL_9
2435 * @arg @ref LL_ADC_CHANNEL_10
2436 * @arg @ref LL_ADC_CHANNEL_11
2437 * @arg @ref LL_ADC_CHANNEL_12
2438 * @arg @ref LL_ADC_CHANNEL_13
2439 * @arg @ref LL_ADC_CHANNEL_14
2440 * @arg @ref LL_ADC_CHANNEL_15
2441 * @arg @ref LL_ADC_CHANNEL_16
2442 * @arg @ref LL_ADC_CHANNEL_17
2443 * @arg @ref LL_ADC_CHANNEL_18
2444 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2445 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2446 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2447 *
2448 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2449 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2450 * @retval None
2451 */
2452 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2453 {
2454 /* Set bits with content of parameter "Channel" with bits position */
2455 /* in register and register position depending on parameter "Rank". */
2456 /* Parameters "Rank" and "Channel" are used with masks because containing */
2457 /* other bits reserved for other purpose. */
2458 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2459
2460 MODIFY_REG(*preg,
2461 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2462 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2463 }
2464
2465 /**
2466 * @brief Get ADC group regular sequence: channel on the selected
2467 * scan sequence rank.
2468 * @note On this STM32 serie, ADC group regular sequencer is
2469 * fully configurable: sequencer length and each rank
2470 * affectation to a channel are configurable.
2471 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2472 * @note Depending on devices and packages, some channels may not be available.
2473 * Refer to device datasheet for channels availability.
2474 * @note Usage of the returned channel number:
2475 * - To reinject this channel into another function LL_ADC_xxx:
2476 * the returned channel number is only partly formatted on definition
2477 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2478 * with parts of literals LL_ADC_CHANNEL_x or using
2479 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2480 * Then the selected literal LL_ADC_CHANNEL_x can be used
2481 * as parameter for another function.
2482 * - To get the channel number in decimal format:
2483 * process the returned value with the helper macro
2484 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2485 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2486 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2487 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2488 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2489 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2490 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2491 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2492 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2493 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2494 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2495 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2496 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2497 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2498 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2499 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2500 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2501 * @param ADCx ADC instance
2502 * @param Rank This parameter can be one of the following values:
2503 * @arg @ref LL_ADC_REG_RANK_1
2504 * @arg @ref LL_ADC_REG_RANK_2
2505 * @arg @ref LL_ADC_REG_RANK_3
2506 * @arg @ref LL_ADC_REG_RANK_4
2507 * @arg @ref LL_ADC_REG_RANK_5
2508 * @arg @ref LL_ADC_REG_RANK_6
2509 * @arg @ref LL_ADC_REG_RANK_7
2510 * @arg @ref LL_ADC_REG_RANK_8
2511 * @arg @ref LL_ADC_REG_RANK_9
2512 * @arg @ref LL_ADC_REG_RANK_10
2513 * @arg @ref LL_ADC_REG_RANK_11
2514 * @arg @ref LL_ADC_REG_RANK_12
2515 * @arg @ref LL_ADC_REG_RANK_13
2516 * @arg @ref LL_ADC_REG_RANK_14
2517 * @arg @ref LL_ADC_REG_RANK_15
2518 * @arg @ref LL_ADC_REG_RANK_16
2519 * @retval Returned value can be one of the following values:
2520 * @arg @ref LL_ADC_CHANNEL_0
2521 * @arg @ref LL_ADC_CHANNEL_1
2522 * @arg @ref LL_ADC_CHANNEL_2
2523 * @arg @ref LL_ADC_CHANNEL_3
2524 * @arg @ref LL_ADC_CHANNEL_4
2525 * @arg @ref LL_ADC_CHANNEL_5
2526 * @arg @ref LL_ADC_CHANNEL_6
2527 * @arg @ref LL_ADC_CHANNEL_7
2528 * @arg @ref LL_ADC_CHANNEL_8
2529 * @arg @ref LL_ADC_CHANNEL_9
2530 * @arg @ref LL_ADC_CHANNEL_10
2531 * @arg @ref LL_ADC_CHANNEL_11
2532 * @arg @ref LL_ADC_CHANNEL_12
2533 * @arg @ref LL_ADC_CHANNEL_13
2534 * @arg @ref LL_ADC_CHANNEL_14
2535 * @arg @ref LL_ADC_CHANNEL_15
2536 * @arg @ref LL_ADC_CHANNEL_16
2537 * @arg @ref LL_ADC_CHANNEL_17
2538 * @arg @ref LL_ADC_CHANNEL_18
2539 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2540 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2541 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2542 *
2543 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2544 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2545 * (1) For ADC channel read back from ADC register,
2546 * comparison with internal channel parameter to be done
2547 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2548 */
2549 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2550 {
2551 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2552
2553 return (uint32_t) (READ_BIT(*preg,
2554 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2555 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2556 );
2557 }
2558
2559 /**
2560 * @brief Set ADC continuous conversion mode on ADC group regular.
2561 * @note Description of ADC continuous conversion mode:
2562 * - single mode: one conversion per trigger
2563 * - continuous mode: after the first trigger, following
2564 * conversions launched successively automatically.
2565 * @note It is not possible to enable both ADC group regular
2566 * continuous mode and sequencer discontinuous mode.
2567 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2568 * @param ADCx ADC instance
2569 * @param Continuous This parameter can be one of the following values:
2570 * @arg @ref LL_ADC_REG_CONV_SINGLE
2571 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2572 * @retval None
2573 */
2574 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2575 {
2576 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2577 }
2578
2579 /**
2580 * @brief Get ADC continuous conversion mode on ADC group regular.
2581 * @note Description of ADC continuous conversion mode:
2582 * - single mode: one conversion per trigger
2583 * - continuous mode: after the first trigger, following
2584 * conversions launched successively automatically.
2585 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2586 * @param ADCx ADC instance
2587 * @retval Returned value can be one of the following values:
2588 * @arg @ref LL_ADC_REG_CONV_SINGLE
2589 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2590 */
2591 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2592 {
2593 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2594 }
2595
2596 /**
2597 * @brief Set ADC group regular conversion data transfer: no transfer or
2598 * transfer by DMA, and DMA requests mode.
2599 * @note If transfer by DMA selected, specifies the DMA requests
2600 * mode:
2601 * - Limited mode (One shot mode): DMA transfer requests are stopped
2602 * when number of DMA data transfers (number of
2603 * ADC conversions) is reached.
2604 * This ADC mode is intended to be used with DMA mode non-circular.
2605 * - Unlimited mode: DMA transfer requests are unlimited,
2606 * whatever number of DMA data transfers (number of
2607 * ADC conversions).
2608 * This ADC mode is intended to be used with DMA mode circular.
2609 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2610 * mode non-circular:
2611 * when DMA transfers size will be reached, DMA will stop transfers of
2612 * ADC conversions data ADC will raise an overrun error
2613 * (overrun flag and interruption if enabled).
2614 * @note For devices with several ADC instances: ADC multimode DMA
2615 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2616 * @note To configure DMA source address (peripheral address),
2617 * use function @ref LL_ADC_DMA_GetRegAddr().
2618 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2619 * CR2 DDS LL_ADC_REG_SetDMATransfer
2620 * @param ADCx ADC instance
2621 * @param DMATransfer This parameter can be one of the following values:
2622 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2623 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2624 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2625 * @retval None
2626 */
2627 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2628 {
2629 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2630 }
2631
2632 /**
2633 * @brief Get ADC group regular conversion data transfer: no transfer or
2634 * transfer by DMA, and DMA requests mode.
2635 * @note If transfer by DMA selected, specifies the DMA requests
2636 * mode:
2637 * - Limited mode (One shot mode): DMA transfer requests are stopped
2638 * when number of DMA data transfers (number of
2639 * ADC conversions) is reached.
2640 * This ADC mode is intended to be used with DMA mode non-circular.
2641 * - Unlimited mode: DMA transfer requests are unlimited,
2642 * whatever number of DMA data transfers (number of
2643 * ADC conversions).
2644 * This ADC mode is intended to be used with DMA mode circular.
2645 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2646 * mode non-circular:
2647 * when DMA transfers size will be reached, DMA will stop transfers of
2648 * ADC conversions data ADC will raise an overrun error
2649 * (overrun flag and interruption if enabled).
2650 * @note For devices with several ADC instances: ADC multimode DMA
2651 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2652 * @note To configure DMA source address (peripheral address),
2653 * use function @ref LL_ADC_DMA_GetRegAddr().
2654 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2655 * CR2 DDS LL_ADC_REG_GetDMATransfer
2656 * @param ADCx ADC instance
2657 * @retval Returned value can be one of the following values:
2658 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2659 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2660 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2661 */
2662 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2663 {
2664 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2665 }
2666
2667 /**
2668 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2669 * or EOS (end of sequence conversions) is used to indicate
2670 * the end of conversion.
2671 * @note This feature is aimed to be set when using ADC with
2672 * programming model by polling or interruption
2673 * (programming model by DMA usually uses DMA interruptions
2674 * to indicate end of conversion and data transfer).
2675 * @note For ADC group injected, end of conversion (flag&IT) is raised
2676 * only at the end of the sequence.
2677 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2678 * @param ADCx ADC instance
2679 * @param EocSelection This parameter can be one of the following values:
2680 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2681 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2682 * @retval None
2683 */
2684 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2685 {
2686 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2687 }
2688
2689 /**
2690 * @brief Get which ADC flag between EOC (end of unitary conversion)
2691 * or EOS (end of sequence conversions) is used to indicate
2692 * the end of conversion.
2693 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2694 * @param ADCx ADC instance
2695 * @retval Returned value can be one of the following values:
2696 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2697 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2698 */
2699 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2700 {
2701 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2702 }
2703
2704 /**
2705 * @}
2706 */
2707
2708 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2709 * @{
2710 */
2711
2712 /**
2713 * @brief Set ADC group injected conversion trigger source:
2714 * internal (SW start) or from external IP (timer event,
2715 * external interrupt line).
2716 * @note On this STM32 serie, setting of external trigger edge is performed
2717 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2718 * @note Availability of parameters of trigger sources from timer
2719 * depends on timers availability on the selected device.
2720 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2721 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2722 * @param ADCx ADC instance
2723 * @param TriggerSource This parameter can be one of the following values:
2724 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
2733 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
2734 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
2735 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
2736 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2737 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
2738 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
2739 * @retval None
2740 */
2741 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2742 {
2743 /* Note: On this STM32 serie, ADC group injected external trigger edge */
2744 /* is used to perform a ADC conversion start. */
2745 /* This function does not set external trigger edge. */
2746 /* This feature is set using function */
2747 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2748 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2749 }
2750
2751 /**
2752 * @brief Get ADC group injected conversion trigger source:
2753 * internal (SW start) or from external IP (timer event,
2754 * external interrupt line).
2755 * @note To determine whether group injected trigger source is
2756 * internal (SW start) or external, without detail
2757 * of which peripheral is selected as external trigger,
2758 * (equivalent to
2759 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2760 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2761 * @note Availability of parameters of trigger sources from timer
2762 * depends on timers availability on the selected device.
2763 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2764 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2765 * @param ADCx ADC instance
2766 * @retval Returned value can be one of the following values:
2767 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
2779 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2780 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
2781 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
2782 */
2783 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2784 {
2785 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2786
2787 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2788 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2789 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
2790
2791 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2792 /* to match with triggers literals definition. */
2793 return ((TriggerSource
2794 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2795 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2796 );
2797 }
2798
2799 /**
2800 * @brief Get ADC group injected conversion trigger source internal (SW start)
2801 or external
2802 * @note In case of group injected trigger source set to external trigger,
2803 * to determine which peripheral is selected as external trigger,
2804 * use function @ref LL_ADC_INJ_GetTriggerSource.
2805 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2806 * @param ADCx ADC instance
2807 * @retval Value "0" if trigger source external trigger
2808 * Value "1" if trigger source SW start.
2809 */
2810 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2811 {
2812 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2813 }
2814
2815 /**
2816 * @brief Get ADC group injected conversion trigger polarity.
2817 * Applicable only for trigger source set to external trigger.
2818 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2819 * @param ADCx ADC instance
2820 * @retval Returned value can be one of the following values:
2821 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2822 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2823 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2824 */
2825 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2826 {
2827 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2828 }
2829
2830 /**
2831 * @brief Set ADC group injected sequencer length and scan direction.
2832 * @note This function performs configuration of:
2833 * - Sequence length: Number of ranks in the scan sequence.
2834 * - Sequence direction: Unless specified in parameters, sequencer
2835 * scan direction is forward (from rank 1 to rank n).
2836 * @note On this STM32 serie, group injected sequencer configuration
2837 * is conditioned to ADC instance sequencer mode.
2838 * If ADC instance sequencer mode is disabled, sequencers of
2839 * all groups (group regular, group injected) can be configured
2840 * but their execution is disabled (limited to rank 1).
2841 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2842 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2843 * ADC conversion on only 1 channel.
2844 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2845 * @param ADCx ADC instance
2846 * @param SequencerNbRanks This parameter can be one of the following values:
2847 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2848 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2849 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2850 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2851 * @retval None
2852 */
2853 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2854 {
2855 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2856 }
2857
2858 /**
2859 * @brief Get ADC group injected sequencer length and scan direction.
2860 * @note This function retrieves:
2861 * - Sequence length: Number of ranks in the scan sequence.
2862 * - Sequence direction: Unless specified in parameters, sequencer
2863 * scan direction is forward (from rank 1 to rank n).
2864 * @note On this STM32 serie, group injected sequencer configuration
2865 * is conditioned to ADC instance sequencer mode.
2866 * If ADC instance sequencer mode is disabled, sequencers of
2867 * all groups (group regular, group injected) can be configured
2868 * but their execution is disabled (limited to rank 1).
2869 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2870 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2871 * ADC conversion on only 1 channel.
2872 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2873 * @param ADCx ADC instance
2874 * @retval Returned value can be one of the following values:
2875 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2876 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2877 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2878 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2879 */
2880 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2881 {
2882 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2883 }
2884
2885 /**
2886 * @brief Set ADC group injected sequencer discontinuous mode:
2887 * sequence subdivided and scan conversions interrupted every selected
2888 * number of ranks.
2889 * @note It is not possible to enable both ADC group injected
2890 * auto-injected mode and sequencer discontinuous mode.
2891 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2892 * @param ADCx ADC instance
2893 * @param SeqDiscont This parameter can be one of the following values:
2894 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2895 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2896 * @retval None
2897 */
2898 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2899 {
2900 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2901 }
2902
2903 /**
2904 * @brief Get ADC group injected sequencer discontinuous mode:
2905 * sequence subdivided and scan conversions interrupted every selected
2906 * number of ranks.
2907 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2908 * @param ADCx ADC instance
2909 * @retval Returned value can be one of the following values:
2910 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2911 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2912 */
2913 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2914 {
2915 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2916 }
2917
2918 /**
2919 * @brief Set ADC group injected sequence: channel on the selected
2920 * sequence rank.
2921 * @note Depending on devices and packages, some channels may not be available.
2922 * Refer to device datasheet for channels availability.
2923 * @note On this STM32 serie, to measure internal channels (VrefInt,
2924 * TempSensor, ...), measurement paths to internal channels must be
2925 * enabled separately.
2926 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2927 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2928 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2929 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2930 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2931 * @param ADCx ADC instance
2932 * @param Rank This parameter can be one of the following values:
2933 * @arg @ref LL_ADC_INJ_RANK_1
2934 * @arg @ref LL_ADC_INJ_RANK_2
2935 * @arg @ref LL_ADC_INJ_RANK_3
2936 * @arg @ref LL_ADC_INJ_RANK_4
2937 * @param Channel This parameter can be one of the following values:
2938 * @arg @ref LL_ADC_CHANNEL_0
2939 * @arg @ref LL_ADC_CHANNEL_1
2940 * @arg @ref LL_ADC_CHANNEL_2
2941 * @arg @ref LL_ADC_CHANNEL_3
2942 * @arg @ref LL_ADC_CHANNEL_4
2943 * @arg @ref LL_ADC_CHANNEL_5
2944 * @arg @ref LL_ADC_CHANNEL_6
2945 * @arg @ref LL_ADC_CHANNEL_7
2946 * @arg @ref LL_ADC_CHANNEL_8
2947 * @arg @ref LL_ADC_CHANNEL_9
2948 * @arg @ref LL_ADC_CHANNEL_10
2949 * @arg @ref LL_ADC_CHANNEL_11
2950 * @arg @ref LL_ADC_CHANNEL_12
2951 * @arg @ref LL_ADC_CHANNEL_13
2952 * @arg @ref LL_ADC_CHANNEL_14
2953 * @arg @ref LL_ADC_CHANNEL_15
2954 * @arg @ref LL_ADC_CHANNEL_16
2955 * @arg @ref LL_ADC_CHANNEL_17
2956 * @arg @ref LL_ADC_CHANNEL_18
2957 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2958 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2959 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2960 *
2961 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2962 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2963 * @retval None
2964 */
2965 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2966 {
2967 /* Set bits with content of parameter "Channel" with bits position */
2968 /* in register depending on parameter "Rank". */
2969 /* Parameters "Rank" and "Channel" are used with masks because containing */
2970 /* other bits reserved for other purpose. */
2971 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2972
2973 MODIFY_REG(ADCx->JSQR,
2974 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2975 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2976 }
2977
2978 /**
2979 * @brief Get ADC group injected sequence: channel on the selected
2980 * sequence rank.
2981 * @note Depending on devices and packages, some channels may not be available.
2982 * Refer to device datasheet for channels availability.
2983 * @note Usage of the returned channel number:
2984 * - To reinject this channel into another function LL_ADC_xxx:
2985 * the returned channel number is only partly formatted on definition
2986 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2987 * with parts of literals LL_ADC_CHANNEL_x or using
2988 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2989 * Then the selected literal LL_ADC_CHANNEL_x can be used
2990 * as parameter for another function.
2991 * - To get the channel number in decimal format:
2992 * process the returned value with the helper macro
2993 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2994 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2995 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2996 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2997 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2998 * @param ADCx ADC instance
2999 * @param Rank This parameter can be one of the following values:
3000 * @arg @ref LL_ADC_INJ_RANK_1
3001 * @arg @ref LL_ADC_INJ_RANK_2
3002 * @arg @ref LL_ADC_INJ_RANK_3
3003 * @arg @ref LL_ADC_INJ_RANK_4
3004 * @retval Returned value can be one of the following values:
3005 * @arg @ref LL_ADC_CHANNEL_0
3006 * @arg @ref LL_ADC_CHANNEL_1
3007 * @arg @ref LL_ADC_CHANNEL_2
3008 * @arg @ref LL_ADC_CHANNEL_3
3009 * @arg @ref LL_ADC_CHANNEL_4
3010 * @arg @ref LL_ADC_CHANNEL_5
3011 * @arg @ref LL_ADC_CHANNEL_6
3012 * @arg @ref LL_ADC_CHANNEL_7
3013 * @arg @ref LL_ADC_CHANNEL_8
3014 * @arg @ref LL_ADC_CHANNEL_9
3015 * @arg @ref LL_ADC_CHANNEL_10
3016 * @arg @ref LL_ADC_CHANNEL_11
3017 * @arg @ref LL_ADC_CHANNEL_12
3018 * @arg @ref LL_ADC_CHANNEL_13
3019 * @arg @ref LL_ADC_CHANNEL_14
3020 * @arg @ref LL_ADC_CHANNEL_15
3021 * @arg @ref LL_ADC_CHANNEL_16
3022 * @arg @ref LL_ADC_CHANNEL_17
3023 * @arg @ref LL_ADC_CHANNEL_18
3024 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3025 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3026 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3027 *
3028 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3029 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
3030 * (1) For ADC channel read back from ADC register,
3031 * comparison with internal channel parameter to be done
3032 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3033 */
3034 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3035 {
3036 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
3037
3038 return (uint32_t)(READ_BIT(ADCx->JSQR,
3039 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
3040 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
3041 );
3042 }
3043
3044 /**
3045 * @brief Set ADC group injected conversion trigger:
3046 * independent or from ADC group regular.
3047 * @note This mode can be used to extend number of data registers
3048 * updated after one ADC conversion trigger and with data
3049 * permanently kept (not erased by successive conversions of scan of
3050 * ADC sequencer ranks), up to 5 data registers:
3051 * 1 data register on ADC group regular, 4 data registers
3052 * on ADC group injected.
3053 * @note If ADC group injected injected trigger source is set to an
3054 * external trigger, this feature must be must be set to
3055 * independent trigger.
3056 * ADC group injected automatic trigger is compliant only with
3057 * group injected trigger source set to SW start, without any
3058 * further action on ADC group injected conversion start or stop:
3059 * in this case, ADC group injected is controlled only
3060 * from ADC group regular.
3061 * @note It is not possible to enable both ADC group injected
3062 * auto-injected mode and sequencer discontinuous mode.
3063 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3064 * @param ADCx ADC instance
3065 * @param TrigAuto This parameter can be one of the following values:
3066 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3067 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3068 * @retval None
3069 */
3070 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3071 {
3072 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3073 }
3074
3075 /**
3076 * @brief Get ADC group injected conversion trigger:
3077 * independent or from ADC group regular.
3078 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3079 * @param ADCx ADC instance
3080 * @retval Returned value can be one of the following values:
3081 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3082 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3083 */
3084 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3085 {
3086 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3087 }
3088
3089 /**
3090 * @brief Set ADC group injected offset.
3091 * @note It sets:
3092 * - ADC group injected rank to which the offset programmed
3093 * will be applied
3094 * - Offset level (offset to be subtracted from the raw
3095 * converted data).
3096 * Caution: Offset format is dependent to ADC resolution:
3097 * offset has to be left-aligned on bit 11, the LSB (right bits)
3098 * are set to 0.
3099 * @note Offset cannot be enabled or disabled.
3100 * To emulate offset disabled, set an offset value equal to 0.
3101 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3102 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3103 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3104 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3105 * @param ADCx ADC instance
3106 * @param Rank This parameter can be one of the following values:
3107 * @arg @ref LL_ADC_INJ_RANK_1
3108 * @arg @ref LL_ADC_INJ_RANK_2
3109 * @arg @ref LL_ADC_INJ_RANK_3
3110 * @arg @ref LL_ADC_INJ_RANK_4
3111 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3112 * @retval None
3113 */
3114 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3115 {
3116 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3117
3118 MODIFY_REG(*preg,
3119 ADC_JOFR1_JOFFSET1,
3120 OffsetLevel);
3121 }
3122
3123 /**
3124 * @brief Get ADC group injected offset.
3125 * @note It gives offset level (offset to be subtracted from the raw converted data).
3126 * Caution: Offset format is dependent to ADC resolution:
3127 * offset has to be left-aligned on bit 11, the LSB (right bits)
3128 * are set to 0.
3129 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3130 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3131 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3132 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3133 * @param ADCx ADC instance
3134 * @param Rank This parameter can be one of the following values:
3135 * @arg @ref LL_ADC_INJ_RANK_1
3136 * @arg @ref LL_ADC_INJ_RANK_2
3137 * @arg @ref LL_ADC_INJ_RANK_3
3138 * @arg @ref LL_ADC_INJ_RANK_4
3139 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3140 */
3141 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3142 {
3143 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3144
3145 return (uint32_t)(READ_BIT(*preg,
3146 ADC_JOFR1_JOFFSET1)
3147 );
3148 }
3149
3150 /**
3151 * @}
3152 */
3153
3154 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3155 * @{
3156 */
3157
3158 /**
3159 * @brief Set sampling time of the selected ADC channel
3160 * Unit: ADC clock cycles.
3161 * @note On this device, sampling time is on channel scope: independently
3162 * of channel mapped on ADC group regular or injected.
3163 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3164 * converted:
3165 * sampling time constraints must be respected (sampling time can be
3166 * adjusted in function of ADC clock frequency and sampling time
3167 * setting).
3168 * Refer to device datasheet for timings values (parameters TS_vrefint,
3169 * TS_temp, ...).
3170 * @note Conversion time is the addition of sampling time and processing time.
3171 * Refer to reference manual for ADC processing time of
3172 * this STM32 serie.
3173 * @note In case of ADC conversion of internal channel (VrefInt,
3174 * temperature sensor, ...), a sampling time minimum value
3175 * is required.
3176 * Refer to device datasheet.
3177 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3178 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3179 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3180 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3181 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3182 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3183 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3184 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3185 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3186 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3187 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3188 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3189 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3190 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3191 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3192 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3193 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3194 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3195 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3196 * @param ADCx ADC instance
3197 * @param Channel This parameter can be one of the following values:
3198 * @arg @ref LL_ADC_CHANNEL_0
3199 * @arg @ref LL_ADC_CHANNEL_1
3200 * @arg @ref LL_ADC_CHANNEL_2
3201 * @arg @ref LL_ADC_CHANNEL_3
3202 * @arg @ref LL_ADC_CHANNEL_4
3203 * @arg @ref LL_ADC_CHANNEL_5
3204 * @arg @ref LL_ADC_CHANNEL_6
3205 * @arg @ref LL_ADC_CHANNEL_7
3206 * @arg @ref LL_ADC_CHANNEL_8
3207 * @arg @ref LL_ADC_CHANNEL_9
3208 * @arg @ref LL_ADC_CHANNEL_10
3209 * @arg @ref LL_ADC_CHANNEL_11
3210 * @arg @ref LL_ADC_CHANNEL_12
3211 * @arg @ref LL_ADC_CHANNEL_13
3212 * @arg @ref LL_ADC_CHANNEL_14
3213 * @arg @ref LL_ADC_CHANNEL_15
3214 * @arg @ref LL_ADC_CHANNEL_16
3215 * @arg @ref LL_ADC_CHANNEL_17
3216 * @arg @ref LL_ADC_CHANNEL_18
3217 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3218 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3219 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3220 *
3221 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3222 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3223 * @param SamplingTime This parameter can be one of the following values:
3224 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3225 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3226 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3227 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3228 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3229 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3230 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3231 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3232 * @retval None
3233 */
3234 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3235 {
3236 /* Set bits with content of parameter "SamplingTime" with bits position */
3237 /* in register and register position depending on parameter "Channel". */
3238 /* Parameter "Channel" is used with masks because containing */
3239 /* other bits reserved for other purpose. */
3240 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3241
3242 MODIFY_REG(*preg,
3243 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3244 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3245 }
3246
3247 /**
3248 * @brief Get sampling time of the selected ADC channel
3249 * Unit: ADC clock cycles.
3250 * @note On this device, sampling time is on channel scope: independently
3251 * of channel mapped on ADC group regular or injected.
3252 * @note Conversion time is the addition of sampling time and processing time.
3253 * Refer to reference manual for ADC processing time of
3254 * this STM32 serie.
3255 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3256 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3257 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3258 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3259 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3260 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3261 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3262 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3263 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3264 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3265 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3266 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3267 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3268 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3269 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3270 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3271 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3272 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3273 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3274 * @param ADCx ADC instance
3275 * @param Channel This parameter can be one of the following values:
3276 * @arg @ref LL_ADC_CHANNEL_0
3277 * @arg @ref LL_ADC_CHANNEL_1
3278 * @arg @ref LL_ADC_CHANNEL_2
3279 * @arg @ref LL_ADC_CHANNEL_3
3280 * @arg @ref LL_ADC_CHANNEL_4
3281 * @arg @ref LL_ADC_CHANNEL_5
3282 * @arg @ref LL_ADC_CHANNEL_6
3283 * @arg @ref LL_ADC_CHANNEL_7
3284 * @arg @ref LL_ADC_CHANNEL_8
3285 * @arg @ref LL_ADC_CHANNEL_9
3286 * @arg @ref LL_ADC_CHANNEL_10
3287 * @arg @ref LL_ADC_CHANNEL_11
3288 * @arg @ref LL_ADC_CHANNEL_12
3289 * @arg @ref LL_ADC_CHANNEL_13
3290 * @arg @ref LL_ADC_CHANNEL_14
3291 * @arg @ref LL_ADC_CHANNEL_15
3292 * @arg @ref LL_ADC_CHANNEL_16
3293 * @arg @ref LL_ADC_CHANNEL_17
3294 * @arg @ref LL_ADC_CHANNEL_18
3295 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3296 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3297 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3298 *
3299 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3300 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3301 * @retval Returned value can be one of the following values:
3302 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3303 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3304 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3305 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3306 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3307 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3308 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3309 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3310 */
3311 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3312 {
3313 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3314
3315 return (uint32_t)(READ_BIT(*preg,
3316 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3317 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3318 );
3319 }
3320
3321 /**
3322 * @}
3323 */
3324
3325 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3326 * @{
3327 */
3328
3329 /**
3330 * @brief Set ADC analog watchdog monitored channels:
3331 * a single channel or all channels,
3332 * on ADC groups regular and-or injected.
3333 * @note Once monitored channels are selected, analog watchdog
3334 * is enabled.
3335 * @note In case of need to define a single channel to monitor
3336 * with analog watchdog from sequencer channel definition,
3337 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3338 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3339 * instance:
3340 * - AWD standard (instance AWD1):
3341 * - channels monitored: can monitor 1 channel or all channels.
3342 * - groups monitored: ADC groups regular and-or injected.
3343 * - resolution: resolution is not limited (corresponds to
3344 * ADC resolution configured).
3345 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3346 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3347 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3348 * @param ADCx ADC instance
3349 * @param AWDChannelGroup This parameter can be one of the following values:
3350 * @arg @ref LL_ADC_AWD_DISABLE
3351 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3352 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3353 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3354 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3355 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3356 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3357 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3358 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3359 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3360 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3361 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3362 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3363 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3364 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3365 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3366 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3367 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3368 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3369 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3370 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3371 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3372 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3373 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3374 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3375 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3376 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3377 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3378 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3379 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3380 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3381 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3382 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3383 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3384 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3385 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3386 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3387 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3388 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3389 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3390 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3391 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3392 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3393 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3394 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3395 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3396 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3397 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3398 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3399 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3400 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3401 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3402 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3403 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3404 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3405 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3406 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3407 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3408 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3409 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3410 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3411 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3412 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3413 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3414 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3415 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3416 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3417 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3418 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3419 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3420 *
3421 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3422 * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3423 * @retval None
3424 */
3425 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3426 {
3427 MODIFY_REG(ADCx->CR1,
3428 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3429 AWDChannelGroup);
3430 }
3431
3432 /**
3433 * @brief Get ADC analog watchdog monitored channel.
3434 * @note Usage of the returned channel number:
3435 * - To reinject this channel into another function LL_ADC_xxx:
3436 * the returned channel number is only partly formatted on definition
3437 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3438 * with parts of literals LL_ADC_CHANNEL_x or using
3439 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3440 * Then the selected literal LL_ADC_CHANNEL_x can be used
3441 * as parameter for another function.
3442 * - To get the channel number in decimal format:
3443 * process the returned value with the helper macro
3444 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3445 * Applicable only when the analog watchdog is set to monitor
3446 * one channel.
3447 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3448 * instance:
3449 * - AWD standard (instance AWD1):
3450 * - channels monitored: can monitor 1 channel or all channels.
3451 * - groups monitored: ADC groups regular and-or injected.
3452 * - resolution: resolution is not limited (corresponds to
3453 * ADC resolution configured).
3454 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3455 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3456 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3457 * @param ADCx ADC instance
3458 * @retval Returned value can be one of the following values:
3459 * @arg @ref LL_ADC_AWD_DISABLE
3460 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3461 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3462 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3463 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3464 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3465 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3466 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3467 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3468 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3469 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3470 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3471 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3472 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3473 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3474 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3475 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3476 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3477 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3478 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3479 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3480 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3481 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3482 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3483 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3484 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3485 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3486 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3487 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3488 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3489 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3490 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3491 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3492 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3493 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3494 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3495 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3496 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3497 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3498 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3499 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3500 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3501 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3502 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3503 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3504 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3505 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3506 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3507 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3508 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3509 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3510 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3511 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3512 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3513 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3514 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3515 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3516 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3517 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3518 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3519 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3520 */
3521 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3522 {
3523 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3524 }
3525
3526 /**
3527 * @brief Set ADC analog watchdog threshold value of threshold
3528 * high or low.
3529 * @note In case of ADC resolution different of 12 bits,
3530 * analog watchdog thresholds data require a specific shift.
3531 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3532 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3533 * instance:
3534 * - AWD standard (instance AWD1):
3535 * - channels monitored: can monitor 1 channel or all channels.
3536 * - groups monitored: ADC groups regular and-or injected.
3537 * - resolution: resolution is not limited (corresponds to
3538 * ADC resolution configured).
3539 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3540 * LTR LT LL_ADC_SetAnalogWDThresholds
3541 * @param ADCx ADC instance
3542 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3543 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3544 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3545 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3546 * @retval None
3547 */
3548 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3549 {
3550 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3551
3552 MODIFY_REG(*preg,
3553 ADC_HTR_HT,
3554 AWDThresholdValue);
3555 }
3556
3557 /**
3558 * @brief Get ADC analog watchdog threshold value of threshold high or
3559 * threshold low.
3560 * @note In case of ADC resolution different of 12 bits,
3561 * analog watchdog thresholds data require a specific shift.
3562 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3563 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3564 * LTR LT LL_ADC_GetAnalogWDThresholds
3565 * @param ADCx ADC instance
3566 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3567 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3568 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3569 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3570 */
3571 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3572 {
3573 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3574
3575 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3576 }
3577
3578 /**
3579 * @}
3580 */
3581
3582 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3583 * @{
3584 */
3585
3586 /**
3587 * @brief Set ADC multimode configuration to operate in independent mode
3588 * or multimode (for devices with several ADC instances).
3589 * @note If multimode configuration: the selected ADC instance is
3590 * either master or slave depending on hardware.
3591 * Refer to reference manual.
3592 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3593 * @param ADCxy_COMMON ADC common instance
3594 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3595 * @param Multimode This parameter can be one of the following values:
3596 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3597 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3598 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3599 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3600 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3601 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3602 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3603 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3604 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3605 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3606 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3607 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3608 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3609 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3610 * @retval None
3611 */
3612 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3613 {
3614 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3615 }
3616
3617 /**
3618 * @brief Get ADC multimode configuration to operate in independent mode
3619 * or multimode (for devices with several ADC instances).
3620 * @note If multimode configuration: the selected ADC instance is
3621 * either master or slave depending on hardware.
3622 * Refer to reference manual.
3623 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3624 * @param ADCxy_COMMON ADC common instance
3625 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3626 * @retval Returned value can be one of the following values:
3627 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3628 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3629 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3630 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3631 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3632 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3633 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3634 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3635 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3636 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3637 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3638 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3639 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3640 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3641 */
3642 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3643 {
3644 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3645 }
3646
3647 /**
3648 * @brief Set ADC multimode conversion data transfer: no transfer
3649 * or transfer by DMA.
3650 * @note If ADC multimode transfer by DMA is not selected:
3651 * each ADC uses its own DMA channel, with its individual
3652 * DMA transfer settings.
3653 * If ADC multimode transfer by DMA is selected:
3654 * One DMA channel is used for both ADC (DMA of ADC master)
3655 * Specifies the DMA requests mode:
3656 * - Limited mode (One shot mode): DMA transfer requests are stopped
3657 * when number of DMA data transfers (number of
3658 * ADC conversions) is reached.
3659 * This ADC mode is intended to be used with DMA mode non-circular.
3660 * - Unlimited mode: DMA transfer requests are unlimited,
3661 * whatever number of DMA data transfers (number of
3662 * ADC conversions).
3663 * This ADC mode is intended to be used with DMA mode circular.
3664 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3665 * mode non-circular:
3666 * when DMA transfers size will be reached, DMA will stop transfers of
3667 * ADC conversions data ADC will raise an overrun error
3668 * (overrun flag and interruption if enabled).
3669 * @note How to retrieve multimode conversion data:
3670 * Whatever multimode transfer by DMA setting: using function
3671 * @ref LL_ADC_REG_ReadMultiConversionData32().
3672 * If ADC multimode transfer by DMA is selected: conversion data
3673 * is a raw data with ADC master and slave concatenated.
3674 * A macro is available to get the conversion data of
3675 * ADC master or ADC slave: see helper macro
3676 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3677 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3678 * CCR DDS LL_ADC_SetMultiDMATransfer
3679 * @param ADCxy_COMMON ADC common instance
3680 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3681 * @param MultiDMATransfer This parameter can be one of the following values:
3682 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3683 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3684 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3685 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3686 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3687 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3688 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3689 * @retval None
3690 */
3691 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3692 {
3693 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3694 }
3695
3696 /**
3697 * @brief Get ADC multimode conversion data transfer: no transfer
3698 * or transfer by DMA.
3699 * @note If ADC multimode transfer by DMA is not selected:
3700 * each ADC uses its own DMA channel, with its individual
3701 * DMA transfer settings.
3702 * If ADC multimode transfer by DMA is selected:
3703 * One DMA channel is used for both ADC (DMA of ADC master)
3704 * Specifies the DMA requests mode:
3705 * - Limited mode (One shot mode): DMA transfer requests are stopped
3706 * when number of DMA data transfers (number of
3707 * ADC conversions) is reached.
3708 * This ADC mode is intended to be used with DMA mode non-circular.
3709 * - Unlimited mode: DMA transfer requests are unlimited,
3710 * whatever number of DMA data transfers (number of
3711 * ADC conversions).
3712 * This ADC mode is intended to be used with DMA mode circular.
3713 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3714 * mode non-circular:
3715 * when DMA transfers size will be reached, DMA will stop transfers of
3716 * ADC conversions data ADC will raise an overrun error
3717 * (overrun flag and interruption if enabled).
3718 * @note How to retrieve multimode conversion data:
3719 * Whatever multimode transfer by DMA setting: using function
3720 * @ref LL_ADC_REG_ReadMultiConversionData32().
3721 * If ADC multimode transfer by DMA is selected: conversion data
3722 * is a raw data with ADC master and slave concatenated.
3723 * A macro is available to get the conversion data of
3724 * ADC master or ADC slave: see helper macro
3725 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3726 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3727 * CCR DDS LL_ADC_GetMultiDMATransfer
3728 * @param ADCxy_COMMON ADC common instance
3729 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3730 * @retval Returned value can be one of the following values:
3731 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3732 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3733 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3734 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3735 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3736 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3737 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3738 */
3739 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3740 {
3741 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3742 }
3743
3744 /**
3745 * @brief Set ADC multimode delay between 2 sampling phases.
3746 * @note The sampling delay range depends on ADC resolution:
3747 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3748 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3749 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3750 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3751 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3752 * @param ADCxy_COMMON ADC common instance
3753 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3754 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3755 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3756 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3757 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3758 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3759 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3760 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3761 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3762 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3763 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3764 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3765 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3766 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3767 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3768 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3769 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3770 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3771 * @retval None
3772 */
3773 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3774 {
3775 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3776 }
3777
3778 /**
3779 * @brief Get ADC multimode delay between 2 sampling phases.
3780 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3781 * @param ADCxy_COMMON ADC common instance
3782 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3783 * @retval Returned value can be one of the following values:
3784 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3785 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3786 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3787 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3788 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3789 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3790 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3791 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3792 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3793 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3794 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3795 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3796 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3797 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3800 */
3801 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3802 {
3803 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3804 }
3805
3806 /**
3807 * @}
3808 */
3809 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3810 * @{
3811 */
3812
3813 /**
3814 * @brief Enable the selected ADC instance.
3815 * @note On this STM32 serie, after ADC enable, a delay for
3816 * ADC internal analog stabilization is required before performing a
3817 * ADC conversion start.
3818 * Refer to device datasheet, parameter tSTAB.
3819 * @rmtoll CR2 ADON LL_ADC_Enable
3820 * @param ADCx ADC instance
3821 * @retval None
3822 */
3823 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3824 {
3825 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3826 }
3827
3828 /**
3829 * @brief Disable the selected ADC instance.
3830 * @rmtoll CR2 ADON LL_ADC_Disable
3831 * @param ADCx ADC instance
3832 * @retval None
3833 */
3834 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3835 {
3836 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3837 }
3838
3839 /**
3840 * @brief Get the selected ADC instance enable state.
3841 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3842 * @param ADCx ADC instance
3843 * @retval 0: ADC is disabled, 1: ADC is enabled.
3844 */
3845 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3846 {
3847 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3848 }
3849
3850 /**
3851 * @}
3852 */
3853
3854 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3855 * @{
3856 */
3857
3858 /**
3859 * @brief Start ADC group regular conversion.
3860 * @note On this STM32 serie, this function is relevant only for
3861 * internal trigger (SW start), not for external trigger:
3862 * - If ADC trigger has been set to software start, ADC conversion
3863 * starts immediately.
3864 * - If ADC trigger has been set to external trigger, ADC conversion
3865 * start must be performed using function
3866 * @ref LL_ADC_REG_StartConversionExtTrig().
3867 * (if external trigger edge would have been set during ADC other
3868 * settings, ADC conversion would start at trigger event
3869 * as soon as ADC is enabled).
3870 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3871 * @param ADCx ADC instance
3872 * @retval None
3873 */
3874 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3875 {
3876 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3877 }
3878
3879 /**
3880 * @brief Start ADC group regular conversion from external trigger.
3881 * @note ADC conversion will start at next trigger event (on the selected
3882 * trigger edge) following the ADC start conversion command.
3883 * @note On this STM32 serie, this function is relevant for
3884 * ADC conversion start from external trigger.
3885 * If internal trigger (SW start) is needed, perform ADC conversion
3886 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3887 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3888 * @param ExternalTriggerEdge This parameter can be one of the following values:
3889 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3890 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3891 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3892 * @param ADCx ADC instance
3893 * @retval None
3894 */
3895 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3896 {
3897 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3898 }
3899
3900 /**
3901 * @brief Stop ADC group regular conversion from external trigger.
3902 * @note No more ADC conversion will start at next trigger event
3903 * following the ADC stop conversion command.
3904 * If a conversion is on-going, it will be completed.
3905 * @note On this STM32 serie, there is no specific command
3906 * to stop a conversion on-going or to stop ADC converting
3907 * in continuous mode. These actions can be performed
3908 * using function @ref LL_ADC_Disable().
3909 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3910 * @param ADCx ADC instance
3911 * @retval None
3912 */
3913 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3914 {
3915 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3916 }
3917
3918 /**
3919 * @brief Get ADC group regular conversion data, range fit for
3920 * all ADC configurations: all ADC resolutions and
3921 * all oversampling increased data width (for devices
3922 * with feature oversampling).
3923 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3924 * @param ADCx ADC instance
3925 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3926 */
3927 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3928 {
3929 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3930 }
3931
3932 /**
3933 * @brief Get ADC group regular conversion data, range fit for
3934 * ADC resolution 12 bits.
3935 * @note For devices with feature oversampling: Oversampling
3936 * can increase data width, function for extended range
3937 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3938 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3939 * @param ADCx ADC instance
3940 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3941 */
3942 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3943 {
3944 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3945 }
3946
3947 /**
3948 * @brief Get ADC group regular conversion data, range fit for
3949 * ADC resolution 10 bits.
3950 * @note For devices with feature oversampling: Oversampling
3951 * can increase data width, function for extended range
3952 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3953 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3954 * @param ADCx ADC instance
3955 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3956 */
3957 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3958 {
3959 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3960 }
3961
3962 /**
3963 * @brief Get ADC group regular conversion data, range fit for
3964 * ADC resolution 8 bits.
3965 * @note For devices with feature oversampling: Oversampling
3966 * can increase data width, function for extended range
3967 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3968 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
3969 * @param ADCx ADC instance
3970 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3971 */
3972 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3973 {
3974 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3975 }
3976
3977 /**
3978 * @brief Get ADC group regular conversion data, range fit for
3979 * ADC resolution 6 bits.
3980 * @note For devices with feature oversampling: Oversampling
3981 * can increase data width, function for extended range
3982 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3983 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
3984 * @param ADCx ADC instance
3985 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3986 */
3987 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3988 {
3989 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3990 }
3991
3992 /**
3993 * @brief Get ADC multimode conversion data of ADC master, ADC slave
3994 * or raw data with ADC master and slave concatenated.
3995 * @note If raw data with ADC master and slave concatenated is retrieved,
3996 * a macro is available to get the conversion data of
3997 * ADC master or ADC slave: see helper macro
3998 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3999 * (however this macro is mainly intended for multimode
4000 * transfer by DMA, because this function can do the same
4001 * by getting multimode conversion data of ADC master or ADC slave
4002 * separately).
4003 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
4004 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
4005 * @param ADCxy_COMMON ADC common instance
4006 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4007 * @param ConversionData This parameter can be one of the following values:
4008 * @arg @ref LL_ADC_MULTI_MASTER
4009 * @arg @ref LL_ADC_MULTI_SLAVE
4010 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
4011 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4012 */
4013 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4014 {
4015 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4016 ADC_DR_ADC2DATA)
4017 >> POSITION_VAL(ConversionData)
4018 );
4019 }
4020
4021 /**
4022 * @}
4023 */
4024
4025 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4026 * @{
4027 */
4028
4029 /**
4030 * @brief Start ADC group injected conversion.
4031 * @note On this STM32 serie, this function is relevant only for
4032 * internal trigger (SW start), not for external trigger:
4033 * - If ADC trigger has been set to software start, ADC conversion
4034 * starts immediately.
4035 * - If ADC trigger has been set to external trigger, ADC conversion
4036 * start must be performed using function
4037 * @ref LL_ADC_INJ_StartConversionExtTrig().
4038 * (if external trigger edge would have been set during ADC other
4039 * settings, ADC conversion would start at trigger event
4040 * as soon as ADC is enabled).
4041 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4042 * @param ADCx ADC instance
4043 * @retval None
4044 */
4045 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4046 {
4047 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4048 }
4049
4050 /**
4051 * @brief Start ADC group injected conversion from external trigger.
4052 * @note ADC conversion will start at next trigger event (on the selected
4053 * trigger edge) following the ADC start conversion command.
4054 * @note On this STM32 serie, this function is relevant for
4055 * ADC conversion start from external trigger.
4056 * If internal trigger (SW start) is needed, perform ADC conversion
4057 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4058 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4059 * @param ExternalTriggerEdge This parameter can be one of the following values:
4060 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4061 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4062 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4063 * @param ADCx ADC instance
4064 * @retval None
4065 */
4066 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4067 {
4068 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4069 }
4070
4071 /**
4072 * @brief Stop ADC group injected conversion from external trigger.
4073 * @note No more ADC conversion will start at next trigger event
4074 * following the ADC stop conversion command.
4075 * If a conversion is on-going, it will be completed.
4076 * @note On this STM32 serie, there is no specific command
4077 * to stop a conversion on-going or to stop ADC converting
4078 * in continuous mode. These actions can be performed
4079 * using function @ref LL_ADC_Disable().
4080 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4081 * @param ADCx ADC instance
4082 * @retval None
4083 */
4084 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4085 {
4086 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4087 }
4088
4089 /**
4090 * @brief Get ADC group regular conversion data, range fit for
4091 * all ADC configurations: all ADC resolutions and
4092 * all oversampling increased data width (for devices
4093 * with feature oversampling).
4094 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4095 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4096 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4097 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4098 * @param ADCx ADC instance
4099 * @param Rank This parameter can be one of the following values:
4100 * @arg @ref LL_ADC_INJ_RANK_1
4101 * @arg @ref LL_ADC_INJ_RANK_2
4102 * @arg @ref LL_ADC_INJ_RANK_3
4103 * @arg @ref LL_ADC_INJ_RANK_4
4104 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4105 */
4106 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4107 {
4108 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4109
4110 return (uint32_t)(READ_BIT(*preg,
4111 ADC_JDR1_JDATA)
4112 );
4113 }
4114
4115 /**
4116 * @brief Get ADC group injected conversion data, range fit for
4117 * ADC resolution 12 bits.
4118 * @note For devices with feature oversampling: Oversampling
4119 * can increase data width, function for extended range
4120 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4121 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4122 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4123 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4124 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4125 * @param ADCx ADC instance
4126 * @param Rank This parameter can be one of the following values:
4127 * @arg @ref LL_ADC_INJ_RANK_1
4128 * @arg @ref LL_ADC_INJ_RANK_2
4129 * @arg @ref LL_ADC_INJ_RANK_3
4130 * @arg @ref LL_ADC_INJ_RANK_4
4131 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4132 */
4133 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4134 {
4135 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4136
4137 return (uint16_t)(READ_BIT(*preg,
4138 ADC_JDR1_JDATA)
4139 );
4140 }
4141
4142 /**
4143 * @brief Get ADC group injected conversion data, range fit for
4144 * ADC resolution 10 bits.
4145 * @note For devices with feature oversampling: Oversampling
4146 * can increase data width, function for extended range
4147 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4148 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4149 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4150 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4151 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4152 * @param ADCx ADC instance
4153 * @param Rank This parameter can be one of the following values:
4154 * @arg @ref LL_ADC_INJ_RANK_1
4155 * @arg @ref LL_ADC_INJ_RANK_2
4156 * @arg @ref LL_ADC_INJ_RANK_3
4157 * @arg @ref LL_ADC_INJ_RANK_4
4158 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4159 */
4160 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4161 {
4162 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4163
4164 return (uint16_t)(READ_BIT(*preg,
4165 ADC_JDR1_JDATA)
4166 );
4167 }
4168
4169 /**
4170 * @brief Get ADC group injected conversion data, range fit for
4171 * ADC resolution 8 bits.
4172 * @note For devices with feature oversampling: Oversampling
4173 * can increase data width, function for extended range
4174 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4175 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4176 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4177 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4178 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4179 * @param ADCx ADC instance
4180 * @param Rank This parameter can be one of the following values:
4181 * @arg @ref LL_ADC_INJ_RANK_1
4182 * @arg @ref LL_ADC_INJ_RANK_2
4183 * @arg @ref LL_ADC_INJ_RANK_3
4184 * @arg @ref LL_ADC_INJ_RANK_4
4185 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4186 */
4187 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4188 {
4189 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4190
4191 return (uint8_t)(READ_BIT(*preg,
4192 ADC_JDR1_JDATA)
4193 );
4194 }
4195
4196 /**
4197 * @brief Get ADC group injected conversion data, range fit for
4198 * ADC resolution 6 bits.
4199 * @note For devices with feature oversampling: Oversampling
4200 * can increase data width, function for extended range
4201 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4202 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4203 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4204 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4205 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4206 * @param ADCx ADC instance
4207 * @param Rank This parameter can be one of the following values:
4208 * @arg @ref LL_ADC_INJ_RANK_1
4209 * @arg @ref LL_ADC_INJ_RANK_2
4210 * @arg @ref LL_ADC_INJ_RANK_3
4211 * @arg @ref LL_ADC_INJ_RANK_4
4212 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4213 */
4214 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4215 {
4216 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4217
4218 return (uint8_t)(READ_BIT(*preg,
4219 ADC_JDR1_JDATA)
4220 );
4221 }
4222
4223 /**
4224 * @}
4225 */
4226
4227 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4228 * @{
4229 */
4230
4231 /**
4232 * @brief Get flag ADC group regular end of unitary conversion
4233 * or end of sequence conversions, depending on
4234 * ADC configuration.
4235 * @note To configure flag of end of conversion,
4236 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4237 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4238 * @param ADCx ADC instance
4239 * @retval State of bit (1 or 0).
4240 */
4241 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4242 {
4243 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4244 }
4245
4246 /**
4247 * @brief Get flag ADC group regular overrun.
4248 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4249 * @param ADCx ADC instance
4250 * @retval State of bit (1 or 0).
4251 */
4252 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4253 {
4254 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4255 }
4256
4257
4258 /**
4259 * @brief Get flag ADC group injected end of sequence conversions.
4260 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4261 * @param ADCx ADC instance
4262 * @retval State of bit (1 or 0).
4263 */
4264 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4265 {
4266 /* Note: on this STM32 serie, there is no flag ADC group injected */
4267 /* end of unitary conversion. */
4268 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4269 /* in other STM32 families). */
4270 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4271 }
4272
4273 /**
4274 * @brief Get flag ADC analog watchdog 1 flag
4275 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4276 * @param ADCx ADC instance
4277 * @retval State of bit (1 or 0).
4278 */
4279 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4280 {
4281 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4282 }
4283
4284 /**
4285 * @brief Clear flag ADC group regular end of unitary conversion
4286 * or end of sequence conversions, depending on
4287 * ADC configuration.
4288 * @note To configure flag of end of conversion,
4289 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4290 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4291 * @param ADCx ADC instance
4292 * @retval None
4293 */
4294 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4295 {
4296 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4297 }
4298
4299 /**
4300 * @brief Clear flag ADC group regular overrun.
4301 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4302 * @param ADCx ADC instance
4303 * @retval None
4304 */
4305 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4306 {
4307 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4308 }
4309
4310
4311 /**
4312 * @brief Clear flag ADC group injected end of sequence conversions.
4313 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4314 * @param ADCx ADC instance
4315 * @retval None
4316 */
4317 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4318 {
4319 /* Note: on this STM32 serie, there is no flag ADC group injected */
4320 /* end of unitary conversion. */
4321 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4322 /* in other STM32 families). */
4323 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4324 }
4325
4326 /**
4327 * @brief Clear flag ADC analog watchdog 1.
4328 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4329 * @param ADCx ADC instance
4330 * @retval None
4331 */
4332 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4333 {
4334 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4335 }
4336
4337 /**
4338 * @brief Get flag multimode ADC group regular end of unitary conversion
4339 * or end of sequence conversions, depending on
4340 * ADC configuration, of the ADC master.
4341 * @note To configure flag of end of conversion,
4342 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4343 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4344 * @param ADCxy_COMMON ADC common instance
4345 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4346 * @retval State of bit (1 or 0).
4347 */
4348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4349 {
4350 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4351 }
4352
4353 /**
4354 * @brief Get flag multimode ADC group regular end of unitary conversion
4355 * or end of sequence conversions, depending on
4356 * ADC configuration, of the ADC slave 1.
4357 * @note To configure flag of end of conversion,
4358 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4359 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4360 * @param ADCxy_COMMON ADC common instance
4361 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4362 * @retval State of bit (1 or 0).
4363 */
4364 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4365 {
4366 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4367 }
4368
4369 /**
4370 * @brief Get flag multimode ADC group regular end of unitary conversion
4371 * or end of sequence conversions, depending on
4372 * ADC configuration, of the ADC slave 2.
4373 * @note To configure flag of end of conversion,
4374 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4375 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4376 * @param ADCxy_COMMON ADC common instance
4377 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4378 * @retval State of bit (1 or 0).
4379 */
4380 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4381 {
4382 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4383 }
4384 /**
4385 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4386 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4387 * @param ADCxy_COMMON ADC common instance
4388 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4389 * @retval State of bit (1 or 0).
4390 */
4391 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4392 {
4393 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4394 }
4395
4396 /**
4397 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4398 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4399 * @param ADCxy_COMMON ADC common instance
4400 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4401 * @retval State of bit (1 or 0).
4402 */
4403 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4404 {
4405 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4406 }
4407
4408 /**
4409 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4410 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4411 * @param ADCxy_COMMON ADC common instance
4412 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4413 * @retval State of bit (1 or 0).
4414 */
4415 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4416 {
4417 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4418 }
4419
4420
4421 /**
4422 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4423 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4424 * @param ADCxy_COMMON ADC common instance
4425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4426 * @retval State of bit (1 or 0).
4427 */
4428 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4429 {
4430 /* Note: on this STM32 serie, there is no flag ADC group injected */
4431 /* end of unitary conversion. */
4432 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4433 /* in other STM32 families). */
4434 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4435 }
4436
4437 /**
4438 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4439 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4440 * @param ADCxy_COMMON ADC common instance
4441 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4442 * @retval State of bit (1 or 0).
4443 */
4444 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4445 {
4446 /* Note: on this STM32 serie, there is no flag ADC group injected */
4447 /* end of unitary conversion. */
4448 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4449 /* in other STM32 families). */
4450 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4451 }
4452
4453 /**
4454 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4455 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4456 * @param ADCxy_COMMON ADC common instance
4457 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4458 * @retval State of bit (1 or 0).
4459 */
4460 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4461 {
4462 /* Note: on this STM32 serie, there is no flag ADC group injected */
4463 /* end of unitary conversion. */
4464 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4465 /* in other STM32 families). */
4466 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4467 }
4468
4469 /**
4470 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4471 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4472 * @param ADCxy_COMMON ADC common instance
4473 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4474 * @retval State of bit (1 or 0).
4475 */
4476 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4477 {
4478 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4479 }
4480
4481 /**
4482 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4483 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4484 * @param ADCxy_COMMON ADC common instance
4485 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4486 * @retval State of bit (1 or 0).
4487 */
4488 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4489 {
4490 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4491 }
4492
4493 /**
4494 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4495 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4496 * @param ADCxy_COMMON ADC common instance
4497 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4498 * @retval State of bit (1 or 0).
4499 */
4500 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4501 {
4502 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4503 }
4504
4505
4506 /**
4507 * @}
4508 */
4509
4510 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4511 * @{
4512 */
4513
4514 /**
4515 * @brief Enable interruption ADC group regular end of unitary conversion
4516 * or end of sequence conversions, depending on
4517 * ADC configuration.
4518 * @note To configure flag of end of conversion,
4519 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4520 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4521 * @param ADCx ADC instance
4522 * @retval None
4523 */
4524 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4525 {
4526 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4527 }
4528
4529 /**
4530 * @brief Enable ADC group regular interruption overrun.
4531 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4532 * @param ADCx ADC instance
4533 * @retval None
4534 */
4535 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4536 {
4537 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4538 }
4539
4540
4541 /**
4542 * @brief Enable interruption ADC group injected end of sequence conversions.
4543 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4544 * @param ADCx ADC instance
4545 * @retval None
4546 */
4547 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4548 {
4549 /* Note: on this STM32 serie, there is no flag ADC group injected */
4550 /* end of unitary conversion. */
4551 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4552 /* in other STM32 families). */
4553 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4554 }
4555
4556 /**
4557 * @brief Enable interruption ADC analog watchdog 1.
4558 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4559 * @param ADCx ADC instance
4560 * @retval None
4561 */
4562 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4563 {
4564 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4565 }
4566
4567 /**
4568 * @brief Disable interruption ADC group regular end of unitary conversion
4569 * or end of sequence conversions, depending on
4570 * ADC configuration.
4571 * @note To configure flag of end of conversion,
4572 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4573 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4574 * @param ADCx ADC instance
4575 * @retval None
4576 */
4577 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4578 {
4579 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4580 }
4581
4582 /**
4583 * @brief Disable interruption ADC group regular overrun.
4584 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4585 * @param ADCx ADC instance
4586 * @retval None
4587 */
4588 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4589 {
4590 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4591 }
4592
4593
4594 /**
4595 * @brief Disable interruption ADC group injected end of sequence conversions.
4596 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4597 * @param ADCx ADC instance
4598 * @retval None
4599 */
4600 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4601 {
4602 /* Note: on this STM32 serie, there is no flag ADC group injected */
4603 /* end of unitary conversion. */
4604 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4605 /* in other STM32 families). */
4606 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4607 }
4608
4609 /**
4610 * @brief Disable interruption ADC analog watchdog 1.
4611 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4612 * @param ADCx ADC instance
4613 * @retval None
4614 */
4615 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4616 {
4617 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4618 }
4619
4620 /**
4621 * @brief Get state of interruption ADC group regular end of unitary conversion
4622 * or end of sequence conversions, depending on
4623 * ADC configuration.
4624 * @note To configure flag of end of conversion,
4625 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4626 * (0: interrupt disabled, 1: interrupt enabled)
4627 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4628 * @param ADCx ADC instance
4629 * @retval State of bit (1 or 0).
4630 */
4631 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4632 {
4633 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4634 }
4635
4636 /**
4637 * @brief Get state of interruption ADC group regular overrun
4638 * (0: interrupt disabled, 1: interrupt enabled).
4639 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4640 * @param ADCx ADC instance
4641 * @retval State of bit (1 or 0).
4642 */
4643 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4644 {
4645 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4646 }
4647
4648
4649 /**
4650 * @brief Get state of interruption ADC group injected end of sequence conversions
4651 * (0: interrupt disabled, 1: interrupt enabled).
4652 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4653 * @param ADCx ADC instance
4654 * @retval State of bit (1 or 0).
4655 */
4656 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4657 {
4658 /* Note: on this STM32 serie, there is no flag ADC group injected */
4659 /* end of unitary conversion. */
4660 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4661 /* in other STM32 families). */
4662 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4663 }
4664
4665 /**
4666 * @brief Get state of interruption ADC analog watchdog 1
4667 * (0: interrupt disabled, 1: interrupt enabled).
4668 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4669 * @param ADCx ADC instance
4670 * @retval State of bit (1 or 0).
4671 */
4672 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4673 {
4674 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4675 }
4676
4677 /**
4678 * @}
4679 */
4680
4681 #if defined(USE_FULL_LL_DRIVER)
4682 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4683 * @{
4684 */
4685
4686 /* Initialization of some features of ADC common parameters and multimode */
4687 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4688 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4689 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4690
4691 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4692 /* (availability of ADC group injected depends on STM32 families) */
4693 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4694
4695 /* Initialization of some features of ADC instance */
4696 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4697 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4698
4699 /* Initialization of some features of ADC instance and ADC group regular */
4700 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4701 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4702
4703 /* Initialization of some features of ADC instance and ADC group injected */
4704 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4705 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4706
4707 /**
4708 * @}
4709 */
4710 #endif /* USE_FULL_LL_DRIVER */
4711
4712 /**
4713 * @}
4714 */
4715
4716 /**
4717 * @}
4718 */
4719
4720 #endif /* ADC1 || ADC2 || ADC3 */
4721
4722 /**
4723 * @}
4724 */
4725
4726 #ifdef __cplusplus
4727 }
4728 #endif
4729
4730 #endif /* __STM32F7xx_LL_ADC_H */
4731
4732 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/