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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_dac.h
blob1ed5031ce518cd40948ce123c979efd13277fdf4
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_DAC_H
22 #define __STM32F7xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined(DAC)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into register CR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
60 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
61 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
62
63 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
64 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
65 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
66 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
67 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
69 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
70 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
71 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
72 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
73
74 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
75 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
76 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
77
78 /* DAC registers bits positions */
79 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
80 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
81 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
82
83 /* Miscellaneous data */
84 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
85
86 /**
87 * @}
88 */
89
90
91 /* Private macros ------------------------------------------------------------*/
92 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
93 * @{
94 */
95
96 /**
97 * @brief Driver macro reserved for internal use: isolate bits with the
98 * selected mask and shift them to the register LSB
99 * (shift mask on register position bit 0).
100 * @param __BITS__ Bits in register 32 bits
101 * @param __MASK__ Mask in register 32 bits
102 * @retval Bits in register 32 bits
103 */
104 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
105 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
106
107 /**
108 * @brief Driver macro reserved for internal use: set a pointer to
109 * a register from a register basis from which an offset
110 * is applied.
111 * @param __REG__ Register basis from which the offset is applied.
112 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
113 * @retval Pointer to register address
114 */
115 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
116 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
117
118 /**
119 * @}
120 */
121
122
123 /* Exported types ------------------------------------------------------------*/
124 #if defined(USE_FULL_LL_DRIVER)
125 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
126 * @{
127 */
128
129 /**
130 * @brief Structure definition of some features of DAC instance.
131 */
132 typedef struct
133 {
134 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
135 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
136
137 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
138
139 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
140 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
141
142 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
143
144 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
145 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
146 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
147 @note If waveform automatic generation mode is disabled, this parameter is discarded.
148
149 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
150
151 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
152 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
153
154 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
155
156 } LL_DAC_InitTypeDef;
157
158 /**
159 * @}
160 */
161 #endif /* USE_FULL_LL_DRIVER */
162
163 /* Exported constants --------------------------------------------------------*/
164 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
165 * @{
166 */
167
168 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
169 * @brief Flags defines which can be used with LL_DAC_ReadReg function
170 * @{
171 */
172 /* DAC channel 1 flags */
173 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
174
175 /* DAC channel 2 flags */
176 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
177 /**
178 * @}
179 */
180
181 /** @defgroup DAC_LL_EC_IT DAC interruptions
182 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
183 * @{
184 */
185 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
186 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
187 /**
188 * @}
189 */
190
191 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
192 * @{
193 */
194 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
195 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
196 /**
197 * @}
198 */
199
200 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
201 * @{
202 */
203 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
204 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
205 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
206 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
207 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
208 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
209 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
210 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
211 /**
212 * @}
213 */
214
215 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
216 * @{
217 */
218 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
219 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
220 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
221 /**
222 * @}
223 */
224
225 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
226 * @{
227 */
228 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
229 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
230 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
231 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
232 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
233 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
234 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
235 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
236 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
237 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
238 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
239 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
240 /**
241 * @}
242 */
243
244 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
245 * @{
246 */
247 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
248 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
249 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
250 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
251 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
252 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
253 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
254 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
255 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
256 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
257 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
258 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
259 /**
260 * @}
261 */
262
263 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
264 * @{
265 */
266 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
267 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
268 /**
269 * @}
270 */
271
272
273 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
274 * @{
275 */
276 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
277 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
278 /**
279 * @}
280 */
281
282 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
283 * @{
284 */
285 /* List of DAC registers intended to be used (most commonly) with */
286 /* DMA transfer. */
287 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
288 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
289 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
290 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
291 /**
292 * @}
293 */
294
295 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
296 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
297 * not timeout values.
298 * For details on delays values, refer to descriptions in source code
299 * above each literal definition.
300 * @{
301 */
302
303 /* Delay for DAC channel voltage settling time from DAC channel startup */
304 /* (transition from disable to enable). */
305 /* Note: DAC channel startup time depends on board application environment: */
306 /* impedance connected to DAC channel output. */
307 /* The delay below is specified under conditions: */
308 /* - voltage maximum transition (lowest to highest value) */
309 /* - until voltage reaches final value +-1LSB */
310 /* - DAC channel output buffer enabled */
311 /* - load impedance of 5kOhm (min), 50pF (max) */
312 /* Literal set to maximum value (refer to device datasheet, */
313 /* parameter "tWAKEUP"). */
314 /* Unit: us */
315 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
316
317 /* Delay for DAC channel voltage settling time. */
318 /* Note: DAC channel startup time depends on board application environment: */
319 /* impedance connected to DAC channel output. */
320 /* The delay below is specified under conditions: */
321 /* - voltage maximum transition (lowest to highest value) */
322 /* - until voltage reaches final value +-1LSB */
323 /* - DAC channel output buffer enabled */
324 /* - load impedance of 5kOhm min, 50pF max */
325 /* Literal set to maximum value (refer to device datasheet, */
326 /* parameter "tSETTLING"). */
327 /* Unit: us */
328 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /* Exported macro ------------------------------------------------------------*/
338 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
339 * @{
340 */
341
342 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
343 * @{
344 */
345
346 /**
347 * @brief Write a value in DAC register
348 * @param __INSTANCE__ DAC Instance
349 * @param __REG__ Register to be written
350 * @param __VALUE__ Value to be written in the register
351 * @retval None
352 */
353 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
354
355 /**
356 * @brief Read a value in DAC register
357 * @param __INSTANCE__ DAC Instance
358 * @param __REG__ Register to be read
359 * @retval Register value
360 */
361 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
362
363 /**
364 * @}
365 */
366
367 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
368 * @{
369 */
370
371 /**
372 * @brief Helper macro to get DAC channel number in decimal format
373 * from literals LL_DAC_CHANNEL_x.
374 * Example:
375 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
376 * will return decimal number "1".
377 * @note The input can be a value from functions where a channel
378 * number is returned.
379 * @param __CHANNEL__ This parameter can be one of the following values:
380 * @arg @ref LL_DAC_CHANNEL_1
381 * @arg @ref LL_DAC_CHANNEL_2
382 * @retval 1...2
383 */
384 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
385 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
386
387 /**
388 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
389 * from number in decimal format.
390 * Example:
391 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
392 * will return a data equivalent to "LL_DAC_CHANNEL_1".
393 * @note If the input parameter does not correspond to a DAC channel,
394 * this macro returns value '0'.
395 * @param __DECIMAL_NB__ 1...2
396 * @retval Returned value can be one of the following values:
397 * @arg @ref LL_DAC_CHANNEL_1
398 * @arg @ref LL_DAC_CHANNEL_2
399 */
400 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
401 (((__DECIMAL_NB__) == 1U) \
402 ? ( \
403 LL_DAC_CHANNEL_1 \
404 ) \
405 : \
406 (((__DECIMAL_NB__) == 2U) \
407 ? ( \
408 LL_DAC_CHANNEL_2 \
409 ) \
410 : \
411 ( \
412 0 \
413 ) \
414 ) \
415 )
416
417 /**
418 * @brief Helper macro to define the DAC conversion data full-scale digital
419 * value corresponding to the selected DAC resolution.
420 * @note DAC conversion data full-scale corresponds to voltage range
421 * determined by analog voltage references Vref+ and Vref-
422 * (refer to reference manual).
423 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
424 * @arg @ref LL_DAC_RESOLUTION_12B
425 * @arg @ref LL_DAC_RESOLUTION_8B
426 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
427 */
428 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
429 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
430
431 /**
432 * @brief Helper macro to calculate the DAC conversion data (unit: digital
433 * value) corresponding to a voltage (unit: mVolt).
434 * @note This helper macro is intended to provide input data in voltage
435 * rather than digital value,
436 * to be used with LL DAC functions such as
437 * @ref LL_DAC_ConvertData12RightAligned().
438 * @note Analog reference voltage (Vref+) must be either known from
439 * user board environment or can be calculated using ADC measurement
440 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
441 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
442 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
443 * (unit: mVolt).
444 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
445 * @arg @ref LL_DAC_RESOLUTION_12B
446 * @arg @ref LL_DAC_RESOLUTION_8B
447 * @retval DAC conversion data (unit: digital value)
448 */
449 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
450 __DAC_VOLTAGE__,\
451 __DAC_RESOLUTION__) \
452 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
453 / (__VREFANALOG_VOLTAGE__) \
454 )
455
456 /**
457 * @}
458 */
459
460 /**
461 * @}
462 */
463
464
465 /* Exported functions --------------------------------------------------------*/
466 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
467 * @{
468 */
469 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
470 * @{
471 */
472
473 /**
474 * @brief Set the conversion trigger source for the selected DAC channel.
475 * @note For conversion trigger source to be effective, DAC trigger
476 * must be enabled using function @ref LL_DAC_EnableTrigger().
477 * @note To set conversion trigger source, DAC channel must be disabled.
478 * Otherwise, the setting is discarded.
479 * @note Availability of parameters of trigger sources from timer
480 * depends on timers availability on the selected device.
481 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
482 * CR TSEL2 LL_DAC_SetTriggerSource
483 * @param DACx DAC instance
484 * @param DAC_Channel This parameter can be one of the following values:
485 * @arg @ref LL_DAC_CHANNEL_1
486 * @arg @ref LL_DAC_CHANNEL_2
487 * @param TriggerSource This parameter can be one of the following values:
488 * @arg @ref LL_DAC_TRIG_SOFTWARE
489 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
490 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
491 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
492 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
493 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
494 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
495 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
496 * @retval None
497 */
498 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
499 {
500 MODIFY_REG(DACx->CR,
501 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
502 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
503 }
504
505 /**
506 * @brief Get the conversion trigger source for the selected DAC channel.
507 * @note For conversion trigger source to be effective, DAC trigger
508 * must be enabled using function @ref LL_DAC_EnableTrigger().
509 * @note Availability of parameters of trigger sources from timer
510 * depends on timers availability on the selected device.
511 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
512 * CR TSEL2 LL_DAC_GetTriggerSource
513 * @param DACx DAC instance
514 * @param DAC_Channel This parameter can be one of the following values:
515 * @arg @ref LL_DAC_CHANNEL_1
516 * @arg @ref LL_DAC_CHANNEL_2
517 * @retval Returned value can be one of the following values:
518 * @arg @ref LL_DAC_TRIG_SOFTWARE
519 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
520 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
521 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
522 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
523 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
524 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
525 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
526 */
527 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
528 {
529 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
530 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
531 );
532 }
533
534 /**
535 * @brief Set the waveform automatic generation mode
536 * for the selected DAC channel.
537 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
538 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
539 * @param DACx DAC instance
540 * @param DAC_Channel This parameter can be one of the following values:
541 * @arg @ref LL_DAC_CHANNEL_1
542 * @arg @ref LL_DAC_CHANNEL_2
543 * @param WaveAutoGeneration This parameter can be one of the following values:
544 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
545 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
546 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
547 * @retval None
548 */
549 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
550 {
551 MODIFY_REG(DACx->CR,
552 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
553 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
554 }
555
556 /**
557 * @brief Get the waveform automatic generation mode
558 * for the selected DAC channel.
559 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
560 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
561 * @param DACx DAC instance
562 * @param DAC_Channel This parameter can be one of the following values:
563 * @arg @ref LL_DAC_CHANNEL_1
564 * @arg @ref LL_DAC_CHANNEL_2
565 * @retval Returned value can be one of the following values:
566 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
567 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
568 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
569 */
570 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
571 {
572 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
573 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
574 );
575 }
576
577 /**
578 * @brief Set the noise waveform generation for the selected DAC channel:
579 * Noise mode and parameters LFSR (linear feedback shift register).
580 * @note For wave generation to be effective, DAC channel
581 * wave generation mode must be enabled using
582 * function @ref LL_DAC_SetWaveAutoGeneration().
583 * @note This setting can be set when the selected DAC channel is disabled
584 * (otherwise, the setting operation is ignored).
585 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
586 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
587 * @param DACx DAC instance
588 * @param DAC_Channel This parameter can be one of the following values:
589 * @arg @ref LL_DAC_CHANNEL_1
590 * @arg @ref LL_DAC_CHANNEL_2
591 * @param NoiseLFSRMask This parameter can be one of the following values:
592 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
593 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
594 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
595 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
596 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
597 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
598 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
599 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
600 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
601 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
602 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
603 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
604 * @retval None
605 */
606 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
607 {
608 MODIFY_REG(DACx->CR,
609 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
610 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
611 }
612
613 /**
614 * @brief Set the noise waveform generation for the selected DAC channel:
615 * Noise mode and parameters LFSR (linear feedback shift register).
616 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
617 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
618 * @param DACx DAC instance
619 * @param DAC_Channel This parameter can be one of the following values:
620 * @arg @ref LL_DAC_CHANNEL_1
621 * @arg @ref LL_DAC_CHANNEL_2
622 * @retval Returned value can be one of the following values:
623 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
625 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
626 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
627 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
628 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
629 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
630 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
631 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
632 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
633 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
634 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
635 */
636 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
637 {
638 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
639 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
640 );
641 }
642
643 /**
644 * @brief Set the triangle waveform generation for the selected DAC channel:
645 * triangle mode and amplitude.
646 * @note For wave generation to be effective, DAC channel
647 * wave generation mode must be enabled using
648 * function @ref LL_DAC_SetWaveAutoGeneration().
649 * @note This setting can be set when the selected DAC channel is disabled
650 * (otherwise, the setting operation is ignored).
651 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
652 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
653 * @param DACx DAC instance
654 * @param DAC_Channel This parameter can be one of the following values:
655 * @arg @ref LL_DAC_CHANNEL_1
656 * @arg @ref LL_DAC_CHANNEL_2
657 * @param TriangleAmplitude This parameter can be one of the following values:
658 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
659 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
660 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
661 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
662 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
663 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
664 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
665 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
666 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
667 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
668 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
669 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
670 * @retval None
671 */
672 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
673 {
674 MODIFY_REG(DACx->CR,
675 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
676 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
677 }
678
679 /**
680 * @brief Set the triangle waveform generation for the selected DAC channel:
681 * triangle mode and amplitude.
682 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
683 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
684 * @param DACx DAC instance
685 * @param DAC_Channel This parameter can be one of the following values:
686 * @arg @ref LL_DAC_CHANNEL_1
687 * @arg @ref LL_DAC_CHANNEL_2
688 * @retval Returned value can be one of the following values:
689 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
691 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
692 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
693 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
694 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
695 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
696 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
697 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
698 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
699 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
700 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
701 */
702 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
703 {
704 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
705 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
706 );
707 }
708
709 /**
710 * @brief Set the output buffer for the selected DAC channel.
711 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
712 * CR BOFF2 LL_DAC_SetOutputBuffer
713 * @param DACx DAC instance
714 * @param DAC_Channel This parameter can be one of the following values:
715 * @arg @ref LL_DAC_CHANNEL_1
716 * @arg @ref LL_DAC_CHANNEL_2
717 * @param OutputBuffer This parameter can be one of the following values:
718 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
719 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
720 * @retval None
721 */
722 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
723 {
724 MODIFY_REG(DACx->CR,
725 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
726 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
727 }
728
729 /**
730 * @brief Get the output buffer state for the selected DAC channel.
731 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
732 * CR BOFF2 LL_DAC_GetOutputBuffer
733 * @param DACx DAC instance
734 * @param DAC_Channel This parameter can be one of the following values:
735 * @arg @ref LL_DAC_CHANNEL_1
736 * @arg @ref LL_DAC_CHANNEL_2
737 * @retval Returned value can be one of the following values:
738 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
739 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
740 */
741 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
742 {
743 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
744 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
745 );
746 }
747
748 /**
749 * @}
750 */
751
752 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
753 * @{
754 */
755
756 /**
757 * @brief Enable DAC DMA transfer request of the selected channel.
758 * @note To configure DMA source address (peripheral address),
759 * use function @ref LL_DAC_DMA_GetRegAddr().
760 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
761 * CR DMAEN2 LL_DAC_EnableDMAReq
762 * @param DACx DAC instance
763 * @param DAC_Channel This parameter can be one of the following values:
764 * @arg @ref LL_DAC_CHANNEL_1
765 * @arg @ref LL_DAC_CHANNEL_2
766 * @retval None
767 */
768 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
769 {
770 SET_BIT(DACx->CR,
771 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
772 }
773
774 /**
775 * @brief Disable DAC DMA transfer request of the selected channel.
776 * @note To configure DMA source address (peripheral address),
777 * use function @ref LL_DAC_DMA_GetRegAddr().
778 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
779 * CR DMAEN2 LL_DAC_DisableDMAReq
780 * @param DACx DAC instance
781 * @param DAC_Channel This parameter can be one of the following values:
782 * @arg @ref LL_DAC_CHANNEL_1
783 * @arg @ref LL_DAC_CHANNEL_2
784 * @retval None
785 */
786 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
787 {
788 CLEAR_BIT(DACx->CR,
789 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
790 }
791
792 /**
793 * @brief Get DAC DMA transfer request state of the selected channel.
794 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
795 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
796 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
797 * @param DACx DAC instance
798 * @param DAC_Channel This parameter can be one of the following values:
799 * @arg @ref LL_DAC_CHANNEL_1
800 * @arg @ref LL_DAC_CHANNEL_2
801 * @retval State of bit (1 or 0).
802 */
803 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
804 {
805 return (READ_BIT(DACx->CR,
806 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
807 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
808 }
809
810 /**
811 * @brief Function to help to configure DMA transfer to DAC: retrieve the
812 * DAC register address from DAC instance and a list of DAC registers
813 * intended to be used (most commonly) with DMA transfer.
814 * @note These DAC registers are data holding registers:
815 * when DAC conversion is requested, DAC generates a DMA transfer
816 * request to have data available in DAC data holding registers.
817 * @note This macro is intended to be used with LL DMA driver, refer to
818 * function "LL_DMA_ConfigAddresses()".
819 * Example:
820 * LL_DMA_ConfigAddresses(DMA1,
821 * LL_DMA_CHANNEL_1,
822 * (uint32_t)&< array or variable >,
823 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
824 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
825 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
826 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
827 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
828 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
829 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
830 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
831 * @param DACx DAC instance
832 * @param DAC_Channel This parameter can be one of the following values:
833 * @arg @ref LL_DAC_CHANNEL_1
834 * @arg @ref LL_DAC_CHANNEL_2
835 * @param Register This parameter can be one of the following values:
836 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
837 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
838 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
839 * @retval DAC register address
840 */
841 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
842 {
843 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
844 /* DAC channel selected. */
845 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
846 }
847 /**
848 * @}
849 */
850
851 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
852 * @{
853 */
854
855 /**
856 * @brief Enable DAC selected channel.
857 * @rmtoll CR EN1 LL_DAC_Enable\n
858 * CR EN2 LL_DAC_Enable
859 * @note After enable from off state, DAC channel requires a delay
860 * for output voltage to reach accuracy +/- 1 LSB.
861 * Refer to device datasheet, parameter "tWAKEUP".
862 * @param DACx DAC instance
863 * @param DAC_Channel This parameter can be one of the following values:
864 * @arg @ref LL_DAC_CHANNEL_1
865 * @arg @ref LL_DAC_CHANNEL_2
866 * @retval None
867 */
868 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
869 {
870 SET_BIT(DACx->CR,
871 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
872 }
873
874 /**
875 * @brief Disable DAC selected channel.
876 * @rmtoll CR EN1 LL_DAC_Disable\n
877 * CR EN2 LL_DAC_Disable
878 * @param DACx DAC instance
879 * @param DAC_Channel This parameter can be one of the following values:
880 * @arg @ref LL_DAC_CHANNEL_1
881 * @arg @ref LL_DAC_CHANNEL_2
882 * @retval None
883 */
884 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
885 {
886 CLEAR_BIT(DACx->CR,
887 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
888 }
889
890 /**
891 * @brief Get DAC enable state of the selected channel.
892 * (0: DAC channel is disabled, 1: DAC channel is enabled)
893 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
894 * CR EN2 LL_DAC_IsEnabled
895 * @param DACx DAC instance
896 * @param DAC_Channel This parameter can be one of the following values:
897 * @arg @ref LL_DAC_CHANNEL_1
898 * @arg @ref LL_DAC_CHANNEL_2
899 * @retval State of bit (1 or 0).
900 */
901 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
902 {
903 return (READ_BIT(DACx->CR,
904 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
905 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
906 }
907
908 /**
909 * @brief Enable DAC trigger of the selected channel.
910 * @note - If DAC trigger is disabled, DAC conversion is performed
911 * automatically once the data holding register is updated,
912 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
913 * @ref LL_DAC_ConvertData12RightAligned(), ...
914 * - If DAC trigger is enabled, DAC conversion is performed
915 * only when a hardware of software trigger event is occurring.
916 * Select trigger source using
917 * function @ref LL_DAC_SetTriggerSource().
918 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
919 * CR TEN2 LL_DAC_EnableTrigger
920 * @param DACx DAC instance
921 * @param DAC_Channel This parameter can be one of the following values:
922 * @arg @ref LL_DAC_CHANNEL_1
923 * @arg @ref LL_DAC_CHANNEL_2
924 * @retval None
925 */
926 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
927 {
928 SET_BIT(DACx->CR,
929 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
930 }
931
932 /**
933 * @brief Disable DAC trigger of the selected channel.
934 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
935 * CR TEN2 LL_DAC_DisableTrigger
936 * @param DACx DAC instance
937 * @param DAC_Channel This parameter can be one of the following values:
938 * @arg @ref LL_DAC_CHANNEL_1
939 * @arg @ref LL_DAC_CHANNEL_2
940 * @retval None
941 */
942 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
943 {
944 CLEAR_BIT(DACx->CR,
945 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
946 }
947
948 /**
949 * @brief Get DAC trigger state of the selected channel.
950 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
951 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
952 * CR TEN2 LL_DAC_IsTriggerEnabled
953 * @param DACx DAC instance
954 * @param DAC_Channel This parameter can be one of the following values:
955 * @arg @ref LL_DAC_CHANNEL_1
956 * @arg @ref LL_DAC_CHANNEL_2
957 * @retval State of bit (1 or 0).
958 */
959 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
960 {
961 return (READ_BIT(DACx->CR,
962 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
963 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
964 }
965
966 /**
967 * @brief Trig DAC conversion by software for the selected DAC channel.
968 * @note Preliminarily, DAC trigger must be set to software trigger
969 * using function @ref LL_DAC_SetTriggerSource()
970 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
971 * and DAC trigger must be enabled using
972 * function @ref LL_DAC_EnableTrigger().
973 * @note For devices featuring DAC with 2 channels: this function
974 * can perform a SW start of both DAC channels simultaneously.
975 * Two channels can be selected as parameter.
976 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
977 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
978 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
979 * @param DACx DAC instance
980 * @param DAC_Channel This parameter can a combination of the following values:
981 * @arg @ref LL_DAC_CHANNEL_1
982 * @arg @ref LL_DAC_CHANNEL_2
983 * @retval None
984 */
985 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
986 {
987 SET_BIT(DACx->SWTRIGR,
988 (DAC_Channel & DAC_SWTR_CHX_MASK));
989 }
990
991 /**
992 * @brief Set the data to be loaded in the data holding register
993 * in format 12 bits left alignment (LSB aligned on bit 0),
994 * for the selected DAC channel.
995 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
996 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
997 * @param DACx DAC instance
998 * @param DAC_Channel This parameter can be one of the following values:
999 * @arg @ref LL_DAC_CHANNEL_1
1000 * @arg @ref LL_DAC_CHANNEL_2
1001 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1002 * @retval None
1003 */
1004 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1005 {
1006 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1007
1008 MODIFY_REG(*preg,
1009 DAC_DHR12R1_DACC1DHR,
1010 Data);
1011 }
1012
1013 /**
1014 * @brief Set the data to be loaded in the data holding register
1015 * in format 12 bits left alignment (MSB aligned on bit 15),
1016 * for the selected DAC channel.
1017 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1018 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1019 * @param DACx DAC instance
1020 * @param DAC_Channel This parameter can be one of the following values:
1021 * @arg @ref LL_DAC_CHANNEL_1
1022 * @arg @ref LL_DAC_CHANNEL_2
1023 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1024 * @retval None
1025 */
1026 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1027 {
1028 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1029
1030 MODIFY_REG(*preg,
1031 DAC_DHR12L1_DACC1DHR,
1032 Data);
1033 }
1034
1035 /**
1036 * @brief Set the data to be loaded in the data holding register
1037 * in format 8 bits left alignment (LSB aligned on bit 0),
1038 * for the selected DAC channel.
1039 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1040 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1041 * @param DACx DAC instance
1042 * @param DAC_Channel This parameter can be one of the following values:
1043 * @arg @ref LL_DAC_CHANNEL_1
1044 * @arg @ref LL_DAC_CHANNEL_2
1045 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1046 * @retval None
1047 */
1048 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1049 {
1050 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1051
1052 MODIFY_REG(*preg,
1053 DAC_DHR8R1_DACC1DHR,
1054 Data);
1055 }
1056
1057 /**
1058 * @brief Set the data to be loaded in the data holding register
1059 * in format 12 bits left alignment (LSB aligned on bit 0),
1060 * for both DAC channels.
1061 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1062 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1063 * @param DACx DAC instance
1064 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1065 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1066 * @retval None
1067 */
1068 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1069 {
1070 MODIFY_REG(DACx->DHR12RD,
1071 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1072 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1073 }
1074
1075 /**
1076 * @brief Set the data to be loaded in the data holding register
1077 * in format 12 bits left alignment (MSB aligned on bit 15),
1078 * for both DAC channels.
1079 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1080 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1081 * @param DACx DAC instance
1082 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1083 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1084 * @retval None
1085 */
1086 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1087 {
1088 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1089 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1090 /* the 4 LSB must be taken into account for the shift value. */
1091 MODIFY_REG(DACx->DHR12LD,
1092 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1093 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1094 }
1095
1096 /**
1097 * @brief Set the data to be loaded in the data holding register
1098 * in format 8 bits left alignment (LSB aligned on bit 0),
1099 * for both DAC channels.
1100 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1101 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1102 * @param DACx DAC instance
1103 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1104 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1105 * @retval None
1106 */
1107 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1108 {
1109 MODIFY_REG(DACx->DHR8RD,
1110 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1111 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1112 }
1113
1114 /**
1115 * @brief Retrieve output data currently generated for the selected DAC channel.
1116 * @note Whatever alignment and resolution settings
1117 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1118 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1119 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1120 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1121 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1122 * @param DACx DAC instance
1123 * @param DAC_Channel This parameter can be one of the following values:
1124 * @arg @ref LL_DAC_CHANNEL_1
1125 * @arg @ref LL_DAC_CHANNEL_2
1126 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1127 */
1128 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1129 {
1130 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1131
1132 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1133 }
1134
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1140 * @{
1141 */
1142 /**
1143 * @brief Get DAC underrun flag for DAC channel 1
1144 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1145 * @param DACx DAC instance
1146 * @retval State of bit (1 or 0).
1147 */
1148 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1149 {
1150 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1151 }
1152
1153 /**
1154 * @brief Get DAC underrun flag for DAC channel 2
1155 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1156 * @param DACx DAC instance
1157 * @retval State of bit (1 or 0).
1158 */
1159 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1160 {
1161 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1162 }
1163
1164 /**
1165 * @brief Clear DAC underrun flag for DAC channel 1
1166 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1167 * @param DACx DAC instance
1168 * @retval None
1169 */
1170 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1171 {
1172 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1173 }
1174
1175 /**
1176 * @brief Clear DAC underrun flag for DAC channel 2
1177 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1178 * @param DACx DAC instance
1179 * @retval None
1180 */
1181 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1182 {
1183 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1184 }
1185
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup DAC_LL_EF_IT_Management IT management
1191 * @{
1192 */
1193
1194 /**
1195 * @brief Enable DMA underrun interrupt for DAC channel 1
1196 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1197 * @param DACx DAC instance
1198 * @retval None
1199 */
1200 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1201 {
1202 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1203 }
1204
1205 /**
1206 * @brief Enable DMA underrun interrupt for DAC channel 2
1207 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1208 * @param DACx DAC instance
1209 * @retval None
1210 */
1211 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1212 {
1213 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1214 }
1215
1216 /**
1217 * @brief Disable DMA underrun interrupt for DAC channel 1
1218 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1219 * @param DACx DAC instance
1220 * @retval None
1221 */
1222 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1223 {
1224 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1225 }
1226
1227 /**
1228 * @brief Disable DMA underrun interrupt for DAC channel 2
1229 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1230 * @param DACx DAC instance
1231 * @retval None
1232 */
1233 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1234 {
1235 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1236 }
1237
1238 /**
1239 * @brief Get DMA underrun interrupt for DAC channel 1
1240 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1241 * @param DACx DAC instance
1242 * @retval State of bit (1 or 0).
1243 */
1244 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1245 {
1246 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1247 }
1248
1249 /**
1250 * @brief Get DMA underrun interrupt for DAC channel 2
1251 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1252 * @param DACx DAC instance
1253 * @retval State of bit (1 or 0).
1254 */
1255 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1256 {
1257 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1258 }
1259
1260 /**
1261 * @}
1262 */
1263
1264 #if defined(USE_FULL_LL_DRIVER)
1265 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1266 * @{
1267 */
1268
1269 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1270 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1271 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1272
1273 /**
1274 * @}
1275 */
1276 #endif /* USE_FULL_LL_DRIVER */
1277
1278 /**
1279 * @}
1280 */
1281
1282 /**
1283 * @}
1284 */
1285
1286 #endif /* DAC */
1287
1288 /**
1289 * @}
1290 */
1291
1292 #ifdef __cplusplus
1293 }
1294 #endif
1295
1296 #endif /* __STM32F7xx_LL_DAC_H */
1297
1298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/