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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_dma.h
blob37d48b50869e3a876b79609728ba1a73df4b77d2
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_DMA_H
22 #define __STM32F7xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
47 static const uint8_t STREAM_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
57 };
58
59 /**
60 * @}
61 */
62
63 /* Private constants ---------------------------------------------------------*/
64 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
65 * @{
66 */
67 #if defined(DMA_SxCR_CHSEL_3)
68 #define DMA_CHANNEL_SELECTION_8_15
69 #endif /* DMA_SxCR_CHSEL_3 */
70 /**
71 * @}
72 */
73
74
75 /* Private macros ------------------------------------------------------------*/
76 /* Exported types ------------------------------------------------------------*/
77 #if defined(USE_FULL_LL_DRIVER)
78 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
79 * @{
80 */
81 typedef struct
82 {
83 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
84 or as Source base address in case of memory to memory transfer direction.
85
86 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
87
88 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
89 or as Destination base address in case of memory to memory transfer direction.
90
91 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
92
93 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
94 from memory to memory or from peripheral to memory.
95 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
96
97 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
98
99 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
100 This parameter can be a value of @ref DMA_LL_EC_MODE
101 @note The circular buffer mode cannot be used if the memory to memory
102 data transfer direction is configured on the selected Stream
103
104 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
105
106 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
107 is incremented or not.
108 This parameter can be a value of @ref DMA_LL_EC_PERIPH
109
110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
111
112 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
113 is incremented or not.
114 This parameter can be a value of @ref DMA_LL_EC_MEMORY
115
116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
117
118 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
119 in case of memory to memory transfer direction.
120 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
121
122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
123
124 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
125 in case of memory to memory transfer direction.
126 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
129
130 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
131 The data unit is equal to the source buffer configuration set in PeripheralSize
132 or MemorySize parameters depending in the transfer direction.
133 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
136
137 uint32_t Channel; /*!< Specifies the peripheral channel.
138 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
141
142 uint32_t Priority; /*!< Specifies the channel priority level.
143 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
144
145 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
146
147 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
148 This parameter can be a value of @ref DMA_LL_FIFOMODE
149 @note The Direct mode (FIFO mode disabled) cannot be used if the
150 memory-to-memory data transfer is configured on the selected stream
151
152 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
153
154 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
155 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
156
157 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
158
159 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
160 It specifies the amount of data to be transferred in a single non interruptible
161 transaction.
162 This parameter can be a value of @ref DMA_LL_EC_MBURST
163 @note The burst mode is possible only if the address Increment mode is enabled.
164
165 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
166
167 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
168 It specifies the amount of data to be transferred in a single non interruptible
169 transaction.
170 This parameter can be a value of @ref DMA_LL_EC_PBURST
171 @note The burst mode is possible only if the address Increment mode is enabled.
172
173 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
174
175 } LL_DMA_InitTypeDef;
176 /**
177 * @}
178 */
179 #endif /*USE_FULL_LL_DRIVER*/
180 /* Exported constants --------------------------------------------------------*/
181 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
182 * @{
183 */
184
185 /** @defgroup DMA_LL_EC_STREAM STREAM
186 * @{
187 */
188 #define LL_DMA_STREAM_0 0x00000000U
189 #define LL_DMA_STREAM_1 0x00000001U
190 #define LL_DMA_STREAM_2 0x00000002U
191 #define LL_DMA_STREAM_3 0x00000003U
192 #define LL_DMA_STREAM_4 0x00000004U
193 #define LL_DMA_STREAM_5 0x00000005U
194 #define LL_DMA_STREAM_6 0x00000006U
195 #define LL_DMA_STREAM_7 0x00000007U
196 #define LL_DMA_STREAM_ALL 0xFFFF0000U
197 /**
198 * @}
199 */
200
201 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
202 * @{
203 */
204 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
205 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
206 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
207 /**
208 * @}
209 */
210
211 /** @defgroup DMA_LL_EC_MODE MODE
212 * @{
213 */
214 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
215 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
216 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
217 /**
218 * @}
219 */
220
221 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
222 * @{
223 */
224 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
225 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
226 /**
227 * @}
228 */
229
230 /** @defgroup DMA_LL_EC_PERIPH PERIPH
231 * @{
232 */
233 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
234 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
235 /**
236 * @}
237 */
238
239 /** @defgroup DMA_LL_EC_MEMORY MEMORY
240 * @{
241 */
242 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
243 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
244 /**
245 * @}
246 */
247
248 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
249 * @{
250 */
251 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
252 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
253 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
254 /**
255 * @}
256 */
257
258 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
259 * @{
260 */
261 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
262 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
263 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
264 /**
265 * @}
266 */
267
268 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
269 * @{
270 */
271 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
272 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
273 /**
274 * @}
275 */
276
277 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
278 * @{
279 */
280 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
281 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
282 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
283 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
284 /**
285 * @}
286 */
287
288 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
289 * @{
290 */
291 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
292 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
293 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
294 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
295 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
296 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
297 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
298 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
299 #if defined(DMA_CHANNEL_SELECTION_8_15)
300 #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
301 #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
302 #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
303 #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
304 #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
305 #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
306 #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
307 #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */
308 #endif /* DMA_CHANNEL_SELECTION_8_15 */
309 /**
310 * @}
311 */
312
313 /** @defgroup DMA_LL_EC_MBURST MBURST
314 * @{
315 */
316 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
317 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
318 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
319 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
320 /**
321 * @}
322 */
323
324 /** @defgroup DMA_LL_EC_PBURST PBURST
325 * @{
326 */
327 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
328 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
329 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
330 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
331 /**
332 * @}
333 */
334
335 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
336 * @{
337 */
338 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
339 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
340 /**
341 * @}
342 */
343
344 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
345 * @{
346 */
347 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
348 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
349 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
350 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
351 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
352 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
353 /**
354 * @}
355 */
356
357 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
358 * @{
359 */
360 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
361 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
362 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
363 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
364 /**
365 * @}
366 */
367
368 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
369 * @{
370 */
371 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
372 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
373 /**
374 * @}
375 */
376
377 /**
378 * @}
379 */
380
381 /* Exported macro ------------------------------------------------------------*/
382 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
383 * @{
384 */
385
386 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
387 * @{
388 */
389 /**
390 * @brief Write a value in DMA register
391 * @param __INSTANCE__ DMA Instance
392 * @param __REG__ Register to be written
393 * @param __VALUE__ Value to be written in the register
394 * @retval None
395 */
396 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
397
398 /**
399 * @brief Read a value in DMA register
400 * @param __INSTANCE__ DMA Instance
401 * @param __REG__ Register to be read
402 * @retval Register value
403 */
404 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
405 /**
406 * @}
407 */
408
409 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
410 * @{
411 */
412 /**
413 * @brief Convert DMAx_Streamy into DMAx
414 * @param __STREAM_INSTANCE__ DMAx_Streamy
415 * @retval DMAx
416 */
417 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
418 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
419
420 /**
421 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
422 * @param __STREAM_INSTANCE__ DMAx_Streamy
423 * @retval LL_DMA_CHANNEL_y
424 */
425 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
426 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
437 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
438 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
439 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
440 LL_DMA_STREAM_7)
441
442 /**
443 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
444 * @param __DMA_INSTANCE__ DMAx
445 * @param __STREAM__ LL_DMA_STREAM_y
446 * @retval DMAx_Streamy
447 */
448 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
449 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
464 DMA2_Stream7)
465
466 /**
467 * @}
468 */
469
470 /**
471 * @}
472 */
473
474
475 /* Exported functions --------------------------------------------------------*/
476 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
477 * @{
478 */
479
480 /** @defgroup DMA_LL_EF_Configuration Configuration
481 * @{
482 */
483 /**
484 * @brief Enable DMA stream.
485 * @rmtoll CR EN LL_DMA_EnableStream
486 * @param DMAx DMAx Instance
487 * @param Stream This parameter can be one of the following values:
488 * @arg @ref LL_DMA_STREAM_0
489 * @arg @ref LL_DMA_STREAM_1
490 * @arg @ref LL_DMA_STREAM_2
491 * @arg @ref LL_DMA_STREAM_3
492 * @arg @ref LL_DMA_STREAM_4
493 * @arg @ref LL_DMA_STREAM_5
494 * @arg @ref LL_DMA_STREAM_6
495 * @arg @ref LL_DMA_STREAM_7
496 * @retval None
497 */
498 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
499 {
500 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
501 }
502
503 /**
504 * @brief Disable DMA stream.
505 * @rmtoll CR EN LL_DMA_DisableStream
506 * @param DMAx DMAx Instance
507 * @param Stream This parameter can be one of the following values:
508 * @arg @ref LL_DMA_STREAM_0
509 * @arg @ref LL_DMA_STREAM_1
510 * @arg @ref LL_DMA_STREAM_2
511 * @arg @ref LL_DMA_STREAM_3
512 * @arg @ref LL_DMA_STREAM_4
513 * @arg @ref LL_DMA_STREAM_5
514 * @arg @ref LL_DMA_STREAM_6
515 * @arg @ref LL_DMA_STREAM_7
516 * @retval None
517 */
518 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
519 {
520 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
521 }
522
523 /**
524 * @brief Check if DMA stream is enabled or disabled.
525 * @rmtoll CR EN LL_DMA_IsEnabledStream
526 * @param DMAx DMAx Instance
527 * @param Stream This parameter can be one of the following values:
528 * @arg @ref LL_DMA_STREAM_0
529 * @arg @ref LL_DMA_STREAM_1
530 * @arg @ref LL_DMA_STREAM_2
531 * @arg @ref LL_DMA_STREAM_3
532 * @arg @ref LL_DMA_STREAM_4
533 * @arg @ref LL_DMA_STREAM_5
534 * @arg @ref LL_DMA_STREAM_6
535 * @arg @ref LL_DMA_STREAM_7
536 * @retval State of bit (1 or 0).
537 */
538 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
539 {
540 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
541 }
542
543 /**
544 * @brief Configure all parameters linked to DMA transfer.
545 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
546 * CR CIRC LL_DMA_ConfigTransfer\n
547 * CR PINC LL_DMA_ConfigTransfer\n
548 * CR MINC LL_DMA_ConfigTransfer\n
549 * CR PSIZE LL_DMA_ConfigTransfer\n
550 * CR MSIZE LL_DMA_ConfigTransfer\n
551 * CR PL LL_DMA_ConfigTransfer\n
552 * CR PFCTRL LL_DMA_ConfigTransfer
553 * @param DMAx DMAx Instance
554 * @param Stream This parameter can be one of the following values:
555 * @arg @ref LL_DMA_STREAM_0
556 * @arg @ref LL_DMA_STREAM_1
557 * @arg @ref LL_DMA_STREAM_2
558 * @arg @ref LL_DMA_STREAM_3
559 * @arg @ref LL_DMA_STREAM_4
560 * @arg @ref LL_DMA_STREAM_5
561 * @arg @ref LL_DMA_STREAM_6
562 * @arg @ref LL_DMA_STREAM_7
563 * @param Configuration This parameter must be a combination of all the following values:
564 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
565 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
566 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
567 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
568 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
569 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
570 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
571 *@retval None
572 */
573 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
574 {
575 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
576 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
577 Configuration);
578 }
579
580 /**
581 * @brief Set Data transfer direction (read from peripheral or from memory).
582 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
583 * @param DMAx DMAx Instance
584 * @param Stream This parameter can be one of the following values:
585 * @arg @ref LL_DMA_STREAM_0
586 * @arg @ref LL_DMA_STREAM_1
587 * @arg @ref LL_DMA_STREAM_2
588 * @arg @ref LL_DMA_STREAM_3
589 * @arg @ref LL_DMA_STREAM_4
590 * @arg @ref LL_DMA_STREAM_5
591 * @arg @ref LL_DMA_STREAM_6
592 * @arg @ref LL_DMA_STREAM_7
593 * @param Direction This parameter can be one of the following values:
594 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
595 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
596 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
597 * @retval None
598 */
599 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
600 {
601 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
602 }
603
604 /**
605 * @brief Get Data transfer direction (read from peripheral or from memory).
606 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
607 * @param DMAx DMAx Instance
608 * @param Stream This parameter can be one of the following values:
609 * @arg @ref LL_DMA_STREAM_0
610 * @arg @ref LL_DMA_STREAM_1
611 * @arg @ref LL_DMA_STREAM_2
612 * @arg @ref LL_DMA_STREAM_3
613 * @arg @ref LL_DMA_STREAM_4
614 * @arg @ref LL_DMA_STREAM_5
615 * @arg @ref LL_DMA_STREAM_6
616 * @arg @ref LL_DMA_STREAM_7
617 * @retval Returned value can be one of the following values:
618 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
619 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
620 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
621 */
622 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
623 {
624 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
625 }
626
627 /**
628 * @brief Set DMA mode normal, circular or peripheral flow control.
629 * @rmtoll CR CIRC LL_DMA_SetMode\n
630 * CR PFCTRL LL_DMA_SetMode
631 * @param DMAx DMAx Instance
632 * @param Stream This parameter can be one of the following values:
633 * @arg @ref LL_DMA_STREAM_0
634 * @arg @ref LL_DMA_STREAM_1
635 * @arg @ref LL_DMA_STREAM_2
636 * @arg @ref LL_DMA_STREAM_3
637 * @arg @ref LL_DMA_STREAM_4
638 * @arg @ref LL_DMA_STREAM_5
639 * @arg @ref LL_DMA_STREAM_6
640 * @arg @ref LL_DMA_STREAM_7
641 * @param Mode This parameter can be one of the following values:
642 * @arg @ref LL_DMA_MODE_NORMAL
643 * @arg @ref LL_DMA_MODE_CIRCULAR
644 * @arg @ref LL_DMA_MODE_PFCTRL
645 * @retval None
646 */
647 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
648 {
649 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
650 }
651
652 /**
653 * @brief Get DMA mode normal, circular or peripheral flow control.
654 * @rmtoll CR CIRC LL_DMA_GetMode\n
655 * CR PFCTRL LL_DMA_GetMode
656 * @param DMAx DMAx Instance
657 * @param Stream This parameter can be one of the following values:
658 * @arg @ref LL_DMA_STREAM_0
659 * @arg @ref LL_DMA_STREAM_1
660 * @arg @ref LL_DMA_STREAM_2
661 * @arg @ref LL_DMA_STREAM_3
662 * @arg @ref LL_DMA_STREAM_4
663 * @arg @ref LL_DMA_STREAM_5
664 * @arg @ref LL_DMA_STREAM_6
665 * @arg @ref LL_DMA_STREAM_7
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_DMA_MODE_NORMAL
668 * @arg @ref LL_DMA_MODE_CIRCULAR
669 * @arg @ref LL_DMA_MODE_PFCTRL
670 */
671 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
672 {
673 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
674 }
675
676 /**
677 * @brief Set Peripheral increment mode.
678 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
679 * @param DMAx DMAx Instance
680 * @param Stream This parameter can be one of the following values:
681 * @arg @ref LL_DMA_STREAM_0
682 * @arg @ref LL_DMA_STREAM_1
683 * @arg @ref LL_DMA_STREAM_2
684 * @arg @ref LL_DMA_STREAM_3
685 * @arg @ref LL_DMA_STREAM_4
686 * @arg @ref LL_DMA_STREAM_5
687 * @arg @ref LL_DMA_STREAM_6
688 * @arg @ref LL_DMA_STREAM_7
689 * @param IncrementMode This parameter can be one of the following values:
690 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
691 * @arg @ref LL_DMA_PERIPH_INCREMENT
692 * @retval None
693 */
694 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
695 {
696 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
697 }
698
699 /**
700 * @brief Get Peripheral increment mode.
701 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
702 * @param DMAx DMAx Instance
703 * @param Stream This parameter can be one of the following values:
704 * @arg @ref LL_DMA_STREAM_0
705 * @arg @ref LL_DMA_STREAM_1
706 * @arg @ref LL_DMA_STREAM_2
707 * @arg @ref LL_DMA_STREAM_3
708 * @arg @ref LL_DMA_STREAM_4
709 * @arg @ref LL_DMA_STREAM_5
710 * @arg @ref LL_DMA_STREAM_6
711 * @arg @ref LL_DMA_STREAM_7
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
714 * @arg @ref LL_DMA_PERIPH_INCREMENT
715 */
716 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
717 {
718 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
719 }
720
721 /**
722 * @brief Set Memory increment mode.
723 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
724 * @param DMAx DMAx Instance
725 * @param Stream This parameter can be one of the following values:
726 * @arg @ref LL_DMA_STREAM_0
727 * @arg @ref LL_DMA_STREAM_1
728 * @arg @ref LL_DMA_STREAM_2
729 * @arg @ref LL_DMA_STREAM_3
730 * @arg @ref LL_DMA_STREAM_4
731 * @arg @ref LL_DMA_STREAM_5
732 * @arg @ref LL_DMA_STREAM_6
733 * @arg @ref LL_DMA_STREAM_7
734 * @param IncrementMode This parameter can be one of the following values:
735 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
736 * @arg @ref LL_DMA_MEMORY_INCREMENT
737 * @retval None
738 */
739 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
740 {
741 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
742 }
743
744 /**
745 * @brief Get Memory increment mode.
746 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
747 * @param DMAx DMAx Instance
748 * @param Stream This parameter can be one of the following values:
749 * @arg @ref LL_DMA_STREAM_0
750 * @arg @ref LL_DMA_STREAM_1
751 * @arg @ref LL_DMA_STREAM_2
752 * @arg @ref LL_DMA_STREAM_3
753 * @arg @ref LL_DMA_STREAM_4
754 * @arg @ref LL_DMA_STREAM_5
755 * @arg @ref LL_DMA_STREAM_6
756 * @arg @ref LL_DMA_STREAM_7
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
759 * @arg @ref LL_DMA_MEMORY_INCREMENT
760 */
761 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
762 {
763 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
764 }
765
766 /**
767 * @brief Set Peripheral size.
768 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
769 * @param DMAx DMAx Instance
770 * @param Stream This parameter can be one of the following values:
771 * @arg @ref LL_DMA_STREAM_0
772 * @arg @ref LL_DMA_STREAM_1
773 * @arg @ref LL_DMA_STREAM_2
774 * @arg @ref LL_DMA_STREAM_3
775 * @arg @ref LL_DMA_STREAM_4
776 * @arg @ref LL_DMA_STREAM_5
777 * @arg @ref LL_DMA_STREAM_6
778 * @arg @ref LL_DMA_STREAM_7
779 * @param Size This parameter can be one of the following values:
780 * @arg @ref LL_DMA_PDATAALIGN_BYTE
781 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
782 * @arg @ref LL_DMA_PDATAALIGN_WORD
783 * @retval None
784 */
785 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
786 {
787 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
788 }
789
790 /**
791 * @brief Get Peripheral size.
792 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
793 * @param DMAx DMAx Instance
794 * @param Stream This parameter can be one of the following values:
795 * @arg @ref LL_DMA_STREAM_0
796 * @arg @ref LL_DMA_STREAM_1
797 * @arg @ref LL_DMA_STREAM_2
798 * @arg @ref LL_DMA_STREAM_3
799 * @arg @ref LL_DMA_STREAM_4
800 * @arg @ref LL_DMA_STREAM_5
801 * @arg @ref LL_DMA_STREAM_6
802 * @arg @ref LL_DMA_STREAM_7
803 * @retval Returned value can be one of the following values:
804 * @arg @ref LL_DMA_PDATAALIGN_BYTE
805 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
806 * @arg @ref LL_DMA_PDATAALIGN_WORD
807 */
808 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
809 {
810 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
811 }
812
813 /**
814 * @brief Set Memory size.
815 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
816 * @param DMAx DMAx Instance
817 * @param Stream This parameter can be one of the following values:
818 * @arg @ref LL_DMA_STREAM_0
819 * @arg @ref LL_DMA_STREAM_1
820 * @arg @ref LL_DMA_STREAM_2
821 * @arg @ref LL_DMA_STREAM_3
822 * @arg @ref LL_DMA_STREAM_4
823 * @arg @ref LL_DMA_STREAM_5
824 * @arg @ref LL_DMA_STREAM_6
825 * @arg @ref LL_DMA_STREAM_7
826 * @param Size This parameter can be one of the following values:
827 * @arg @ref LL_DMA_MDATAALIGN_BYTE
828 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
829 * @arg @ref LL_DMA_MDATAALIGN_WORD
830 * @retval None
831 */
832 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
833 {
834 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
835 }
836
837 /**
838 * @brief Get Memory size.
839 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
840 * @param DMAx DMAx Instance
841 * @param Stream This parameter can be one of the following values:
842 * @arg @ref LL_DMA_STREAM_0
843 * @arg @ref LL_DMA_STREAM_1
844 * @arg @ref LL_DMA_STREAM_2
845 * @arg @ref LL_DMA_STREAM_3
846 * @arg @ref LL_DMA_STREAM_4
847 * @arg @ref LL_DMA_STREAM_5
848 * @arg @ref LL_DMA_STREAM_6
849 * @arg @ref LL_DMA_STREAM_7
850 * @retval Returned value can be one of the following values:
851 * @arg @ref LL_DMA_MDATAALIGN_BYTE
852 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
853 * @arg @ref LL_DMA_MDATAALIGN_WORD
854 */
855 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
856 {
857 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
858 }
859
860 /**
861 * @brief Set Peripheral increment offset size.
862 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
863 * @param DMAx DMAx Instance
864 * @param Stream This parameter can be one of the following values:
865 * @arg @ref LL_DMA_STREAM_0
866 * @arg @ref LL_DMA_STREAM_1
867 * @arg @ref LL_DMA_STREAM_2
868 * @arg @ref LL_DMA_STREAM_3
869 * @arg @ref LL_DMA_STREAM_4
870 * @arg @ref LL_DMA_STREAM_5
871 * @arg @ref LL_DMA_STREAM_6
872 * @arg @ref LL_DMA_STREAM_7
873 * @param OffsetSize This parameter can be one of the following values:
874 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
875 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
876 * @retval None
877 */
878 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
879 {
880 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
881 }
882
883 /**
884 * @brief Get Peripheral increment offset size.
885 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
886 * @param DMAx DMAx Instance
887 * @param Stream This parameter can be one of the following values:
888 * @arg @ref LL_DMA_STREAM_0
889 * @arg @ref LL_DMA_STREAM_1
890 * @arg @ref LL_DMA_STREAM_2
891 * @arg @ref LL_DMA_STREAM_3
892 * @arg @ref LL_DMA_STREAM_4
893 * @arg @ref LL_DMA_STREAM_5
894 * @arg @ref LL_DMA_STREAM_6
895 * @arg @ref LL_DMA_STREAM_7
896 * @retval Returned value can be one of the following values:
897 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
898 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
899 */
900 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
901 {
902 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
903 }
904
905 /**
906 * @brief Set Stream priority level.
907 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
908 * @param DMAx DMAx Instance
909 * @param Stream This parameter can be one of the following values:
910 * @arg @ref LL_DMA_STREAM_0
911 * @arg @ref LL_DMA_STREAM_1
912 * @arg @ref LL_DMA_STREAM_2
913 * @arg @ref LL_DMA_STREAM_3
914 * @arg @ref LL_DMA_STREAM_4
915 * @arg @ref LL_DMA_STREAM_5
916 * @arg @ref LL_DMA_STREAM_6
917 * @arg @ref LL_DMA_STREAM_7
918 * @param Priority This parameter can be one of the following values:
919 * @arg @ref LL_DMA_PRIORITY_LOW
920 * @arg @ref LL_DMA_PRIORITY_MEDIUM
921 * @arg @ref LL_DMA_PRIORITY_HIGH
922 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
923 * @retval None
924 */
925 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
926 {
927 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
928 }
929
930 /**
931 * @brief Get Stream priority level.
932 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
933 * @param DMAx DMAx Instance
934 * @param Stream This parameter can be one of the following values:
935 * @arg @ref LL_DMA_STREAM_0
936 * @arg @ref LL_DMA_STREAM_1
937 * @arg @ref LL_DMA_STREAM_2
938 * @arg @ref LL_DMA_STREAM_3
939 * @arg @ref LL_DMA_STREAM_4
940 * @arg @ref LL_DMA_STREAM_5
941 * @arg @ref LL_DMA_STREAM_6
942 * @arg @ref LL_DMA_STREAM_7
943 * @retval Returned value can be one of the following values:
944 * @arg @ref LL_DMA_PRIORITY_LOW
945 * @arg @ref LL_DMA_PRIORITY_MEDIUM
946 * @arg @ref LL_DMA_PRIORITY_HIGH
947 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
948 */
949 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
950 {
951 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
952 }
953
954 /**
955 * @brief Set Number of data to transfer.
956 * @rmtoll NDTR NDT LL_DMA_SetDataLength
957 * @note This action has no effect if
958 * stream is enabled.
959 * @param DMAx DMAx Instance
960 * @param Stream This parameter can be one of the following values:
961 * @arg @ref LL_DMA_STREAM_0
962 * @arg @ref LL_DMA_STREAM_1
963 * @arg @ref LL_DMA_STREAM_2
964 * @arg @ref LL_DMA_STREAM_3
965 * @arg @ref LL_DMA_STREAM_4
966 * @arg @ref LL_DMA_STREAM_5
967 * @arg @ref LL_DMA_STREAM_6
968 * @arg @ref LL_DMA_STREAM_7
969 * @param NbData Between 0 to 0xFFFFFFFF
970 * @retval None
971 */
972 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
973 {
974 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
975 }
976
977 /**
978 * @brief Get Number of data to transfer.
979 * @rmtoll NDTR NDT LL_DMA_GetDataLength
980 * @note Once the stream is enabled, the return value indicate the
981 * remaining bytes to be transmitted.
982 * @param DMAx DMAx Instance
983 * @param Stream This parameter can be one of the following values:
984 * @arg @ref LL_DMA_STREAM_0
985 * @arg @ref LL_DMA_STREAM_1
986 * @arg @ref LL_DMA_STREAM_2
987 * @arg @ref LL_DMA_STREAM_3
988 * @arg @ref LL_DMA_STREAM_4
989 * @arg @ref LL_DMA_STREAM_5
990 * @arg @ref LL_DMA_STREAM_6
991 * @arg @ref LL_DMA_STREAM_7
992 * @retval Between 0 to 0xFFFFFFFF
993 */
994 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
995 {
996 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
997 }
998
999 /**
1000 * @brief Select Channel number associated to the Stream.
1001 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
1002 * @param DMAx DMAx Instance
1003 * @param Stream This parameter can be one of the following values:
1004 * @arg @ref LL_DMA_STREAM_0
1005 * @arg @ref LL_DMA_STREAM_1
1006 * @arg @ref LL_DMA_STREAM_2
1007 * @arg @ref LL_DMA_STREAM_3
1008 * @arg @ref LL_DMA_STREAM_4
1009 * @arg @ref LL_DMA_STREAM_5
1010 * @arg @ref LL_DMA_STREAM_6
1011 * @arg @ref LL_DMA_STREAM_7
1012 * @param Channel This parameter can be one of the following values:
1013 * @arg @ref LL_DMA_CHANNEL_0
1014 * @arg @ref LL_DMA_CHANNEL_1
1015 * @arg @ref LL_DMA_CHANNEL_2
1016 * @arg @ref LL_DMA_CHANNEL_3
1017 * @arg @ref LL_DMA_CHANNEL_4
1018 * @arg @ref LL_DMA_CHANNEL_5
1019 * @arg @ref LL_DMA_CHANNEL_6
1020 * @arg @ref LL_DMA_CHANNEL_7
1021 * @arg @ref LL_DMA_CHANNEL_8 (*)
1022 * @arg @ref LL_DMA_CHANNEL_9 (*)
1023 * @arg @ref LL_DMA_CHANNEL_10 (*)
1024 * @arg @ref LL_DMA_CHANNEL_11 (*)
1025 * @arg @ref LL_DMA_CHANNEL_12 (*)
1026 * @arg @ref LL_DMA_CHANNEL_13 (*)
1027 * @arg @ref LL_DMA_CHANNEL_14 (*)
1028 * @arg @ref LL_DMA_CHANNEL_15 (*)
1029 *
1030 * (*) value not defined in all devices.
1031 * @retval None
1032 */
1033 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1034 {
1035 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1036 }
1037
1038 /**
1039 * @brief Get the Channel number associated to the Stream.
1040 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1041 * @param DMAx DMAx Instance
1042 * @param Stream This parameter can be one of the following values:
1043 * @arg @ref LL_DMA_STREAM_0
1044 * @arg @ref LL_DMA_STREAM_1
1045 * @arg @ref LL_DMA_STREAM_2
1046 * @arg @ref LL_DMA_STREAM_3
1047 * @arg @ref LL_DMA_STREAM_4
1048 * @arg @ref LL_DMA_STREAM_5
1049 * @arg @ref LL_DMA_STREAM_6
1050 * @arg @ref LL_DMA_STREAM_7
1051 * @retval Returned value can be one of the following values:
1052 * @arg @ref LL_DMA_CHANNEL_0
1053 * @arg @ref LL_DMA_CHANNEL_1
1054 * @arg @ref LL_DMA_CHANNEL_2
1055 * @arg @ref LL_DMA_CHANNEL_3
1056 * @arg @ref LL_DMA_CHANNEL_4
1057 * @arg @ref LL_DMA_CHANNEL_5
1058 * @arg @ref LL_DMA_CHANNEL_6
1059 * @arg @ref LL_DMA_CHANNEL_7
1060 * @arg @ref LL_DMA_CHANNEL_8 (*)
1061 * @arg @ref LL_DMA_CHANNEL_9 (*)
1062 * @arg @ref LL_DMA_CHANNEL_10 (*)
1063 * @arg @ref LL_DMA_CHANNEL_11 (*)
1064 * @arg @ref LL_DMA_CHANNEL_12 (*)
1065 * @arg @ref LL_DMA_CHANNEL_13 (*)
1066 * @arg @ref LL_DMA_CHANNEL_14 (*)
1067 * @arg @ref LL_DMA_CHANNEL_15 (*)
1068 *
1069 * (*) value not defined in all devices.
1070 */
1071 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1072 {
1073 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1074 }
1075
1076 /**
1077 * @brief Set Memory burst transfer configuration.
1078 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1079 * @param DMAx DMAx Instance
1080 * @param Stream This parameter can be one of the following values:
1081 * @arg @ref LL_DMA_STREAM_0
1082 * @arg @ref LL_DMA_STREAM_1
1083 * @arg @ref LL_DMA_STREAM_2
1084 * @arg @ref LL_DMA_STREAM_3
1085 * @arg @ref LL_DMA_STREAM_4
1086 * @arg @ref LL_DMA_STREAM_5
1087 * @arg @ref LL_DMA_STREAM_6
1088 * @arg @ref LL_DMA_STREAM_7
1089 * @param Mburst This parameter can be one of the following values:
1090 * @arg @ref LL_DMA_MBURST_SINGLE
1091 * @arg @ref LL_DMA_MBURST_INC4
1092 * @arg @ref LL_DMA_MBURST_INC8
1093 * @arg @ref LL_DMA_MBURST_INC16
1094 * @retval None
1095 */
1096 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1097 {
1098 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1099 }
1100
1101 /**
1102 * @brief Get Memory burst transfer configuration.
1103 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1104 * @param DMAx DMAx Instance
1105 * @param Stream This parameter can be one of the following values:
1106 * @arg @ref LL_DMA_STREAM_0
1107 * @arg @ref LL_DMA_STREAM_1
1108 * @arg @ref LL_DMA_STREAM_2
1109 * @arg @ref LL_DMA_STREAM_3
1110 * @arg @ref LL_DMA_STREAM_4
1111 * @arg @ref LL_DMA_STREAM_5
1112 * @arg @ref LL_DMA_STREAM_6
1113 * @arg @ref LL_DMA_STREAM_7
1114 * @retval Returned value can be one of the following values:
1115 * @arg @ref LL_DMA_MBURST_SINGLE
1116 * @arg @ref LL_DMA_MBURST_INC4
1117 * @arg @ref LL_DMA_MBURST_INC8
1118 * @arg @ref LL_DMA_MBURST_INC16
1119 */
1120 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1121 {
1122 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1123 }
1124
1125 /**
1126 * @brief Set Peripheral burst transfer configuration.
1127 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1128 * @param DMAx DMAx Instance
1129 * @param Stream This parameter can be one of the following values:
1130 * @arg @ref LL_DMA_STREAM_0
1131 * @arg @ref LL_DMA_STREAM_1
1132 * @arg @ref LL_DMA_STREAM_2
1133 * @arg @ref LL_DMA_STREAM_3
1134 * @arg @ref LL_DMA_STREAM_4
1135 * @arg @ref LL_DMA_STREAM_5
1136 * @arg @ref LL_DMA_STREAM_6
1137 * @arg @ref LL_DMA_STREAM_7
1138 * @param Pburst This parameter can be one of the following values:
1139 * @arg @ref LL_DMA_PBURST_SINGLE
1140 * @arg @ref LL_DMA_PBURST_INC4
1141 * @arg @ref LL_DMA_PBURST_INC8
1142 * @arg @ref LL_DMA_PBURST_INC16
1143 * @retval None
1144 */
1145 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1146 {
1147 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1148 }
1149
1150 /**
1151 * @brief Get Peripheral burst transfer configuration.
1152 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1153 * @param DMAx DMAx Instance
1154 * @param Stream This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_STREAM_0
1156 * @arg @ref LL_DMA_STREAM_1
1157 * @arg @ref LL_DMA_STREAM_2
1158 * @arg @ref LL_DMA_STREAM_3
1159 * @arg @ref LL_DMA_STREAM_4
1160 * @arg @ref LL_DMA_STREAM_5
1161 * @arg @ref LL_DMA_STREAM_6
1162 * @arg @ref LL_DMA_STREAM_7
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_DMA_PBURST_SINGLE
1165 * @arg @ref LL_DMA_PBURST_INC4
1166 * @arg @ref LL_DMA_PBURST_INC8
1167 * @arg @ref LL_DMA_PBURST_INC16
1168 */
1169 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1170 {
1171 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1172 }
1173
1174 /**
1175 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1176 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1177 * @param DMAx DMAx Instance
1178 * @param Stream This parameter can be one of the following values:
1179 * @arg @ref LL_DMA_STREAM_0
1180 * @arg @ref LL_DMA_STREAM_1
1181 * @arg @ref LL_DMA_STREAM_2
1182 * @arg @ref LL_DMA_STREAM_3
1183 * @arg @ref LL_DMA_STREAM_4
1184 * @arg @ref LL_DMA_STREAM_5
1185 * @arg @ref LL_DMA_STREAM_6
1186 * @arg @ref LL_DMA_STREAM_7
1187 * @param CurrentMemory This parameter can be one of the following values:
1188 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1189 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1190 * @retval None
1191 */
1192 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1193 {
1194 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1195 }
1196
1197 /**
1198 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1199 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1200 * @param DMAx DMAx Instance
1201 * @param Stream This parameter can be one of the following values:
1202 * @arg @ref LL_DMA_STREAM_0
1203 * @arg @ref LL_DMA_STREAM_1
1204 * @arg @ref LL_DMA_STREAM_2
1205 * @arg @ref LL_DMA_STREAM_3
1206 * @arg @ref LL_DMA_STREAM_4
1207 * @arg @ref LL_DMA_STREAM_5
1208 * @arg @ref LL_DMA_STREAM_6
1209 * @arg @ref LL_DMA_STREAM_7
1210 * @retval Returned value can be one of the following values:
1211 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1212 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1213 */
1214 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1215 {
1216 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1217 }
1218
1219 /**
1220 * @brief Enable the double buffer mode.
1221 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1222 * @param DMAx DMAx Instance
1223 * @param Stream This parameter can be one of the following values:
1224 * @arg @ref LL_DMA_STREAM_0
1225 * @arg @ref LL_DMA_STREAM_1
1226 * @arg @ref LL_DMA_STREAM_2
1227 * @arg @ref LL_DMA_STREAM_3
1228 * @arg @ref LL_DMA_STREAM_4
1229 * @arg @ref LL_DMA_STREAM_5
1230 * @arg @ref LL_DMA_STREAM_6
1231 * @arg @ref LL_DMA_STREAM_7
1232 * @retval None
1233 */
1234 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1235 {
1236 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1237 }
1238
1239 /**
1240 * @brief Disable the double buffer mode.
1241 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1242 * @param DMAx DMAx Instance
1243 * @param Stream This parameter can be one of the following values:
1244 * @arg @ref LL_DMA_STREAM_0
1245 * @arg @ref LL_DMA_STREAM_1
1246 * @arg @ref LL_DMA_STREAM_2
1247 * @arg @ref LL_DMA_STREAM_3
1248 * @arg @ref LL_DMA_STREAM_4
1249 * @arg @ref LL_DMA_STREAM_5
1250 * @arg @ref LL_DMA_STREAM_6
1251 * @arg @ref LL_DMA_STREAM_7
1252 * @retval None
1253 */
1254 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1255 {
1256 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1257 }
1258
1259 /**
1260 * @brief Get FIFO status.
1261 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1262 * @param DMAx DMAx Instance
1263 * @param Stream This parameter can be one of the following values:
1264 * @arg @ref LL_DMA_STREAM_0
1265 * @arg @ref LL_DMA_STREAM_1
1266 * @arg @ref LL_DMA_STREAM_2
1267 * @arg @ref LL_DMA_STREAM_3
1268 * @arg @ref LL_DMA_STREAM_4
1269 * @arg @ref LL_DMA_STREAM_5
1270 * @arg @ref LL_DMA_STREAM_6
1271 * @arg @ref LL_DMA_STREAM_7
1272 * @retval Returned value can be one of the following values:
1273 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1274 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1275 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1276 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1277 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1278 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1279 */
1280 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1281 {
1282 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1283 }
1284
1285 /**
1286 * @brief Disable Fifo mode.
1287 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1288 * @param DMAx DMAx Instance
1289 * @param Stream This parameter can be one of the following values:
1290 * @arg @ref LL_DMA_STREAM_0
1291 * @arg @ref LL_DMA_STREAM_1
1292 * @arg @ref LL_DMA_STREAM_2
1293 * @arg @ref LL_DMA_STREAM_3
1294 * @arg @ref LL_DMA_STREAM_4
1295 * @arg @ref LL_DMA_STREAM_5
1296 * @arg @ref LL_DMA_STREAM_6
1297 * @arg @ref LL_DMA_STREAM_7
1298 * @retval None
1299 */
1300 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1301 {
1302 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1303 }
1304
1305 /**
1306 * @brief Enable Fifo mode.
1307 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1308 * @param DMAx DMAx Instance
1309 * @param Stream This parameter can be one of the following values:
1310 * @arg @ref LL_DMA_STREAM_0
1311 * @arg @ref LL_DMA_STREAM_1
1312 * @arg @ref LL_DMA_STREAM_2
1313 * @arg @ref LL_DMA_STREAM_3
1314 * @arg @ref LL_DMA_STREAM_4
1315 * @arg @ref LL_DMA_STREAM_5
1316 * @arg @ref LL_DMA_STREAM_6
1317 * @arg @ref LL_DMA_STREAM_7
1318 * @retval None
1319 */
1320 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1321 {
1322 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1323 }
1324
1325 /**
1326 * @brief Select FIFO threshold.
1327 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1328 * @param DMAx DMAx Instance
1329 * @param Stream This parameter can be one of the following values:
1330 * @arg @ref LL_DMA_STREAM_0
1331 * @arg @ref LL_DMA_STREAM_1
1332 * @arg @ref LL_DMA_STREAM_2
1333 * @arg @ref LL_DMA_STREAM_3
1334 * @arg @ref LL_DMA_STREAM_4
1335 * @arg @ref LL_DMA_STREAM_5
1336 * @arg @ref LL_DMA_STREAM_6
1337 * @arg @ref LL_DMA_STREAM_7
1338 * @param Threshold This parameter can be one of the following values:
1339 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1340 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1341 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1342 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1343 * @retval None
1344 */
1345 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1346 {
1347 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1348 }
1349
1350 /**
1351 * @brief Get FIFO threshold.
1352 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1353 * @param DMAx DMAx Instance
1354 * @param Stream This parameter can be one of the following values:
1355 * @arg @ref LL_DMA_STREAM_0
1356 * @arg @ref LL_DMA_STREAM_1
1357 * @arg @ref LL_DMA_STREAM_2
1358 * @arg @ref LL_DMA_STREAM_3
1359 * @arg @ref LL_DMA_STREAM_4
1360 * @arg @ref LL_DMA_STREAM_5
1361 * @arg @ref LL_DMA_STREAM_6
1362 * @arg @ref LL_DMA_STREAM_7
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1365 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1366 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1367 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1368 */
1369 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1370 {
1371 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1372 }
1373
1374 /**
1375 * @brief Configure the FIFO .
1376 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1377 * FCR DMDIS LL_DMA_ConfigFifo
1378 * @param DMAx DMAx Instance
1379 * @param Stream This parameter can be one of the following values:
1380 * @arg @ref LL_DMA_STREAM_0
1381 * @arg @ref LL_DMA_STREAM_1
1382 * @arg @ref LL_DMA_STREAM_2
1383 * @arg @ref LL_DMA_STREAM_3
1384 * @arg @ref LL_DMA_STREAM_4
1385 * @arg @ref LL_DMA_STREAM_5
1386 * @arg @ref LL_DMA_STREAM_6
1387 * @arg @ref LL_DMA_STREAM_7
1388 * @param FifoMode This parameter can be one of the following values:
1389 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1390 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1391 * @param FifoThreshold This parameter can be one of the following values:
1392 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1393 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1394 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1395 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1396 * @retval None
1397 */
1398 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1399 {
1400 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1401 }
1402
1403 /**
1404 * @brief Configure the Source and Destination addresses.
1405 * @note This API must not be called when the DMA stream is enabled.
1406 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1407 * PAR PA LL_DMA_ConfigAddresses
1408 * @param DMAx DMAx Instance
1409 * @param Stream This parameter can be one of the following values:
1410 * @arg @ref LL_DMA_STREAM_0
1411 * @arg @ref LL_DMA_STREAM_1
1412 * @arg @ref LL_DMA_STREAM_2
1413 * @arg @ref LL_DMA_STREAM_3
1414 * @arg @ref LL_DMA_STREAM_4
1415 * @arg @ref LL_DMA_STREAM_5
1416 * @arg @ref LL_DMA_STREAM_6
1417 * @arg @ref LL_DMA_STREAM_7
1418 * @param SrcAddress Between 0 to 0xFFFFFFFF
1419 * @param DstAddress Between 0 to 0xFFFFFFFF
1420 * @param Direction This parameter can be one of the following values:
1421 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1422 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1423 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1424 * @retval None
1425 */
1426 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1427 {
1428 /* Direction Memory to Periph */
1429 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1430 {
1431 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1432 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1433 }
1434 /* Direction Periph to Memory and Memory to Memory */
1435 else
1436 {
1437 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1438 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1439 }
1440 }
1441
1442 /**
1443 * @brief Set the Memory address.
1444 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1445 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1446 * @note This API must not be called when the DMA channel is enabled.
1447 * @param DMAx DMAx Instance
1448 * @param Stream This parameter can be one of the following values:
1449 * @arg @ref LL_DMA_STREAM_0
1450 * @arg @ref LL_DMA_STREAM_1
1451 * @arg @ref LL_DMA_STREAM_2
1452 * @arg @ref LL_DMA_STREAM_3
1453 * @arg @ref LL_DMA_STREAM_4
1454 * @arg @ref LL_DMA_STREAM_5
1455 * @arg @ref LL_DMA_STREAM_6
1456 * @arg @ref LL_DMA_STREAM_7
1457 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1458 * @retval None
1459 */
1460 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1461 {
1462 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1463 }
1464
1465 /**
1466 * @brief Set the Peripheral address.
1467 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1468 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1469 * @note This API must not be called when the DMA channel is enabled.
1470 * @param DMAx DMAx Instance
1471 * @param Stream This parameter can be one of the following values:
1472 * @arg @ref LL_DMA_STREAM_0
1473 * @arg @ref LL_DMA_STREAM_1
1474 * @arg @ref LL_DMA_STREAM_2
1475 * @arg @ref LL_DMA_STREAM_3
1476 * @arg @ref LL_DMA_STREAM_4
1477 * @arg @ref LL_DMA_STREAM_5
1478 * @arg @ref LL_DMA_STREAM_6
1479 * @arg @ref LL_DMA_STREAM_7
1480 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1481 * @retval None
1482 */
1483 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1484 {
1485 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1486 }
1487
1488 /**
1489 * @brief Get the Memory address.
1490 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1491 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1492 * @param DMAx DMAx Instance
1493 * @param Stream This parameter can be one of the following values:
1494 * @arg @ref LL_DMA_STREAM_0
1495 * @arg @ref LL_DMA_STREAM_1
1496 * @arg @ref LL_DMA_STREAM_2
1497 * @arg @ref LL_DMA_STREAM_3
1498 * @arg @ref LL_DMA_STREAM_4
1499 * @arg @ref LL_DMA_STREAM_5
1500 * @arg @ref LL_DMA_STREAM_6
1501 * @arg @ref LL_DMA_STREAM_7
1502 * @retval Between 0 to 0xFFFFFFFF
1503 */
1504 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1505 {
1506 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1507 }
1508
1509 /**
1510 * @brief Get the Peripheral address.
1511 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1512 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1513 * @param DMAx DMAx Instance
1514 * @param Stream This parameter can be one of the following values:
1515 * @arg @ref LL_DMA_STREAM_0
1516 * @arg @ref LL_DMA_STREAM_1
1517 * @arg @ref LL_DMA_STREAM_2
1518 * @arg @ref LL_DMA_STREAM_3
1519 * @arg @ref LL_DMA_STREAM_4
1520 * @arg @ref LL_DMA_STREAM_5
1521 * @arg @ref LL_DMA_STREAM_6
1522 * @arg @ref LL_DMA_STREAM_7
1523 * @retval Between 0 to 0xFFFFFFFF
1524 */
1525 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1526 {
1527 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1528 }
1529
1530 /**
1531 * @brief Set the Memory to Memory Source address.
1532 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1533 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1534 * @note This API must not be called when the DMA channel is enabled.
1535 * @param DMAx DMAx Instance
1536 * @param Stream This parameter can be one of the following values:
1537 * @arg @ref LL_DMA_STREAM_0
1538 * @arg @ref LL_DMA_STREAM_1
1539 * @arg @ref LL_DMA_STREAM_2
1540 * @arg @ref LL_DMA_STREAM_3
1541 * @arg @ref LL_DMA_STREAM_4
1542 * @arg @ref LL_DMA_STREAM_5
1543 * @arg @ref LL_DMA_STREAM_6
1544 * @arg @ref LL_DMA_STREAM_7
1545 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1546 * @retval None
1547 */
1548 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1549 {
1550 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1551 }
1552
1553 /**
1554 * @brief Set the Memory to Memory Destination address.
1555 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1556 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1557 * @note This API must not be called when the DMA channel is enabled.
1558 * @param DMAx DMAx Instance
1559 * @param Stream This parameter can be one of the following values:
1560 * @arg @ref LL_DMA_STREAM_0
1561 * @arg @ref LL_DMA_STREAM_1
1562 * @arg @ref LL_DMA_STREAM_2
1563 * @arg @ref LL_DMA_STREAM_3
1564 * @arg @ref LL_DMA_STREAM_4
1565 * @arg @ref LL_DMA_STREAM_5
1566 * @arg @ref LL_DMA_STREAM_6
1567 * @arg @ref LL_DMA_STREAM_7
1568 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1569 * @retval None
1570 */
1571 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1572 {
1573 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1574 }
1575
1576 /**
1577 * @brief Get the Memory to Memory Source address.
1578 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1579 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1580 * @param DMAx DMAx Instance
1581 * @param Stream This parameter can be one of the following values:
1582 * @arg @ref LL_DMA_STREAM_0
1583 * @arg @ref LL_DMA_STREAM_1
1584 * @arg @ref LL_DMA_STREAM_2
1585 * @arg @ref LL_DMA_STREAM_3
1586 * @arg @ref LL_DMA_STREAM_4
1587 * @arg @ref LL_DMA_STREAM_5
1588 * @arg @ref LL_DMA_STREAM_6
1589 * @arg @ref LL_DMA_STREAM_7
1590 * @retval Between 0 to 0xFFFFFFFF
1591 */
1592 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1593 {
1594 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1595 }
1596
1597 /**
1598 * @brief Get the Memory to Memory Destination address.
1599 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1600 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1601 * @param DMAx DMAx Instance
1602 * @param Stream This parameter can be one of the following values:
1603 * @arg @ref LL_DMA_STREAM_0
1604 * @arg @ref LL_DMA_STREAM_1
1605 * @arg @ref LL_DMA_STREAM_2
1606 * @arg @ref LL_DMA_STREAM_3
1607 * @arg @ref LL_DMA_STREAM_4
1608 * @arg @ref LL_DMA_STREAM_5
1609 * @arg @ref LL_DMA_STREAM_6
1610 * @arg @ref LL_DMA_STREAM_7
1611 * @retval Between 0 to 0xFFFFFFFF
1612 */
1613 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1614 {
1615 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1616 }
1617
1618 /**
1619 * @brief Set Memory 1 address (used in case of Double buffer mode).
1620 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1621 * @param DMAx DMAx Instance
1622 * @param Stream This parameter can be one of the following values:
1623 * @arg @ref LL_DMA_STREAM_0
1624 * @arg @ref LL_DMA_STREAM_1
1625 * @arg @ref LL_DMA_STREAM_2
1626 * @arg @ref LL_DMA_STREAM_3
1627 * @arg @ref LL_DMA_STREAM_4
1628 * @arg @ref LL_DMA_STREAM_5
1629 * @arg @ref LL_DMA_STREAM_6
1630 * @arg @ref LL_DMA_STREAM_7
1631 * @param Address Between 0 to 0xFFFFFFFF
1632 * @retval None
1633 */
1634 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1635 {
1636 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1637 }
1638
1639 /**
1640 * @brief Get Memory 1 address (used in case of Double buffer mode).
1641 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1642 * @param DMAx DMAx Instance
1643 * @param Stream This parameter can be one of the following values:
1644 * @arg @ref LL_DMA_STREAM_0
1645 * @arg @ref LL_DMA_STREAM_1
1646 * @arg @ref LL_DMA_STREAM_2
1647 * @arg @ref LL_DMA_STREAM_3
1648 * @arg @ref LL_DMA_STREAM_4
1649 * @arg @ref LL_DMA_STREAM_5
1650 * @arg @ref LL_DMA_STREAM_6
1651 * @arg @ref LL_DMA_STREAM_7
1652 * @retval Between 0 to 0xFFFFFFFF
1653 */
1654 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1655 {
1656 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1657 }
1658
1659 /**
1660 * @}
1661 */
1662
1663 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1664 * @{
1665 */
1666
1667 /**
1668 * @brief Get Stream 0 half transfer flag.
1669 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1670 * @param DMAx DMAx Instance
1671 * @retval State of bit (1 or 0).
1672 */
1673 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1674 {
1675 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1676 }
1677
1678 /**
1679 * @brief Get Stream 1 half transfer flag.
1680 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1681 * @param DMAx DMAx Instance
1682 * @retval State of bit (1 or 0).
1683 */
1684 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1685 {
1686 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1687 }
1688
1689 /**
1690 * @brief Get Stream 2 half transfer flag.
1691 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1692 * @param DMAx DMAx Instance
1693 * @retval State of bit (1 or 0).
1694 */
1695 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1696 {
1697 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1698 }
1699
1700 /**
1701 * @brief Get Stream 3 half transfer flag.
1702 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1703 * @param DMAx DMAx Instance
1704 * @retval State of bit (1 or 0).
1705 */
1706 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1707 {
1708 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1709 }
1710
1711 /**
1712 * @brief Get Stream 4 half transfer flag.
1713 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1714 * @param DMAx DMAx Instance
1715 * @retval State of bit (1 or 0).
1716 */
1717 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1718 {
1719 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1720 }
1721
1722 /**
1723 * @brief Get Stream 5 half transfer flag.
1724 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1725 * @param DMAx DMAx Instance
1726 * @retval State of bit (1 or 0).
1727 */
1728 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1729 {
1730 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1731 }
1732
1733 /**
1734 * @brief Get Stream 6 half transfer flag.
1735 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1736 * @param DMAx DMAx Instance
1737 * @retval State of bit (1 or 0).
1738 */
1739 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1740 {
1741 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1742 }
1743
1744 /**
1745 * @brief Get Stream 7 half transfer flag.
1746 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1747 * @param DMAx DMAx Instance
1748 * @retval State of bit (1 or 0).
1749 */
1750 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1751 {
1752 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1753 }
1754
1755 /**
1756 * @brief Get Stream 0 transfer complete flag.
1757 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1758 * @param DMAx DMAx Instance
1759 * @retval State of bit (1 or 0).
1760 */
1761 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1762 {
1763 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1764 }
1765
1766 /**
1767 * @brief Get Stream 1 transfer complete flag.
1768 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1769 * @param DMAx DMAx Instance
1770 * @retval State of bit (1 or 0).
1771 */
1772 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1773 {
1774 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1775 }
1776
1777 /**
1778 * @brief Get Stream 2 transfer complete flag.
1779 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1780 * @param DMAx DMAx Instance
1781 * @retval State of bit (1 or 0).
1782 */
1783 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1784 {
1785 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1786 }
1787
1788 /**
1789 * @brief Get Stream 3 transfer complete flag.
1790 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1791 * @param DMAx DMAx Instance
1792 * @retval State of bit (1 or 0).
1793 */
1794 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1795 {
1796 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1797 }
1798
1799 /**
1800 * @brief Get Stream 4 transfer complete flag.
1801 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1802 * @param DMAx DMAx Instance
1803 * @retval State of bit (1 or 0).
1804 */
1805 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1806 {
1807 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1808 }
1809
1810 /**
1811 * @brief Get Stream 5 transfer complete flag.
1812 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1813 * @param DMAx DMAx Instance
1814 * @retval State of bit (1 or 0).
1815 */
1816 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1817 {
1818 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1819 }
1820
1821 /**
1822 * @brief Get Stream 6 transfer complete flag.
1823 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1824 * @param DMAx DMAx Instance
1825 * @retval State of bit (1 or 0).
1826 */
1827 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1828 {
1829 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1830 }
1831
1832 /**
1833 * @brief Get Stream 7 transfer complete flag.
1834 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1835 * @param DMAx DMAx Instance
1836 * @retval State of bit (1 or 0).
1837 */
1838 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1839 {
1840 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1841 }
1842
1843 /**
1844 * @brief Get Stream 0 transfer error flag.
1845 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1846 * @param DMAx DMAx Instance
1847 * @retval State of bit (1 or 0).
1848 */
1849 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1850 {
1851 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1852 }
1853
1854 /**
1855 * @brief Get Stream 1 transfer error flag.
1856 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1857 * @param DMAx DMAx Instance
1858 * @retval State of bit (1 or 0).
1859 */
1860 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1861 {
1862 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1863 }
1864
1865 /**
1866 * @brief Get Stream 2 transfer error flag.
1867 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1868 * @param DMAx DMAx Instance
1869 * @retval State of bit (1 or 0).
1870 */
1871 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1872 {
1873 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1874 }
1875
1876 /**
1877 * @brief Get Stream 3 transfer error flag.
1878 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1879 * @param DMAx DMAx Instance
1880 * @retval State of bit (1 or 0).
1881 */
1882 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1883 {
1884 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1885 }
1886
1887 /**
1888 * @brief Get Stream 4 transfer error flag.
1889 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1890 * @param DMAx DMAx Instance
1891 * @retval State of bit (1 or 0).
1892 */
1893 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1894 {
1895 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1896 }
1897
1898 /**
1899 * @brief Get Stream 5 transfer error flag.
1900 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1901 * @param DMAx DMAx Instance
1902 * @retval State of bit (1 or 0).
1903 */
1904 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1905 {
1906 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1907 }
1908
1909 /**
1910 * @brief Get Stream 6 transfer error flag.
1911 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1912 * @param DMAx DMAx Instance
1913 * @retval State of bit (1 or 0).
1914 */
1915 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1916 {
1917 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1918 }
1919
1920 /**
1921 * @brief Get Stream 7 transfer error flag.
1922 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1923 * @param DMAx DMAx Instance
1924 * @retval State of bit (1 or 0).
1925 */
1926 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1927 {
1928 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1929 }
1930
1931 /**
1932 * @brief Get Stream 0 direct mode error flag.
1933 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1934 * @param DMAx DMAx Instance
1935 * @retval State of bit (1 or 0).
1936 */
1937 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1938 {
1939 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1940 }
1941
1942 /**
1943 * @brief Get Stream 1 direct mode error flag.
1944 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1945 * @param DMAx DMAx Instance
1946 * @retval State of bit (1 or 0).
1947 */
1948 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1949 {
1950 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1951 }
1952
1953 /**
1954 * @brief Get Stream 2 direct mode error flag.
1955 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1956 * @param DMAx DMAx Instance
1957 * @retval State of bit (1 or 0).
1958 */
1959 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1960 {
1961 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1962 }
1963
1964 /**
1965 * @brief Get Stream 3 direct mode error flag.
1966 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1967 * @param DMAx DMAx Instance
1968 * @retval State of bit (1 or 0).
1969 */
1970 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1971 {
1972 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1973 }
1974
1975 /**
1976 * @brief Get Stream 4 direct mode error flag.
1977 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1978 * @param DMAx DMAx Instance
1979 * @retval State of bit (1 or 0).
1980 */
1981 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1982 {
1983 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1984 }
1985
1986 /**
1987 * @brief Get Stream 5 direct mode error flag.
1988 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1989 * @param DMAx DMAx Instance
1990 * @retval State of bit (1 or 0).
1991 */
1992 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1993 {
1994 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1995 }
1996
1997 /**
1998 * @brief Get Stream 6 direct mode error flag.
1999 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2000 * @param DMAx DMAx Instance
2001 * @retval State of bit (1 or 0).
2002 */
2003 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
2004 {
2005 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
2006 }
2007
2008 /**
2009 * @brief Get Stream 7 direct mode error flag.
2010 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2011 * @param DMAx DMAx Instance
2012 * @retval State of bit (1 or 0).
2013 */
2014 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2015 {
2016 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
2017 }
2018
2019 /**
2020 * @brief Get Stream 0 FIFO error flag.
2021 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2022 * @param DMAx DMAx Instance
2023 * @retval State of bit (1 or 0).
2024 */
2025 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2026 {
2027 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2028 }
2029
2030 /**
2031 * @brief Get Stream 1 FIFO error flag.
2032 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2033 * @param DMAx DMAx Instance
2034 * @retval State of bit (1 or 0).
2035 */
2036 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2037 {
2038 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2039 }
2040
2041 /**
2042 * @brief Get Stream 2 FIFO error flag.
2043 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2044 * @param DMAx DMAx Instance
2045 * @retval State of bit (1 or 0).
2046 */
2047 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2048 {
2049 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2050 }
2051
2052 /**
2053 * @brief Get Stream 3 FIFO error flag.
2054 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2055 * @param DMAx DMAx Instance
2056 * @retval State of bit (1 or 0).
2057 */
2058 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2059 {
2060 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2061 }
2062
2063 /**
2064 * @brief Get Stream 4 FIFO error flag.
2065 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2066 * @param DMAx DMAx Instance
2067 * @retval State of bit (1 or 0).
2068 */
2069 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2070 {
2071 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2072 }
2073
2074 /**
2075 * @brief Get Stream 5 FIFO error flag.
2076 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2077 * @param DMAx DMAx Instance
2078 * @retval State of bit (1 or 0).
2079 */
2080 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2081 {
2082 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2083 }
2084
2085 /**
2086 * @brief Get Stream 6 FIFO error flag.
2087 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2088 * @param DMAx DMAx Instance
2089 * @retval State of bit (1 or 0).
2090 */
2091 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2092 {
2093 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2094 }
2095
2096 /**
2097 * @brief Get Stream 7 FIFO error flag.
2098 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2099 * @param DMAx DMAx Instance
2100 * @retval State of bit (1 or 0).
2101 */
2102 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2103 {
2104 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2105 }
2106
2107 /**
2108 * @brief Clear Stream 0 half transfer flag.
2109 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2110 * @param DMAx DMAx Instance
2111 * @retval None
2112 */
2113 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2114 {
2115 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2116 }
2117
2118 /**
2119 * @brief Clear Stream 1 half transfer flag.
2120 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2121 * @param DMAx DMAx Instance
2122 * @retval None
2123 */
2124 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2125 {
2126 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2127 }
2128
2129 /**
2130 * @brief Clear Stream 2 half transfer flag.
2131 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2132 * @param DMAx DMAx Instance
2133 * @retval None
2134 */
2135 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2136 {
2137 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2138 }
2139
2140 /**
2141 * @brief Clear Stream 3 half transfer flag.
2142 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2143 * @param DMAx DMAx Instance
2144 * @retval None
2145 */
2146 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2147 {
2148 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2149 }
2150
2151 /**
2152 * @brief Clear Stream 4 half transfer flag.
2153 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2154 * @param DMAx DMAx Instance
2155 * @retval None
2156 */
2157 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2158 {
2159 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2160 }
2161
2162 /**
2163 * @brief Clear Stream 5 half transfer flag.
2164 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2165 * @param DMAx DMAx Instance
2166 * @retval None
2167 */
2168 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2169 {
2170 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2171 }
2172
2173 /**
2174 * @brief Clear Stream 6 half transfer flag.
2175 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2176 * @param DMAx DMAx Instance
2177 * @retval None
2178 */
2179 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2180 {
2181 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2182 }
2183
2184 /**
2185 * @brief Clear Stream 7 half transfer flag.
2186 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2187 * @param DMAx DMAx Instance
2188 * @retval None
2189 */
2190 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2191 {
2192 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2193 }
2194
2195 /**
2196 * @brief Clear Stream 0 transfer complete flag.
2197 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2198 * @param DMAx DMAx Instance
2199 * @retval None
2200 */
2201 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2202 {
2203 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2204 }
2205
2206 /**
2207 * @brief Clear Stream 1 transfer complete flag.
2208 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2209 * @param DMAx DMAx Instance
2210 * @retval None
2211 */
2212 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2213 {
2214 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2215 }
2216
2217 /**
2218 * @brief Clear Stream 2 transfer complete flag.
2219 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2220 * @param DMAx DMAx Instance
2221 * @retval None
2222 */
2223 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2224 {
2225 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2226 }
2227
2228 /**
2229 * @brief Clear Stream 3 transfer complete flag.
2230 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2231 * @param DMAx DMAx Instance
2232 * @retval None
2233 */
2234 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2235 {
2236 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2237 }
2238
2239 /**
2240 * @brief Clear Stream 4 transfer complete flag.
2241 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2242 * @param DMAx DMAx Instance
2243 * @retval None
2244 */
2245 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2246 {
2247 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2248 }
2249
2250 /**
2251 * @brief Clear Stream 5 transfer complete flag.
2252 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2253 * @param DMAx DMAx Instance
2254 * @retval None
2255 */
2256 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2257 {
2258 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2259 }
2260
2261 /**
2262 * @brief Clear Stream 6 transfer complete flag.
2263 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2264 * @param DMAx DMAx Instance
2265 * @retval None
2266 */
2267 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2268 {
2269 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2270 }
2271
2272 /**
2273 * @brief Clear Stream 7 transfer complete flag.
2274 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2275 * @param DMAx DMAx Instance
2276 * @retval None
2277 */
2278 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2279 {
2280 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2281 }
2282
2283 /**
2284 * @brief Clear Stream 0 transfer error flag.
2285 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2286 * @param DMAx DMAx Instance
2287 * @retval None
2288 */
2289 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2290 {
2291 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2292 }
2293
2294 /**
2295 * @brief Clear Stream 1 transfer error flag.
2296 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2297 * @param DMAx DMAx Instance
2298 * @retval None
2299 */
2300 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2301 {
2302 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2303 }
2304
2305 /**
2306 * @brief Clear Stream 2 transfer error flag.
2307 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2308 * @param DMAx DMAx Instance
2309 * @retval None
2310 */
2311 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2312 {
2313 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2314 }
2315
2316 /**
2317 * @brief Clear Stream 3 transfer error flag.
2318 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2319 * @param DMAx DMAx Instance
2320 * @retval None
2321 */
2322 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2323 {
2324 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2325 }
2326
2327 /**
2328 * @brief Clear Stream 4 transfer error flag.
2329 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2330 * @param DMAx DMAx Instance
2331 * @retval None
2332 */
2333 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2334 {
2335 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2336 }
2337
2338 /**
2339 * @brief Clear Stream 5 transfer error flag.
2340 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2341 * @param DMAx DMAx Instance
2342 * @retval None
2343 */
2344 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2345 {
2346 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2347 }
2348
2349 /**
2350 * @brief Clear Stream 6 transfer error flag.
2351 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2352 * @param DMAx DMAx Instance
2353 * @retval None
2354 */
2355 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2356 {
2357 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2358 }
2359
2360 /**
2361 * @brief Clear Stream 7 transfer error flag.
2362 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2363 * @param DMAx DMAx Instance
2364 * @retval None
2365 */
2366 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2367 {
2368 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2369 }
2370
2371 /**
2372 * @brief Clear Stream 0 direct mode error flag.
2373 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2374 * @param DMAx DMAx Instance
2375 * @retval None
2376 */
2377 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2378 {
2379 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2380 }
2381
2382 /**
2383 * @brief Clear Stream 1 direct mode error flag.
2384 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2385 * @param DMAx DMAx Instance
2386 * @retval None
2387 */
2388 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2389 {
2390 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2391 }
2392
2393 /**
2394 * @brief Clear Stream 2 direct mode error flag.
2395 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2396 * @param DMAx DMAx Instance
2397 * @retval None
2398 */
2399 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2400 {
2401 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2402 }
2403
2404 /**
2405 * @brief Clear Stream 3 direct mode error flag.
2406 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2407 * @param DMAx DMAx Instance
2408 * @retval None
2409 */
2410 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2411 {
2412 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2413 }
2414
2415 /**
2416 * @brief Clear Stream 4 direct mode error flag.
2417 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2418 * @param DMAx DMAx Instance
2419 * @retval None
2420 */
2421 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2422 {
2423 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2424 }
2425
2426 /**
2427 * @brief Clear Stream 5 direct mode error flag.
2428 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2429 * @param DMAx DMAx Instance
2430 * @retval None
2431 */
2432 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2433 {
2434 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2435 }
2436
2437 /**
2438 * @brief Clear Stream 6 direct mode error flag.
2439 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2440 * @param DMAx DMAx Instance
2441 * @retval None
2442 */
2443 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2444 {
2445 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2446 }
2447
2448 /**
2449 * @brief Clear Stream 7 direct mode error flag.
2450 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2451 * @param DMAx DMAx Instance
2452 * @retval None
2453 */
2454 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2455 {
2456 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2457 }
2458
2459 /**
2460 * @brief Clear Stream 0 FIFO error flag.
2461 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2462 * @param DMAx DMAx Instance
2463 * @retval None
2464 */
2465 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2466 {
2467 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2468 }
2469
2470 /**
2471 * @brief Clear Stream 1 FIFO error flag.
2472 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2473 * @param DMAx DMAx Instance
2474 * @retval None
2475 */
2476 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2477 {
2478 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2479 }
2480
2481 /**
2482 * @brief Clear Stream 2 FIFO error flag.
2483 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2484 * @param DMAx DMAx Instance
2485 * @retval None
2486 */
2487 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2488 {
2489 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2490 }
2491
2492 /**
2493 * @brief Clear Stream 3 FIFO error flag.
2494 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2495 * @param DMAx DMAx Instance
2496 * @retval None
2497 */
2498 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2499 {
2500 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2501 }
2502
2503 /**
2504 * @brief Clear Stream 4 FIFO error flag.
2505 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2506 * @param DMAx DMAx Instance
2507 * @retval None
2508 */
2509 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2510 {
2511 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2512 }
2513
2514 /**
2515 * @brief Clear Stream 5 FIFO error flag.
2516 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2517 * @param DMAx DMAx Instance
2518 * @retval None
2519 */
2520 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2521 {
2522 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2523 }
2524
2525 /**
2526 * @brief Clear Stream 6 FIFO error flag.
2527 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2528 * @param DMAx DMAx Instance
2529 * @retval None
2530 */
2531 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2532 {
2533 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2534 }
2535
2536 /**
2537 * @brief Clear Stream 7 FIFO error flag.
2538 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2539 * @param DMAx DMAx Instance
2540 * @retval None
2541 */
2542 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2543 {
2544 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2545 }
2546
2547 /**
2548 * @}
2549 */
2550
2551 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2552 * @{
2553 */
2554
2555 /**
2556 * @brief Enable Half transfer interrupt.
2557 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2558 * @param DMAx DMAx Instance
2559 * @param Stream This parameter can be one of the following values:
2560 * @arg @ref LL_DMA_STREAM_0
2561 * @arg @ref LL_DMA_STREAM_1
2562 * @arg @ref LL_DMA_STREAM_2
2563 * @arg @ref LL_DMA_STREAM_3
2564 * @arg @ref LL_DMA_STREAM_4
2565 * @arg @ref LL_DMA_STREAM_5
2566 * @arg @ref LL_DMA_STREAM_6
2567 * @arg @ref LL_DMA_STREAM_7
2568 * @retval None
2569 */
2570 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2571 {
2572 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2573 }
2574
2575 /**
2576 * @brief Enable Transfer error interrupt.
2577 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2578 * @param DMAx DMAx Instance
2579 * @param Stream This parameter can be one of the following values:
2580 * @arg @ref LL_DMA_STREAM_0
2581 * @arg @ref LL_DMA_STREAM_1
2582 * @arg @ref LL_DMA_STREAM_2
2583 * @arg @ref LL_DMA_STREAM_3
2584 * @arg @ref LL_DMA_STREAM_4
2585 * @arg @ref LL_DMA_STREAM_5
2586 * @arg @ref LL_DMA_STREAM_6
2587 * @arg @ref LL_DMA_STREAM_7
2588 * @retval None
2589 */
2590 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2591 {
2592 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2593 }
2594
2595 /**
2596 * @brief Enable Transfer complete interrupt.
2597 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2598 * @param DMAx DMAx Instance
2599 * @param Stream This parameter can be one of the following values:
2600 * @arg @ref LL_DMA_STREAM_0
2601 * @arg @ref LL_DMA_STREAM_1
2602 * @arg @ref LL_DMA_STREAM_2
2603 * @arg @ref LL_DMA_STREAM_3
2604 * @arg @ref LL_DMA_STREAM_4
2605 * @arg @ref LL_DMA_STREAM_5
2606 * @arg @ref LL_DMA_STREAM_6
2607 * @arg @ref LL_DMA_STREAM_7
2608 * @retval None
2609 */
2610 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2611 {
2612 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2613 }
2614
2615 /**
2616 * @brief Enable Direct mode error interrupt.
2617 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2618 * @param DMAx DMAx Instance
2619 * @param Stream This parameter can be one of the following values:
2620 * @arg @ref LL_DMA_STREAM_0
2621 * @arg @ref LL_DMA_STREAM_1
2622 * @arg @ref LL_DMA_STREAM_2
2623 * @arg @ref LL_DMA_STREAM_3
2624 * @arg @ref LL_DMA_STREAM_4
2625 * @arg @ref LL_DMA_STREAM_5
2626 * @arg @ref LL_DMA_STREAM_6
2627 * @arg @ref LL_DMA_STREAM_7
2628 * @retval None
2629 */
2630 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2631 {
2632 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2633 }
2634
2635 /**
2636 * @brief Enable FIFO error interrupt.
2637 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2638 * @param DMAx DMAx Instance
2639 * @param Stream This parameter can be one of the following values:
2640 * @arg @ref LL_DMA_STREAM_0
2641 * @arg @ref LL_DMA_STREAM_1
2642 * @arg @ref LL_DMA_STREAM_2
2643 * @arg @ref LL_DMA_STREAM_3
2644 * @arg @ref LL_DMA_STREAM_4
2645 * @arg @ref LL_DMA_STREAM_5
2646 * @arg @ref LL_DMA_STREAM_6
2647 * @arg @ref LL_DMA_STREAM_7
2648 * @retval None
2649 */
2650 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2651 {
2652 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2653 }
2654
2655 /**
2656 * @brief Disable Half transfer interrupt.
2657 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2658 * @param DMAx DMAx Instance
2659 * @param Stream This parameter can be one of the following values:
2660 * @arg @ref LL_DMA_STREAM_0
2661 * @arg @ref LL_DMA_STREAM_1
2662 * @arg @ref LL_DMA_STREAM_2
2663 * @arg @ref LL_DMA_STREAM_3
2664 * @arg @ref LL_DMA_STREAM_4
2665 * @arg @ref LL_DMA_STREAM_5
2666 * @arg @ref LL_DMA_STREAM_6
2667 * @arg @ref LL_DMA_STREAM_7
2668 * @retval None
2669 */
2670 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2671 {
2672 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2673 }
2674
2675 /**
2676 * @brief Disable Transfer error interrupt.
2677 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2678 * @param DMAx DMAx Instance
2679 * @param Stream This parameter can be one of the following values:
2680 * @arg @ref LL_DMA_STREAM_0
2681 * @arg @ref LL_DMA_STREAM_1
2682 * @arg @ref LL_DMA_STREAM_2
2683 * @arg @ref LL_DMA_STREAM_3
2684 * @arg @ref LL_DMA_STREAM_4
2685 * @arg @ref LL_DMA_STREAM_5
2686 * @arg @ref LL_DMA_STREAM_6
2687 * @arg @ref LL_DMA_STREAM_7
2688 * @retval None
2689 */
2690 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2691 {
2692 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2693 }
2694
2695 /**
2696 * @brief Disable Transfer complete interrupt.
2697 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2698 * @param DMAx DMAx Instance
2699 * @param Stream This parameter can be one of the following values:
2700 * @arg @ref LL_DMA_STREAM_0
2701 * @arg @ref LL_DMA_STREAM_1
2702 * @arg @ref LL_DMA_STREAM_2
2703 * @arg @ref LL_DMA_STREAM_3
2704 * @arg @ref LL_DMA_STREAM_4
2705 * @arg @ref LL_DMA_STREAM_5
2706 * @arg @ref LL_DMA_STREAM_6
2707 * @arg @ref LL_DMA_STREAM_7
2708 * @retval None
2709 */
2710 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2711 {
2712 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2713 }
2714
2715 /**
2716 * @brief Disable Direct mode error interrupt.
2717 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2718 * @param DMAx DMAx Instance
2719 * @param Stream This parameter can be one of the following values:
2720 * @arg @ref LL_DMA_STREAM_0
2721 * @arg @ref LL_DMA_STREAM_1
2722 * @arg @ref LL_DMA_STREAM_2
2723 * @arg @ref LL_DMA_STREAM_3
2724 * @arg @ref LL_DMA_STREAM_4
2725 * @arg @ref LL_DMA_STREAM_5
2726 * @arg @ref LL_DMA_STREAM_6
2727 * @arg @ref LL_DMA_STREAM_7
2728 * @retval None
2729 */
2730 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2731 {
2732 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2733 }
2734
2735 /**
2736 * @brief Disable FIFO error interrupt.
2737 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2738 * @param DMAx DMAx Instance
2739 * @param Stream This parameter can be one of the following values:
2740 * @arg @ref LL_DMA_STREAM_0
2741 * @arg @ref LL_DMA_STREAM_1
2742 * @arg @ref LL_DMA_STREAM_2
2743 * @arg @ref LL_DMA_STREAM_3
2744 * @arg @ref LL_DMA_STREAM_4
2745 * @arg @ref LL_DMA_STREAM_5
2746 * @arg @ref LL_DMA_STREAM_6
2747 * @arg @ref LL_DMA_STREAM_7
2748 * @retval None
2749 */
2750 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2751 {
2752 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2753 }
2754
2755 /**
2756 * @brief Check if Half transfer interrup is enabled.
2757 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2758 * @param DMAx DMAx Instance
2759 * @param Stream This parameter can be one of the following values:
2760 * @arg @ref LL_DMA_STREAM_0
2761 * @arg @ref LL_DMA_STREAM_1
2762 * @arg @ref LL_DMA_STREAM_2
2763 * @arg @ref LL_DMA_STREAM_3
2764 * @arg @ref LL_DMA_STREAM_4
2765 * @arg @ref LL_DMA_STREAM_5
2766 * @arg @ref LL_DMA_STREAM_6
2767 * @arg @ref LL_DMA_STREAM_7
2768 * @retval State of bit (1 or 0).
2769 */
2770 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2771 {
2772 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2773 }
2774
2775 /**
2776 * @brief Check if Transfer error nterrup is enabled.
2777 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2778 * @param DMAx DMAx Instance
2779 * @param Stream This parameter can be one of the following values:
2780 * @arg @ref LL_DMA_STREAM_0
2781 * @arg @ref LL_DMA_STREAM_1
2782 * @arg @ref LL_DMA_STREAM_2
2783 * @arg @ref LL_DMA_STREAM_3
2784 * @arg @ref LL_DMA_STREAM_4
2785 * @arg @ref LL_DMA_STREAM_5
2786 * @arg @ref LL_DMA_STREAM_6
2787 * @arg @ref LL_DMA_STREAM_7
2788 * @retval State of bit (1 or 0).
2789 */
2790 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2791 {
2792 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2793 }
2794
2795 /**
2796 * @brief Check if Transfer complete interrup is enabled.
2797 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2798 * @param DMAx DMAx Instance
2799 * @param Stream This parameter can be one of the following values:
2800 * @arg @ref LL_DMA_STREAM_0
2801 * @arg @ref LL_DMA_STREAM_1
2802 * @arg @ref LL_DMA_STREAM_2
2803 * @arg @ref LL_DMA_STREAM_3
2804 * @arg @ref LL_DMA_STREAM_4
2805 * @arg @ref LL_DMA_STREAM_5
2806 * @arg @ref LL_DMA_STREAM_6
2807 * @arg @ref LL_DMA_STREAM_7
2808 * @retval State of bit (1 or 0).
2809 */
2810 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2811 {
2812 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2813 }
2814
2815 /**
2816 * @brief Check if Direct mode error interrupt is enabled.
2817 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2818 * @param DMAx DMAx Instance
2819 * @param Stream This parameter can be one of the following values:
2820 * @arg @ref LL_DMA_STREAM_0
2821 * @arg @ref LL_DMA_STREAM_1
2822 * @arg @ref LL_DMA_STREAM_2
2823 * @arg @ref LL_DMA_STREAM_3
2824 * @arg @ref LL_DMA_STREAM_4
2825 * @arg @ref LL_DMA_STREAM_5
2826 * @arg @ref LL_DMA_STREAM_6
2827 * @arg @ref LL_DMA_STREAM_7
2828 * @retval State of bit (1 or 0).
2829 */
2830 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2831 {
2832 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2833 }
2834
2835 /**
2836 * @brief Check if FIFO error interrup is enabled.
2837 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2838 * @param DMAx DMAx Instance
2839 * @param Stream This parameter can be one of the following values:
2840 * @arg @ref LL_DMA_STREAM_0
2841 * @arg @ref LL_DMA_STREAM_1
2842 * @arg @ref LL_DMA_STREAM_2
2843 * @arg @ref LL_DMA_STREAM_3
2844 * @arg @ref LL_DMA_STREAM_4
2845 * @arg @ref LL_DMA_STREAM_5
2846 * @arg @ref LL_DMA_STREAM_6
2847 * @arg @ref LL_DMA_STREAM_7
2848 * @retval State of bit (1 or 0).
2849 */
2850 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2851 {
2852 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2853 }
2854
2855 /**
2856 * @}
2857 */
2858
2859 #if defined(USE_FULL_LL_DRIVER)
2860 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2861 * @{
2862 */
2863
2864 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2865 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2866 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2867
2868 /**
2869 * @}
2870 */
2871 #endif /* USE_FULL_LL_DRIVER */
2872
2873 /**
2874 * @}
2875 */
2876
2877 /**
2878 * @}
2879 */
2880
2881 #endif /* DMA1 || DMA2 */
2882
2883 /**
2884 * @}
2885 */
2886
2887 #ifdef __cplusplus
2888 }
2889 #endif
2890
2891 #endif /* __STM32F7xx_LL_DMA_H */
2892
2893 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/