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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_dma2d.h
blobf8e1f1131154cfdaeb9df7c84485a652712c4082
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_LL_DMA2D_H
22 #define STM32F7xx_LL_DMA2D_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA2D)
36
37 /** @defgroup DMA2D_LL DMA2D
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
47 * @{
48 */
49
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
58 * @{
59 */
60
61 /**
62 * @brief LL DMA2D Init Structure Definition
63 */
64 typedef struct
65 {
66 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
67 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
68
69 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
75
76 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
77 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
78 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
79 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
80 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
81 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
82
83 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
84 function @ref LL_DMA2D_ConfigOutputColor(). */
85
86 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
87 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
88 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
89 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
90 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
91 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
92
93 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
94 function @ref LL_DMA2D_ConfigOutputColor(). */
95
96 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
98 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
99 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
100 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
101 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
102
103 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
104 function @ref LL_DMA2D_ConfigOutputColor(). */
105
106 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
108 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
109 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
110 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
111
112 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
113 function @ref LL_DMA2D_ConfigOutputColor(). */
114
115 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
116 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
117
118 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
119
120
121
122 uint32_t LineOffset; /*!< Specifies the output line offset value.
123 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
124
125 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
126
127 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
128 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
129
130 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
131
132 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
133 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
134
135 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
136
137 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
138 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
139 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
140
141 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
142
143 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
144 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
145
146 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
147 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
148
149 } LL_DMA2D_InitTypeDef;
150
151 /**
152 * @brief LL DMA2D Layer Configuration Structure Definition
153 */
154 typedef struct
155 {
156 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
157 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
158
159 This parameter can be modified afterwards using unitary functions
160 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
161 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
162
163 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
164 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
165
166 This parameter can be modified afterwards using unitary functions
167 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
168 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
169
170 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
171 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
172
173 This parameter can be modified afterwards using unitary functions
174 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
175 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
176
177 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
178 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
179
180 This parameter can be modified afterwards using unitary functions
181 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
182 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
183
184 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
185 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
186
187 This parameter can be modified afterwards using unitary functions
188 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
189 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
190
191 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
192 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
193
194 This parameter can be modified afterwards using unitary functions
195 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
196 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
197
198 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
199 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
200
201 This parameter can be modified afterwards using unitary functions
202 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
203 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
204
205 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
206 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
207
208 This parameter can be modified afterwards using unitary functions
209 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
210 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
211
212 uint32_t Green; /*!< Specifies the foreground or background Green color value.
213 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
214
215 This parameter can be modified afterwards using unitary functions
216 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
217 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
218
219 uint32_t Red; /*!< Specifies the foreground or background Red color value.
220 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
221
222 This parameter can be modified afterwards using unitary functions
223 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
224 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
225
226 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
227 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
228
229 This parameter can be modified afterwards using unitary functions
230 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
231 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
232
233 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
234 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
235 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
236
237 This parameter can be modified afterwards using unitary functions
238 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
239 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
240
241 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
242 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
243
244 This parameter can be modified afterwards using unitary functions
245 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
246 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
247 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
248
249
250 } LL_DMA2D_LayerCfgTypeDef;
251
252 /**
253 * @brief LL DMA2D Output Color Structure Definition
254 */
255 typedef struct
256 {
257 uint32_t ColorMode; /*!< Specifies the color format of the output image.
258 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
259
260 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
261
262 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
263 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
264 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
265 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
266 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
267 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
268
269 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
270 function @ref LL_DMA2D_ConfigOutputColor(). */
271
272 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
273 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
274 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
275 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
276 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
277 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
278
279 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
280 function @ref LL_DMA2D_ConfigOutputColor(). */
281
282 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
283 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
284 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
285 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
286 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
287 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
288
289 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
290 function @ref LL_DMA2D_ConfigOutputColor(). */
291
292 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
293 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
294 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
295 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
296 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
297
298 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
299 function @ref LL_DMA2D_ConfigOutputColor(). */
300
301 } LL_DMA2D_ColorTypeDef;
302
303 /**
304 * @}
305 */
306 #endif /* USE_FULL_LL_DRIVER */
307
308 /* Exported constants --------------------------------------------------------*/
309 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
310 * @{
311 */
312
313 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
314 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
315 * @{
316 */
317 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
318 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
319 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
320 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
321 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
322 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
323 /**
324 * @}
325 */
326
327 /** @defgroup DMA2D_LL_EC_IT IT Defines
328 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
329 * @{
330 */
331 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
332 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
333 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
334 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
335 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
336 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
337 /**
338 * @}
339 */
340
341 /** @defgroup DMA2D_LL_EC_MODE Mode
342 * @{
343 */
344 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
345 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
346 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
347 #define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
348 /**
349 * @}
350 */
351
352 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
353 * @{
354 */
355 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
356 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
357 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
358 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
359 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
360 /**
361 * @}
362 */
363
364 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
365 * @{
366 */
367 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
368 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
369 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
370 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
371 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
372 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
373 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
374 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
375 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
376 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
377 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
378 /**
379 * @}
380 */
381
382 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
383 * @{
384 */
385 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
386 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
387 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
388 with original alpha channel value */
389 /**
390 * @}
391 */
392
393
394 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
395 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
396 * @{
397 */
398 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
399 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
400 /**
401 * @}
402 */
403
404 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
405 * @{
406 */
407 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
408 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
409 /**
410 * @}
411 */
412
413 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
414
415
416 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
417 * @{
418 */
419 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
420 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
421 /**
422 * @}
423 */
424
425
426 /**
427 * @}
428 */
429
430 /* Exported macro ------------------------------------------------------------*/
431 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
432 * @{
433 */
434
435 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
436 * @{
437 */
438
439 /**
440 * @brief Write a value in DMA2D register.
441 * @param __INSTANCE__ DMA2D Instance
442 * @param __REG__ Register to be written
443 * @param __VALUE__ Value to be written in the register
444 * @retval None
445 */
446 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
447
448 /**
449 * @brief Read a value in DMA2D register.
450 * @param __INSTANCE__ DMA2D Instance
451 * @param __REG__ Register to be read
452 * @retval Register value
453 */
454 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
455 /**
456 * @}
457 */
458
459 /**
460 * @}
461 */
462
463 /* Exported functions --------------------------------------------------------*/
464 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
465 * @{
466 */
467
468 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
469 * @{
470 */
471
472 /**
473 * @brief Start a DMA2D transfer.
474 * @rmtoll CR START LL_DMA2D_Start
475 * @param DMA2Dx DMA2D Instance
476 * @retval None
477 */
478 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
479 {
480 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
481 }
482
483 /**
484 * @brief Indicate if a DMA2D transfer is ongoing.
485 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
486 * @param DMA2Dx DMA2D Instance
487 * @retval State of bit (1 or 0).
488 */
489 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
490 {
491 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
492 }
493
494 /**
495 * @brief Suspend DMA2D transfer.
496 * @note This API can be used to suspend automatic foreground or background CLUT loading.
497 * @rmtoll CR SUSP LL_DMA2D_Suspend
498 * @param DMA2Dx DMA2D Instance
499 * @retval None
500 */
501 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
502 {
503 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
504 }
505
506 /**
507 * @brief Resume DMA2D transfer.
508 * @note This API can be used to resume automatic foreground or background CLUT loading.
509 * @rmtoll CR SUSP LL_DMA2D_Resume
510 * @param DMA2Dx DMA2D Instance
511 * @retval None
512 */
513 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
514 {
515 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
516 }
517
518 /**
519 * @brief Indicate if DMA2D transfer is suspended.
520 * @note This API can be used to indicate whether or not automatic foreground or
521 * background CLUT loading is suspended.
522 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
523 * @param DMA2Dx DMA2D Instance
524 * @retval State of bit (1 or 0).
525 */
526 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
527 {
528 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
529 }
530
531 /**
532 * @brief Abort DMA2D transfer.
533 * @note This API can be used to abort automatic foreground or background CLUT loading.
534 * @rmtoll CR ABORT LL_DMA2D_Abort
535 * @param DMA2Dx DMA2D Instance
536 * @retval None
537 */
538 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
539 {
540 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
541 }
542
543 /**
544 * @brief Indicate if DMA2D transfer is aborted.
545 * @note This API can be used to indicate whether or not automatic foreground or
546 * background CLUT loading is aborted.
547 * @rmtoll CR ABORT LL_DMA2D_IsAborted
548 * @param DMA2Dx DMA2D Instance
549 * @retval State of bit (1 or 0).
550 */
551 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
552 {
553 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
554 }
555
556 /**
557 * @brief Set DMA2D mode.
558 * @rmtoll CR MODE LL_DMA2D_SetMode
559 * @param DMA2Dx DMA2D Instance
560 * @param Mode This parameter can be one of the following values:
561 * @arg @ref LL_DMA2D_MODE_M2M
562 * @arg @ref LL_DMA2D_MODE_M2M_PFC
563 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
564 * @arg @ref LL_DMA2D_MODE_R2M
565 * @retval None
566 */
567 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
568 {
569 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
570 }
571
572 /**
573 * @brief Return DMA2D mode
574 * @rmtoll CR MODE LL_DMA2D_GetMode
575 * @param DMA2Dx DMA2D Instance
576 * @retval Returned value can be one of the following values:
577 * @arg @ref LL_DMA2D_MODE_M2M
578 * @arg @ref LL_DMA2D_MODE_M2M_PFC
579 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
580 * @arg @ref LL_DMA2D_MODE_R2M
581 */
582 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
583 {
584 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
585 }
586
587 /**
588 * @brief Set DMA2D output color mode.
589 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
590 * @param DMA2Dx DMA2D Instance
591 * @param ColorMode This parameter can be one of the following values:
592 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
593 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
594 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
595 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
596 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
597 * @retval None
598 */
599 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
600 {
601 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
602 }
603
604 /**
605 * @brief Return DMA2D output color mode.
606 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
607 * @param DMA2Dx DMA2D Instance
608 * @retval Returned value can be one of the following values:
609 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
610 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
611 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
612 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
613 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
614 */
615 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
616 {
617 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
618 }
619
620 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
621 /**
622 * @brief Set DMA2D output Red Blue swap mode.
623 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
624 * @param DMA2Dx DMA2D Instance
625 * @param RBSwapMode This parameter can be one of the following values:
626 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
627 * @arg @ref LL_DMA2D_RB_MODE_SWAP
628 * @retval None
629 */
630 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
631 {
632 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
633 }
634
635 /**
636 * @brief Return DMA2D output Red Blue swap mode.
637 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
638 * @param DMA2Dx DMA2D Instance
639 * @retval Returned value can be one of the following values:
640 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
641 * @arg @ref LL_DMA2D_RB_MODE_SWAP
642 */
643 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
644 {
645 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
646 }
647
648 /**
649 * @brief Set DMA2D output alpha inversion mode.
650 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
651 * @param DMA2Dx DMA2D Instance
652 * @param AlphaInversionMode This parameter can be one of the following values:
653 * @arg @ref LL_DMA2D_ALPHA_REGULAR
654 * @arg @ref LL_DMA2D_ALPHA_INVERTED
655 * @retval None
656 */
657 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
658 {
659 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
660 }
661
662 /**
663 * @brief Return DMA2D output alpha inversion mode.
664 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
665 * @param DMA2Dx DMA2D Instance
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_DMA2D_ALPHA_REGULAR
668 * @arg @ref LL_DMA2D_ALPHA_INVERTED
669 */
670 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
671 {
672 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
673 }
674
675 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
676
677
678
679 /**
680 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
681 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
682 * @param DMA2Dx DMA2D Instance
683 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
684 * @retval None
685 */
686 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
687 {
688 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
689 }
690
691 /**
692 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
693 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
694 * @param DMA2Dx DMA2D Instance
695 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
696 */
697 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
698 {
699 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
700 }
701
702 /**
703 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
704 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
705 * @param DMA2Dx DMA2D Instance
706 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
707 * @retval None
708 */
709 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
710 {
711 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
712 }
713
714 /**
715 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
716 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
717 * @param DMA2Dx DMA2D Instance
718 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
719 */
720 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
721 {
722 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
723 }
724
725 /**
726 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
727 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
728 * @param DMA2Dx DMA2D Instance
729 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
730 * @retval None
731 */
732 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
733 {
734 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
735 }
736
737 /**
738 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
739 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
740 * @param DMA2Dx DMA2D Instance
741 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
742 */
743 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
744 {
745 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
746 }
747
748 /**
749 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
750 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
751 * @param DMA2Dx DMA2D Instance
752 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
753 * @retval None
754 */
755 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
756 {
757 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
758 }
759
760 /**
761 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
762 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
763 * @param DMA2Dx DMA2D Instance
764 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
765 */
766 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
767 {
768 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
769 }
770
771 /**
772 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
773 * @note Output color format depends on output color mode, ARGB8888, RGB888,
774 * RGB565, ARGB1555 or ARGB4444.
775 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
776 * with respect to color mode is not done by the user code.
777 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
778 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
779 * OCOLR RED LL_DMA2D_SetOutputColor\n
780 * OCOLR ALPHA LL_DMA2D_SetOutputColor
781 * @param DMA2Dx DMA2D Instance
782 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
783 * @retval None
784 */
785 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
786 {
787 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
788 OutputColor);
789 }
790
791 /**
792 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
793 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
794 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
795 * as set by @ref LL_DMA2D_SetOutputColorMode.
796 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
797 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
798 * OCOLR RED LL_DMA2D_GetOutputColor\n
799 * OCOLR ALPHA LL_DMA2D_GetOutputColor
800 * @param DMA2Dx DMA2D Instance
801 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
802 */
803 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
804 {
805 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
806 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
807 }
808
809 /**
810 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
811 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
812 * @param DMA2Dx DMA2D Instance
813 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
814 * @retval None
815 */
816 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
817 {
818 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
819 }
820
821 /**
822 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
823 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
824 * @param DMA2Dx DMA2D Instance
825 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
826 */
827 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
828 {
829 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
830 }
831
832 /**
833 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
834 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
835 * @param DMA2Dx DMA2D Instance
836 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
837 * @retval None
838 */
839 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
840 {
841 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
842 }
843
844 /**
845 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
846 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
847 * @param DMA2Dx DMA2D Instance
848 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
849 */
850 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
851 {
852 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
853 }
854
855 /**
856 * @brief Enable DMA2D dead time functionality.
857 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
858 * @param DMA2Dx DMA2D Instance
859 * @retval None
860 */
861 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
862 {
863 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
864 }
865
866 /**
867 * @brief Disable DMA2D dead time functionality.
868 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
869 * @param DMA2Dx DMA2D Instance
870 * @retval None
871 */
872 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
873 {
874 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
875 }
876
877 /**
878 * @brief Indicate if DMA2D dead time functionality is enabled.
879 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
880 * @param DMA2Dx DMA2D Instance
881 * @retval State of bit (1 or 0).
882 */
883 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
884 {
885 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
886 }
887
888 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
889 * @{
890 */
891
892 /**
893 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
894 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
895 * @param DMA2Dx DMA2D Instance
896 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
897 * @retval None
898 */
899 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
900 {
901 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
902 }
903
904 /**
905 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
906 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
907 * @param DMA2Dx DMA2D Instance
908 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
909 */
910 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
911 {
912 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
913 }
914
915 /**
916 * @brief Enable DMA2D foreground CLUT loading.
917 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
918 * @param DMA2Dx DMA2D Instance
919 * @retval None
920 */
921 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
922 {
923 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
924 }
925
926 /**
927 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
928 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
929 * @param DMA2Dx DMA2D Instance
930 * @retval State of bit (1 or 0).
931 */
932 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
933 {
934 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
935 }
936
937 /**
938 * @brief Set DMA2D foreground color mode.
939 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
940 * @param DMA2Dx DMA2D Instance
941 * @param ColorMode This parameter can be one of the following values:
942 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
943 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
944 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
945 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
946 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
947 * @arg @ref LL_DMA2D_INPUT_MODE_L8
948 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
949 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
950 * @arg @ref LL_DMA2D_INPUT_MODE_L4
951 * @arg @ref LL_DMA2D_INPUT_MODE_A8
952 * @arg @ref LL_DMA2D_INPUT_MODE_A4
953 * @retval None
954 */
955 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
956 {
957 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
958 }
959
960 /**
961 * @brief Return DMA2D foreground color mode.
962 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
963 * @param DMA2Dx DMA2D Instance
964 * @retval Returned value can be one of the following values:
965 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
966 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
967 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
968 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
969 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
970 * @arg @ref LL_DMA2D_INPUT_MODE_L8
971 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
972 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
973 * @arg @ref LL_DMA2D_INPUT_MODE_L4
974 * @arg @ref LL_DMA2D_INPUT_MODE_A8
975 * @arg @ref LL_DMA2D_INPUT_MODE_A4
976 */
977 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
978 {
979 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
980 }
981
982 /**
983 * @brief Set DMA2D foreground alpha mode.
984 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
985 * @param DMA2Dx DMA2D Instance
986 * @param AphaMode This parameter can be one of the following values:
987 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
988 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
989 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
990 * @retval None
991 */
992 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
993 {
994 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
995 }
996
997 /**
998 * @brief Return DMA2D foreground alpha mode.
999 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1000 * @param DMA2Dx DMA2D Instance
1001 * @retval Returned value can be one of the following values:
1002 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1003 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1004 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1005 */
1006 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1007 {
1008 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1009 }
1010
1011 /**
1012 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1013 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1014 * @param DMA2Dx DMA2D Instance
1015 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1016 * @retval None
1017 */
1018 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1019 {
1020 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1021 }
1022
1023 /**
1024 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1025 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1026 * @param DMA2Dx DMA2D Instance
1027 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1028 */
1029 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1030 {
1031 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1032 }
1033
1034 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1035 /**
1036 * @brief Set DMA2D foreground Red Blue swap mode.
1037 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1038 * @param DMA2Dx DMA2D Instance
1039 * @param RBSwapMode This parameter can be one of the following values:
1040 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1041 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1042 * @retval None
1043 */
1044 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1045 {
1046 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1047 }
1048
1049 /**
1050 * @brief Return DMA2D foreground Red Blue swap mode.
1051 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1052 * @param DMA2Dx DMA2D Instance
1053 * @retval Returned value can be one of the following values:
1054 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1055 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1056 */
1057 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1058 {
1059 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1060 }
1061
1062 /**
1063 * @brief Set DMA2D foreground alpha inversion mode.
1064 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1065 * @param DMA2Dx DMA2D Instance
1066 * @param AlphaInversionMode This parameter can be one of the following values:
1067 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1068 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1069 * @retval None
1070 */
1071 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1072 {
1073 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1074 }
1075
1076 /**
1077 * @brief Return DMA2D foreground alpha inversion mode.
1078 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1079 * @param DMA2Dx DMA2D Instance
1080 * @retval Returned value can be one of the following values:
1081 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1082 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1083 */
1084 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1085 {
1086 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1087 }
1088
1089 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1090
1091 /**
1092 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1093 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1094 * @param DMA2Dx DMA2D Instance
1095 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1096 * @retval None
1097 */
1098 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1099 {
1100 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1101 }
1102
1103 /**
1104 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1105 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1106 * @param DMA2Dx DMA2D Instance
1107 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1108 */
1109 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1110 {
1111 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1112 }
1113
1114 /**
1115 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1116 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1117 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1118 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1119 * @param DMA2Dx DMA2D Instance
1120 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1121 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1122 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1123 * @retval None
1124 */
1125 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1126 {
1127 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1128 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1129 }
1130
1131 /**
1132 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1133 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1134 * @param DMA2Dx DMA2D Instance
1135 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1136 * @retval None
1137 */
1138 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1139 {
1140 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1141 }
1142
1143 /**
1144 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1145 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1146 * @param DMA2Dx DMA2D Instance
1147 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1148 */
1149 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1150 {
1151 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1152 }
1153
1154 /**
1155 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1156 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1157 * @param DMA2Dx DMA2D Instance
1158 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1159 * @retval None
1160 */
1161 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1162 {
1163 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1164 }
1165
1166 /**
1167 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1168 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1169 * @param DMA2Dx DMA2D Instance
1170 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1171 */
1172 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1173 {
1174 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1175 }
1176
1177 /**
1178 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1179 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1180 * @param DMA2Dx DMA2D Instance
1181 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1182 * @retval None
1183 */
1184 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1185 {
1186 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1187 }
1188
1189 /**
1190 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1191 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1192 * @param DMA2Dx DMA2D Instance
1193 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1194 */
1195 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1196 {
1197 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1198 }
1199
1200 /**
1201 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1202 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1203 * @param DMA2Dx DMA2D Instance
1204 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1205 * @retval None
1206 */
1207 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1208 {
1209 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1210 }
1211
1212 /**
1213 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1214 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1215 * @param DMA2Dx DMA2D Instance
1216 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1217 */
1218 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1219 {
1220 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1221 }
1222
1223 /**
1224 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1225 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1226 * @param DMA2Dx DMA2D Instance
1227 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1228 * @retval None
1229 */
1230 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1231 {
1232 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1233 }
1234
1235 /**
1236 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1237 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1238 * @param DMA2Dx DMA2D Instance
1239 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1240 */
1241 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1242 {
1243 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1244 }
1245
1246 /**
1247 * @brief Set DMA2D foreground CLUT color mode.
1248 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1249 * @param DMA2Dx DMA2D Instance
1250 * @param CLUTColorMode This parameter can be one of the following values:
1251 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1252 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1253 * @retval None
1254 */
1255 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1256 {
1257 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1258 }
1259
1260 /**
1261 * @brief Return DMA2D foreground CLUT color mode.
1262 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1263 * @param DMA2Dx DMA2D Instance
1264 * @retval Returned value can be one of the following values:
1265 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1266 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1267 */
1268 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1269 {
1270 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1271 }
1272
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1278 * @{
1279 */
1280
1281 /**
1282 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1283 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1284 * @param DMA2Dx DMA2D Instance
1285 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1286 * @retval None
1287 */
1288 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1289 {
1290 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1291 }
1292
1293 /**
1294 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1295 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1296 * @param DMA2Dx DMA2D Instance
1297 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1298 */
1299 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1300 {
1301 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1302 }
1303
1304 /**
1305 * @brief Enable DMA2D background CLUT loading.
1306 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1307 * @param DMA2Dx DMA2D Instance
1308 * @retval None
1309 */
1310 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1311 {
1312 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1313 }
1314
1315 /**
1316 * @brief Indicate if DMA2D background CLUT loading is enabled.
1317 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1318 * @param DMA2Dx DMA2D Instance
1319 * @retval State of bit (1 or 0).
1320 */
1321 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1322 {
1323 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1324 }
1325
1326 /**
1327 * @brief Set DMA2D background color mode.
1328 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1329 * @param DMA2Dx DMA2D Instance
1330 * @param ColorMode This parameter can be one of the following values:
1331 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1332 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1333 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1334 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1335 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1336 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1337 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1338 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1339 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1340 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1341 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1342 * @retval None
1343 */
1344 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1345 {
1346 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1347 }
1348
1349 /**
1350 * @brief Return DMA2D background color mode.
1351 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1352 * @param DMA2Dx DMA2D Instance
1353 * @retval Returned value can be one of the following values:
1354 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1355 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1356 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1357 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1358 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1359 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1360 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1361 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1362 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1363 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1364 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1365 */
1366 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1367 {
1368 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1369 }
1370
1371 /**
1372 * @brief Set DMA2D background alpha mode.
1373 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1374 * @param DMA2Dx DMA2D Instance
1375 * @param AphaMode This parameter can be one of the following values:
1376 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1377 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1378 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1379 * @retval None
1380 */
1381 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1382 {
1383 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1384 }
1385
1386 /**
1387 * @brief Return DMA2D background alpha mode.
1388 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1389 * @param DMA2Dx DMA2D Instance
1390 * @retval Returned value can be one of the following values:
1391 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1392 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1393 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1394 */
1395 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1396 {
1397 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1398 }
1399
1400 /**
1401 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1402 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1403 * @param DMA2Dx DMA2D Instance
1404 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1408 {
1409 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1410 }
1411
1412 /**
1413 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1414 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1415 * @param DMA2Dx DMA2D Instance
1416 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1417 */
1418 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1419 {
1420 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1421 }
1422
1423 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1424 /**
1425 * @brief Set DMA2D background Red Blue swap mode.
1426 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1427 * @param DMA2Dx DMA2D Instance
1428 * @param RBSwapMode This parameter can be one of the following values:
1429 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1430 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1431 * @retval None
1432 */
1433 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1434 {
1435 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1436 }
1437
1438 /**
1439 * @brief Return DMA2D background Red Blue swap mode.
1440 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1441 * @param DMA2Dx DMA2D Instance
1442 * @retval Returned value can be one of the following values:
1443 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1444 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1445 */
1446 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1447 {
1448 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1449 }
1450
1451 /**
1452 * @brief Set DMA2D background alpha inversion mode.
1453 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1454 * @param DMA2Dx DMA2D Instance
1455 * @param AlphaInversionMode This parameter can be one of the following values:
1456 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1457 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1458 * @retval None
1459 */
1460 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1461 {
1462 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1463 }
1464
1465 /**
1466 * @brief Return DMA2D background alpha inversion mode.
1467 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1468 * @param DMA2Dx DMA2D Instance
1469 * @retval Returned value can be one of the following values:
1470 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1471 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1472 */
1473 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1474 {
1475 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1476 }
1477
1478 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1479
1480 /**
1481 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1482 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1483 * @param DMA2Dx DMA2D Instance
1484 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1485 * @retval None
1486 */
1487 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1488 {
1489 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1490 }
1491
1492 /**
1493 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1494 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1495 * @param DMA2Dx DMA2D Instance
1496 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1497 */
1498 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1499 {
1500 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1501 }
1502
1503 /**
1504 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1505 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1506 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1507 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1508 * @param DMA2Dx DMA2D Instance
1509 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1510 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1511 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1512 * @retval None
1513 */
1514 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1515 {
1516 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1517 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1518 }
1519
1520 /**
1521 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1522 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1523 * @param DMA2Dx DMA2D Instance
1524 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1525 * @retval None
1526 */
1527 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1528 {
1529 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1530 }
1531
1532 /**
1533 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1534 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1535 * @param DMA2Dx DMA2D Instance
1536 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1537 */
1538 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1539 {
1540 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1541 }
1542
1543 /**
1544 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1545 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1546 * @param DMA2Dx DMA2D Instance
1547 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1548 * @retval None
1549 */
1550 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1551 {
1552 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1553 }
1554
1555 /**
1556 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1557 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1558 * @param DMA2Dx DMA2D Instance
1559 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1560 */
1561 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1562 {
1563 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1564 }
1565
1566 /**
1567 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1568 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1569 * @param DMA2Dx DMA2D Instance
1570 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1571 * @retval None
1572 */
1573 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1574 {
1575 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1576 }
1577
1578 /**
1579 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1580 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1581 * @param DMA2Dx DMA2D Instance
1582 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1583 */
1584 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1585 {
1586 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1587 }
1588
1589 /**
1590 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1591 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1592 * @param DMA2Dx DMA2D Instance
1593 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1594 * @retval None
1595 */
1596 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1597 {
1598 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1599 }
1600
1601 /**
1602 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1603 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1604 * @param DMA2Dx DMA2D Instance
1605 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1606 */
1607 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1608 {
1609 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1610 }
1611
1612 /**
1613 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1614 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1615 * @param DMA2Dx DMA2D Instance
1616 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1617 * @retval None
1618 */
1619 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1620 {
1621 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1622 }
1623
1624 /**
1625 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1626 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1627 * @param DMA2Dx DMA2D Instance
1628 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1629 */
1630 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1631 {
1632 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1633 }
1634
1635 /**
1636 * @brief Set DMA2D background CLUT color mode.
1637 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1638 * @param DMA2Dx DMA2D Instance
1639 * @param CLUTColorMode This parameter can be one of the following values:
1640 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1641 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1642 * @retval None
1643 */
1644 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1645 {
1646 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1647 }
1648
1649 /**
1650 * @brief Return DMA2D background CLUT color mode.
1651 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1652 * @param DMA2Dx DMA2D Instance
1653 * @retval Returned value can be one of the following values:
1654 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1655 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1656 */
1657 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1658 {
1659 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1660 }
1661
1662 /**
1663 * @}
1664 */
1665
1666 /**
1667 * @}
1668 */
1669
1670
1671 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1672 * @{
1673 */
1674
1675 /**
1676 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1677 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1678 * @param DMA2Dx DMA2D Instance
1679 * @retval State of bit (1 or 0).
1680 */
1681 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1682 {
1683 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1684 }
1685
1686 /**
1687 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1688 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1689 * @param DMA2Dx DMA2D Instance
1690 * @retval State of bit (1 or 0).
1691 */
1692 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1693 {
1694 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1695 }
1696
1697 /**
1698 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1699 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1700 * @param DMA2Dx DMA2D Instance
1701 * @retval State of bit (1 or 0).
1702 */
1703 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1704 {
1705 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1706 }
1707
1708 /**
1709 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1710 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1711 * @param DMA2Dx DMA2D Instance
1712 * @retval State of bit (1 or 0).
1713 */
1714 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1715 {
1716 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1721 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1722 * @param DMA2Dx DMA2D Instance
1723 * @retval State of bit (1 or 0).
1724 */
1725 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1726 {
1727 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1732 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1733 * @param DMA2Dx DMA2D Instance
1734 * @retval State of bit (1 or 0).
1735 */
1736 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1737 {
1738 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1739 }
1740
1741 /**
1742 * @brief Clear DMA2D Configuration Error Interrupt Flag
1743 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1744 * @param DMA2Dx DMA2D Instance
1745 * @retval None
1746 */
1747 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1748 {
1749 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1750 }
1751
1752 /**
1753 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1754 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1755 * @param DMA2Dx DMA2D Instance
1756 * @retval None
1757 */
1758 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1759 {
1760 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1761 }
1762
1763 /**
1764 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1765 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1766 * @param DMA2Dx DMA2D Instance
1767 * @retval None
1768 */
1769 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1770 {
1771 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1772 }
1773
1774 /**
1775 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1776 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1777 * @param DMA2Dx DMA2D Instance
1778 * @retval None
1779 */
1780 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1781 {
1782 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1783 }
1784
1785 /**
1786 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1787 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1788 * @param DMA2Dx DMA2D Instance
1789 * @retval None
1790 */
1791 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1792 {
1793 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1794 }
1795
1796 /**
1797 * @brief Clear DMA2D Transfer Error Interrupt Flag
1798 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1799 * @param DMA2Dx DMA2D Instance
1800 * @retval None
1801 */
1802 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1803 {
1804 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1805 }
1806
1807 /**
1808 * @}
1809 */
1810
1811 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1812 * @{
1813 */
1814
1815 /**
1816 * @brief Enable Configuration Error Interrupt
1817 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1818 * @param DMA2Dx DMA2D Instance
1819 * @retval None
1820 */
1821 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1822 {
1823 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1824 }
1825
1826 /**
1827 * @brief Enable CLUT Transfer Complete Interrupt
1828 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1829 * @param DMA2Dx DMA2D Instance
1830 * @retval None
1831 */
1832 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1833 {
1834 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1835 }
1836
1837 /**
1838 * @brief Enable CLUT Access Error Interrupt
1839 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1840 * @param DMA2Dx DMA2D Instance
1841 * @retval None
1842 */
1843 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1844 {
1845 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1846 }
1847
1848 /**
1849 * @brief Enable Transfer Watermark Interrupt
1850 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1851 * @param DMA2Dx DMA2D Instance
1852 * @retval None
1853 */
1854 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1855 {
1856 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1857 }
1858
1859 /**
1860 * @brief Enable Transfer Complete Interrupt
1861 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1862 * @param DMA2Dx DMA2D Instance
1863 * @retval None
1864 */
1865 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1866 {
1867 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1868 }
1869
1870 /**
1871 * @brief Enable Transfer Error Interrupt
1872 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1873 * @param DMA2Dx DMA2D Instance
1874 * @retval None
1875 */
1876 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1877 {
1878 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1879 }
1880
1881 /**
1882 * @brief Disable Configuration Error Interrupt
1883 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1884 * @param DMA2Dx DMA2D Instance
1885 * @retval None
1886 */
1887 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1888 {
1889 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1890 }
1891
1892 /**
1893 * @brief Disable CLUT Transfer Complete Interrupt
1894 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1895 * @param DMA2Dx DMA2D Instance
1896 * @retval None
1897 */
1898 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1899 {
1900 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1901 }
1902
1903 /**
1904 * @brief Disable CLUT Access Error Interrupt
1905 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
1906 * @param DMA2Dx DMA2D Instance
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1910 {
1911 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1912 }
1913
1914 /**
1915 * @brief Disable Transfer Watermark Interrupt
1916 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
1917 * @param DMA2Dx DMA2D Instance
1918 * @retval None
1919 */
1920 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
1921 {
1922 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1923 }
1924
1925 /**
1926 * @brief Disable Transfer Complete Interrupt
1927 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
1928 * @param DMA2Dx DMA2D Instance
1929 * @retval None
1930 */
1931 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
1932 {
1933 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1934 }
1935
1936 /**
1937 * @brief Disable Transfer Error Interrupt
1938 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
1939 * @param DMA2Dx DMA2D Instance
1940 * @retval None
1941 */
1942 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
1943 {
1944 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1945 }
1946
1947 /**
1948 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
1949 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
1950 * @param DMA2Dx DMA2D Instance
1951 * @retval State of bit (1 or 0).
1952 */
1953 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
1954 {
1955 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
1956 }
1957
1958 /**
1959 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
1960 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
1961 * @param DMA2Dx DMA2D Instance
1962 * @retval State of bit (1 or 0).
1963 */
1964 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
1965 {
1966 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
1967 }
1968
1969 /**
1970 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
1971 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
1972 * @param DMA2Dx DMA2D Instance
1973 * @retval State of bit (1 or 0).
1974 */
1975 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
1976 {
1977 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
1978 }
1979
1980 /**
1981 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
1982 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
1983 * @param DMA2Dx DMA2D Instance
1984 * @retval State of bit (1 or 0).
1985 */
1986 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
1987 {
1988 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
1989 }
1990
1991 /**
1992 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
1993 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
1994 * @param DMA2Dx DMA2D Instance
1995 * @retval State of bit (1 or 0).
1996 */
1997 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
1998 {
1999 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2000 }
2001
2002 /**
2003 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2004 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2005 * @param DMA2Dx DMA2D Instance
2006 * @retval State of bit (1 or 0).
2007 */
2008 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2009 {
2010 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2011 }
2012
2013
2014
2015 /**
2016 * @}
2017 */
2018
2019 #if defined(USE_FULL_LL_DRIVER)
2020 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2021 * @{
2022 */
2023
2024 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2025 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2026 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2027 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2028 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2029 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2030 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2031 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2032 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2033 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2034 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2035
2036 /**
2037 * @}
2038 */
2039 #endif /* USE_FULL_LL_DRIVER */
2040
2041 /**
2042 * @}
2043 */
2044
2045 /**
2046 * @}
2047 */
2048
2049 #endif /* defined (DMA2D) */
2050
2051 /**
2052 * @}
2053 */
2054
2055 #ifdef __cplusplus
2056 }
2057 #endif
2058
2059 #endif /* STM32F7xx_LL_DMA2D_H */
2060
2061 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/