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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_fmc.h
blob11bf9b15165e5e2b3a65e135752103e3589bdabc
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_fmc.h
4 * @author MCD Application Team
5 * @brief Header file of FMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_FMC_H
22 #define __STM32F7xx_LL_FMC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30
31 /** @addtogroup STM32F7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup FMC_LL
36 * @{
37 */
38
39 /** @addtogroup FMC_LL_Private_Macros
40 * @{
41 */
42 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
43 ((BANK) == FMC_NORSRAM_BANK2) || \
44 ((BANK) == FMC_NORSRAM_BANK3) || \
45 ((BANK) == FMC_NORSRAM_BANK4))
46
47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
49
50 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
51 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
52 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
53
54 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
55 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
56 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
57
58 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
59 ((__MODE__) == FMC_ACCESS_MODE_B) || \
60 ((__MODE__) == FMC_ACCESS_MODE_C) || \
61 ((__MODE__) == FMC_ACCESS_MODE_D))
62
63 #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
64
65 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
66 ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
67
68 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
69 ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
70
71 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
72 ((STATE) == FMC_NAND_ECC_ENABLE))
73
74 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
75 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
76 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
77 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
78 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
79 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
80
81 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
82 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
83 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
84
85 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
86 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
87
88 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
89 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
90 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
91
92 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
93 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
94
95 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
96 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
97 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
98
99 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
100 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
101 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
102 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
103 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
104 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
105 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
106
107 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
108 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
109 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
110
111 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
112 * @{
113 */
114 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
115 /**
116 * @}
117 */
118
119 /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
120 * @{
121 */
122 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
123 /**
124 * @}
125 */
126
127 /** @defgroup FMC_Setup_Time FMC Setup Time
128 * @{
129 */
130 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
131 /**
132 * @}
133 */
134
135 /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
136 * @{
137 */
138 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
139 /**
140 * @}
141 */
142
143 /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
144 * @{
145 */
146 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
147 /**
148 * @}
149 */
150
151 /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
152 * @{
153 */
154 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
155 /**
156 * @}
157 */
158
159 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
160 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
161
162 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
163 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
164
165 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
166 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
167
168 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
169 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
170
171 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
172 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
173
174 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
175 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
176
177 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
178 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
179
180 /** @defgroup FMC_Data_Latency FMC Data Latency
181 * @{
182 */
183 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
184 /**
185 * @}
186 */
187
188 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
189 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
190
191 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
192 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
193
194
195 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
196 * @{
197 */
198 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
199 /**
200 * @}
201 */
202
203 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
204 * @{
205 */
206 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
207 /**
208 * @}
209 */
210
211 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
212 * @{
213 */
214 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
215 /**
216 * @}
217 */
218
219 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
220 * @{
221 */
222 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
223 /**
224 * @}
225 */
226
227 /** @defgroup FMC_CLK_Division FMC CLK Division
228 * @{
229 */
230 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
231 /**
232 * @}
233 */
234
235 /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
236 * @{
237 */
238 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
239 /**
240 * @}
241 */
242
243 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
244 * @{
245 */
246 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
247 /**
248 * @}
249 */
250
251 /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
252 * @{
253 */
254 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
255 /**
256 * @}
257 */
258
259 /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
260 * @{
261 */
262 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
263 /**
264 * @}
265 */
266
267 /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
268 * @{
269 */
270 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
271 /**
272 * @}
273 */
274
275 /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
276 * @{
277 */
278 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
279 /**
280 * @}
281 */
282
283 /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
284 * @{
285 */
286 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
287 /**
288 * @}
289 */
290
291 /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
292 * @{
293 */
294 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
295 /**
296 * @}
297 */
298
299 /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
300 * @{
301 */
302 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
303 /**
304 * @}
305 */
306
307 /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
308 * @{
309 */
310 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
311 /**
312 * @}
313 */
314
315 /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
316 * @{
317 */
318 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
319 /**
320 * @}
321 */
322
323 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
324 * @{
325 */
326 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
327 /**
328 * @}
329 */
330
331 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
332 * @{
333 */
334 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
335 /**
336 * @}
337 */
338
339 /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
340 * @{
341 */
342 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
343 /**
344 * @}
345 */
346
347 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
348 ((BANK) == FMC_SDRAM_BANK2))
349
350 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
351 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
352 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
353 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
354
355 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
356 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
357 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
358
359 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
360 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
361
362
363 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
364 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
365 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
366
367 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
368 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
369 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
370 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
371 ((__SIZE__) == FMC_PAGE_SIZE_1024))
372
373 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
374 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
375 /**
376 * @}
377 */
378
379 /* Exported typedef ----------------------------------------------------------*/
380 /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
381 * @{
382 */
383 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
384 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
385 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
386 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
387
388 #define FMC_NORSRAM_DEVICE FMC_Bank1
389 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
390 #define FMC_NAND_DEVICE FMC_Bank3
391 #define FMC_SDRAM_DEVICE FMC_Bank5_6
392
393 /**
394 * @brief FMC NORSRAM Configuration Structure definition
395 */
396 typedef struct
397 {
398 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
399 This parameter can be a value of @ref FMC_NORSRAM_Bank */
400
401 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
402 multiplexed on the data bus or not.
403 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
404
405 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
406 the corresponding memory device.
407 This parameter can be a value of @ref FMC_Memory_Type */
408
409 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
410 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
411
412 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
413 valid only with synchronous burst Flash memories.
414 This parameter can be a value of @ref FMC_Burst_Access_Mode */
415
416 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
417 the Flash memory in burst mode.
418 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
419
420 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
421 clock cycle before the wait state or during the wait state,
422 valid only when accessing memories in burst mode.
423 This parameter can be a value of @ref FMC_Wait_Timing */
424
425 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
426 This parameter can be a value of @ref FMC_Write_Operation */
427
428 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
429 signal, valid for Flash memory access in burst mode.
430 This parameter can be a value of @ref FMC_Wait_Signal */
431
432 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
433 This parameter can be a value of @ref FMC_Extended_Mode */
434
435 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
436 valid only with asynchronous Flash memories.
437 This parameter can be a value of @ref FMC_AsynchronousWait */
438
439 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
440 This parameter can be a value of @ref FMC_Write_Burst */
441
442 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
443 This parameter is only enabled through the FMC_BCR1 register, and don't care
444 through FMC_BCR2..4 registers.
445 This parameter can be a value of @ref FMC_Continous_Clock */
446
447 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
448 This parameter is only enabled through the FMC_BCR1 register, and don't care
449 through FMC_BCR2..4 registers.
450 This parameter can be a value of @ref FMC_Write_FIFO */
451
452 uint32_t PageSize; /*!< Specifies the memory page size.
453 This parameter can be a value of @ref FMC_Page_Size */
454
455 }FMC_NORSRAM_InitTypeDef;
456
457 /**
458 * @brief FMC NORSRAM Timing parameters structure definition
459 */
460 typedef struct
461 {
462 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
463 the duration of the address setup time.
464 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
465 @note This parameter is not used with synchronous NOR Flash memories. */
466
467 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
468 the duration of the address hold time.
469 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
470 @note This parameter is not used with synchronous NOR Flash memories. */
471
472 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
473 the duration of the data setup time.
474 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
475 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
476 NOR Flash memories. */
477
478 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
479 the duration of the bus turnaround.
480 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
481 @note This parameter is only used for multiplexed NOR Flash memories. */
482
483 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
484 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
485 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
486 accesses. */
487
488 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
489 to the memory before getting the first data.
490 The parameter value depends on the memory type as shown below:
491 - It must be set to 0 in case of a CRAM
492 - It is don't care in asynchronous NOR, SRAM or ROM accesses
493 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
494 with synchronous burst mode enable */
495
496 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
497 This parameter can be a value of @ref FMC_Access_Mode */
498 }FMC_NORSRAM_TimingTypeDef;
499
500 /**
501 * @brief FMC NAND Configuration Structure definition
502 */
503 typedef struct
504 {
505 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
506 This parameter can be a value of @ref FMC_NAND_Bank */
507
508 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
509 This parameter can be any value of @ref FMC_Wait_feature */
510
511 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
512 This parameter can be any value of @ref FMC_NAND_Data_Width */
513
514 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
515 This parameter can be any value of @ref FMC_ECC */
516
517 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
518 This parameter can be any value of @ref FMC_ECC_Page_Size */
519
520 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
521 delay between CLE low and RE low.
522 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
523
524 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
525 delay between ALE low and RE low.
526 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
527 }FMC_NAND_InitTypeDef;
528
529 /**
530 * @brief FMC NAND Timing parameters structure definition
531 */
532 typedef struct
533 {
534 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
535 the command assertion for NAND-Flash read or write access
536 to common/Attribute or I/O memory space (depending on
537 the memory space timing to be configured).
538 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
539
540 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
541 command for NAND-Flash read or write access to
542 common/Attribute or I/O memory space (depending on the
543 memory space timing to be configured).
544 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
545
546 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
547 (and data for write access) after the command de-assertion
548 for NAND-Flash read or write access to common/Attribute
549 or I/O memory space (depending on the memory space timing
550 to be configured).
551 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
552
553 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
554 data bus is kept in HiZ after the start of a NAND-Flash
555 write access to common/Attribute or I/O memory space (depending
556 on the memory space timing to be configured).
557 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
558 }FMC_NAND_PCC_TimingTypeDef;
559
560 /**
561 * @brief FMC SDRAM Configuration Structure definition
562 */
563 typedef struct
564 {
565 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
566 This parameter can be a value of @ref FMC_SDRAM_Bank */
567
568 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
569 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
570
571 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
572 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
573
574 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
575 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
576
577 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
578 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
579
580 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
581 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
582
583 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
584 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
585
586 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
587 to disable the clock before changing frequency.
588 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
589
590 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
591 commands during the CAS latency and stores data in the Read FIFO.
592 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
593
594 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
595 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
596 }FMC_SDRAM_InitTypeDef;
597
598 /**
599 * @brief FMC SDRAM Timing parameters structure definition
600 */
601 typedef struct
602 {
603 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
604 an active or Refresh command in number of memory clock cycles.
605 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
606
607 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
608 issuing the Activate command in number of memory clock cycles.
609 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
610
611 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
612 cycles.
613 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
614
615 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
616 and the delay between two consecutive Refresh commands in number of
617 memory clock cycles.
618 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
619
620 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
621 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
622
623 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
624 in number of memory clock cycles.
625 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
626
627 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
628 command in number of memory clock cycles.
629 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
630 }FMC_SDRAM_TimingTypeDef;
631
632 /**
633 * @brief SDRAM command parameters structure definition
634 */
635 typedef struct
636 {
637 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
638 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
639
640 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
641 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
642
643 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
644 in auto refresh mode.
645 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
646 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
647 }FMC_SDRAM_CommandTypeDef;
648 /**
649 * @}
650 */
651
652 /* Exported constants --------------------------------------------------------*/
653 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
654 * @{
655 */
656
657 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
658 * @{
659 */
660
661 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
662 * @{
663 */
664 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
665 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
666 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
667 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
668 /**
669 * @}
670 */
671
672 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
673 * @{
674 */
675 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
676 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
677 /**
678 * @}
679 */
680
681 /** @defgroup FMC_Memory_Type FMC Memory Type
682 * @{
683 */
684 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
685 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
686 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
687 /**
688 * @}
689 */
690
691 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
692 * @{
693 */
694 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
695 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
696 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
697 /**
698 * @}
699 */
700
701 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
702 * @{
703 */
704 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
705 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
706 /**
707 * @}
708 */
709
710 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
711 * @{
712 */
713 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
714 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
715 /**
716 * @}
717 */
718
719 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
720 * @{
721 */
722 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
723 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
724 /**
725 * @}
726 */
727
728 /** @defgroup FMC_Wait_Timing FMC Wait Timing
729 * @{
730 */
731 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
732 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
733 /**
734 * @}
735 */
736
737 /** @defgroup FMC_Write_Operation FMC Write Operation
738 * @{
739 */
740 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
741 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
742 /**
743 * @}
744 */
745
746 /** @defgroup FMC_Wait_Signal FMC Wait Signal
747 * @{
748 */
749 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
750 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
751 /**
752 * @}
753 */
754
755 /** @defgroup FMC_Extended_Mode FMC Extended Mode
756 * @{
757 */
758 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
759 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
760 /**
761 * @}
762 */
763
764 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
765 * @{
766 */
767 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
768 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
769 /**
770 * @}
771 */
772
773 /** @defgroup FMC_Page_Size FMC Page Size
774 * @{
775 */
776 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
777 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
778 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
779 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
780 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
781 /**
782 * @}
783 */
784
785 /** @defgroup FMC_Write_Burst FMC Write Burst
786 * @{
787 */
788 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
789 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
790 /**
791 * @}
792 */
793
794 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
795 * @{
796 */
797 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
798 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
799 /**
800 * @}
801 */
802
803 /** @defgroup FMC_Write_FIFO FMC Write FIFO
804 * @{
805 */
806 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
807 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
808 /**
809 * @}
810 */
811
812 /** @defgroup FMC_Access_Mode FMC Access Mode
813 * @{
814 */
815 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
816 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
817 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
818 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
819 /**
820 * @}
821 */
822
823 /**
824 * @}
825 */
826
827 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
828 * @{
829 */
830 /** @defgroup FMC_NAND_Bank FMC NAND Bank
831 * @{
832 */
833 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
834 /**
835 * @}
836 */
837
838 /** @defgroup FMC_Wait_feature FMC Wait feature
839 * @{
840 */
841 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
842 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
843 /**
844 * @}
845 */
846
847 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
848 * @{
849 */
850 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
851 /**
852 * @}
853 */
854
855 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
856 * @{
857 */
858 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
859 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
860 /**
861 * @}
862 */
863
864 /** @defgroup FMC_ECC FMC ECC
865 * @{
866 */
867 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
868 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
869 /**
870 * @}
871 */
872
873 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
874 * @{
875 */
876 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
877 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
878 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
879 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
880 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
881 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
882 /**
883 * @}
884 */
885
886 /**
887 * @}
888 */
889
890 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
891 * @{
892 */
893 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
894 * @{
895 */
896 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
897 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
898 /**
899 * @}
900 */
901
902 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
903 * @{
904 */
905 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
906 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
907 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
908 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
909 /**
910 * @}
911 */
912
913 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
914 * @{
915 */
916 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
917 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
918 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
919 /**
920 * @}
921 */
922
923 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
924 * @{
925 */
926 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
927 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
928 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
929 /**
930 * @}
931 */
932
933 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
934 * @{
935 */
936 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
937 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
938 /**
939 * @}
940 */
941
942 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
943 * @{
944 */
945 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
946 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
947 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
948 /**
949 * @}
950 */
951
952 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
953 * @{
954 */
955 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
956 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
957 /**
958 * @}
959 */
960
961 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
962 * @{
963 */
964 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
965 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
966 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
967 /**
968 * @}
969 */
970
971 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
972 * @{
973 */
974 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
975 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
976 /**
977 * @}
978 */
979
980 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
981 * @{
982 */
983 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
984 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
985 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
986 /**
987 * @}
988 */
989
990 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
991 * @{
992 */
993 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
994 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
995 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
996 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
997 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
998 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
999 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
1000 /**
1001 * @}
1002 */
1003
1004 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
1005 * @{
1006 */
1007 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
1008 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
1009 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
1015 * @{
1016 */
1017 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
1018 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
1019 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
1020 /**
1021 * @}
1022 */
1023
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
1029 * @{
1030 */
1031 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
1032 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
1033 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
1034 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
1040 * @{
1041 */
1042 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
1043 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
1044 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
1045 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
1046 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
1047 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
1048 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
1049 /**
1050 * @}
1051 */
1052 /**
1053 * @}
1054 */
1055
1056 /**
1057 * @}
1058 */
1059
1060 /* Private macro -------------------------------------------------------------*/
1061 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
1062 * @{
1063 */
1064
1065 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
1066 * @brief macros to handle NOR device enable/disable and read/write operations
1067 * @{
1068 */
1069
1070 /**
1071 * @brief Enable the NORSRAM device access.
1072 * @param __INSTANCE__ FMC_NORSRAM Instance
1073 * @param __BANK__ FMC_NORSRAM Bank
1074 * @retval None
1075 */
1076 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
1077
1078 /**
1079 * @brief Disable the NORSRAM device access.
1080 * @param __INSTANCE__ FMC_NORSRAM Instance
1081 * @param __BANK__ FMC_NORSRAM Bank
1082 * @retval None
1083 */
1084 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
1085
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
1091 * @brief macros to handle NAND device enable/disable
1092 * @{
1093 */
1094
1095 /**
1096 * @brief Enable the NAND device access.
1097 * @param __INSTANCE__ FMC_NAND Instance
1098 * @retval None
1099 */
1100 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1101
1102 /**
1103 * @brief Disable the NAND device access.
1104 * @param __INSTANCE__ FMC_NAND Instance
1105 * @retval None
1106 */
1107 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
1108
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup FMC_Interrupt FMC Interrupt
1114 * @brief macros to handle FMC interrupts
1115 * @{
1116 */
1117
1118 /**
1119 * @brief Enable the NAND device interrupt.
1120 * @param __INSTANCE__ FMC_NAND instance
1121 * @param __INTERRUPT__ FMC_NAND interrupt
1122 * This parameter can be any combination of the following values:
1123 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1124 * @arg FMC_IT_LEVEL: Interrupt level.
1125 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1126 * @retval None
1127 */
1128 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
1129
1130 /**
1131 * @brief Disable the NAND device interrupt.
1132 * @param __INSTANCE__ FMC_NAND Instance
1133 * @param __INTERRUPT__ FMC_NAND interrupt
1134 * This parameter can be any combination of the following values:
1135 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1136 * @arg FMC_IT_LEVEL: Interrupt level.
1137 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1138 * @retval None
1139 */
1140 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
1141
1142 /**
1143 * @brief Get flag status of the NAND device.
1144 * @param __INSTANCE__ FMC_NAND Instance
1145 * @param __BANK__ FMC_NAND Bank
1146 * @param __FLAG__ FMC_NAND flag
1147 * This parameter can be any combination of the following values:
1148 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1149 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1150 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1151 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1152 * @retval The state of FLAG (SET or RESET).
1153 */
1154 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
1155
1156 /**
1157 * @brief Clear flag status of the NAND device.
1158 * @param __INSTANCE__ FMC_NAND Instance
1159 * @param __FLAG__ FMC_NAND flag
1160 * This parameter can be any combination of the following values:
1161 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1162 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1163 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1164 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1165 * @retval None
1166 */
1167 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
1168
1169 /**
1170 * @brief Enable the SDRAM device interrupt.
1171 * @param __INSTANCE__ FMC_SDRAM instance
1172 * @param __INTERRUPT__ FMC_SDRAM interrupt
1173 * This parameter can be any combination of the following values:
1174 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1175 * @retval None
1176 */
1177 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1178
1179 /**
1180 * @brief Disable the SDRAM device interrupt.
1181 * @param __INSTANCE__ FMC_SDRAM instance
1182 * @param __INTERRUPT__ FMC_SDRAM interrupt
1183 * This parameter can be any combination of the following values:
1184 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1185 * @retval None
1186 */
1187 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1188
1189 /**
1190 * @brief Get flag status of the SDRAM device.
1191 * @param __INSTANCE__ FMC_SDRAM instance
1192 * @param __FLAG__ FMC_SDRAM flag
1193 * This parameter can be any combination of the following values:
1194 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1195 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1196 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1197 * @retval The state of FLAG (SET or RESET).
1198 */
1199 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1200
1201 /**
1202 * @brief Clear flag status of the SDRAM device.
1203 * @param __INSTANCE__ FMC_SDRAM instance
1204 * @param __FLAG__ FMC_SDRAM flag
1205 * This parameter can be any combination of the following values:
1206 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1207 * @retval None
1208 */
1209 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1210 /**
1211 * @}
1212 */
1213
1214 /**
1215 * @}
1216 */
1217
1218 /* Private functions ---------------------------------------------------------*/
1219 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1220 * @{
1221 */
1222
1223 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1224 * @{
1225 */
1226 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1227 * @{
1228 */
1229 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1230 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1231 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1232 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1238 * @{
1239 */
1240 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1241 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1242 /**
1243 * @}
1244 */
1245 /**
1246 * @}
1247 */
1248
1249 /** @defgroup FMC_LL_NAND NAND
1250 * @{
1251 */
1252 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1253 * @{
1254 */
1255 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1256 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1257 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1258 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1259 /**
1260 * @}
1261 */
1262
1263 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1264 * @{
1265 */
1266 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1267 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1268 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1269 /**
1270 * @}
1271 */
1272
1273 /** @defgroup FMC_LL_SDRAM SDRAM
1274 * @{
1275 */
1276 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1277 * @{
1278 */
1279 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1280 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1281 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1282
1283 /**
1284 * @}
1285 */
1286
1287 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1288 * @{
1289 */
1290 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1291 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1292 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1293 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1294 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1295 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1296 /**
1297 * @}
1298 */
1299
1300 /**
1301 * @}
1302 */
1303
1304 /**
1305 * @}
1306 */
1307
1308 /**
1309 * @}
1310 */
1311
1312 /**
1313 * @}
1314 */
1315 #ifdef __cplusplus
1316 }
1317 #endif
1318
1319 #endif /* __STM32F7xx_LL_FMC_H */
1320
1321 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/