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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_i2c.h
blobcb56430deb2fc69926759cce3fbcc100bbe6f800
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_LL_I2C_H
22 #define STM32F7xx_LL_I2C_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
36
37 /** @defgroup I2C_LL I2C
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
55 * @{
56 */
57 /**
58 * @}
59 */
60 #endif /*USE_FULL_LL_DRIVER*/
61
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
65 * @{
66 */
67 typedef struct
68 {
69 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
70 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
71
72 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
77
78 This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
79
80 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
81 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
82
83 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
84
85 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
86 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
87
88 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
89
90 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
91 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
92
93 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
94
95 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
96 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
97
98 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
99
100 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
101 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
102
103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
104 } LL_I2C_InitTypeDef;
105 /**
106 * @}
107 */
108 #endif /*USE_FULL_LL_DRIVER*/
109
110 /* Exported constants --------------------------------------------------------*/
111 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
112 * @{
113 */
114
115 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
116 * @brief Flags defines which can be used with LL_I2C_WriteReg function
117 * @{
118 */
119 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
120 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
121 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
122 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
123 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
124 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
125 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
126 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
127 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
128 /**
129 * @}
130 */
131
132 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
133 * @brief Flags defines which can be used with LL_I2C_ReadReg function
134 * @{
135 */
136 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
137 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
138 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
139 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
140 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
141 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
142 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
143 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
144 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
145 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
146 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
147 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
148 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
149 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
150 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
151 /**
152 * @}
153 */
154
155 /** @defgroup I2C_LL_EC_IT IT Defines
156 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
157 * @{
158 */
159 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
160 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
161 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
162 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
163 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
164 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
165 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
166 /**
167 * @}
168 */
169
170 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
171 * @{
172 */
173 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
174 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
175 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
176 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
177 /**
178 * @}
179 */
180
181 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
182 * @{
183 */
184 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
185 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
186 /**
187 * @}
188 */
189
190 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
191 * @{
192 */
193 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
194 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
195 /**
196 * @}
197 */
198
199 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
200 * @{
201 */
202 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
203 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
209 * @{
210 */
211 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
212 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
213 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
214 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
215 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
216 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
217 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
218 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
219 /**
220 * @}
221 */
222
223 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
224 * @{
225 */
226 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
227 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
228 /**
229 * @}
230 */
231
232 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
233 * @{
234 */
235 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
236 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
242 * @{
243 */
244 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
245 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
251 * @{
252 */
253 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
254 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
255 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
256 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
257 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
258 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
259 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
260 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
261 /**
262 * @}
263 */
264
265 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
266 * @{
267 */
268 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
269 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
270 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
271 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
272 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
273 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
274 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
275 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
276 /**
277 * @}
278 */
279
280 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
281 * @{
282 */
283 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
284 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
285 /**
286 * @}
287 */
288
289 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
290 * @{
291 */
292 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
293 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
294 /**
295 * @}
296 */
297
298 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
299 * @{
300 */
301 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
302 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
303 /**
304 * @}
305 */
306
307 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
308 * @{
309 */
310 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
311 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
312 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
313 /**
314 * @}
315 */
316
317 /**
318 * @}
319 */
320
321 /* Exported macro ------------------------------------------------------------*/
322 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
323 * @{
324 */
325
326 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
327 * @{
328 */
329
330 /**
331 * @brief Write a value in I2C register
332 * @param __INSTANCE__ I2C Instance
333 * @param __REG__ Register to be written
334 * @param __VALUE__ Value to be written in the register
335 * @retval None
336 */
337 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
338
339 /**
340 * @brief Read a value in I2C register
341 * @param __INSTANCE__ I2C Instance
342 * @param __REG__ Register to be read
343 * @retval Register value
344 */
345 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
346 /**
347 * @}
348 */
349
350 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
351 * @{
352 */
353 /**
354 * @brief Configure the SDA setup, hold time and the SCL high, low period.
355 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
356 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
357 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
358 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
359 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
360 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
361 */
362 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
363 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
364 (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
365 (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
366 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
367 (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /* Exported functions --------------------------------------------------------*/
377 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
378 * @{
379 */
380
381 /** @defgroup I2C_LL_EF_Configuration Configuration
382 * @{
383 */
384
385 /**
386 * @brief Enable I2C peripheral (PE = 1).
387 * @rmtoll CR1 PE LL_I2C_Enable
388 * @param I2Cx I2C Instance.
389 * @retval None
390 */
391 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
392 {
393 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
394 }
395
396 /**
397 * @brief Disable I2C peripheral (PE = 0).
398 * @note When PE = 0, the I2C SCL and SDA lines are released.
399 * Internal state machines and status bits are put back to their reset value.
400 * When cleared, PE must be kept low for at least 3 APB clock cycles.
401 * @rmtoll CR1 PE LL_I2C_Disable
402 * @param I2Cx I2C Instance.
403 * @retval None
404 */
405 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
406 {
407 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
408 }
409
410 /**
411 * @brief Check if the I2C peripheral is enabled or disabled.
412 * @rmtoll CR1 PE LL_I2C_IsEnabled
413 * @param I2Cx I2C Instance.
414 * @retval State of bit (1 or 0).
415 */
416 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
417 {
418 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
419 }
420
421 /**
422 * @brief Configure Noise Filters (Analog and Digital).
423 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
424 * The filters can only be programmed when the I2C is disabled (PE = 0).
425 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
426 * CR1 DNF LL_I2C_ConfigFilters
427 * @param I2Cx I2C Instance.
428 * @param AnalogFilter This parameter can be one of the following values:
429 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
430 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
431 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
432 * This parameter is used to configure the digital noise filter on SDA and SCL input.
433 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
434 * @retval None
435 */
436 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
437 {
438 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
439 }
440
441 /**
442 * @brief Configure Digital Noise Filter.
443 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
444 * This filter can only be programmed when the I2C is disabled (PE = 0).
445 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
446 * @param I2Cx I2C Instance.
447 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
448 * This parameter is used to configure the digital noise filter on SDA and SCL input.
449 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
450 * @retval None
451 */
452 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
453 {
454 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
455 }
456
457 /**
458 * @brief Get the current Digital Noise Filter configuration.
459 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
460 * @param I2Cx I2C Instance.
461 * @retval Value between Min_Data=0x0 and Max_Data=0xF
462 */
463 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
464 {
465 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
466 }
467
468 /**
469 * @brief Enable Analog Noise Filter.
470 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
471 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
472 * @param I2Cx I2C Instance.
473 * @retval None
474 */
475 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
476 {
477 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
478 }
479
480 /**
481 * @brief Disable Analog Noise Filter.
482 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
483 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
484 * @param I2Cx I2C Instance.
485 * @retval None
486 */
487 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
488 {
489 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
490 }
491
492 /**
493 * @brief Check if Analog Noise Filter is enabled or disabled.
494 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
495 * @param I2Cx I2C Instance.
496 * @retval State of bit (1 or 0).
497 */
498 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
499 {
500 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
501 }
502
503 /**
504 * @brief Enable DMA transmission requests.
505 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
506 * @param I2Cx I2C Instance.
507 * @retval None
508 */
509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
510 {
511 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
512 }
513
514 /**
515 * @brief Disable DMA transmission requests.
516 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
517 * @param I2Cx I2C Instance.
518 * @retval None
519 */
520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
521 {
522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
523 }
524
525 /**
526 * @brief Check if DMA transmission requests are enabled or disabled.
527 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
528 * @param I2Cx I2C Instance.
529 * @retval State of bit (1 or 0).
530 */
531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
532 {
533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
534 }
535
536 /**
537 * @brief Enable DMA reception requests.
538 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
539 * @param I2Cx I2C Instance.
540 * @retval None
541 */
542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
543 {
544 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
545 }
546
547 /**
548 * @brief Disable DMA reception requests.
549 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
550 * @param I2Cx I2C Instance.
551 * @retval None
552 */
553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
554 {
555 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
556 }
557
558 /**
559 * @brief Check if DMA reception requests are enabled or disabled.
560 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
561 * @param I2Cx I2C Instance.
562 * @retval State of bit (1 or 0).
563 */
564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
565 {
566 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
567 }
568
569 /**
570 * @brief Get the data register address used for DMA transfer
571 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
572 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
573 * @param I2Cx I2C Instance
574 * @param Direction This parameter can be one of the following values:
575 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
576 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
577 * @retval Address of data register
578 */
579 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
580 {
581 register uint32_t data_reg_addr;
582
583 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
584 {
585 /* return address of TXDR register */
586 data_reg_addr = (uint32_t) & (I2Cx->TXDR);
587 }
588 else
589 {
590 /* return address of RXDR register */
591 data_reg_addr = (uint32_t) & (I2Cx->RXDR);
592 }
593
594 return data_reg_addr;
595 }
596
597 /**
598 * @brief Enable Clock stretching.
599 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
600 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
601 * @param I2Cx I2C Instance.
602 * @retval None
603 */
604 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
605 {
606 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
607 }
608
609 /**
610 * @brief Disable Clock stretching.
611 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
612 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
613 * @param I2Cx I2C Instance.
614 * @retval None
615 */
616 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
617 {
618 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
619 }
620
621 /**
622 * @brief Check if Clock stretching is enabled or disabled.
623 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
624 * @param I2Cx I2C Instance.
625 * @retval State of bit (1 or 0).
626 */
627 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
628 {
629 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
630 }
631
632 /**
633 * @brief Enable hardware byte control in slave mode.
634 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
635 * @param I2Cx I2C Instance.
636 * @retval None
637 */
638 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
639 {
640 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
641 }
642
643 /**
644 * @brief Disable hardware byte control in slave mode.
645 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
646 * @param I2Cx I2C Instance.
647 * @retval None
648 */
649 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
650 {
651 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
652 }
653
654 /**
655 * @brief Check if hardware byte control in slave mode is enabled or disabled.
656 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
657 * @param I2Cx I2C Instance.
658 * @retval State of bit (1 or 0).
659 */
660 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
661 {
662 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
663 }
664
665
666 /**
667 * @brief Enable General Call.
668 * @note When enabled the Address 0x00 is ACKed.
669 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
670 * @param I2Cx I2C Instance.
671 * @retval None
672 */
673 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
674 {
675 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
676 }
677
678 /**
679 * @brief Disable General Call.
680 * @note When disabled the Address 0x00 is NACKed.
681 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
682 * @param I2Cx I2C Instance.
683 * @retval None
684 */
685 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
686 {
687 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
688 }
689
690 /**
691 * @brief Check if General Call is enabled or disabled.
692 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
693 * @param I2Cx I2C Instance.
694 * @retval State of bit (1 or 0).
695 */
696 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
697 {
698 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
699 }
700
701 /**
702 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
703 * @note Changing this bit is not allowed, when the START bit is set.
704 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
705 * @param I2Cx I2C Instance.
706 * @param AddressingMode This parameter can be one of the following values:
707 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
708 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
709 * @retval None
710 */
711 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
712 {
713 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
714 }
715
716 /**
717 * @brief Get the Master addressing mode.
718 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
719 * @param I2Cx I2C Instance.
720 * @retval Returned value can be one of the following values:
721 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
722 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
723 */
724 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
725 {
726 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
727 }
728
729 /**
730 * @brief Set the Own Address1.
731 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
732 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
733 * @param I2Cx I2C Instance.
734 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
735 * @param OwnAddrSize This parameter can be one of the following values:
736 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
737 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
738 * @retval None
739 */
740 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
741 {
742 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
743 }
744
745 /**
746 * @brief Enable acknowledge on Own Address1 match address.
747 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
748 * @param I2Cx I2C Instance.
749 * @retval None
750 */
751 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
752 {
753 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
754 }
755
756 /**
757 * @brief Disable acknowledge on Own Address1 match address.
758 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
759 * @param I2Cx I2C Instance.
760 * @retval None
761 */
762 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
763 {
764 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
765 }
766
767 /**
768 * @brief Check if Own Address1 acknowledge is enabled or disabled.
769 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
770 * @param I2Cx I2C Instance.
771 * @retval State of bit (1 or 0).
772 */
773 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
774 {
775 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
776 }
777
778 /**
779 * @brief Set the 7bits Own Address2.
780 * @note This action has no effect if own address2 is enabled.
781 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
782 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
783 * @param I2Cx I2C Instance.
784 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
785 * @param OwnAddrMask This parameter can be one of the following values:
786 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
787 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
788 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
789 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
790 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
791 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
792 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
793 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
794 * @retval None
795 */
796 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
797 {
798 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
799 }
800
801 /**
802 * @brief Enable acknowledge on Own Address2 match address.
803 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
804 * @param I2Cx I2C Instance.
805 * @retval None
806 */
807 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
808 {
809 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
810 }
811
812 /**
813 * @brief Disable acknowledge on Own Address2 match address.
814 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
815 * @param I2Cx I2C Instance.
816 * @retval None
817 */
818 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
819 {
820 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
821 }
822
823 /**
824 * @brief Check if Own Address1 acknowledge is enabled or disabled.
825 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
826 * @param I2Cx I2C Instance.
827 * @retval State of bit (1 or 0).
828 */
829 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
830 {
831 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
832 }
833
834 /**
835 * @brief Configure the SDA setup, hold time and the SCL high, low period.
836 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
837 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
838 * @param I2Cx I2C Instance.
839 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
840 * @note This parameter is computed with the STM32CubeMX Tool.
841 * @retval None
842 */
843 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
844 {
845 WRITE_REG(I2Cx->TIMINGR, Timing);
846 }
847
848 /**
849 * @brief Get the Timing Prescaler setting.
850 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
851 * @param I2Cx I2C Instance.
852 * @retval Value between Min_Data=0x0 and Max_Data=0xF
853 */
854 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
855 {
856 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
857 }
858
859 /**
860 * @brief Get the SCL low period setting.
861 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
862 * @param I2Cx I2C Instance.
863 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
864 */
865 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
866 {
867 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
868 }
869
870 /**
871 * @brief Get the SCL high period setting.
872 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
873 * @param I2Cx I2C Instance.
874 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
875 */
876 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
877 {
878 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
879 }
880
881 /**
882 * @brief Get the SDA hold time.
883 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
884 * @param I2Cx I2C Instance.
885 * @retval Value between Min_Data=0x0 and Max_Data=0xF
886 */
887 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
888 {
889 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
890 }
891
892 /**
893 * @brief Get the SDA setup time.
894 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
895 * @param I2Cx I2C Instance.
896 * @retval Value between Min_Data=0x0 and Max_Data=0xF
897 */
898 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
899 {
900 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
901 }
902
903 /**
904 * @brief Configure peripheral mode.
905 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
906 * SMBus feature is supported by the I2Cx Instance.
907 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
908 * CR1 SMBDEN LL_I2C_SetMode
909 * @param I2Cx I2C Instance.
910 * @param PeripheralMode This parameter can be one of the following values:
911 * @arg @ref LL_I2C_MODE_I2C
912 * @arg @ref LL_I2C_MODE_SMBUS_HOST
913 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
914 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
915 * @retval None
916 */
917 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
918 {
919 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
920 }
921
922 /**
923 * @brief Get peripheral mode.
924 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
925 * SMBus feature is supported by the I2Cx Instance.
926 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
927 * CR1 SMBDEN LL_I2C_GetMode
928 * @param I2Cx I2C Instance.
929 * @retval Returned value can be one of the following values:
930 * @arg @ref LL_I2C_MODE_I2C
931 * @arg @ref LL_I2C_MODE_SMBUS_HOST
932 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
933 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
934 */
935 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
936 {
937 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
938 }
939
940 /**
941 * @brief Enable SMBus alert (Host or Device mode)
942 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
943 * SMBus feature is supported by the I2Cx Instance.
944 * @note SMBus Device mode:
945 * - SMBus Alert pin is drived low and
946 * Alert Response Address Header acknowledge is enabled.
947 * SMBus Host mode:
948 * - SMBus Alert pin management is supported.
949 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
950 * @param I2Cx I2C Instance.
951 * @retval None
952 */
953 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
954 {
955 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
956 }
957
958 /**
959 * @brief Disable SMBus alert (Host or Device mode)
960 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
961 * SMBus feature is supported by the I2Cx Instance.
962 * @note SMBus Device mode:
963 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
964 * Alert Response Address Header acknowledge is disabled.
965 * SMBus Host mode:
966 * - SMBus Alert pin management is not supported.
967 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
968 * @param I2Cx I2C Instance.
969 * @retval None
970 */
971 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
972 {
973 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
974 }
975
976 /**
977 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
978 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
979 * SMBus feature is supported by the I2Cx Instance.
980 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
981 * @param I2Cx I2C Instance.
982 * @retval State of bit (1 or 0).
983 */
984 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
985 {
986 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
987 }
988
989 /**
990 * @brief Enable SMBus Packet Error Calculation (PEC).
991 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
992 * SMBus feature is supported by the I2Cx Instance.
993 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
994 * @param I2Cx I2C Instance.
995 * @retval None
996 */
997 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
998 {
999 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1000 }
1001
1002 /**
1003 * @brief Disable SMBus Packet Error Calculation (PEC).
1004 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1005 * SMBus feature is supported by the I2Cx Instance.
1006 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1007 * @param I2Cx I2C Instance.
1008 * @retval None
1009 */
1010 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1011 {
1012 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1013 }
1014
1015 /**
1016 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1017 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1018 * SMBus feature is supported by the I2Cx Instance.
1019 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1020 * @param I2Cx I2C Instance.
1021 * @retval State of bit (1 or 0).
1022 */
1023 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1024 {
1025 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1026 }
1027
1028 /**
1029 * @brief Configure the SMBus Clock Timeout.
1030 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1031 * SMBus feature is supported by the I2Cx Instance.
1032 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1033 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1034 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1035 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1036 * @param I2Cx I2C Instance.
1037 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1038 * @param TimeoutAMode This parameter can be one of the following values:
1039 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1040 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1041 * @param TimeoutB
1042 * @retval None
1043 */
1044 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1045 uint32_t TimeoutB)
1046 {
1047 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1048 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1049 }
1050
1051 /**
1052 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1053 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1054 * SMBus feature is supported by the I2Cx Instance.
1055 * @note These bits can only be programmed when TimeoutA is disabled.
1056 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1057 * @param I2Cx I2C Instance.
1058 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1059 * @retval None
1060 */
1061 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1062 {
1063 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1064 }
1065
1066 /**
1067 * @brief Get the SMBus Clock TimeoutA setting.
1068 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1069 * SMBus feature is supported by the I2Cx Instance.
1070 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1071 * @param I2Cx I2C Instance.
1072 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1073 */
1074 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1075 {
1076 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1077 }
1078
1079 /**
1080 * @brief Set the SMBus Clock TimeoutA mode.
1081 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1082 * SMBus feature is supported by the I2Cx Instance.
1083 * @note This bit can only be programmed when TimeoutA is disabled.
1084 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1085 * @param I2Cx I2C Instance.
1086 * @param TimeoutAMode This parameter can be one of the following values:
1087 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1088 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1089 * @retval None
1090 */
1091 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1092 {
1093 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1094 }
1095
1096 /**
1097 * @brief Get the SMBus Clock TimeoutA mode.
1098 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1099 * SMBus feature is supported by the I2Cx Instance.
1100 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1101 * @param I2Cx I2C Instance.
1102 * @retval Returned value can be one of the following values:
1103 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1104 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1105 */
1106 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1107 {
1108 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1109 }
1110
1111 /**
1112 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1113 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1114 * SMBus feature is supported by the I2Cx Instance.
1115 * @note These bits can only be programmed when TimeoutB is disabled.
1116 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1117 * @param I2Cx I2C Instance.
1118 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1119 * @retval None
1120 */
1121 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1122 {
1123 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1124 }
1125
1126 /**
1127 * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
1128 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1129 * SMBus feature is supported by the I2Cx Instance.
1130 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1131 * @param I2Cx I2C Instance.
1132 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1133 */
1134 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1135 {
1136 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1137 }
1138
1139 /**
1140 * @brief Enable the SMBus Clock Timeout.
1141 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1142 * SMBus feature is supported by the I2Cx Instance.
1143 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1144 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1145 * @param I2Cx I2C Instance.
1146 * @param ClockTimeout This parameter can be one of the following values:
1147 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1148 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1149 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1150 * @retval None
1151 */
1152 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1153 {
1154 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1155 }
1156
1157 /**
1158 * @brief Disable the SMBus Clock Timeout.
1159 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1160 * SMBus feature is supported by the I2Cx Instance.
1161 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1162 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1163 * @param I2Cx I2C Instance.
1164 * @param ClockTimeout This parameter can be one of the following values:
1165 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1166 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1167 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1168 * @retval None
1169 */
1170 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1171 {
1172 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1173 }
1174
1175 /**
1176 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1177 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1178 * SMBus feature is supported by the I2Cx Instance.
1179 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1180 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1181 * @param I2Cx I2C Instance.
1182 * @param ClockTimeout This parameter can be one of the following values:
1183 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1184 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1185 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1186 * @retval State of bit (1 or 0).
1187 */
1188 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1189 {
1190 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
1191 }
1192
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1198 * @{
1199 */
1200
1201 /**
1202 * @brief Enable TXIS interrupt.
1203 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1204 * @param I2Cx I2C Instance.
1205 * @retval None
1206 */
1207 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1208 {
1209 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1210 }
1211
1212 /**
1213 * @brief Disable TXIS interrupt.
1214 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1215 * @param I2Cx I2C Instance.
1216 * @retval None
1217 */
1218 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1219 {
1220 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1221 }
1222
1223 /**
1224 * @brief Check if the TXIS Interrupt is enabled or disabled.
1225 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1226 * @param I2Cx I2C Instance.
1227 * @retval State of bit (1 or 0).
1228 */
1229 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1230 {
1231 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1232 }
1233
1234 /**
1235 * @brief Enable RXNE interrupt.
1236 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1237 * @param I2Cx I2C Instance.
1238 * @retval None
1239 */
1240 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1241 {
1242 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1243 }
1244
1245 /**
1246 * @brief Disable RXNE interrupt.
1247 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1248 * @param I2Cx I2C Instance.
1249 * @retval None
1250 */
1251 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1252 {
1253 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1254 }
1255
1256 /**
1257 * @brief Check if the RXNE Interrupt is enabled or disabled.
1258 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1259 * @param I2Cx I2C Instance.
1260 * @retval State of bit (1 or 0).
1261 */
1262 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1263 {
1264 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1265 }
1266
1267 /**
1268 * @brief Enable Address match interrupt (slave mode only).
1269 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1270 * @param I2Cx I2C Instance.
1271 * @retval None
1272 */
1273 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1274 {
1275 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1276 }
1277
1278 /**
1279 * @brief Disable Address match interrupt (slave mode only).
1280 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1281 * @param I2Cx I2C Instance.
1282 * @retval None
1283 */
1284 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1285 {
1286 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1287 }
1288
1289 /**
1290 * @brief Check if Address match interrupt is enabled or disabled.
1291 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1292 * @param I2Cx I2C Instance.
1293 * @retval State of bit (1 or 0).
1294 */
1295 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1296 {
1297 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1298 }
1299
1300 /**
1301 * @brief Enable Not acknowledge received interrupt.
1302 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1303 * @param I2Cx I2C Instance.
1304 * @retval None
1305 */
1306 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1307 {
1308 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1309 }
1310
1311 /**
1312 * @brief Disable Not acknowledge received interrupt.
1313 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1314 * @param I2Cx I2C Instance.
1315 * @retval None
1316 */
1317 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1318 {
1319 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1320 }
1321
1322 /**
1323 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1324 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1325 * @param I2Cx I2C Instance.
1326 * @retval State of bit (1 or 0).
1327 */
1328 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1329 {
1330 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1331 }
1332
1333 /**
1334 * @brief Enable STOP detection interrupt.
1335 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1336 * @param I2Cx I2C Instance.
1337 * @retval None
1338 */
1339 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1340 {
1341 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1342 }
1343
1344 /**
1345 * @brief Disable STOP detection interrupt.
1346 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1347 * @param I2Cx I2C Instance.
1348 * @retval None
1349 */
1350 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1351 {
1352 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1353 }
1354
1355 /**
1356 * @brief Check if STOP detection interrupt is enabled or disabled.
1357 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1358 * @param I2Cx I2C Instance.
1359 * @retval State of bit (1 or 0).
1360 */
1361 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1362 {
1363 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1364 }
1365
1366 /**
1367 * @brief Enable Transfer Complete interrupt.
1368 * @note Any of these events will generate interrupt :
1369 * Transfer Complete (TC)
1370 * Transfer Complete Reload (TCR)
1371 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1372 * @param I2Cx I2C Instance.
1373 * @retval None
1374 */
1375 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1376 {
1377 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1378 }
1379
1380 /**
1381 * @brief Disable Transfer Complete interrupt.
1382 * @note Any of these events will generate interrupt :
1383 * Transfer Complete (TC)
1384 * Transfer Complete Reload (TCR)
1385 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1386 * @param I2Cx I2C Instance.
1387 * @retval None
1388 */
1389 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1390 {
1391 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1392 }
1393
1394 /**
1395 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1396 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1397 * @param I2Cx I2C Instance.
1398 * @retval State of bit (1 or 0).
1399 */
1400 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1401 {
1402 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Enable Error interrupts.
1407 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1408 * SMBus feature is supported by the I2Cx Instance.
1409 * @note Any of these errors will generate interrupt :
1410 * Arbitration Loss (ARLO)
1411 * Bus Error detection (BERR)
1412 * Overrun/Underrun (OVR)
1413 * SMBus Timeout detection (TIMEOUT)
1414 * SMBus PEC error detection (PECERR)
1415 * SMBus Alert pin event detection (ALERT)
1416 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1417 * @param I2Cx I2C Instance.
1418 * @retval None
1419 */
1420 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1421 {
1422 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1423 }
1424
1425 /**
1426 * @brief Disable Error interrupts.
1427 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1428 * SMBus feature is supported by the I2Cx Instance.
1429 * @note Any of these errors will generate interrupt :
1430 * Arbitration Loss (ARLO)
1431 * Bus Error detection (BERR)
1432 * Overrun/Underrun (OVR)
1433 * SMBus Timeout detection (TIMEOUT)
1434 * SMBus PEC error detection (PECERR)
1435 * SMBus Alert pin event detection (ALERT)
1436 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1437 * @param I2Cx I2C Instance.
1438 * @retval None
1439 */
1440 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1441 {
1442 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1443 }
1444
1445 /**
1446 * @brief Check if Error interrupts are enabled or disabled.
1447 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1448 * @param I2Cx I2C Instance.
1449 * @retval State of bit (1 or 0).
1450 */
1451 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1452 {
1453 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1454 }
1455
1456 /**
1457 * @}
1458 */
1459
1460 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1461 * @{
1462 */
1463
1464 /**
1465 * @brief Indicate the status of Transmit data register empty flag.
1466 * @note RESET: When next data is written in Transmit data register.
1467 * SET: When Transmit data register is empty.
1468 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1469 * @param I2Cx I2C Instance.
1470 * @retval State of bit (1 or 0).
1471 */
1472 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1473 {
1474 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1475 }
1476
1477 /**
1478 * @brief Indicate the status of Transmit interrupt flag.
1479 * @note RESET: When next data is written in Transmit data register.
1480 * SET: When Transmit data register is empty.
1481 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1482 * @param I2Cx I2C Instance.
1483 * @retval State of bit (1 or 0).
1484 */
1485 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1486 {
1487 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1488 }
1489
1490 /**
1491 * @brief Indicate the status of Receive data register not empty flag.
1492 * @note RESET: When Receive data register is read.
1493 * SET: When the received data is copied in Receive data register.
1494 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1495 * @param I2Cx I2C Instance.
1496 * @retval State of bit (1 or 0).
1497 */
1498 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1499 {
1500 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Indicate the status of Address matched flag (slave mode).
1505 * @note RESET: Clear default value.
1506 * SET: When the received slave address matched with one of the enabled slave address.
1507 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1508 * @param I2Cx I2C Instance.
1509 * @retval State of bit (1 or 0).
1510 */
1511 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1512 {
1513 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1514 }
1515
1516 /**
1517 * @brief Indicate the status of Not Acknowledge received flag.
1518 * @note RESET: Clear default value.
1519 * SET: When a NACK is received after a byte transmission.
1520 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1521 * @param I2Cx I2C Instance.
1522 * @retval State of bit (1 or 0).
1523 */
1524 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1525 {
1526 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1527 }
1528
1529 /**
1530 * @brief Indicate the status of Stop detection flag.
1531 * @note RESET: Clear default value.
1532 * SET: When a Stop condition is detected.
1533 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1534 * @param I2Cx I2C Instance.
1535 * @retval State of bit (1 or 0).
1536 */
1537 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1538 {
1539 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1540 }
1541
1542 /**
1543 * @brief Indicate the status of Transfer complete flag (master mode).
1544 * @note RESET: Clear default value.
1545 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1546 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1547 * @param I2Cx I2C Instance.
1548 * @retval State of bit (1 or 0).
1549 */
1550 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1551 {
1552 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1553 }
1554
1555 /**
1556 * @brief Indicate the status of Transfer complete flag (master mode).
1557 * @note RESET: Clear default value.
1558 * SET: When RELOAD=1 and NBYTES date have been transferred.
1559 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1560 * @param I2Cx I2C Instance.
1561 * @retval State of bit (1 or 0).
1562 */
1563 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1564 {
1565 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1566 }
1567
1568 /**
1569 * @brief Indicate the status of Bus error flag.
1570 * @note RESET: Clear default value.
1571 * SET: When a misplaced Start or Stop condition is detected.
1572 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1573 * @param I2Cx I2C Instance.
1574 * @retval State of bit (1 or 0).
1575 */
1576 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1577 {
1578 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1579 }
1580
1581 /**
1582 * @brief Indicate the status of Arbitration lost flag.
1583 * @note RESET: Clear default value.
1584 * SET: When arbitration lost.
1585 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1586 * @param I2Cx I2C Instance.
1587 * @retval State of bit (1 or 0).
1588 */
1589 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1590 {
1591 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1596 * @note RESET: Clear default value.
1597 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1598 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1599 * @param I2Cx I2C Instance.
1600 * @retval State of bit (1 or 0).
1601 */
1602 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1603 {
1604 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief Indicate the status of SMBus PEC error flag in reception.
1609 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1610 * SMBus feature is supported by the I2Cx Instance.
1611 * @note RESET: Clear default value.
1612 * SET: When the received PEC does not match with the PEC register content.
1613 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1614 * @param I2Cx I2C Instance.
1615 * @retval State of bit (1 or 0).
1616 */
1617 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1618 {
1619 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1620 }
1621
1622 /**
1623 * @brief Indicate the status of SMBus Timeout detection flag.
1624 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1625 * SMBus feature is supported by the I2Cx Instance.
1626 * @note RESET: Clear default value.
1627 * SET: When a timeout or extended clock timeout occurs.
1628 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1629 * @param I2Cx I2C Instance.
1630 * @retval State of bit (1 or 0).
1631 */
1632 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1633 {
1634 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @brief Indicate the status of SMBus alert flag.
1639 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1640 * SMBus feature is supported by the I2Cx Instance.
1641 * @note RESET: Clear default value.
1642 * SET: When SMBus host configuration, SMBus alert enabled and
1643 * a falling edge event occurs on SMBA pin.
1644 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1645 * @param I2Cx I2C Instance.
1646 * @retval State of bit (1 or 0).
1647 */
1648 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1649 {
1650 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1651 }
1652
1653 /**
1654 * @brief Indicate the status of Bus Busy flag.
1655 * @note RESET: Clear default value.
1656 * SET: When a Start condition is detected.
1657 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1658 * @param I2Cx I2C Instance.
1659 * @retval State of bit (1 or 0).
1660 */
1661 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1662 {
1663 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1664 }
1665
1666 /**
1667 * @brief Clear Address Matched flag.
1668 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1669 * @param I2Cx I2C Instance.
1670 * @retval None
1671 */
1672 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1673 {
1674 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1675 }
1676
1677 /**
1678 * @brief Clear Not Acknowledge flag.
1679 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1680 * @param I2Cx I2C Instance.
1681 * @retval None
1682 */
1683 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1684 {
1685 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1686 }
1687
1688 /**
1689 * @brief Clear Stop detection flag.
1690 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1691 * @param I2Cx I2C Instance.
1692 * @retval None
1693 */
1694 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1695 {
1696 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1697 }
1698
1699 /**
1700 * @brief Clear Transmit data register empty flag (TXE).
1701 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1702 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1703 * @param I2Cx I2C Instance.
1704 * @retval None
1705 */
1706 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1707 {
1708 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1709 }
1710
1711 /**
1712 * @brief Clear Bus error flag.
1713 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1714 * @param I2Cx I2C Instance.
1715 * @retval None
1716 */
1717 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1718 {
1719 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1720 }
1721
1722 /**
1723 * @brief Clear Arbitration lost flag.
1724 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1725 * @param I2Cx I2C Instance.
1726 * @retval None
1727 */
1728 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1729 {
1730 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1731 }
1732
1733 /**
1734 * @brief Clear Overrun/Underrun flag.
1735 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1736 * @param I2Cx I2C Instance.
1737 * @retval None
1738 */
1739 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1740 {
1741 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1742 }
1743
1744 /**
1745 * @brief Clear SMBus PEC error flag.
1746 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1747 * SMBus feature is supported by the I2Cx Instance.
1748 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1749 * @param I2Cx I2C Instance.
1750 * @retval None
1751 */
1752 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1753 {
1754 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1755 }
1756
1757 /**
1758 * @brief Clear SMBus Timeout detection flag.
1759 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1760 * SMBus feature is supported by the I2Cx Instance.
1761 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1762 * @param I2Cx I2C Instance.
1763 * @retval None
1764 */
1765 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1766 {
1767 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1768 }
1769
1770 /**
1771 * @brief Clear SMBus Alert flag.
1772 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1773 * SMBus feature is supported by the I2Cx Instance.
1774 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1775 * @param I2Cx I2C Instance.
1776 * @retval None
1777 */
1778 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1779 {
1780 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1781 }
1782
1783 /**
1784 * @}
1785 */
1786
1787 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1788 * @{
1789 */
1790
1791 /**
1792 * @brief Enable automatic STOP condition generation (master mode).
1793 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1794 * This bit has no effect in slave mode or when RELOAD bit is set.
1795 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1796 * @param I2Cx I2C Instance.
1797 * @retval None
1798 */
1799 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1800 {
1801 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1802 }
1803
1804 /**
1805 * @brief Disable automatic STOP condition generation (master mode).
1806 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1807 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1808 * @param I2Cx I2C Instance.
1809 * @retval None
1810 */
1811 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1812 {
1813 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1814 }
1815
1816 /**
1817 * @brief Check if automatic STOP condition is enabled or disabled.
1818 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1819 * @param I2Cx I2C Instance.
1820 * @retval State of bit (1 or 0).
1821 */
1822 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1823 {
1824 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1825 }
1826
1827 /**
1828 * @brief Enable reload mode (master mode).
1829 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1830 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1831 * @param I2Cx I2C Instance.
1832 * @retval None
1833 */
1834 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1835 {
1836 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1837 }
1838
1839 /**
1840 * @brief Disable reload mode (master mode).
1841 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1842 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1843 * @param I2Cx I2C Instance.
1844 * @retval None
1845 */
1846 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1847 {
1848 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1849 }
1850
1851 /**
1852 * @brief Check if reload mode is enabled or disabled.
1853 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1854 * @param I2Cx I2C Instance.
1855 * @retval State of bit (1 or 0).
1856 */
1857 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1858 {
1859 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1860 }
1861
1862 /**
1863 * @brief Configure the number of bytes for transfer.
1864 * @note Changing these bits when START bit is set is not allowed.
1865 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1866 * @param I2Cx I2C Instance.
1867 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1868 * @retval None
1869 */
1870 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1871 {
1872 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1873 }
1874
1875 /**
1876 * @brief Get the number of bytes configured for transfer.
1877 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1878 * @param I2Cx I2C Instance.
1879 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1880 */
1881 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1882 {
1883 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1884 }
1885
1886 /**
1887 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1888 * @note Usage in Slave mode only.
1889 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1890 * @param I2Cx I2C Instance.
1891 * @param TypeAcknowledge This parameter can be one of the following values:
1892 * @arg @ref LL_I2C_ACK
1893 * @arg @ref LL_I2C_NACK
1894 * @retval None
1895 */
1896 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1897 {
1898 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1899 }
1900
1901 /**
1902 * @brief Generate a START or RESTART condition
1903 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1904 * This action has no effect when RELOAD is set.
1905 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1906 * @param I2Cx I2C Instance.
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1910 {
1911 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1912 }
1913
1914 /**
1915 * @brief Generate a STOP condition after the current byte transfer (master mode).
1916 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1917 * @param I2Cx I2C Instance.
1918 * @retval None
1919 */
1920 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1921 {
1922 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1923 }
1924
1925 /**
1926 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1927 * @note The master sends the complete 10bit slave address read sequence :
1928 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
1929 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1930 * @param I2Cx I2C Instance.
1931 * @retval None
1932 */
1933 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1934 {
1935 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1936 }
1937
1938 /**
1939 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1940 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1941 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1942 * @param I2Cx I2C Instance.
1943 * @retval None
1944 */
1945 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
1946 {
1947 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1948 }
1949
1950 /**
1951 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1952 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
1953 * @param I2Cx I2C Instance.
1954 * @retval State of bit (1 or 0).
1955 */
1956 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
1957 {
1958 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
1959 }
1960
1961 /**
1962 * @brief Configure the transfer direction (master mode).
1963 * @note Changing these bits when START bit is set is not allowed.
1964 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
1965 * @param I2Cx I2C Instance.
1966 * @param TransferRequest This parameter can be one of the following values:
1967 * @arg @ref LL_I2C_REQUEST_WRITE
1968 * @arg @ref LL_I2C_REQUEST_READ
1969 * @retval None
1970 */
1971 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
1972 {
1973 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
1974 }
1975
1976 /**
1977 * @brief Get the transfer direction requested (master mode).
1978 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
1979 * @param I2Cx I2C Instance.
1980 * @retval Returned value can be one of the following values:
1981 * @arg @ref LL_I2C_REQUEST_WRITE
1982 * @arg @ref LL_I2C_REQUEST_READ
1983 */
1984 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
1985 {
1986 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
1987 }
1988
1989 /**
1990 * @brief Configure the slave address for transfer (master mode).
1991 * @note Changing these bits when START bit is set is not allowed.
1992 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
1993 * @param I2Cx I2C Instance.
1994 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
1995 * @retval None
1996 */
1997 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
1998 {
1999 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2000 }
2001
2002 /**
2003 * @brief Get the slave address programmed for transfer.
2004 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2005 * @param I2Cx I2C Instance.
2006 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2007 */
2008 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2009 {
2010 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2011 }
2012
2013 /**
2014 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2015 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2016 * CR2 ADD10 LL_I2C_HandleTransfer\n
2017 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2018 * CR2 START LL_I2C_HandleTransfer\n
2019 * CR2 STOP LL_I2C_HandleTransfer\n
2020 * CR2 RELOAD LL_I2C_HandleTransfer\n
2021 * CR2 NBYTES LL_I2C_HandleTransfer\n
2022 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2023 * CR2 HEAD10R LL_I2C_HandleTransfer
2024 * @param I2Cx I2C Instance.
2025 * @param SlaveAddr Specifies the slave address to be programmed.
2026 * @param SlaveAddrSize This parameter can be one of the following values:
2027 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2028 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2029 * @param TransferSize Specifies the number of bytes to be programmed.
2030 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2031 * @param EndMode This parameter can be one of the following values:
2032 * @arg @ref LL_I2C_MODE_RELOAD
2033 * @arg @ref LL_I2C_MODE_AUTOEND
2034 * @arg @ref LL_I2C_MODE_SOFTEND
2035 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2036 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2037 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2038 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2039 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2040 * @param Request This parameter can be one of the following values:
2041 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2042 * @arg @ref LL_I2C_GENERATE_STOP
2043 * @arg @ref LL_I2C_GENERATE_START_READ
2044 * @arg @ref LL_I2C_GENERATE_START_WRITE
2045 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2046 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2047 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2048 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2049 * @retval None
2050 */
2051 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2052 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2053 {
2054 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2055 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2056 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2057 }
2058
2059 /**
2060 * @brief Indicate the value of transfer direction (slave mode).
2061 * @note RESET: Write transfer, Slave enters in receiver mode.
2062 * SET: Read transfer, Slave enters in transmitter mode.
2063 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2064 * @param I2Cx I2C Instance.
2065 * @retval Returned value can be one of the following values:
2066 * @arg @ref LL_I2C_DIRECTION_WRITE
2067 * @arg @ref LL_I2C_DIRECTION_READ
2068 */
2069 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2070 {
2071 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2072 }
2073
2074 /**
2075 * @brief Return the slave matched address.
2076 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2077 * @param I2Cx I2C Instance.
2078 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2079 */
2080 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2081 {
2082 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2083 }
2084
2085 /**
2086 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2087 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2088 * SMBus feature is supported by the I2Cx Instance.
2089 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
2090 * This bit has no effect when RELOAD bit is set.
2091 * This bit has no effect in device mode when SBC bit is not set.
2092 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2093 * @param I2Cx I2C Instance.
2094 * @retval None
2095 */
2096 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2097 {
2098 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2099 }
2100
2101 /**
2102 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2103 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2104 * SMBus feature is supported by the I2Cx Instance.
2105 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2106 * @param I2Cx I2C Instance.
2107 * @retval State of bit (1 or 0).
2108 */
2109 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2110 {
2111 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Get the SMBus Packet Error byte calculated.
2116 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2117 * SMBus feature is supported by the I2Cx Instance.
2118 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2119 * @param I2Cx I2C Instance.
2120 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2121 */
2122 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2123 {
2124 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2125 }
2126
2127 /**
2128 * @brief Read Receive Data register.
2129 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2130 * @param I2Cx I2C Instance.
2131 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2132 */
2133 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2134 {
2135 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2136 }
2137
2138 /**
2139 * @brief Write in Transmit Data Register .
2140 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2141 * @param I2Cx I2C Instance.
2142 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2143 * @retval None
2144 */
2145 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2146 {
2147 WRITE_REG(I2Cx->TXDR, Data);
2148 }
2149
2150 /**
2151 * @}
2152 */
2153
2154 #if defined(USE_FULL_LL_DRIVER)
2155 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2156 * @{
2157 */
2158
2159 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2160 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2161 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2162
2163
2164 /**
2165 * @}
2166 */
2167 #endif /* USE_FULL_LL_DRIVER */
2168
2169 /**
2170 * @}
2171 */
2172
2173 /**
2174 * @}
2175 */
2176
2177 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
2178
2179 /**
2180 * @}
2181 */
2182
2183 #ifdef __cplusplus
2184 }
2185 #endif
2186
2187 #endif /* STM32F7xx_LL_I2C_H */
2188
2189 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/