lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_ll_pwr.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of PWR LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32F7xx_LL_PWR_H
  22 #define __STM32F7xx_LL_PWR_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32f7xx.h"
  30
  31 /** @addtogroup STM32F7xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined(PWR)
  36
  37 /** @defgroup PWR_LL PWR
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45 /* Exported types ------------------------------------------------------------*/
  46 /* Exported constants --------------------------------------------------------*/
  47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
  48   * @{
  49   */
  50
  51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
  52   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
  53   * @{
  54   */
  55 #define LL_PWR_CR1_CSBF                    PWR_CR1_CSBF            /*!< Clear standby flag */
  56
  57 #define LL_PWR_CR2_CWUF6                   PWR_CR2_CWUF6           /*!< Clear WKUP pin 6 */
  58 #define LL_PWR_CR2_CWUF5                   PWR_CR2_CWUF5           /*!< Clear WKUP pin 5 */
  59 #define LL_PWR_CR2_CWUF4                   PWR_CR2_CWUF4           /*!< Clear WKUP pin 4 */
  60 #define LL_PWR_CR2_CWUF3                   PWR_CR2_CWUF3           /*!< Clear WKUP pin 3 */
  61 #define LL_PWR_CR2_CWUF2                   PWR_CR2_CWUF2           /*!< Clear WKUP pin 2 */
  62 #define LL_PWR_CR2_CWUF1                   PWR_CR2_CWUF1           /*!< Clear WKUP pin 1 */
  63 /**
  64   * @}
  65   */
  66
  67 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
  68   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
  69   * @{
  70   */
  71 #define LL_PWR_CSR1_WUIF                   PWR_CSR1_WUIF           /*!< Wakeup flag */
  72 #define LL_PWR_CSR1_SBF                    PWR_CSR1_SBF            /*!< Standby flag */
  73 #define LL_PWR_CSR1_PVDO                   PWR_CSR1_PVDO           /*!< Power voltage detector output flag */
  74 #define LL_PWR_CSR1_BRR                    PWR_CSR1_BRR            /*!< Backup Regulator ready flag */
  75 #define LL_PWR_CSR1_VOSRDY                 PWR_CSR1_VOSRDY         /*!< Voltage scaling select flag */
  76 #define LL_PWR_CSR1_ODRDY                  PWR_CSR1_ODRDY          /*!< Over-drive mode ready */
  77 #define LL_PWR_CSR1_ODSWRDY                PWR_CSR1_ODSWRDY        /*!< Over-drive mode switching ready */
  78 #define LL_PWR_CSR1_UDRDY                  PWR_CSR1_UDRDY          /*!< Under-drive ready flag */
  79
  80 #define LL_PWR_CSR2_EWUP1                  PWR_CSR2_EWUP1          /*!< Enable WKUP pin 1 */
  81 #define LL_PWR_CSR2_EWUP2                  PWR_CSR2_EWUP2          /*!< Enable WKUP pin 2 */
  82 #define LL_PWR_CSR2_EWUP3                  PWR_CSR2_EWUP3          /*!< Enable WKUP pin 3 */
  83 #define LL_PWR_CSR2_EWUP4                  PWR_CSR2_EWUP4          /*!< Enable WKUP pin 4 */
  84 #define LL_PWR_CSR2_EWUP5                  PWR_CSR2_EWUP5          /*!< Enable WKUP pin 5 */
  85 #define LL_PWR_CSR2_EWUP6                  PWR_CSR2_EWUP6          /*!< Enable WKUP pin 6 */
  86 /**
  87   * @}
  88   */
  89
  90 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
  91   * @{
  92   */
  93 #define LL_PWR_MODE_STOP_MAINREGU                     0x00000000U                                    /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */
  94 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE          (PWR_CR1_MRUDS | PWR_CR1_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
  95 #define LL_PWR_MODE_STOP_LPREGU                       PWR_CR1_LPDS                                   /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
  96 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE            (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS)  /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
  97 #define LL_PWR_MODE_STANDBY                           PWR_CR1_PDDS                                   /*!< Enter Standby mode when the CPU enters deepsleep */
  98 /**
  99   * @}
 100   */
 101
 102 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
 103   * @{
 104   */
 105 #define LL_PWR_REGU_VOLTAGE_SCALE3         PWR_CR1_VOS_0
 106 #define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
 107 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0 | PWR_CR1_VOS_1)
 108 /**
 109   * @}
 110   */
 111
 112 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
 113   * @{
 114   */
 115 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U                    /*!< Voltage Regulator in main mode during deepsleep mode */
 116 #define LL_PWR_REGU_DSMODE_LOW_POWER   PWR_CR1_LPDS                   /*!< Voltage Regulator in low-power mode during deepsleep mode */
 117 /**
 118   * @}
 119   */
 120
 121 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
 122   * @{
 123   */
 124 #define LL_PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0      /*!< Voltage threshold detected by PVD 2.0 V */
 125 #define LL_PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1      /*!< Voltage threshold detected by PVD 2.1 V */
 126 #define LL_PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2      /*!< Voltage threshold detected by PVD 2.3 V */
 127 #define LL_PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3      /*!< Voltage threshold detected by PVD 2.5 V */
 128 #define LL_PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4      /*!< Voltage threshold detected by PVD 2.6 V */
 129 #define LL_PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5      /*!< Voltage threshold detected by PVD 2.7 V */
 130 #define LL_PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6      /*!< Voltage threshold detected by PVD 2.8 V */
 131 #define LL_PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7      /*!< Voltage threshold detected by PVD 2.9 V */
 132 /**
 133   * @}
 134   */
 135
 136 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
 137   * @{
 138   */
 139 #define LL_PWR_WAKEUP_PIN1                 PWR_CSR2_EWUP1        /*!< WKUP pin 1 : PA0  */
 140 #define LL_PWR_WAKEUP_PIN2                 PWR_CSR2_EWUP2        /*!< WKUP pin 2 : PA2  */
 141 #define LL_PWR_WAKEUP_PIN3                 PWR_CSR2_EWUP3        /*!< WKUP pin 3 : PC1  */
 142 #define LL_PWR_WAKEUP_PIN4                 PWR_CSR2_EWUP4        /*!< WKUP pin 4 : PC13 */
 143 #define LL_PWR_WAKEUP_PIN5                 PWR_CSR2_EWUP5        /*!< WKUP pin 5 : PI8  */
 144 #define LL_PWR_WAKEUP_PIN6                 PWR_CSR2_EWUP6        /*!< WKUP pin 6 : PI11 */
 145 /**
 146   * @}
 147   */
 148
 149 /**
 150   * @}
 151   */
 152 /* Exported macro ------------------------------------------------------------*/
 153 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
 154   * @{
 155   */
 156
 157 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
 158   * @{
 159   */
 160
 161 /**
 162   * @brief  Write a value in PWR register
 163   * @param  __REG__ Register to be written
 164   * @param  __VALUE__ Value to be written in the register
 165   * @retval None
 166   */
 167 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
 168
 169 /**
 170   * @brief  Read a value in PWR register
 171   * @param  __REG__ Register to be read
 172   * @retval Register value
 173   */
 174 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
 175 /**
 176   * @}
 177   */
 178
 179 /**
 180   * @}
 181   */
 182 /* Exported functions --------------------------------------------------------*/
 183 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
 184   * @{
 185   */
 186
 187 /** @defgroup PWR_LL_EF_Configuration Configuration
 188   * @{
 189   */
 190
 191 /**
 192   * @brief  Enable Under Drive Mode
 193   * @rmtoll CR1    UDEN       LL_PWR_EnableUnderDriveMode
 194   * @note  This mode is enabled only with STOP low power mode.
 195   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
 196   *        mode is only available when the main Regulator or the low power Regulator
 197   *        is in low voltage mode.
 198   * @note  If the Under-drive mode was enabled, it is automatically disabled after
 199   *        exiting Stop mode.
 200   *        When the voltage Regulator operates in Under-drive mode, an additional
 201   *        startup delay is induced when waking up from Stop mode.
 202   * @retval None
 203   */
 204 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
 205 {
 206   SET_BIT(PWR->CR1, PWR_CR1_UDEN);
 207 }
 208
 209 /**
 210   * @brief  Disable Under Drive Mode
 211   * @rmtoll CR1    UDEN       LL_PWR_DisableUnderDriveMode
 212   * @retval None
 213   */
 214 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
 215 {
 216   CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);
 217 }
 218
 219 /**
 220   * @brief  Check if Under Drive Mode is enabled
 221   * @rmtoll CR1    UDEN       LL_PWR_IsEnabledUnderDriveMode
 222   * @retval State of bit (1 or 0).
 223   */
 224 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
 225 {
 226   return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));
 227 }
 228
 229 /**
 230   * @brief  Enable Over drive switching
 231   * @rmtoll CR1    ODSWEN       LL_PWR_EnableOverDriveSwitching
 232   * @retval None
 233   */
 234 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
 235 {
 236   SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);
 237 }
 238
 239 /**
 240   * @brief  Disable Over drive switching
 241   * @rmtoll CR1    ODSWEN       LL_PWR_DisableOverDriveSwitching
 242   * @retval None
 243   */
 244 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
 245 {
 246   CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);
 247 }
 248
 249 /**
 250   * @brief  Check if Over drive switching is enabled
 251   * @rmtoll CR1    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
 252   * @retval State of bit (1 or 0).
 253   */
 254 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
 255 {
 256   return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));
 257 }
 258
 259 /**
 260   * @brief  Enable Over drive Mode
 261   * @rmtoll CR1    ODEN       LL_PWR_EnableOverDriveMode
 262   * @retval None
 263   */
 264 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
 265 {
 266   SET_BIT(PWR->CR1, PWR_CR1_ODEN);
 267 }
 268
 269 /**
 270   * @brief  Disable Over drive Mode
 271   * @rmtoll CR1    ODEN       LL_PWR_DisableOverDriveMode
 272   * @retval None
 273   */
 274 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
 275 {
 276   CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);
 277 }
 278
 279 /**
 280   * @brief  Check if Over drive switching is enabled
 281   * @rmtoll CR1    ODEN       LL_PWR_IsEnabledOverDriveMode
 282   * @retval State of bit (1 or 0).
 283   */
 284 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
 285 {
 286   return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));
 287 }
 288
 289 /**
 290   * @brief  Set the main internal Regulator output voltage
 291   * @rmtoll CR1    VOS       LL_PWR_SetRegulVoltageScaling
 292   * @param  VoltageScaling This parameter can be one of the following values:
 293   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
 294   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
 295   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
 296   * @retval None
 297   */
 298 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
 299 {
 300   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
 301 }
 302
 303 /**
 304   * @brief  Get the main internal Regulator output voltage
 305   * @rmtoll CR1    VOS       LL_PWR_GetRegulVoltageScaling
 306   * @retval Returned value can be one of the following values:
 307   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
 308   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
 309   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
 310   */
 311 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
 312 {
 313   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
 314 }
 315
 316 /**
 317   * @brief  Enable Main Regulator in deepsleep under-drive Mode
 318   * @rmtoll CR1    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
 319   * @retval None
 320   */
 321 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
 322 {
 323   SET_BIT(PWR->CR1, PWR_CR1_MRUDS);
 324 }
 325
 326 /**
 327   * @brief  Disable Main Regulator in deepsleep under-drive Mode
 328   * @rmtoll CR1    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
 329   * @retval None
 330   */
 331 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
 332 {
 333   CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS);
 334 }
 335
 336 /**
 337   * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
 338   * @rmtoll CR1    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
 339   * @retval State of bit (1 or 0).
 340   */
 341 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
 342 {
 343   return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS));
 344 }
 345
 346 /**
 347   * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
 348   * @rmtoll CR1    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
 349   * @retval None
 350   */
 351 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
 352 {
 353   SET_BIT(PWR->CR1, PWR_CR1_LPUDS);
 354 }
 355
 356 /**
 357   * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
 358   * @rmtoll CR1    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
 359   * @retval None
 360   */
 361 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
 362 {
 363   CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS);
 364 }
 365
 366 /**
 367   * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
 368   * @rmtoll CR1    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
 369   * @retval State of bit (1 or 0).
 370   */
 371 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
 372 {
 373   return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS));
 374 }
 375
 376 /**
 377   * @brief  Enable the Flash Power Down in Stop Mode
 378   * @rmtoll CR1    FPDS       LL_PWR_EnableFlashPowerDown
 379   * @retval None
 380   */
 381 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
 382 {
 383   SET_BIT(PWR->CR1, PWR_CR1_FPDS);
 384 }
 385
 386 /**
 387   * @brief  Disable the Flash Power Down in Stop Mode
 388   * @rmtoll CR1    FPDS       LL_PWR_DisableFlashPowerDown
 389   * @retval None
 390   */
 391 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
 392 {
 393   CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS);
 394 }
 395
 396 /**
 397   * @brief  Check if the Flash Power Down in Stop Mode is enabled
 398   * @rmtoll CR1    FPDS       LL_PWR_IsEnabledFlashPowerDown
 399   * @retval State of bit (1 or 0).
 400   */
 401 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
 402 {
 403   return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS));
 404 }
 405
 406 /**
 407   * @brief  Enable access to the backup domain
 408   * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
 409   * @retval None
 410   */
 411 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
 412 {
 413   SET_BIT(PWR->CR1, PWR_CR1_DBP);
 414 }
 415
 416 /**
 417   * @brief  Disable access to the backup domain
 418   * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
 419   * @retval None
 420   */
 421 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
 422 {
 423   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
 424 }
 425
 426 /**
 427   * @brief  Check if the backup domain is enabled
 428   * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
 429   * @retval State of bit (1 or 0).
 430   */
 431 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
 432 {
 433   return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
 434 }
 435
 436 /**
 437   * @brief  Enable Backup Regulator
 438   * @rmtoll CSR1    BRE       LL_PWR_EnableBkUpRegulator
 439   * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
 440   *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
 441   *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
 442   *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
 443   *       the data written into the RAM will be maintained in the Standby and VBAT modes.
 444   * @retval None
 445   */
 446 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
 447 {
 448   SET_BIT(PWR->CSR1, PWR_CSR1_BRE);
 449 }
 450
 451 /**
 452   * @brief  Disable Backup Regulator
 453   * @rmtoll CSR1    BRE       LL_PWR_DisableBkUpRegulator
 454   * @retval None
 455   */
 456 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
 457 {
 458   CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE);
 459 }
 460
 461 /**
 462   * @brief  Check if the backup Regulator is enabled
 463   * @rmtoll CSR1    BRE      LL_PWR_IsEnabledBkUpRegulator
 464   * @retval State of bit (1 or 0).
 465   */
 466 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
 467 {
 468   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE));
 469 }
 470
 471 /**
 472   * @brief  Set voltage Regulator mode during deep sleep mode
 473   * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
 474   * @param  RegulMode This parameter can be one of the following values:
 475   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 476   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 477   * @retval None
 478   */
 479 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
 480 {
 481   MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
 482 }
 483
 484 /**
 485   * @brief  Get voltage Regulator mode during deep sleep mode
 486   * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
 487   * @retval Returned value can be one of the following values:
 488   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 489   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 490   */
 491 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
 492 {
 493   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
 494 }
 495
 496 /**
 497   * @brief  Set Power Down mode when CPU enters deepsleep
 498   * @rmtoll CR1    PDDS         LL_PWR_SetPowerMode\n
 499   *         CR1    LPDS         LL_PWR_SetPowerMode\n
 500   *         CR1    FPDS         LL_PWR_SetPowerMode\n
 501   *         CR1    LPUDS        LL_PWR_SetPowerMode\n
 502   *         CR1    MRUDS        LL_PWR_SetPowerMode
 503   * @param  PDMode This parameter can be one of the following values:
 504   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 505   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
 506   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 507   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
 508   *         @arg @ref LL_PWR_MODE_STANDBY
 509   * @retval None
 510   */
 511 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
 512 {
 513   MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode);
 514 }
 515
 516 /**
 517   * @brief  Get Power Down mode when CPU enters deepsleep
 518   * @rmtoll CR1    PDDS         LL_PWR_GetPowerMode\n
 519   *         CR1    LPDS         LL_PWR_GetPowerMode\n
 520   *         CR1    FPDS         LL_PWR_GetPowerMode\n
 521   *         CR1    LPUDS        LL_PWR_GetPowerMode\n
 522   *         CR1    MRUDS        LL_PWR_GetPowerMode
 523   * @retval Returned value can be one of the following values:
 524   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 525   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
 526   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 527   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
 528   *         @arg @ref LL_PWR_MODE_STANDBY
 529   */
 530 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
 531 {
 532   return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS)));
 533 }
 534
 535 /**
 536   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
 537   * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
 538   * @param  PVDLevel This parameter can be one of the following values:
 539   *         @arg @ref LL_PWR_PVDLEVEL_0
 540   *         @arg @ref LL_PWR_PVDLEVEL_1
 541   *         @arg @ref LL_PWR_PVDLEVEL_2
 542   *         @arg @ref LL_PWR_PVDLEVEL_3
 543   *         @arg @ref LL_PWR_PVDLEVEL_4
 544   *         @arg @ref LL_PWR_PVDLEVEL_5
 545   *         @arg @ref LL_PWR_PVDLEVEL_6
 546   *         @arg @ref LL_PWR_PVDLEVEL_7
 547   * @retval None
 548   */
 549 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
 550 {
 551   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
 552 }
 553
 554 /**
 555   * @brief  Get the voltage threshold detection
 556   * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
 557   * @retval Returned value can be one of the following values:
 558   *         @arg @ref LL_PWR_PVDLEVEL_0
 559   *         @arg @ref LL_PWR_PVDLEVEL_1
 560   *         @arg @ref LL_PWR_PVDLEVEL_2
 561   *         @arg @ref LL_PWR_PVDLEVEL_3
 562   *         @arg @ref LL_PWR_PVDLEVEL_4
 563   *         @arg @ref LL_PWR_PVDLEVEL_5
 564   *         @arg @ref LL_PWR_PVDLEVEL_6
 565   *         @arg @ref LL_PWR_PVDLEVEL_7
 566   */
 567 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
 568 {
 569   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
 570 }
 571
 572 /**
 573   * @brief  Enable Power Voltage Detector
 574   * @rmtoll CR1    PVDE       LL_PWR_EnablePVD
 575   * @retval None
 576   */
 577 __STATIC_INLINE void LL_PWR_EnablePVD(void)
 578 {
 579   SET_BIT(PWR->CR1, PWR_CR1_PVDE);
 580 }
 581
 582 /**
 583   * @brief  Disable Power Voltage Detector
 584   * @rmtoll CR1    PVDE       LL_PWR_DisablePVD
 585   * @retval None
 586   */
 587 __STATIC_INLINE void LL_PWR_DisablePVD(void)
 588 {
 589   CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
 590 }
 591
 592 /**
 593   * @brief  Check if Power Voltage Detector is enabled
 594   * @rmtoll CR1    PVDE       LL_PWR_IsEnabledPVD
 595   * @retval State of bit (1 or 0).
 596   */
 597 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
 598 {
 599   return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE));
 600 }
 601
 602 /**
 603   * @brief  Enable the WakeUp PINx functionality
 604   * @rmtoll CSR2   EWUP1       LL_PWR_EnableWakeUpPin\n
 605   *         CSR2   EWUP2       LL_PWR_EnableWakeUpPin\n
 606   *         CSR2   EWUP3       LL_PWR_EnableWakeUpPin\n
 607   *         CSR2   EWUP4       LL_PWR_EnableWakeUpPin\n
 608   *         CSR2   EWUP5       LL_PWR_EnableWakeUpPin\n
 609   *         CSR2   EWUP6       LL_PWR_EnableWakeUpPin
 610   * @param  WakeUpPin This parameter can be one of the following values:
 611   *         @arg @ref LL_PWR_WAKEUP_PIN1
 612   *         @arg @ref LL_PWR_WAKEUP_PIN2
 613   *         @arg @ref LL_PWR_WAKEUP_PIN3
 614   *         @arg @ref LL_PWR_WAKEUP_PIN4
 615   *         @arg @ref LL_PWR_WAKEUP_PIN5
 616   *         @arg @ref LL_PWR_WAKEUP_PIN6
 617   * @retval None
 618   */
 619 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
 620 {
 621   SET_BIT(PWR->CSR2, WakeUpPin);
 622 }
 623
 624 /**
 625   * @brief  Disable the WakeUp PINx functionality
 626   * @rmtoll CSR2   EWUP1       LL_PWR_DisableWakeUpPin\n
 627   *         CSR2   EWUP2       LL_PWR_DisableWakeUpPin\n
 628   *         CSR2   EWUP3       LL_PWR_DisableWakeUpPin\n
 629   *         CSR2   EWUP4       LL_PWR_DisableWakeUpPin\n
 630   *         CSR2   EWUP5       LL_PWR_DisableWakeUpPin\n
 631   *         CSR2   EWUP6       LL_PWR_DisableWakeUpPin
 632   * @param  WakeUpPin This parameter can be one of the following values:
 633   *         @arg @ref LL_PWR_WAKEUP_PIN1
 634   *         @arg @ref LL_PWR_WAKEUP_PIN2
 635   *         @arg @ref LL_PWR_WAKEUP_PIN3
 636   *         @arg @ref LL_PWR_WAKEUP_PIN4
 637   *         @arg @ref LL_PWR_WAKEUP_PIN5
 638   *         @arg @ref LL_PWR_WAKEUP_PIN6
 639   * @retval None
 640   */
 641 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
 642 {
 643   CLEAR_BIT(PWR->CSR2, WakeUpPin);
 644 }
 645
 646 /**
 647   * @brief  Check if the WakeUp PINx functionality is enabled
 648   * @rmtoll CSR2   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
 649   *         CSR2   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
 650   *         CSR2   EWUP3       LL_PWR_IsEnabledWakeUpPin\n
 651   *         CSR2   EWUP4       LL_PWR_IsEnabledWakeUpPin\n
 652   *         CSR2   EWUP5       LL_PWR_IsEnabledWakeUpPin\n
 653   *         CSR2   EWUP6       LL_PWR_IsEnabledWakeUpPin
 654   * @param  WakeUpPin This parameter can be one of the following values:
 655   *         @arg @ref LL_PWR_WAKEUP_PIN1
 656   *         @arg @ref LL_PWR_WAKEUP_PIN2
 657   *         @arg @ref LL_PWR_WAKEUP_PIN3
 658   *         @arg @ref LL_PWR_WAKEUP_PIN4
 659   *         @arg @ref LL_PWR_WAKEUP_PIN5
 660   *         @arg @ref LL_PWR_WAKEUP_PIN6
 661   * @retval State of bit (1 or 0).
 662   */
 663 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
 664 {
 665   return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin));
 666 }
 667
 668 /**
 669   * @brief  Set the Wake-Up pin polarity low for the event detection
 670   * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
 671   *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
 672   *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
 673   *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
 674   *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
 675   *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityLow
 676   * @param  WakeUpPin This parameter can be one of the following values:
 677   *         @arg @ref LL_PWR_WAKEUP_PIN1
 678   *         @arg @ref LL_PWR_WAKEUP_PIN2
 679   *         @arg @ref LL_PWR_WAKEUP_PIN3
 680   *         @arg @ref LL_PWR_WAKEUP_PIN4
 681   *         @arg @ref LL_PWR_WAKEUP_PIN5
 682   *         @arg @ref LL_PWR_WAKEUP_PIN6
 683   * @retval None
 684   */
 685 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
 686 {
 687   SET_BIT(PWR->CR2, WakeUpPin);
 688 }
 689
 690 /**
 691   * @brief  Set the Wake-Up pin polarity high for the event detection
 692   * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
 693   *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
 694   *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
 695   *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
 696   *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
 697   *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityHigh
 698   * @param  WakeUpPin This parameter can be one of the following values:
 699   *         @arg @ref LL_PWR_WAKEUP_PIN1
 700   *         @arg @ref LL_PWR_WAKEUP_PIN2
 701   *         @arg @ref LL_PWR_WAKEUP_PIN3
 702   *         @arg @ref LL_PWR_WAKEUP_PIN4
 703   *         @arg @ref LL_PWR_WAKEUP_PIN5
 704   *         @arg @ref LL_PWR_WAKEUP_PIN6
 705   * @retval None
 706   */
 707 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
 708 {
 709   CLEAR_BIT(PWR->CR2, WakeUpPin);
 710 }
 711
 712 /**
 713   * @brief  Get the Wake-Up pin polarity for the event detection
 714   * @rmtoll CR2   WUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
 715   *         CR2   WUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
 716   *         CR2   WUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
 717   *         CR2   WUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
 718   *         CR2   WUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
 719   *         CR2   WUPP6       LL_PWR_IsWakeUpPinPolarityLow
 720   * @param  WakeUpPin This parameter can be one of the following values:
 721   *         @arg @ref LL_PWR_WAKEUP_PIN1
 722   *         @arg @ref LL_PWR_WAKEUP_PIN2
 723   *         @arg @ref LL_PWR_WAKEUP_PIN3
 724   *         @arg @ref LL_PWR_WAKEUP_PIN4
 725   *         @arg @ref LL_PWR_WAKEUP_PIN5
 726   *         @arg @ref LL_PWR_WAKEUP_PIN6
 727   * @retval State of bit (1 or 0).
 728   */
 729 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
 730 {
 731   return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin));
 732 }
 733
 734 /**
 735   * @brief  Enable Internal WakeUp
 736   * @rmtoll CSR1    EIWUP       LL_PWR_EnableInternalWakeUp
 737   * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp
 738   *  or RTC Wakeup time) are used to wake up the system from Standby mode.
 739   * @retval None
 740   */
 741 __STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void)
 742 {
 743   SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
 744 }
 745
 746 /**
 747   * @brief  Disable Internal WakeUp
 748   * @rmtoll CSR1    EIWUP       LL_PWR_DisableInternalWakeUp
 749   * @retval None
 750   */
 751 __STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void)
 752 {
 753   CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
 754 }
 755
 756 /**
 757   * @brief  Check if the Internal WakeUp functionality is enabled
 758   * @rmtoll CSR1   EIWUP       LL_PWR_IsEnabledInternalWakeUp
 759   * @retval State of bit (1 or 0).
 760   */
 761 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void)
 762 {
 763   return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP));
 764 }
 765
 766 /**
 767   * @}
 768   */
 769
 770 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
 771   * @{
 772   */
 773
 774 /**
 775   * @brief  Get Wake-up Flag 6
 776   * @rmtoll CSR2          WUPF6          LL_PWR_IsActiveFlag_WU6
 777   * @retval State of bit (1 or 0).
 778   */
 779 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
 780 {
 781   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6));
 782 }
 783
 784 /**
 785   * @brief  Get Wake-up Flag 5
 786   * @rmtoll CSR2          WUPF5          LL_PWR_IsActiveFlag_WU5
 787   * @retval State of bit (1 or 0).
 788   */
 789 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
 790 {
 791   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5));
 792 }
 793
 794 /**
 795   * @brief  Get Wake-up Flag 4
 796   * @rmtoll CSR2          WUPF4          LL_PWR_IsActiveFlag_WU4
 797   * @retval State of bit (1 or 0).
 798   */
 799 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
 800 {
 801   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4));
 802 }
 803
 804 /**
 805   * @brief  Get Wake-up Flag 3
 806   * @rmtoll CSR2          WUPF3          LL_PWR_IsActiveFlag_WU3
 807   * @retval State of bit (1 or 0).
 808   */
 809 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
 810 {
 811   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3));
 812 }
 813
 814 /**
 815   * @brief  Get Wake-up Flag 2
 816   * @rmtoll CSR2          WUPF2          LL_PWR_IsActiveFlag_WU2
 817   * @retval State of bit (1 or 0).
 818   */
 819 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
 820 {
 821   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2));
 822 }
 823
 824 /**
 825   * @brief  Get Wake-up Flag 1
 826   * @rmtoll CSR2          WUPF1          LL_PWR_IsActiveFlag_WU1
 827   * @retval State of bit (1 or 0).
 828   */
 829 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
 830 {
 831   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1));
 832 }
 833
 834 /**
 835   * @brief  Get Standby Flag
 836   * @rmtoll CSR1   SBF       LL_PWR_IsActiveFlag_SB
 837   * @retval State of bit (1 or 0).
 838   */
 839 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
 840 {
 841   return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF));
 842 }
 843
 844 /**
 845   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
 846   * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
 847   * @retval State of bit (1 or 0).
 848   */
 849 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
 850 {
 851   return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO));
 852 }
 853
 854 /**
 855   * @brief  Get Backup Regulator ready Flag
 856   * @rmtoll CSR1   BRR       LL_PWR_IsActiveFlag_BRR
 857   * @retval State of bit (1 or 0).
 858   */
 859 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
 860 {
 861   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR));
 862 }
 863
 864 /**
 865   * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
 866   * @rmtoll CSR1   VOSRDY       LL_PWR_IsActiveFlag_VOS
 867   * @retval State of bit (1 or 0).
 868   */
 869 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
 870 {
 871   return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY));
 872 }
 873
 874 /**
 875   * @brief  Indicate whether the Over-Drive mode is ready or not
 876   * @rmtoll CSR1   ODRDY       LL_PWR_IsActiveFlag_OD
 877   * @retval State of bit (1 or 0).
 878   */
 879 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
 880 {
 881   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY));
 882 }
 883
 884 /**
 885   * @brief  Indicate whether the Over-Drive mode switching is ready or not
 886   * @rmtoll CSR1   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
 887   * @retval State of bit (1 or 0).
 888   */
 889 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
 890 {
 891   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY));
 892 }
 893
 894 /**
 895   * @brief  Indicate whether the Under-Drive mode is ready or not
 896   * @rmtoll CSR1   UDRDY       LL_PWR_IsActiveFlag_UD
 897   * @retval State of bit (1 or 0).
 898   */
 899 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
 900 {
 901   return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY));
 902 }
 903
 904 /**
 905   * @brief  Clear Standby Flag
 906   * @rmtoll CR1   CSBF       LL_PWR_ClearFlag_SB
 907   * @retval None
 908   */
 909 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
 910 {
 911   SET_BIT(PWR->CR1, PWR_CR1_CSBF);
 912 }
 913
 914 /**
 915   * @brief  Clear Wake-up Flag 6
 916   * @rmtoll CR2          CWUF6         LL_PWR_ClearFlag_WU6
 917   * @retval None
 918   */
 919 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
 920 {
 921   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6);
 922 }
 923
 924 /**
 925   * @brief  Clear Wake-up Flag 5
 926   * @rmtoll CR2          CWUF5         LL_PWR_ClearFlag_WU5
 927   * @retval None
 928   */
 929 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
 930 {
 931   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5);
 932 }
 933
 934 /**
 935   * @brief  Clear Wake-up Flag 4
 936   * @rmtoll CR2          CWUF4         LL_PWR_ClearFlag_WU4
 937   * @retval None
 938   */
 939 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
 940 {
 941   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4);
 942 }
 943
 944 /**
 945   * @brief  Clear Wake-up Flag 3
 946   * @rmtoll CR2          CWUF3         LL_PWR_ClearFlag_WU3
 947   * @retval None
 948   */
 949 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
 950 {
 951   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3);
 952 }
 953
 954 /**
 955   * @brief  Clear Wake-up Flag 2
 956   * @rmtoll CR2          CWUF2         LL_PWR_ClearFlag_WU2
 957   * @retval None
 958   */
 959 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
 960 {
 961   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2);
 962 }
 963
 964 /**
 965   * @brief  Clear Wake-up Flag 1
 966   * @rmtoll CR2          CWUF1         LL_PWR_ClearFlag_WU1
 967   * @retval None
 968   */
 969 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
 970 {
 971   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1);
 972 }
 973
 974 /**
 975   * @brief  Clear Under-Drive ready Flag
 976   * @rmtoll CSR1          UDRDY         LL_PWR_ClearFlag_UD
 977   * @retval None
 978   */
 979 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
 980 {
 981   WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY);
 982 }
 983
 984 #if defined(USE_FULL_LL_DRIVER)
 985 /** @defgroup PWR_LL_EF_Init De-initialization function
 986   * @{
 987   */
 988 ErrorStatus LL_PWR_DeInit(void);
 989 /**
 990   * @}
 991   */
 992 #endif /* USE_FULL_LL_DRIVER */
 993
 994 /**
 995   * @}
 996   */
 997
 998 /**
 999   * @}
1000   */
1001
1002 /**
1003   * @}
1004   */
1005
1006 #endif /* defined(PWR) */
1007
1008 /**
1009   * @}
1010   */
1011
1012 #ifdef __cplusplus
1013 }
1014 #endif
1015
1016 #endif /* __STM32F7xx_LL_PWR_H */
1017
1018 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/