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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_rcc.h
blob5e4cc29030638119886af9554b2609ef7bfd0a51
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_RCC_H
22 #define __STM32F7xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx.h"
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
44 * @{
45 */
46
47 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
48 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
49 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
50
51 /**
52 * @}
53 */
54 /* Private constants ---------------------------------------------------------*/
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
58 * @{
59 */
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
67 * @{
68 */
69
70 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
71 * @{
72 */
73
74 /**
75 * @brief RCC Clocks Frequency Structure
76 */
77 typedef struct
78 {
79 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
80 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
81 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
82 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
83 } LL_RCC_ClocksTypeDef;
84
85 /**
86 * @}
87 */
88
89 /**
90 * @}
91 */
92 #endif /* USE_FULL_LL_DRIVER */
93
94 /* Exported constants --------------------------------------------------------*/
95 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
96 * @{
97 */
98
99 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
100 * @brief Defines used to adapt values of different oscillators
101 * @note These values could be modified in the user environment according to
102 * HW set-up.
103 * @{
104 */
105 #if !defined (HSE_VALUE)
106 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
107 #endif /* HSE_VALUE */
108
109 #if !defined (HSI_VALUE)
110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
111 #endif /* HSI_VALUE */
112
113 #if !defined (LSE_VALUE)
114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
115 #endif /* LSE_VALUE */
116
117 #if !defined (LSI_VALUE)
118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
119 #endif /* LSI_VALUE */
120
121 #if !defined (EXTERNAL_CLOCK_VALUE)
122 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
123 #endif /* EXTERNAL_CLOCK_VALUE */
124
125 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
126 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
127 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
128
129 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
130 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
131 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
132 /**
133 * @}
134 */
135
136 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
137 * @brief Flags defines which can be used with LL_RCC_WriteReg function
138 * @{
139 */
140 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
141 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
142 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
143 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
144 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
145 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
146 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
147 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
148 /**
149 * @}
150 */
151
152 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
153 * @brief Flags defines which can be used with LL_RCC_ReadReg function
154 * @{
155 */
156 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
157 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
158 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
159 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
160 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
161 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
162 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
163 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
164 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
165 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
166 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
167 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
168 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
169 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
170 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
171 /**
172 * @}
173 */
174
175 /** @defgroup RCC_LL_EC_IT IT Defines
176 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
177 * @{
178 */
179 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
180 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
181 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
182 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
183 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
184 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
185 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
186 /**
187 * @}
188 */
189
190 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
191 * @{
192 */
193 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
194 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
195 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
196 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
197 /**
198 * @}
199 */
200
201 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
202 * @{
203 */
204 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
205 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
206 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
207 /**
208 * @}
209 */
210
211 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
212 * @{
213 */
214 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
215 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
216 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
217 /**
218 * @}
219 */
220
221 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
222 * @{
223 */
224 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
225 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
226 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
227 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
228 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
229 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
230 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
231 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
232 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
233 /**
234 * @}
235 */
236
237 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
238 * @{
239 */
240 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
241 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
242 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
243 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
244 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
245 /**
246 * @}
247 */
248 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
249 * @{
250 */
251 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
252 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
253 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
254 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
255 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
261 * @{
262 */
263 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
264 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
265 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
266 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
267 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
268 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
269 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
270 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
271 /**
272 * @}
273 */
274
275 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
276 * @{
277 */
278 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
279 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
280 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
281 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
282 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
283 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
284 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
285 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
286 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
287 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
288 /**
289 * @}
290 */
291
292 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
293 * @{
294 */
295 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
296 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
297 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
298 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
299 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
300 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
301 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
302 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
303 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
304 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
305 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
306 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
307 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
308 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
309 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
310 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
311 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
312 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
313 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
314 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
315 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
316 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
317 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
318 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
319 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
320 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
321 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
322 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
323 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
324 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
325 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
326 /**
327 * @}
328 */
329
330 #if defined(USE_FULL_LL_DRIVER)
331 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
332 * @{
333 */
334 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
335 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
336 /**
337 * @}
338 */
339 #endif /* USE_FULL_LL_DRIVER */
340
341 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
342 * @{
343 */
344 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
345 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
346 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
347 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */
348 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
349 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
350 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
351 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */
352 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
353 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
354 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
355 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */
356 #define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */
357 #define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */
358 #define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */
359 #define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */
360 /**
361 * @}
362 */
363
364 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
365 * @{
366 */
367 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
368 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
369 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
370 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */
371 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
372 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
373 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
374 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */
375 #define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */
376 #define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */
377 #define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */
378 #define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */
379 #define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */
380 #define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */
381 #define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */
382 #define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */
383 /**
384 * @}
385 */
386
387 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
388 * @{
389 */
390 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
391 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */
392 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */
393 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
394 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */
395 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */
396 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */
397 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */
398 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */
399 #if defined(I2C4)
400 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */
401 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */
402 #define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */
403 #endif /* I2C4 */
404 /**
405 * @}
406 */
407
408 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
409 * @{
410 */
411 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
412 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
413 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
414 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
415 /**
416 * @}
417 */
418
419 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
420 * @{
421 */
422 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
423 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */
424 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */
425 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
426 #define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */
427 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
428 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
429 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */
430 #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */
431 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
432 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */
433 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
434 /**
435 * @}
436 */
437
438 /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
439 * @{
440 */
441 #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */
442 #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */
443 #if defined(SDMMC2)
444 #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */
445 #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */
446 #endif /* SDMMC2 */
447 /**
448 * @}
449 */
450
451 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
452 * @{
453 */
454 #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */
455 #define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */
456 /**
457 * @}
458 */
459
460 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
461 * @{
462 */
463 #define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */
464 #define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */
465 /**
466 * @}
467 */
468
469 #if defined(DSI)
470 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
471 * @{
472 */
473 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
474 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
475 /**
476 * @}
477 */
478 #endif /* DSI */
479
480 #if defined(CEC)
481 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
482 * @{
483 */
484 #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */
485 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */
486 /**
487 * @}
488 */
489 #endif /* CEC */
490
491 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
492 * @{
493 */
494 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
495 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
496 /**
497 * @}
498 */
499
500 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
501 * @{
502 */
503 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
504 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
505 /**
506 * @}
507 */
508
509 #if defined(DFSDM1_Channel0)
510 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
511 * @{
512 */
513 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
514 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */
515 /**
516 * @}
517 */
518
519 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
520 * @{
521 */
522 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
523 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */
524 /**
525 * @}
526 */
527 #endif /* DFSDM1_Channel0 */
528
529 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
530 * @{
531 */
532 #define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */
533 #define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */
534 #define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */
535 #define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */
536 /**
537 * @}
538 */
539
540 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
541 * @{
542 */
543 #define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */
544 #define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */
545 #define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */
546 #define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */
547 /**
548 * @}
549 */
550
551 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
552 * @{
553 */
554 #define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */
555 #define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */
556 #define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */
557 #if defined(I2C4)
558 #define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */
559 #endif /* I2C4 */
560 /**
561 * @}
562 */
563
564 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
565 * @{
566 */
567 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
568 /**
569 * @}
570 */
571
572 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
573 * @{
574 */
575 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
576 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
577 /**
578 * @}
579 */
580
581 /** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source
582 * @{
583 */
584 #define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */
585 #if defined(SDMMC2)
586 #define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */
587 #endif /* SDMMC2 */
588 /**
589 * @}
590 */
591
592 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
593 * @{
594 */
595 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
596 /**
597 * @}
598 */
599
600 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
601 * @{
602 */
603 #define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
604 /**
605 * @}
606 */
607
608 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
609 * @{
610 */
611 #define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
612 /**
613 * @}
614 */
615
616 #if defined(CEC)
617 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
618 * @{
619 */
620 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
621 /**
622 * @}
623 */
624 #endif /* CEC */
625
626 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
627 * @{
628 */
629 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
630 /**
631 * @}
632 */
633 #if defined(DFSDM1_Channel0)
634 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
635 * @{
636 */
637 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */
638 /**
639 * @}
640 */
641
642 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
643 * @{
644 */
645 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */
646 /**
647 * @}
648 */
649 #endif /* DFSDM1_Channel0 */
650
651 #if defined(DSI)
652 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
653 * @{
654 */
655 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
656 /**
657 * @}
658 */
659 #endif /* DSI */
660
661 #if defined(LTDC)
662 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
663 * @{
664 */
665 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */
666 /**
667 * @}
668 */
669 #endif /* LTDC */
670
671 #if defined(SPDIFRX)
672 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
673 * @{
674 */
675 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */
676 /**
677 * @}
678 */
679 #endif /* SPDIFRX */
680
681 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
682 * @{
683 */
684 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
685 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
686 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
687 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
688 /**
689 * @}
690 */
691
692 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
693 * @{
694 */
695 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
696 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */
697 /**
698 * @}
699 */
700
701 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
702 * @{
703 */
704 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
705 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
706 /**
707 * @}
708 */
709
710 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
711 * @{
712 */
713 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
714 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
715 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
716 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
717 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
718 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
719 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
720 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
721 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
722 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
723 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
724 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
725 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
726 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
727 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
728 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
729 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
730 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
731 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
732 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
733 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
734 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
735 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
736 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
737 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
738 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
739 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
740 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
741 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
742 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
743 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
744 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
745 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
746 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
747 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
748 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
749 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
750 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
751 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
752 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
753 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
754 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
755 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
756 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
757 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
758 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
759 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
760 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
761 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
762 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
763 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
764 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
765 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
766 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
767 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
768 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
769 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
770 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
771 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
772 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
773 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
774 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
775 /**
776 * @}
777 */
778
779 #if defined(RCC_PLLCFGR_PLLR)
780 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
781 * @{
782 */
783 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
784 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
785 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
786 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
787 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
788 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
789 /**
790 * @}
791 */
792 #endif /* RCC_PLLCFGR_PLLR */
793
794 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
795 * @{
796 */
797 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
798 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
799 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
800 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
801 /**
802 * @}
803 */
804
805 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
806 * @{
807 */
808 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
809 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
810 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
811 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
812 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
813 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
814 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
815 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
816 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
817 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
818 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
819 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
820 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
821 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
822 /**
823 * @}
824 */
825
826 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
827 * @{
828 */
829 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
830 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
831 /**
832 * @}
833 */
834
835 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
836 * @{
837 */
838 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
839 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
840 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
841 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
842 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
843 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
844 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
845 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
846 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
847 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
848 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
849 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
850 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
851 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
852 /**
853 * @}
854 */
855
856 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
857 * @{
858 */
859 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
860 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
861 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
862 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
863 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
864 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
865 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
866 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
867 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
868 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
869 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
870 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
871 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
872 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
873 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
874 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
875 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
876 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
877 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
878 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
879 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
880 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
881 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
882 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
883 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
884 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
885 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
886 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
887 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
888 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
889 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
890 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
891 /**
892 * @}
893 */
894
895 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
896 * @{
897 */
898 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
899 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
900 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
901 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
902 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
903 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
904 /**
905 * @}
906 */
907
908 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
909 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
910 * @{
911 */
912 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
913 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
914 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
915 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
916 /**
917 * @}
918 */
919 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
920
921 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
922 * @{
923 */
924 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
925 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
926 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
927 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
928 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
929 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
930 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
931 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
932 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
933 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
934 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
935 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
936 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
937 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
938 /**
939 * @}
940 */
941
942 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
943 * @{
944 */
945 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
946 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
947 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
948 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
949 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
950 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
951 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
952 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
953 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
954 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
955 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
956 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
957 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
958 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
959 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
960 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
961 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
962 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
963 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
964 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
965 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
966 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
967 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
968 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
969 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
970 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
971 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
972 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
973 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
974 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
975 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
976 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
977 /**
978 * @}
979 */
980
981 #if defined(RCC_PLLSAICFGR_PLLSAIR)
982 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
983 * @{
984 */
985 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
986 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
987 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
988 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
989 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
990 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
991 /**
992 * @}
993 */
994 #endif /* RCC_PLLSAICFGR_PLLSAIR */
995
996 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
997 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
998 * @{
999 */
1000 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1001 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1002 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1003 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1004 /**
1005 * @}
1006 */
1007 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
1008
1009 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1010 * @{
1011 */
1012 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1013 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1014 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1015 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1016 /**
1017 * @}
1018 */
1019
1020 /**
1021 * @}
1022 */
1023
1024 /* Exported macro ------------------------------------------------------------*/
1025 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1026 * @{
1027 */
1028
1029 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1030 * @{
1031 */
1032
1033 /**
1034 * @brief Write a value in RCC register
1035 * @param __REG__ Register to be written
1036 * @param __VALUE__ Value to be written in the register
1037 * @retval None
1038 */
1039 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1040
1041 /**
1042 * @brief Read a value in RCC register
1043 * @param __REG__ Register to be read
1044 * @retval Register value
1045 */
1046 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1047 /**
1048 * @}
1049 */
1050
1051 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1052 * @{
1053 */
1054
1055 /**
1056 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1057 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1058 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1059 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1060 * @param __PLLM__ This parameter can be one of the following values:
1061 * @arg @ref LL_RCC_PLLM_DIV_2
1062 * @arg @ref LL_RCC_PLLM_DIV_3
1063 * @arg @ref LL_RCC_PLLM_DIV_4
1064 * @arg @ref LL_RCC_PLLM_DIV_5
1065 * @arg @ref LL_RCC_PLLM_DIV_6
1066 * @arg @ref LL_RCC_PLLM_DIV_7
1067 * @arg @ref LL_RCC_PLLM_DIV_8
1068 * @arg @ref LL_RCC_PLLM_DIV_9
1069 * @arg @ref LL_RCC_PLLM_DIV_10
1070 * @arg @ref LL_RCC_PLLM_DIV_11
1071 * @arg @ref LL_RCC_PLLM_DIV_12
1072 * @arg @ref LL_RCC_PLLM_DIV_13
1073 * @arg @ref LL_RCC_PLLM_DIV_14
1074 * @arg @ref LL_RCC_PLLM_DIV_15
1075 * @arg @ref LL_RCC_PLLM_DIV_16
1076 * @arg @ref LL_RCC_PLLM_DIV_17
1077 * @arg @ref LL_RCC_PLLM_DIV_18
1078 * @arg @ref LL_RCC_PLLM_DIV_19
1079 * @arg @ref LL_RCC_PLLM_DIV_20
1080 * @arg @ref LL_RCC_PLLM_DIV_21
1081 * @arg @ref LL_RCC_PLLM_DIV_22
1082 * @arg @ref LL_RCC_PLLM_DIV_23
1083 * @arg @ref LL_RCC_PLLM_DIV_24
1084 * @arg @ref LL_RCC_PLLM_DIV_25
1085 * @arg @ref LL_RCC_PLLM_DIV_26
1086 * @arg @ref LL_RCC_PLLM_DIV_27
1087 * @arg @ref LL_RCC_PLLM_DIV_28
1088 * @arg @ref LL_RCC_PLLM_DIV_29
1089 * @arg @ref LL_RCC_PLLM_DIV_30
1090 * @arg @ref LL_RCC_PLLM_DIV_31
1091 * @arg @ref LL_RCC_PLLM_DIV_32
1092 * @arg @ref LL_RCC_PLLM_DIV_33
1093 * @arg @ref LL_RCC_PLLM_DIV_34
1094 * @arg @ref LL_RCC_PLLM_DIV_35
1095 * @arg @ref LL_RCC_PLLM_DIV_36
1096 * @arg @ref LL_RCC_PLLM_DIV_37
1097 * @arg @ref LL_RCC_PLLM_DIV_38
1098 * @arg @ref LL_RCC_PLLM_DIV_39
1099 * @arg @ref LL_RCC_PLLM_DIV_40
1100 * @arg @ref LL_RCC_PLLM_DIV_41
1101 * @arg @ref LL_RCC_PLLM_DIV_42
1102 * @arg @ref LL_RCC_PLLM_DIV_43
1103 * @arg @ref LL_RCC_PLLM_DIV_44
1104 * @arg @ref LL_RCC_PLLM_DIV_45
1105 * @arg @ref LL_RCC_PLLM_DIV_46
1106 * @arg @ref LL_RCC_PLLM_DIV_47
1107 * @arg @ref LL_RCC_PLLM_DIV_48
1108 * @arg @ref LL_RCC_PLLM_DIV_49
1109 * @arg @ref LL_RCC_PLLM_DIV_50
1110 * @arg @ref LL_RCC_PLLM_DIV_51
1111 * @arg @ref LL_RCC_PLLM_DIV_52
1112 * @arg @ref LL_RCC_PLLM_DIV_53
1113 * @arg @ref LL_RCC_PLLM_DIV_54
1114 * @arg @ref LL_RCC_PLLM_DIV_55
1115 * @arg @ref LL_RCC_PLLM_DIV_56
1116 * @arg @ref LL_RCC_PLLM_DIV_57
1117 * @arg @ref LL_RCC_PLLM_DIV_58
1118 * @arg @ref LL_RCC_PLLM_DIV_59
1119 * @arg @ref LL_RCC_PLLM_DIV_60
1120 * @arg @ref LL_RCC_PLLM_DIV_61
1121 * @arg @ref LL_RCC_PLLM_DIV_62
1122 * @arg @ref LL_RCC_PLLM_DIV_63
1123 * @param __PLLN__ Between 50 and 432
1124 * @param __PLLP__ This parameter can be one of the following values:
1125 * @arg @ref LL_RCC_PLLP_DIV_2
1126 * @arg @ref LL_RCC_PLLP_DIV_4
1127 * @arg @ref LL_RCC_PLLP_DIV_6
1128 * @arg @ref LL_RCC_PLLP_DIV_8
1129 * @retval PLL clock frequency (in Hz)
1130 */
1131 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1132 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1133
1134 /**
1135 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1136 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1137 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1138 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1139 * @param __PLLM__ This parameter can be one of the following values:
1140 * @arg @ref LL_RCC_PLLM_DIV_2
1141 * @arg @ref LL_RCC_PLLM_DIV_3
1142 * @arg @ref LL_RCC_PLLM_DIV_4
1143 * @arg @ref LL_RCC_PLLM_DIV_5
1144 * @arg @ref LL_RCC_PLLM_DIV_6
1145 * @arg @ref LL_RCC_PLLM_DIV_7
1146 * @arg @ref LL_RCC_PLLM_DIV_8
1147 * @arg @ref LL_RCC_PLLM_DIV_9
1148 * @arg @ref LL_RCC_PLLM_DIV_10
1149 * @arg @ref LL_RCC_PLLM_DIV_11
1150 * @arg @ref LL_RCC_PLLM_DIV_12
1151 * @arg @ref LL_RCC_PLLM_DIV_13
1152 * @arg @ref LL_RCC_PLLM_DIV_14
1153 * @arg @ref LL_RCC_PLLM_DIV_15
1154 * @arg @ref LL_RCC_PLLM_DIV_16
1155 * @arg @ref LL_RCC_PLLM_DIV_17
1156 * @arg @ref LL_RCC_PLLM_DIV_18
1157 * @arg @ref LL_RCC_PLLM_DIV_19
1158 * @arg @ref LL_RCC_PLLM_DIV_20
1159 * @arg @ref LL_RCC_PLLM_DIV_21
1160 * @arg @ref LL_RCC_PLLM_DIV_22
1161 * @arg @ref LL_RCC_PLLM_DIV_23
1162 * @arg @ref LL_RCC_PLLM_DIV_24
1163 * @arg @ref LL_RCC_PLLM_DIV_25
1164 * @arg @ref LL_RCC_PLLM_DIV_26
1165 * @arg @ref LL_RCC_PLLM_DIV_27
1166 * @arg @ref LL_RCC_PLLM_DIV_28
1167 * @arg @ref LL_RCC_PLLM_DIV_29
1168 * @arg @ref LL_RCC_PLLM_DIV_30
1169 * @arg @ref LL_RCC_PLLM_DIV_31
1170 * @arg @ref LL_RCC_PLLM_DIV_32
1171 * @arg @ref LL_RCC_PLLM_DIV_33
1172 * @arg @ref LL_RCC_PLLM_DIV_34
1173 * @arg @ref LL_RCC_PLLM_DIV_35
1174 * @arg @ref LL_RCC_PLLM_DIV_36
1175 * @arg @ref LL_RCC_PLLM_DIV_37
1176 * @arg @ref LL_RCC_PLLM_DIV_38
1177 * @arg @ref LL_RCC_PLLM_DIV_39
1178 * @arg @ref LL_RCC_PLLM_DIV_40
1179 * @arg @ref LL_RCC_PLLM_DIV_41
1180 * @arg @ref LL_RCC_PLLM_DIV_42
1181 * @arg @ref LL_RCC_PLLM_DIV_43
1182 * @arg @ref LL_RCC_PLLM_DIV_44
1183 * @arg @ref LL_RCC_PLLM_DIV_45
1184 * @arg @ref LL_RCC_PLLM_DIV_46
1185 * @arg @ref LL_RCC_PLLM_DIV_47
1186 * @arg @ref LL_RCC_PLLM_DIV_48
1187 * @arg @ref LL_RCC_PLLM_DIV_49
1188 * @arg @ref LL_RCC_PLLM_DIV_50
1189 * @arg @ref LL_RCC_PLLM_DIV_51
1190 * @arg @ref LL_RCC_PLLM_DIV_52
1191 * @arg @ref LL_RCC_PLLM_DIV_53
1192 * @arg @ref LL_RCC_PLLM_DIV_54
1193 * @arg @ref LL_RCC_PLLM_DIV_55
1194 * @arg @ref LL_RCC_PLLM_DIV_56
1195 * @arg @ref LL_RCC_PLLM_DIV_57
1196 * @arg @ref LL_RCC_PLLM_DIV_58
1197 * @arg @ref LL_RCC_PLLM_DIV_59
1198 * @arg @ref LL_RCC_PLLM_DIV_60
1199 * @arg @ref LL_RCC_PLLM_DIV_61
1200 * @arg @ref LL_RCC_PLLM_DIV_62
1201 * @arg @ref LL_RCC_PLLM_DIV_63
1202 * @param __PLLN__ Between 50 and 432
1203 * @param __PLLQ__ This parameter can be one of the following values:
1204 * @arg @ref LL_RCC_PLLQ_DIV_2
1205 * @arg @ref LL_RCC_PLLQ_DIV_3
1206 * @arg @ref LL_RCC_PLLQ_DIV_4
1207 * @arg @ref LL_RCC_PLLQ_DIV_5
1208 * @arg @ref LL_RCC_PLLQ_DIV_6
1209 * @arg @ref LL_RCC_PLLQ_DIV_7
1210 * @arg @ref LL_RCC_PLLQ_DIV_8
1211 * @arg @ref LL_RCC_PLLQ_DIV_9
1212 * @arg @ref LL_RCC_PLLQ_DIV_10
1213 * @arg @ref LL_RCC_PLLQ_DIV_11
1214 * @arg @ref LL_RCC_PLLQ_DIV_12
1215 * @arg @ref LL_RCC_PLLQ_DIV_13
1216 * @arg @ref LL_RCC_PLLQ_DIV_14
1217 * @arg @ref LL_RCC_PLLQ_DIV_15
1218 * @retval PLL clock frequency (in Hz)
1219 */
1220 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1221 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1222
1223 #if defined(DSI)
1224 /**
1225 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1226 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1227 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1228 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1229 * @param __PLLM__ This parameter can be one of the following values:
1230 * @arg @ref LL_RCC_PLLM_DIV_2
1231 * @arg @ref LL_RCC_PLLM_DIV_3
1232 * @arg @ref LL_RCC_PLLM_DIV_4
1233 * @arg @ref LL_RCC_PLLM_DIV_5
1234 * @arg @ref LL_RCC_PLLM_DIV_6
1235 * @arg @ref LL_RCC_PLLM_DIV_7
1236 * @arg @ref LL_RCC_PLLM_DIV_8
1237 * @arg @ref LL_RCC_PLLM_DIV_9
1238 * @arg @ref LL_RCC_PLLM_DIV_10
1239 * @arg @ref LL_RCC_PLLM_DIV_11
1240 * @arg @ref LL_RCC_PLLM_DIV_12
1241 * @arg @ref LL_RCC_PLLM_DIV_13
1242 * @arg @ref LL_RCC_PLLM_DIV_14
1243 * @arg @ref LL_RCC_PLLM_DIV_15
1244 * @arg @ref LL_RCC_PLLM_DIV_16
1245 * @arg @ref LL_RCC_PLLM_DIV_17
1246 * @arg @ref LL_RCC_PLLM_DIV_18
1247 * @arg @ref LL_RCC_PLLM_DIV_19
1248 * @arg @ref LL_RCC_PLLM_DIV_20
1249 * @arg @ref LL_RCC_PLLM_DIV_21
1250 * @arg @ref LL_RCC_PLLM_DIV_22
1251 * @arg @ref LL_RCC_PLLM_DIV_23
1252 * @arg @ref LL_RCC_PLLM_DIV_24
1253 * @arg @ref LL_RCC_PLLM_DIV_25
1254 * @arg @ref LL_RCC_PLLM_DIV_26
1255 * @arg @ref LL_RCC_PLLM_DIV_27
1256 * @arg @ref LL_RCC_PLLM_DIV_28
1257 * @arg @ref LL_RCC_PLLM_DIV_29
1258 * @arg @ref LL_RCC_PLLM_DIV_30
1259 * @arg @ref LL_RCC_PLLM_DIV_31
1260 * @arg @ref LL_RCC_PLLM_DIV_32
1261 * @arg @ref LL_RCC_PLLM_DIV_33
1262 * @arg @ref LL_RCC_PLLM_DIV_34
1263 * @arg @ref LL_RCC_PLLM_DIV_35
1264 * @arg @ref LL_RCC_PLLM_DIV_36
1265 * @arg @ref LL_RCC_PLLM_DIV_37
1266 * @arg @ref LL_RCC_PLLM_DIV_38
1267 * @arg @ref LL_RCC_PLLM_DIV_39
1268 * @arg @ref LL_RCC_PLLM_DIV_40
1269 * @arg @ref LL_RCC_PLLM_DIV_41
1270 * @arg @ref LL_RCC_PLLM_DIV_42
1271 * @arg @ref LL_RCC_PLLM_DIV_43
1272 * @arg @ref LL_RCC_PLLM_DIV_44
1273 * @arg @ref LL_RCC_PLLM_DIV_45
1274 * @arg @ref LL_RCC_PLLM_DIV_46
1275 * @arg @ref LL_RCC_PLLM_DIV_47
1276 * @arg @ref LL_RCC_PLLM_DIV_48
1277 * @arg @ref LL_RCC_PLLM_DIV_49
1278 * @arg @ref LL_RCC_PLLM_DIV_50
1279 * @arg @ref LL_RCC_PLLM_DIV_51
1280 * @arg @ref LL_RCC_PLLM_DIV_52
1281 * @arg @ref LL_RCC_PLLM_DIV_53
1282 * @arg @ref LL_RCC_PLLM_DIV_54
1283 * @arg @ref LL_RCC_PLLM_DIV_55
1284 * @arg @ref LL_RCC_PLLM_DIV_56
1285 * @arg @ref LL_RCC_PLLM_DIV_57
1286 * @arg @ref LL_RCC_PLLM_DIV_58
1287 * @arg @ref LL_RCC_PLLM_DIV_59
1288 * @arg @ref LL_RCC_PLLM_DIV_60
1289 * @arg @ref LL_RCC_PLLM_DIV_61
1290 * @arg @ref LL_RCC_PLLM_DIV_62
1291 * @arg @ref LL_RCC_PLLM_DIV_63
1292 * @param __PLLN__ Between 50 and 432
1293 * @param __PLLR__ This parameter can be one of the following values:
1294 * @arg @ref LL_RCC_PLLR_DIV_2
1295 * @arg @ref LL_RCC_PLLR_DIV_3
1296 * @arg @ref LL_RCC_PLLR_DIV_4
1297 * @arg @ref LL_RCC_PLLR_DIV_5
1298 * @arg @ref LL_RCC_PLLR_DIV_6
1299 * @arg @ref LL_RCC_PLLR_DIV_7
1300 * @retval PLL clock frequency (in Hz)
1301 */
1302 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1303 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1304 #endif /* DSI */
1305
1306 /**
1307 * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
1308 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1309 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
1310 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1311 * @param __PLLM__ This parameter can be one of the following values:
1312 * @arg @ref LL_RCC_PLLM_DIV_2
1313 * @arg @ref LL_RCC_PLLM_DIV_3
1314 * @arg @ref LL_RCC_PLLM_DIV_4
1315 * @arg @ref LL_RCC_PLLM_DIV_5
1316 * @arg @ref LL_RCC_PLLM_DIV_6
1317 * @arg @ref LL_RCC_PLLM_DIV_7
1318 * @arg @ref LL_RCC_PLLM_DIV_8
1319 * @arg @ref LL_RCC_PLLM_DIV_9
1320 * @arg @ref LL_RCC_PLLM_DIV_10
1321 * @arg @ref LL_RCC_PLLM_DIV_11
1322 * @arg @ref LL_RCC_PLLM_DIV_12
1323 * @arg @ref LL_RCC_PLLM_DIV_13
1324 * @arg @ref LL_RCC_PLLM_DIV_14
1325 * @arg @ref LL_RCC_PLLM_DIV_15
1326 * @arg @ref LL_RCC_PLLM_DIV_16
1327 * @arg @ref LL_RCC_PLLM_DIV_17
1328 * @arg @ref LL_RCC_PLLM_DIV_18
1329 * @arg @ref LL_RCC_PLLM_DIV_19
1330 * @arg @ref LL_RCC_PLLM_DIV_20
1331 * @arg @ref LL_RCC_PLLM_DIV_21
1332 * @arg @ref LL_RCC_PLLM_DIV_22
1333 * @arg @ref LL_RCC_PLLM_DIV_23
1334 * @arg @ref LL_RCC_PLLM_DIV_24
1335 * @arg @ref LL_RCC_PLLM_DIV_25
1336 * @arg @ref LL_RCC_PLLM_DIV_26
1337 * @arg @ref LL_RCC_PLLM_DIV_27
1338 * @arg @ref LL_RCC_PLLM_DIV_28
1339 * @arg @ref LL_RCC_PLLM_DIV_29
1340 * @arg @ref LL_RCC_PLLM_DIV_30
1341 * @arg @ref LL_RCC_PLLM_DIV_31
1342 * @arg @ref LL_RCC_PLLM_DIV_32
1343 * @arg @ref LL_RCC_PLLM_DIV_33
1344 * @arg @ref LL_RCC_PLLM_DIV_34
1345 * @arg @ref LL_RCC_PLLM_DIV_35
1346 * @arg @ref LL_RCC_PLLM_DIV_36
1347 * @arg @ref LL_RCC_PLLM_DIV_37
1348 * @arg @ref LL_RCC_PLLM_DIV_38
1349 * @arg @ref LL_RCC_PLLM_DIV_39
1350 * @arg @ref LL_RCC_PLLM_DIV_40
1351 * @arg @ref LL_RCC_PLLM_DIV_41
1352 * @arg @ref LL_RCC_PLLM_DIV_42
1353 * @arg @ref LL_RCC_PLLM_DIV_43
1354 * @arg @ref LL_RCC_PLLM_DIV_44
1355 * @arg @ref LL_RCC_PLLM_DIV_45
1356 * @arg @ref LL_RCC_PLLM_DIV_46
1357 * @arg @ref LL_RCC_PLLM_DIV_47
1358 * @arg @ref LL_RCC_PLLM_DIV_48
1359 * @arg @ref LL_RCC_PLLM_DIV_49
1360 * @arg @ref LL_RCC_PLLM_DIV_50
1361 * @arg @ref LL_RCC_PLLM_DIV_51
1362 * @arg @ref LL_RCC_PLLM_DIV_52
1363 * @arg @ref LL_RCC_PLLM_DIV_53
1364 * @arg @ref LL_RCC_PLLM_DIV_54
1365 * @arg @ref LL_RCC_PLLM_DIV_55
1366 * @arg @ref LL_RCC_PLLM_DIV_56
1367 * @arg @ref LL_RCC_PLLM_DIV_57
1368 * @arg @ref LL_RCC_PLLM_DIV_58
1369 * @arg @ref LL_RCC_PLLM_DIV_59
1370 * @arg @ref LL_RCC_PLLM_DIV_60
1371 * @arg @ref LL_RCC_PLLM_DIV_61
1372 * @arg @ref LL_RCC_PLLM_DIV_62
1373 * @arg @ref LL_RCC_PLLM_DIV_63
1374 * @param __PLLSAIN__ Between 50 and 432
1375 * @param __PLLSAIQ__ This parameter can be one of the following values:
1376 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
1377 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
1378 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
1379 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
1380 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
1381 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
1382 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
1383 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
1384 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
1385 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
1386 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
1387 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
1388 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
1389 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
1390 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
1391 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
1392 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
1393 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
1394 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
1395 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
1396 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
1397 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
1398 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
1399 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
1400 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
1401 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
1402 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
1403 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
1404 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
1405 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
1406 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
1407 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
1408 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
1409 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
1410 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
1411 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
1412 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
1413 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
1414 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
1415 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
1416 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
1417 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
1418 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
1419 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
1420 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
1421 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
1422 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
1423 * @retval PLLSAI clock frequency (in Hz)
1424 */
1425 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1426 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
1427
1428 /**
1429 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
1430 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1431 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
1432 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1433 * @param __PLLM__ This parameter can be one of the following values:
1434 * @arg @ref LL_RCC_PLLM_DIV_2
1435 * @arg @ref LL_RCC_PLLM_DIV_3
1436 * @arg @ref LL_RCC_PLLM_DIV_4
1437 * @arg @ref LL_RCC_PLLM_DIV_5
1438 * @arg @ref LL_RCC_PLLM_DIV_6
1439 * @arg @ref LL_RCC_PLLM_DIV_7
1440 * @arg @ref LL_RCC_PLLM_DIV_8
1441 * @arg @ref LL_RCC_PLLM_DIV_9
1442 * @arg @ref LL_RCC_PLLM_DIV_10
1443 * @arg @ref LL_RCC_PLLM_DIV_11
1444 * @arg @ref LL_RCC_PLLM_DIV_12
1445 * @arg @ref LL_RCC_PLLM_DIV_13
1446 * @arg @ref LL_RCC_PLLM_DIV_14
1447 * @arg @ref LL_RCC_PLLM_DIV_15
1448 * @arg @ref LL_RCC_PLLM_DIV_16
1449 * @arg @ref LL_RCC_PLLM_DIV_17
1450 * @arg @ref LL_RCC_PLLM_DIV_18
1451 * @arg @ref LL_RCC_PLLM_DIV_19
1452 * @arg @ref LL_RCC_PLLM_DIV_20
1453 * @arg @ref LL_RCC_PLLM_DIV_21
1454 * @arg @ref LL_RCC_PLLM_DIV_22
1455 * @arg @ref LL_RCC_PLLM_DIV_23
1456 * @arg @ref LL_RCC_PLLM_DIV_24
1457 * @arg @ref LL_RCC_PLLM_DIV_25
1458 * @arg @ref LL_RCC_PLLM_DIV_26
1459 * @arg @ref LL_RCC_PLLM_DIV_27
1460 * @arg @ref LL_RCC_PLLM_DIV_28
1461 * @arg @ref LL_RCC_PLLM_DIV_29
1462 * @arg @ref LL_RCC_PLLM_DIV_30
1463 * @arg @ref LL_RCC_PLLM_DIV_31
1464 * @arg @ref LL_RCC_PLLM_DIV_32
1465 * @arg @ref LL_RCC_PLLM_DIV_33
1466 * @arg @ref LL_RCC_PLLM_DIV_34
1467 * @arg @ref LL_RCC_PLLM_DIV_35
1468 * @arg @ref LL_RCC_PLLM_DIV_36
1469 * @arg @ref LL_RCC_PLLM_DIV_37
1470 * @arg @ref LL_RCC_PLLM_DIV_38
1471 * @arg @ref LL_RCC_PLLM_DIV_39
1472 * @arg @ref LL_RCC_PLLM_DIV_40
1473 * @arg @ref LL_RCC_PLLM_DIV_41
1474 * @arg @ref LL_RCC_PLLM_DIV_42
1475 * @arg @ref LL_RCC_PLLM_DIV_43
1476 * @arg @ref LL_RCC_PLLM_DIV_44
1477 * @arg @ref LL_RCC_PLLM_DIV_45
1478 * @arg @ref LL_RCC_PLLM_DIV_46
1479 * @arg @ref LL_RCC_PLLM_DIV_47
1480 * @arg @ref LL_RCC_PLLM_DIV_48
1481 * @arg @ref LL_RCC_PLLM_DIV_49
1482 * @arg @ref LL_RCC_PLLM_DIV_50
1483 * @arg @ref LL_RCC_PLLM_DIV_51
1484 * @arg @ref LL_RCC_PLLM_DIV_52
1485 * @arg @ref LL_RCC_PLLM_DIV_53
1486 * @arg @ref LL_RCC_PLLM_DIV_54
1487 * @arg @ref LL_RCC_PLLM_DIV_55
1488 * @arg @ref LL_RCC_PLLM_DIV_56
1489 * @arg @ref LL_RCC_PLLM_DIV_57
1490 * @arg @ref LL_RCC_PLLM_DIV_58
1491 * @arg @ref LL_RCC_PLLM_DIV_59
1492 * @arg @ref LL_RCC_PLLM_DIV_60
1493 * @arg @ref LL_RCC_PLLM_DIV_61
1494 * @arg @ref LL_RCC_PLLM_DIV_62
1495 * @arg @ref LL_RCC_PLLM_DIV_63
1496 * @param __PLLSAIN__ Between 50 and 432
1497 * @param __PLLSAIP__ This parameter can be one of the following values:
1498 * @arg @ref LL_RCC_PLLSAIP_DIV_2
1499 * @arg @ref LL_RCC_PLLSAIP_DIV_4
1500 * @arg @ref LL_RCC_PLLSAIP_DIV_6
1501 * @arg @ref LL_RCC_PLLSAIP_DIV_8
1502 * @retval PLLSAI clock frequency (in Hz)
1503 */
1504 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1505 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
1506
1507 #if defined(LTDC)
1508 /**
1509 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
1510 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1511 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
1512 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1513 * @param __PLLM__ This parameter can be one of the following values:
1514 * @arg @ref LL_RCC_PLLM_DIV_2
1515 * @arg @ref LL_RCC_PLLM_DIV_3
1516 * @arg @ref LL_RCC_PLLM_DIV_4
1517 * @arg @ref LL_RCC_PLLM_DIV_5
1518 * @arg @ref LL_RCC_PLLM_DIV_6
1519 * @arg @ref LL_RCC_PLLM_DIV_7
1520 * @arg @ref LL_RCC_PLLM_DIV_8
1521 * @arg @ref LL_RCC_PLLM_DIV_9
1522 * @arg @ref LL_RCC_PLLM_DIV_10
1523 * @arg @ref LL_RCC_PLLM_DIV_11
1524 * @arg @ref LL_RCC_PLLM_DIV_12
1525 * @arg @ref LL_RCC_PLLM_DIV_13
1526 * @arg @ref LL_RCC_PLLM_DIV_14
1527 * @arg @ref LL_RCC_PLLM_DIV_15
1528 * @arg @ref LL_RCC_PLLM_DIV_16
1529 * @arg @ref LL_RCC_PLLM_DIV_17
1530 * @arg @ref LL_RCC_PLLM_DIV_18
1531 * @arg @ref LL_RCC_PLLM_DIV_19
1532 * @arg @ref LL_RCC_PLLM_DIV_20
1533 * @arg @ref LL_RCC_PLLM_DIV_21
1534 * @arg @ref LL_RCC_PLLM_DIV_22
1535 * @arg @ref LL_RCC_PLLM_DIV_23
1536 * @arg @ref LL_RCC_PLLM_DIV_24
1537 * @arg @ref LL_RCC_PLLM_DIV_25
1538 * @arg @ref LL_RCC_PLLM_DIV_26
1539 * @arg @ref LL_RCC_PLLM_DIV_27
1540 * @arg @ref LL_RCC_PLLM_DIV_28
1541 * @arg @ref LL_RCC_PLLM_DIV_29
1542 * @arg @ref LL_RCC_PLLM_DIV_30
1543 * @arg @ref LL_RCC_PLLM_DIV_31
1544 * @arg @ref LL_RCC_PLLM_DIV_32
1545 * @arg @ref LL_RCC_PLLM_DIV_33
1546 * @arg @ref LL_RCC_PLLM_DIV_34
1547 * @arg @ref LL_RCC_PLLM_DIV_35
1548 * @arg @ref LL_RCC_PLLM_DIV_36
1549 * @arg @ref LL_RCC_PLLM_DIV_37
1550 * @arg @ref LL_RCC_PLLM_DIV_38
1551 * @arg @ref LL_RCC_PLLM_DIV_39
1552 * @arg @ref LL_RCC_PLLM_DIV_40
1553 * @arg @ref LL_RCC_PLLM_DIV_41
1554 * @arg @ref LL_RCC_PLLM_DIV_42
1555 * @arg @ref LL_RCC_PLLM_DIV_43
1556 * @arg @ref LL_RCC_PLLM_DIV_44
1557 * @arg @ref LL_RCC_PLLM_DIV_45
1558 * @arg @ref LL_RCC_PLLM_DIV_46
1559 * @arg @ref LL_RCC_PLLM_DIV_47
1560 * @arg @ref LL_RCC_PLLM_DIV_48
1561 * @arg @ref LL_RCC_PLLM_DIV_49
1562 * @arg @ref LL_RCC_PLLM_DIV_50
1563 * @arg @ref LL_RCC_PLLM_DIV_51
1564 * @arg @ref LL_RCC_PLLM_DIV_52
1565 * @arg @ref LL_RCC_PLLM_DIV_53
1566 * @arg @ref LL_RCC_PLLM_DIV_54
1567 * @arg @ref LL_RCC_PLLM_DIV_55
1568 * @arg @ref LL_RCC_PLLM_DIV_56
1569 * @arg @ref LL_RCC_PLLM_DIV_57
1570 * @arg @ref LL_RCC_PLLM_DIV_58
1571 * @arg @ref LL_RCC_PLLM_DIV_59
1572 * @arg @ref LL_RCC_PLLM_DIV_60
1573 * @arg @ref LL_RCC_PLLM_DIV_61
1574 * @arg @ref LL_RCC_PLLM_DIV_62
1575 * @arg @ref LL_RCC_PLLM_DIV_63
1576 * @param __PLLSAIN__ Between 50 and 432
1577 * @param __PLLSAIR__ This parameter can be one of the following values:
1578 * @arg @ref LL_RCC_PLLSAIR_DIV_2
1579 * @arg @ref LL_RCC_PLLSAIR_DIV_3
1580 * @arg @ref LL_RCC_PLLSAIR_DIV_4
1581 * @arg @ref LL_RCC_PLLSAIR_DIV_5
1582 * @arg @ref LL_RCC_PLLSAIR_DIV_6
1583 * @arg @ref LL_RCC_PLLSAIR_DIV_7
1584 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
1585 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
1586 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
1587 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
1588 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
1589 * @retval PLLSAI clock frequency (in Hz)
1590 */
1591 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1592 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
1593 #endif /* LTDC */
1594
1595 /**
1596 * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
1597 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1598 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
1599 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1600 * @param __PLLM__ This parameter can be one of the following values:
1601 * @arg @ref LL_RCC_PLLM_DIV_2
1602 * @arg @ref LL_RCC_PLLM_DIV_3
1603 * @arg @ref LL_RCC_PLLM_DIV_4
1604 * @arg @ref LL_RCC_PLLM_DIV_5
1605 * @arg @ref LL_RCC_PLLM_DIV_6
1606 * @arg @ref LL_RCC_PLLM_DIV_7
1607 * @arg @ref LL_RCC_PLLM_DIV_8
1608 * @arg @ref LL_RCC_PLLM_DIV_9
1609 * @arg @ref LL_RCC_PLLM_DIV_10
1610 * @arg @ref LL_RCC_PLLM_DIV_11
1611 * @arg @ref LL_RCC_PLLM_DIV_12
1612 * @arg @ref LL_RCC_PLLM_DIV_13
1613 * @arg @ref LL_RCC_PLLM_DIV_14
1614 * @arg @ref LL_RCC_PLLM_DIV_15
1615 * @arg @ref LL_RCC_PLLM_DIV_16
1616 * @arg @ref LL_RCC_PLLM_DIV_17
1617 * @arg @ref LL_RCC_PLLM_DIV_18
1618 * @arg @ref LL_RCC_PLLM_DIV_19
1619 * @arg @ref LL_RCC_PLLM_DIV_20
1620 * @arg @ref LL_RCC_PLLM_DIV_21
1621 * @arg @ref LL_RCC_PLLM_DIV_22
1622 * @arg @ref LL_RCC_PLLM_DIV_23
1623 * @arg @ref LL_RCC_PLLM_DIV_24
1624 * @arg @ref LL_RCC_PLLM_DIV_25
1625 * @arg @ref LL_RCC_PLLM_DIV_26
1626 * @arg @ref LL_RCC_PLLM_DIV_27
1627 * @arg @ref LL_RCC_PLLM_DIV_28
1628 * @arg @ref LL_RCC_PLLM_DIV_29
1629 * @arg @ref LL_RCC_PLLM_DIV_30
1630 * @arg @ref LL_RCC_PLLM_DIV_31
1631 * @arg @ref LL_RCC_PLLM_DIV_32
1632 * @arg @ref LL_RCC_PLLM_DIV_33
1633 * @arg @ref LL_RCC_PLLM_DIV_34
1634 * @arg @ref LL_RCC_PLLM_DIV_35
1635 * @arg @ref LL_RCC_PLLM_DIV_36
1636 * @arg @ref LL_RCC_PLLM_DIV_37
1637 * @arg @ref LL_RCC_PLLM_DIV_38
1638 * @arg @ref LL_RCC_PLLM_DIV_39
1639 * @arg @ref LL_RCC_PLLM_DIV_40
1640 * @arg @ref LL_RCC_PLLM_DIV_41
1641 * @arg @ref LL_RCC_PLLM_DIV_42
1642 * @arg @ref LL_RCC_PLLM_DIV_43
1643 * @arg @ref LL_RCC_PLLM_DIV_44
1644 * @arg @ref LL_RCC_PLLM_DIV_45
1645 * @arg @ref LL_RCC_PLLM_DIV_46
1646 * @arg @ref LL_RCC_PLLM_DIV_47
1647 * @arg @ref LL_RCC_PLLM_DIV_48
1648 * @arg @ref LL_RCC_PLLM_DIV_49
1649 * @arg @ref LL_RCC_PLLM_DIV_50
1650 * @arg @ref LL_RCC_PLLM_DIV_51
1651 * @arg @ref LL_RCC_PLLM_DIV_52
1652 * @arg @ref LL_RCC_PLLM_DIV_53
1653 * @arg @ref LL_RCC_PLLM_DIV_54
1654 * @arg @ref LL_RCC_PLLM_DIV_55
1655 * @arg @ref LL_RCC_PLLM_DIV_56
1656 * @arg @ref LL_RCC_PLLM_DIV_57
1657 * @arg @ref LL_RCC_PLLM_DIV_58
1658 * @arg @ref LL_RCC_PLLM_DIV_59
1659 * @arg @ref LL_RCC_PLLM_DIV_60
1660 * @arg @ref LL_RCC_PLLM_DIV_61
1661 * @arg @ref LL_RCC_PLLM_DIV_62
1662 * @arg @ref LL_RCC_PLLM_DIV_63
1663 * @param __PLLI2SN__ Between 50 and 432
1664 * @param __PLLI2SQ__ This parameter can be one of the following values:
1665 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
1666 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
1667 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
1668 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
1669 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
1670 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
1671 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
1672 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
1673 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
1674 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
1675 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
1676 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
1677 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
1678 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
1679 * @param __PLLI2SDIVQ__ This parameter can be one of the following values:
1680 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
1681 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
1682 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
1683 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
1684 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
1685 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
1686 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
1687 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
1688 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
1689 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
1690 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
1691 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
1692 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
1693 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
1694 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
1695 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
1696 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
1697 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
1698 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
1699 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
1700 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
1701 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
1702 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
1703 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
1704 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
1705 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
1706 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
1707 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
1708 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
1709 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
1710 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
1711 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
1712 * @retval PLLI2S clock frequency (in Hz)
1713 */
1714 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1715 (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
1716
1717 #if defined(SPDIFRX)
1718 /**
1719 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
1720 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1721 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
1722 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1723 * @param __PLLM__ This parameter can be one of the following values:
1724 * @arg @ref LL_RCC_PLLM_DIV_2
1725 * @arg @ref LL_RCC_PLLM_DIV_3
1726 * @arg @ref LL_RCC_PLLM_DIV_4
1727 * @arg @ref LL_RCC_PLLM_DIV_5
1728 * @arg @ref LL_RCC_PLLM_DIV_6
1729 * @arg @ref LL_RCC_PLLM_DIV_7
1730 * @arg @ref LL_RCC_PLLM_DIV_8
1731 * @arg @ref LL_RCC_PLLM_DIV_9
1732 * @arg @ref LL_RCC_PLLM_DIV_10
1733 * @arg @ref LL_RCC_PLLM_DIV_11
1734 * @arg @ref LL_RCC_PLLM_DIV_12
1735 * @arg @ref LL_RCC_PLLM_DIV_13
1736 * @arg @ref LL_RCC_PLLM_DIV_14
1737 * @arg @ref LL_RCC_PLLM_DIV_15
1738 * @arg @ref LL_RCC_PLLM_DIV_16
1739 * @arg @ref LL_RCC_PLLM_DIV_17
1740 * @arg @ref LL_RCC_PLLM_DIV_18
1741 * @arg @ref LL_RCC_PLLM_DIV_19
1742 * @arg @ref LL_RCC_PLLM_DIV_20
1743 * @arg @ref LL_RCC_PLLM_DIV_21
1744 * @arg @ref LL_RCC_PLLM_DIV_22
1745 * @arg @ref LL_RCC_PLLM_DIV_23
1746 * @arg @ref LL_RCC_PLLM_DIV_24
1747 * @arg @ref LL_RCC_PLLM_DIV_25
1748 * @arg @ref LL_RCC_PLLM_DIV_26
1749 * @arg @ref LL_RCC_PLLM_DIV_27
1750 * @arg @ref LL_RCC_PLLM_DIV_28
1751 * @arg @ref LL_RCC_PLLM_DIV_29
1752 * @arg @ref LL_RCC_PLLM_DIV_30
1753 * @arg @ref LL_RCC_PLLM_DIV_31
1754 * @arg @ref LL_RCC_PLLM_DIV_32
1755 * @arg @ref LL_RCC_PLLM_DIV_33
1756 * @arg @ref LL_RCC_PLLM_DIV_34
1757 * @arg @ref LL_RCC_PLLM_DIV_35
1758 * @arg @ref LL_RCC_PLLM_DIV_36
1759 * @arg @ref LL_RCC_PLLM_DIV_37
1760 * @arg @ref LL_RCC_PLLM_DIV_38
1761 * @arg @ref LL_RCC_PLLM_DIV_39
1762 * @arg @ref LL_RCC_PLLM_DIV_40
1763 * @arg @ref LL_RCC_PLLM_DIV_41
1764 * @arg @ref LL_RCC_PLLM_DIV_42
1765 * @arg @ref LL_RCC_PLLM_DIV_43
1766 * @arg @ref LL_RCC_PLLM_DIV_44
1767 * @arg @ref LL_RCC_PLLM_DIV_45
1768 * @arg @ref LL_RCC_PLLM_DIV_46
1769 * @arg @ref LL_RCC_PLLM_DIV_47
1770 * @arg @ref LL_RCC_PLLM_DIV_48
1771 * @arg @ref LL_RCC_PLLM_DIV_49
1772 * @arg @ref LL_RCC_PLLM_DIV_50
1773 * @arg @ref LL_RCC_PLLM_DIV_51
1774 * @arg @ref LL_RCC_PLLM_DIV_52
1775 * @arg @ref LL_RCC_PLLM_DIV_53
1776 * @arg @ref LL_RCC_PLLM_DIV_54
1777 * @arg @ref LL_RCC_PLLM_DIV_55
1778 * @arg @ref LL_RCC_PLLM_DIV_56
1779 * @arg @ref LL_RCC_PLLM_DIV_57
1780 * @arg @ref LL_RCC_PLLM_DIV_58
1781 * @arg @ref LL_RCC_PLLM_DIV_59
1782 * @arg @ref LL_RCC_PLLM_DIV_60
1783 * @arg @ref LL_RCC_PLLM_DIV_61
1784 * @arg @ref LL_RCC_PLLM_DIV_62
1785 * @arg @ref LL_RCC_PLLM_DIV_63
1786 * @param __PLLI2SN__ Between 50 and 432
1787 * @param __PLLI2SP__ This parameter can be one of the following values:
1788 * @arg @ref LL_RCC_PLLI2SP_DIV_2
1789 * @arg @ref LL_RCC_PLLI2SP_DIV_4
1790 * @arg @ref LL_RCC_PLLI2SP_DIV_6
1791 * @arg @ref LL_RCC_PLLI2SP_DIV_8
1792 * @retval PLLI2S clock frequency (in Hz)
1793 */
1794 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1795 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
1796 #endif /* SPDIFRX */
1797
1798 /**
1799 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
1800 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1801 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
1802 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1803 * @param __PLLM__ This parameter can be one of the following values:
1804 * @arg @ref LL_RCC_PLLM_DIV_2
1805 * @arg @ref LL_RCC_PLLM_DIV_3
1806 * @arg @ref LL_RCC_PLLM_DIV_4
1807 * @arg @ref LL_RCC_PLLM_DIV_5
1808 * @arg @ref LL_RCC_PLLM_DIV_6
1809 * @arg @ref LL_RCC_PLLM_DIV_7
1810 * @arg @ref LL_RCC_PLLM_DIV_8
1811 * @arg @ref LL_RCC_PLLM_DIV_9
1812 * @arg @ref LL_RCC_PLLM_DIV_10
1813 * @arg @ref LL_RCC_PLLM_DIV_11
1814 * @arg @ref LL_RCC_PLLM_DIV_12
1815 * @arg @ref LL_RCC_PLLM_DIV_13
1816 * @arg @ref LL_RCC_PLLM_DIV_14
1817 * @arg @ref LL_RCC_PLLM_DIV_15
1818 * @arg @ref LL_RCC_PLLM_DIV_16
1819 * @arg @ref LL_RCC_PLLM_DIV_17
1820 * @arg @ref LL_RCC_PLLM_DIV_18
1821 * @arg @ref LL_RCC_PLLM_DIV_19
1822 * @arg @ref LL_RCC_PLLM_DIV_20
1823 * @arg @ref LL_RCC_PLLM_DIV_21
1824 * @arg @ref LL_RCC_PLLM_DIV_22
1825 * @arg @ref LL_RCC_PLLM_DIV_23
1826 * @arg @ref LL_RCC_PLLM_DIV_24
1827 * @arg @ref LL_RCC_PLLM_DIV_25
1828 * @arg @ref LL_RCC_PLLM_DIV_26
1829 * @arg @ref LL_RCC_PLLM_DIV_27
1830 * @arg @ref LL_RCC_PLLM_DIV_28
1831 * @arg @ref LL_RCC_PLLM_DIV_29
1832 * @arg @ref LL_RCC_PLLM_DIV_30
1833 * @arg @ref LL_RCC_PLLM_DIV_31
1834 * @arg @ref LL_RCC_PLLM_DIV_32
1835 * @arg @ref LL_RCC_PLLM_DIV_33
1836 * @arg @ref LL_RCC_PLLM_DIV_34
1837 * @arg @ref LL_RCC_PLLM_DIV_35
1838 * @arg @ref LL_RCC_PLLM_DIV_36
1839 * @arg @ref LL_RCC_PLLM_DIV_37
1840 * @arg @ref LL_RCC_PLLM_DIV_38
1841 * @arg @ref LL_RCC_PLLM_DIV_39
1842 * @arg @ref LL_RCC_PLLM_DIV_40
1843 * @arg @ref LL_RCC_PLLM_DIV_41
1844 * @arg @ref LL_RCC_PLLM_DIV_42
1845 * @arg @ref LL_RCC_PLLM_DIV_43
1846 * @arg @ref LL_RCC_PLLM_DIV_44
1847 * @arg @ref LL_RCC_PLLM_DIV_45
1848 * @arg @ref LL_RCC_PLLM_DIV_46
1849 * @arg @ref LL_RCC_PLLM_DIV_47
1850 * @arg @ref LL_RCC_PLLM_DIV_48
1851 * @arg @ref LL_RCC_PLLM_DIV_49
1852 * @arg @ref LL_RCC_PLLM_DIV_50
1853 * @arg @ref LL_RCC_PLLM_DIV_51
1854 * @arg @ref LL_RCC_PLLM_DIV_52
1855 * @arg @ref LL_RCC_PLLM_DIV_53
1856 * @arg @ref LL_RCC_PLLM_DIV_54
1857 * @arg @ref LL_RCC_PLLM_DIV_55
1858 * @arg @ref LL_RCC_PLLM_DIV_56
1859 * @arg @ref LL_RCC_PLLM_DIV_57
1860 * @arg @ref LL_RCC_PLLM_DIV_58
1861 * @arg @ref LL_RCC_PLLM_DIV_59
1862 * @arg @ref LL_RCC_PLLM_DIV_60
1863 * @arg @ref LL_RCC_PLLM_DIV_61
1864 * @arg @ref LL_RCC_PLLM_DIV_62
1865 * @arg @ref LL_RCC_PLLM_DIV_63
1866 * @param __PLLI2SN__ Between 50 and 432
1867 * @param __PLLI2SR__ This parameter can be one of the following values:
1868 * @arg @ref LL_RCC_PLLI2SR_DIV_2
1869 * @arg @ref LL_RCC_PLLI2SR_DIV_3
1870 * @arg @ref LL_RCC_PLLI2SR_DIV_4
1871 * @arg @ref LL_RCC_PLLI2SR_DIV_5
1872 * @arg @ref LL_RCC_PLLI2SR_DIV_6
1873 * @arg @ref LL_RCC_PLLI2SR_DIV_7
1874 * @retval PLLI2S clock frequency (in Hz)
1875 */
1876 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1877 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
1878
1879 /**
1880 * @brief Helper macro to calculate the HCLK frequency
1881 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
1882 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1883 * @arg @ref LL_RCC_SYSCLK_DIV_1
1884 * @arg @ref LL_RCC_SYSCLK_DIV_2
1885 * @arg @ref LL_RCC_SYSCLK_DIV_4
1886 * @arg @ref LL_RCC_SYSCLK_DIV_8
1887 * @arg @ref LL_RCC_SYSCLK_DIV_16
1888 * @arg @ref LL_RCC_SYSCLK_DIV_64
1889 * @arg @ref LL_RCC_SYSCLK_DIV_128
1890 * @arg @ref LL_RCC_SYSCLK_DIV_256
1891 * @arg @ref LL_RCC_SYSCLK_DIV_512
1892 * @retval HCLK clock frequency (in Hz)
1893 */
1894 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1895
1896 /**
1897 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1898 * @param __HCLKFREQ__ HCLK frequency
1899 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1900 * @arg @ref LL_RCC_APB1_DIV_1
1901 * @arg @ref LL_RCC_APB1_DIV_2
1902 * @arg @ref LL_RCC_APB1_DIV_4
1903 * @arg @ref LL_RCC_APB1_DIV_8
1904 * @arg @ref LL_RCC_APB1_DIV_16
1905 * @retval PCLK1 clock frequency (in Hz)
1906 */
1907 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1908
1909 /**
1910 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1911 * @param __HCLKFREQ__ HCLK frequency
1912 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1913 * @arg @ref LL_RCC_APB2_DIV_1
1914 * @arg @ref LL_RCC_APB2_DIV_2
1915 * @arg @ref LL_RCC_APB2_DIV_4
1916 * @arg @ref LL_RCC_APB2_DIV_8
1917 * @arg @ref LL_RCC_APB2_DIV_16
1918 * @retval PCLK2 clock frequency (in Hz)
1919 */
1920 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1921
1922 /**
1923 * @}
1924 */
1925
1926 /**
1927 * @}
1928 */
1929
1930 /* Exported functions --------------------------------------------------------*/
1931 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1932 * @{
1933 */
1934
1935 /** @defgroup RCC_LL_EF_HSE HSE
1936 * @{
1937 */
1938
1939 /**
1940 * @brief Enable the Clock Security System.
1941 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1942 * @retval None
1943 */
1944 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1945 {
1946 SET_BIT(RCC->CR, RCC_CR_CSSON);
1947 }
1948
1949 /**
1950 * @brief Enable HSE external oscillator (HSE Bypass)
1951 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1952 * @retval None
1953 */
1954 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1955 {
1956 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1957 }
1958
1959 /**
1960 * @brief Disable HSE external oscillator (HSE Bypass)
1961 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1962 * @retval None
1963 */
1964 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1965 {
1966 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1967 }
1968
1969 /**
1970 * @brief Enable HSE crystal oscillator (HSE ON)
1971 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1972 * @retval None
1973 */
1974 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1975 {
1976 SET_BIT(RCC->CR, RCC_CR_HSEON);
1977 }
1978
1979 /**
1980 * @brief Disable HSE crystal oscillator (HSE ON)
1981 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1982 * @retval None
1983 */
1984 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1985 {
1986 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1987 }
1988
1989 /**
1990 * @brief Check if HSE oscillator Ready
1991 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1992 * @retval State of bit (1 or 0).
1993 */
1994 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1995 {
1996 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1997 }
1998
1999 /**
2000 * @}
2001 */
2002
2003 /** @defgroup RCC_LL_EF_HSI HSI
2004 * @{
2005 */
2006
2007 /**
2008 * @brief Enable HSI oscillator
2009 * @rmtoll CR HSION LL_RCC_HSI_Enable
2010 * @retval None
2011 */
2012 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2013 {
2014 SET_BIT(RCC->CR, RCC_CR_HSION);
2015 }
2016
2017 /**
2018 * @brief Disable HSI oscillator
2019 * @rmtoll CR HSION LL_RCC_HSI_Disable
2020 * @retval None
2021 */
2022 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2023 {
2024 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2025 }
2026
2027 /**
2028 * @brief Check if HSI clock is ready
2029 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
2030 * @retval State of bit (1 or 0).
2031 */
2032 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2033 {
2034 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
2035 }
2036
2037 /**
2038 * @brief Get HSI Calibration value
2039 * @note When HSITRIM is written, HSICAL is updated with the sum of
2040 * HSITRIM and the factory trim value
2041 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
2042 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2043 */
2044 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2045 {
2046 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
2047 }
2048
2049 /**
2050 * @brief Set HSI Calibration trimming
2051 * @note user-programmable trimming value that is added to the HSICAL
2052 * @note Default value is 16, which, when added to the HSICAL value,
2053 * should trim the HSI to 16 MHz +/- 1 %
2054 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
2055 * @param Value Between Min_Data = 0 and Max_Data = 31
2056 * @retval None
2057 */
2058 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2059 {
2060 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
2061 }
2062
2063 /**
2064 * @brief Get HSI Calibration trimming
2065 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
2066 * @retval Between Min_Data = 0 and Max_Data = 31
2067 */
2068 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2069 {
2070 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
2071 }
2072
2073 /**
2074 * @}
2075 */
2076
2077 /** @defgroup RCC_LL_EF_LSE LSE
2078 * @{
2079 */
2080
2081 /**
2082 * @brief Enable Low Speed External (LSE) crystal.
2083 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2084 * @retval None
2085 */
2086 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2087 {
2088 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2089 }
2090
2091 /**
2092 * @brief Disable Low Speed External (LSE) crystal.
2093 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2094 * @retval None
2095 */
2096 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2097 {
2098 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2099 }
2100
2101 /**
2102 * @brief Enable external clock source (LSE bypass).
2103 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2104 * @retval None
2105 */
2106 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2107 {
2108 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2109 }
2110
2111 /**
2112 * @brief Disable external clock source (LSE bypass).
2113 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2114 * @retval None
2115 */
2116 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2117 {
2118 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2119 }
2120
2121 /**
2122 * @brief Set LSE oscillator drive capability
2123 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2124 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2125 * @param LSEDrive This parameter can be one of the following values:
2126 * @arg @ref LL_RCC_LSEDRIVE_LOW
2127 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2128 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2129 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2130 * @retval None
2131 */
2132 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2133 {
2134 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2135 }
2136
2137 /**
2138 * @brief Get LSE oscillator drive capability
2139 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2140 * @retval Returned value can be one of the following values:
2141 * @arg @ref LL_RCC_LSEDRIVE_LOW
2142 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2143 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2144 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2145 */
2146 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2147 {
2148 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2149 }
2150
2151 /**
2152 * @brief Check if LSE oscillator Ready
2153 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2154 * @retval State of bit (1 or 0).
2155 */
2156 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2157 {
2158 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
2159 }
2160
2161 /**
2162 * @}
2163 */
2164
2165 /** @defgroup RCC_LL_EF_LSI LSI
2166 * @{
2167 */
2168
2169 /**
2170 * @brief Enable LSI Oscillator
2171 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2172 * @retval None
2173 */
2174 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2175 {
2176 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2177 }
2178
2179 /**
2180 * @brief Disable LSI Oscillator
2181 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2182 * @retval None
2183 */
2184 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2185 {
2186 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2187 }
2188
2189 /**
2190 * @brief Check if LSI is Ready
2191 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2192 * @retval State of bit (1 or 0).
2193 */
2194 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2195 {
2196 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
2197 }
2198
2199 /**
2200 * @}
2201 */
2202
2203 /** @defgroup RCC_LL_EF_System System
2204 * @{
2205 */
2206
2207 /**
2208 * @brief Configure the system clock source
2209 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2210 * @param Source This parameter can be one of the following values:
2211 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2212 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2213 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2214 * @retval None
2215 */
2216 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2217 {
2218 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2219 }
2220
2221 /**
2222 * @brief Get the system clock source
2223 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2224 * @retval Returned value can be one of the following values:
2225 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2226 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2227 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2228 */
2229 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2230 {
2231 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2232 }
2233
2234 /**
2235 * @brief Set AHB prescaler
2236 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2237 * @param Prescaler This parameter can be one of the following values:
2238 * @arg @ref LL_RCC_SYSCLK_DIV_1
2239 * @arg @ref LL_RCC_SYSCLK_DIV_2
2240 * @arg @ref LL_RCC_SYSCLK_DIV_4
2241 * @arg @ref LL_RCC_SYSCLK_DIV_8
2242 * @arg @ref LL_RCC_SYSCLK_DIV_16
2243 * @arg @ref LL_RCC_SYSCLK_DIV_64
2244 * @arg @ref LL_RCC_SYSCLK_DIV_128
2245 * @arg @ref LL_RCC_SYSCLK_DIV_256
2246 * @arg @ref LL_RCC_SYSCLK_DIV_512
2247 * @retval None
2248 */
2249 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2250 {
2251 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2252 }
2253
2254 /**
2255 * @brief Set APB1 prescaler
2256 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2257 * @param Prescaler This parameter can be one of the following values:
2258 * @arg @ref LL_RCC_APB1_DIV_1
2259 * @arg @ref LL_RCC_APB1_DIV_2
2260 * @arg @ref LL_RCC_APB1_DIV_4
2261 * @arg @ref LL_RCC_APB1_DIV_8
2262 * @arg @ref LL_RCC_APB1_DIV_16
2263 * @retval None
2264 */
2265 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2266 {
2267 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2268 }
2269
2270 /**
2271 * @brief Set APB2 prescaler
2272 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2273 * @param Prescaler This parameter can be one of the following values:
2274 * @arg @ref LL_RCC_APB2_DIV_1
2275 * @arg @ref LL_RCC_APB2_DIV_2
2276 * @arg @ref LL_RCC_APB2_DIV_4
2277 * @arg @ref LL_RCC_APB2_DIV_8
2278 * @arg @ref LL_RCC_APB2_DIV_16
2279 * @retval None
2280 */
2281 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2282 {
2283 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2284 }
2285
2286 /**
2287 * @brief Get AHB prescaler
2288 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2289 * @retval Returned value can be one of the following values:
2290 * @arg @ref LL_RCC_SYSCLK_DIV_1
2291 * @arg @ref LL_RCC_SYSCLK_DIV_2
2292 * @arg @ref LL_RCC_SYSCLK_DIV_4
2293 * @arg @ref LL_RCC_SYSCLK_DIV_8
2294 * @arg @ref LL_RCC_SYSCLK_DIV_16
2295 * @arg @ref LL_RCC_SYSCLK_DIV_64
2296 * @arg @ref LL_RCC_SYSCLK_DIV_128
2297 * @arg @ref LL_RCC_SYSCLK_DIV_256
2298 * @arg @ref LL_RCC_SYSCLK_DIV_512
2299 */
2300 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2301 {
2302 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2303 }
2304
2305 /**
2306 * @brief Get APB1 prescaler
2307 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2308 * @retval Returned value can be one of the following values:
2309 * @arg @ref LL_RCC_APB1_DIV_1
2310 * @arg @ref LL_RCC_APB1_DIV_2
2311 * @arg @ref LL_RCC_APB1_DIV_4
2312 * @arg @ref LL_RCC_APB1_DIV_8
2313 * @arg @ref LL_RCC_APB1_DIV_16
2314 */
2315 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2316 {
2317 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2318 }
2319
2320 /**
2321 * @brief Get APB2 prescaler
2322 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2323 * @retval Returned value can be one of the following values:
2324 * @arg @ref LL_RCC_APB2_DIV_1
2325 * @arg @ref LL_RCC_APB2_DIV_2
2326 * @arg @ref LL_RCC_APB2_DIV_4
2327 * @arg @ref LL_RCC_APB2_DIV_8
2328 * @arg @ref LL_RCC_APB2_DIV_16
2329 */
2330 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2331 {
2332 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2333 }
2334
2335 /**
2336 * @}
2337 */
2338
2339 /** @defgroup RCC_LL_EF_MCO MCO
2340 * @{
2341 */
2342
2343 /**
2344 * @brief Configure MCOx
2345 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2346 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2347 * CFGR MCO2 LL_RCC_ConfigMCO\n
2348 * CFGR MCO2PRE LL_RCC_ConfigMCO
2349 * @param MCOxSource This parameter can be one of the following values:
2350 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2351 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2352 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2353 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2354 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2355 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
2356 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2357 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
2358 * @param MCOxPrescaler This parameter can be one of the following values:
2359 * @arg @ref LL_RCC_MCO1_DIV_1
2360 * @arg @ref LL_RCC_MCO1_DIV_2
2361 * @arg @ref LL_RCC_MCO1_DIV_3
2362 * @arg @ref LL_RCC_MCO1_DIV_4
2363 * @arg @ref LL_RCC_MCO1_DIV_5
2364 * @arg @ref LL_RCC_MCO2_DIV_1
2365 * @arg @ref LL_RCC_MCO2_DIV_2
2366 * @arg @ref LL_RCC_MCO2_DIV_3
2367 * @arg @ref LL_RCC_MCO2_DIV_4
2368 * @arg @ref LL_RCC_MCO2_DIV_5
2369 * @retval None
2370 */
2371 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2372 {
2373 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
2374 }
2375
2376 /**
2377 * @}
2378 */
2379
2380 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2381 * @{
2382 */
2383
2384 /**
2385 * @brief Configure USARTx clock source
2386 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n
2387 * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n
2388 * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n
2389 * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource
2390 * @param USARTxSource This parameter can be one of the following values:
2391 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2392 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2393 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2394 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2395 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2396 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2397 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2398 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2399 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2400 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2401 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2402 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2403 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2404 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2405 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2406 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2407 * @retval None
2408 */
2409 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2410 {
2411 MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2412 }
2413
2414 /**
2415 * @brief Configure UARTx clock source
2416 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n
2417 * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n
2418 * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n
2419 * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource
2420 * @param UARTxSource This parameter can be one of the following values:
2421 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2422 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2423 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2424 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2425 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2426 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2427 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2428 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2429 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2430 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2431 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2432 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2433 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2434 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2435 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2436 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2437 * @retval None
2438 */
2439 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2440 {
2441 MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2442 }
2443
2444 /**
2445 * @brief Configure I2Cx clock source
2446 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n
2447 * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n
2448 * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n
2449 * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource
2450 * @param I2CxSource This parameter can be one of the following values:
2451 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2452 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2453 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2454 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2455 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2456 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2457 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2458 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2459 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2460 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2461 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2462 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2463 *
2464 * (*) value not defined in all devices.
2465 * @retval None
2466 */
2467 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2468 {
2469 MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U));
2470 }
2471
2472 /**
2473 * @brief Configure LPTIMx clock source
2474 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
2475 * @param LPTIMxSource This parameter can be one of the following values:
2476 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2477 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2478 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2479 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2480 * @retval None
2481 */
2482 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2483 {
2484 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
2485 }
2486
2487 /**
2488 * @brief Configure SAIx clock source
2489 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n
2490 * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource
2491 * @param SAIxSource This parameter can be one of the following values:
2492 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2493 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2494 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2495 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2496 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2497 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2498 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2499 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2500 *
2501 * (*) value not defined in all devices.
2502 * @retval None
2503 */
2504 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2505 {
2506 MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
2507 }
2508
2509 /**
2510 * @brief Configure SDMMC clock source
2511 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
2512 * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource
2513 * @param SDMMCxSource This parameter can be one of the following values:
2514 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2515 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2516 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2517 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2518 *
2519 * (*) value not defined in all devices.
2520 * @retval None
2521 */
2522 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2523 {
2524 MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
2525 }
2526
2527 /**
2528 * @brief Configure 48Mhz domain clock source
2529 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
2530 * @param CK48MxSource This parameter can be one of the following values:
2531 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2532 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2533 * @retval None
2534 */
2535 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
2536 {
2537 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
2538 }
2539
2540 /**
2541 * @brief Configure RNG clock source
2542 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
2543 * @param RNGxSource This parameter can be one of the following values:
2544 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2545 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2546 * @retval None
2547 */
2548 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2549 {
2550 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
2551 }
2552
2553 /**
2554 * @brief Configure USB clock source
2555 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
2556 * @param USBxSource This parameter can be one of the following values:
2557 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2558 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2559 * @retval None
2560 */
2561 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2562 {
2563 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
2564 }
2565
2566 #if defined(CEC)
2567 /**
2568 * @brief Configure CEC clock source
2569 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
2570 * @param Source This parameter can be one of the following values:
2571 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2572 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2573 * @retval None
2574 */
2575 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
2576 {
2577 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
2578 }
2579 #endif /* CEC */
2580
2581 /**
2582 * @brief Configure I2S clock source
2583 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
2584 * @param Source This parameter can be one of the following values:
2585 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2586 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2587 * @retval None
2588 */
2589 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
2590 {
2591 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
2592 }
2593
2594 #if defined(DSI)
2595 /**
2596 * @brief Configure DSI clock source
2597 * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource
2598 * @param Source This parameter can be one of the following values:
2599 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2600 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2601 * @retval None
2602 */
2603 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
2604 {
2605 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
2606 }
2607 #endif /* DSI */
2608
2609 #if defined(DFSDM1_Channel0)
2610 /**
2611 * @brief Configure DFSDM Audio clock source
2612 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
2613 * @param Source This parameter can be one of the following values:
2614 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2615 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2616 * @retval None
2617 */
2618 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
2619 {
2620 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
2621 }
2622
2623 /**
2624 * @brief Configure DFSDM Kernel clock source
2625 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource
2626 * @param Source This parameter can be one of the following values:
2627 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2628 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2629 * @retval None
2630 */
2631 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
2632 {
2633 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
2634 }
2635 #endif /* DFSDM1_Channel0 */
2636
2637 /**
2638 * @brief Get USARTx clock source
2639 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n
2640 * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n
2641 * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n
2642 * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource
2643 * @param USARTx This parameter can be one of the following values:
2644 * @arg @ref LL_RCC_USART1_CLKSOURCE
2645 * @arg @ref LL_RCC_USART2_CLKSOURCE
2646 * @arg @ref LL_RCC_USART3_CLKSOURCE
2647 * @arg @ref LL_RCC_USART6_CLKSOURCE
2648 * @retval Returned value can be one of the following values:
2649 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2650 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2651 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2652 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2653 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2654 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2655 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2656 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2657 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2658 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2659 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2660 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2661 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2662 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2663 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2664 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2665 */
2666 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2667 {
2668 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
2669 }
2670
2671 /**
2672 * @brief Get UARTx clock source
2673 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n
2674 * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n
2675 * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n
2676 * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource
2677 * @param UARTx This parameter can be one of the following values:
2678 * @arg @ref LL_RCC_UART4_CLKSOURCE
2679 * @arg @ref LL_RCC_UART5_CLKSOURCE
2680 * @arg @ref LL_RCC_UART7_CLKSOURCE
2681 * @arg @ref LL_RCC_UART8_CLKSOURCE
2682 * @retval Returned value can be one of the following values:
2683 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2684 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2685 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2686 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2687 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2688 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2689 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2690 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2691 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2692 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2693 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2694 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2695 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2696 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2697 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2698 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2699 */
2700 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
2701 {
2702 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
2703 }
2704
2705 /**
2706 * @brief Get I2Cx clock source
2707 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n
2708 * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n
2709 * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n
2710 * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource
2711 * @param I2Cx This parameter can be one of the following values:
2712 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2713 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2714 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2715 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
2716 * @retval Returned value can be one of the following values:
2717 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2718 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2719 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2720 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2721 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2722 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2723 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2724 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2725 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2726 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2727 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2728 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2729 *
2730 * (*) value not defined in all devices.
2731 */
2732 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2733 {
2734 return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
2735 }
2736
2737 /**
2738 * @brief Get LPTIMx clock source
2739 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
2740 * @param LPTIMx This parameter can be one of the following values:
2741 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2742 * @retval Returned value can be one of the following values:
2743 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2744 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2745 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2746 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2747 */
2748 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2749 {
2750 UNUSED(LPTIMx);
2751 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
2752 }
2753
2754 /**
2755 * @brief Get SAIx clock source
2756 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n
2757 * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource
2758 * @param SAIx This parameter can be one of the following values:
2759 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2760 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2761 * @retval Returned value can be one of the following values:
2762 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2763 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2764 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2765 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2766 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2767 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2768 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2769 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2770 *
2771 * (*) value not defined in all devices.
2772 */
2773 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2774 {
2775 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
2776 }
2777
2778 /**
2779 * @brief Get SDMMCx clock source
2780 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
2781 * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource
2782 * @param SDMMCx This parameter can be one of the following values:
2783 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2784 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
2785 * @retval Returned value can be one of the following values:
2786 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2787 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2788 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2789 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2790 *
2791 * (*) value not defined in all devices.
2792 */
2793 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
2794 {
2795 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
2796 }
2797
2798 /**
2799 * @brief Get 48Mhz domain clock source
2800 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
2801 * @param CK48Mx This parameter can be one of the following values:
2802 * @arg @ref LL_RCC_CK48M_CLKSOURCE
2803 * @retval Returned value can be one of the following values:
2804 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2805 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2806 */
2807 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
2808 {
2809 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
2810 }
2811
2812 /**
2813 * @brief Get RNGx clock source
2814 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
2815 * @param RNGx This parameter can be one of the following values:
2816 * @arg @ref LL_RCC_RNG_CLKSOURCE
2817 * @retval Returned value can be one of the following values:
2818 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2819 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2820 */
2821 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2822 {
2823 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
2824 }
2825
2826 /**
2827 * @brief Get USBx clock source
2828 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
2829 * @param USBx This parameter can be one of the following values:
2830 * @arg @ref LL_RCC_USB_CLKSOURCE
2831 * @retval Returned value can be one of the following values:
2832 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2833 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2834 */
2835 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2836 {
2837 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
2838 }
2839
2840 #if defined(CEC)
2841 /**
2842 * @brief Get CEC Clock Source
2843 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
2844 * @param CECx This parameter can be one of the following values:
2845 * @arg @ref LL_RCC_CEC_CLKSOURCE
2846 * @retval Returned value can be one of the following values:
2847 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2848 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2849 */
2850 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
2851 {
2852 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
2853 }
2854 #endif /* CEC */
2855
2856 /**
2857 * @brief Get I2S Clock Source
2858 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
2859 * @param I2Sx This parameter can be one of the following values:
2860 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2861 * @retval Returned value can be one of the following values:
2862 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2863 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2864 */
2865 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2866 {
2867 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
2868 }
2869
2870 #if defined(DFSDM1_Channel0)
2871 /**
2872 * @brief Get DFSDM Audio Clock Source
2873 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
2874 * @param DFSDMx This parameter can be one of the following values:
2875 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
2876 * @retval Returned value can be one of the following values:
2877 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2878 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2879 */
2880 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
2881 {
2882 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2883 }
2884
2885 /**
2886 * @brief Get DFSDM Audio Clock Source
2887 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource
2888 * @param DFSDMx This parameter can be one of the following values:
2889 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
2890 * @retval Returned value can be one of the following values:
2891 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2892 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2893 */
2894 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
2895 {
2896 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2897 }
2898 #endif /* DFSDM1_Channel0 */
2899
2900 #if defined(DSI)
2901 /**
2902 * @brief Get DSI Clock Source
2903 * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource
2904 * @param DSIx This parameter can be one of the following values:
2905 * @arg @ref LL_RCC_DSI_CLKSOURCE
2906 * @retval Returned value can be one of the following values:
2907 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2908 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2909 */
2910 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
2911 {
2912 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
2913 }
2914 #endif /* DSI */
2915
2916 /**
2917 * @}
2918 */
2919
2920 /** @defgroup RCC_LL_EF_RTC RTC
2921 * @{
2922 */
2923
2924 /**
2925 * @brief Set RTC Clock Source
2926 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2927 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2928 * set). The BDRST bit can be used to reset them.
2929 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2930 * @param Source This parameter can be one of the following values:
2931 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2932 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2933 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2934 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2935 * @retval None
2936 */
2937 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2938 {
2939 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2940 }
2941
2942 /**
2943 * @brief Get RTC Clock Source
2944 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2945 * @retval Returned value can be one of the following values:
2946 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2947 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2948 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2949 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2950 */
2951 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2952 {
2953 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2954 }
2955
2956 /**
2957 * @brief Enable RTC
2958 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2959 * @retval None
2960 */
2961 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2962 {
2963 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2964 }
2965
2966 /**
2967 * @brief Disable RTC
2968 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2969 * @retval None
2970 */
2971 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2972 {
2973 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2974 }
2975
2976 /**
2977 * @brief Check if RTC has been enabled or not
2978 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2979 * @retval State of bit (1 or 0).
2980 */
2981 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2982 {
2983 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2984 }
2985
2986 /**
2987 * @brief Force the Backup domain reset
2988 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2989 * @retval None
2990 */
2991 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2992 {
2993 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2994 }
2995
2996 /**
2997 * @brief Release the Backup domain reset
2998 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2999 * @retval None
3000 */
3001 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3002 {
3003 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3004 }
3005
3006 /**
3007 * @brief Set HSE Prescalers for RTC Clock
3008 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
3009 * @param Prescaler This parameter can be one of the following values:
3010 * @arg @ref LL_RCC_RTC_NOCLOCK
3011 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3012 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3013 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3014 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3015 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3016 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3017 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3018 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3019 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3020 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3021 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3022 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3023 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3024 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3025 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3026 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3027 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3028 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3029 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3030 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3031 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3032 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3033 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3034 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3035 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3036 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3037 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3038 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3039 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3040 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3041 * @retval None
3042 */
3043 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
3044 {
3045 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
3046 }
3047
3048 /**
3049 * @brief Get HSE Prescalers for RTC Clock
3050 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
3051 * @retval Returned value can be one of the following values:
3052 * @arg @ref LL_RCC_RTC_NOCLOCK
3053 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3054 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3055 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3056 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3057 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3058 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3059 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3060 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3061 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3062 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3063 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3064 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3065 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3066 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3067 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3068 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3069 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3070 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3071 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3072 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3073 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3074 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3075 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3076 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3077 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3078 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3079 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3080 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3081 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3082 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3083 */
3084 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
3085 {
3086 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
3087 }
3088
3089 /**
3090 * @}
3091 */
3092
3093 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
3094 * @{
3095 */
3096
3097 /**
3098 * @brief Set Timers Clock Prescalers
3099 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler
3100 * @param Prescaler This parameter can be one of the following values:
3101 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3102 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3103 * @retval None
3104 */
3105 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
3106 {
3107 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
3108 }
3109
3110 /**
3111 * @brief Get Timers Clock Prescalers
3112 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler
3113 * @retval Returned value can be one of the following values:
3114 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3115 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3116 */
3117 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
3118 {
3119 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
3120 }
3121
3122 /**
3123 * @}
3124 */
3125
3126 /** @defgroup RCC_LL_EF_PLL PLL
3127 * @{
3128 */
3129
3130 /**
3131 * @brief Enable PLL
3132 * @rmtoll CR PLLON LL_RCC_PLL_Enable
3133 * @retval None
3134 */
3135 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3136 {
3137 SET_BIT(RCC->CR, RCC_CR_PLLON);
3138 }
3139
3140 /**
3141 * @brief Disable PLL
3142 * @note Cannot be disabled if the PLL clock is used as the system clock
3143 * @rmtoll CR PLLON LL_RCC_PLL_Disable
3144 * @retval None
3145 */
3146 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3147 {
3148 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3149 }
3150
3151 /**
3152 * @brief Check if PLL Ready
3153 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3154 * @retval State of bit (1 or 0).
3155 */
3156 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3157 {
3158 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
3159 }
3160
3161 /**
3162 * @brief Configure PLL used for SYSCLK Domain
3163 * @note PLL Source and PLLM Divider can be written only when PLL,
3164 * PLLI2S and PLLSAI are disabled
3165 * @note PLLN/PLLP can be written only when PLL is disabled
3166 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3167 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3168 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3169 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
3170 * @param Source This parameter can be one of the following values:
3171 * @arg @ref LL_RCC_PLLSOURCE_HSI
3172 * @arg @ref LL_RCC_PLLSOURCE_HSE
3173 * @param PLLM This parameter can be one of the following values:
3174 * @arg @ref LL_RCC_PLLM_DIV_2
3175 * @arg @ref LL_RCC_PLLM_DIV_3
3176 * @arg @ref LL_RCC_PLLM_DIV_4
3177 * @arg @ref LL_RCC_PLLM_DIV_5
3178 * @arg @ref LL_RCC_PLLM_DIV_6
3179 * @arg @ref LL_RCC_PLLM_DIV_7
3180 * @arg @ref LL_RCC_PLLM_DIV_8
3181 * @arg @ref LL_RCC_PLLM_DIV_9
3182 * @arg @ref LL_RCC_PLLM_DIV_10
3183 * @arg @ref LL_RCC_PLLM_DIV_11
3184 * @arg @ref LL_RCC_PLLM_DIV_12
3185 * @arg @ref LL_RCC_PLLM_DIV_13
3186 * @arg @ref LL_RCC_PLLM_DIV_14
3187 * @arg @ref LL_RCC_PLLM_DIV_15
3188 * @arg @ref LL_RCC_PLLM_DIV_16
3189 * @arg @ref LL_RCC_PLLM_DIV_17
3190 * @arg @ref LL_RCC_PLLM_DIV_18
3191 * @arg @ref LL_RCC_PLLM_DIV_19
3192 * @arg @ref LL_RCC_PLLM_DIV_20
3193 * @arg @ref LL_RCC_PLLM_DIV_21
3194 * @arg @ref LL_RCC_PLLM_DIV_22
3195 * @arg @ref LL_RCC_PLLM_DIV_23
3196 * @arg @ref LL_RCC_PLLM_DIV_24
3197 * @arg @ref LL_RCC_PLLM_DIV_25
3198 * @arg @ref LL_RCC_PLLM_DIV_26
3199 * @arg @ref LL_RCC_PLLM_DIV_27
3200 * @arg @ref LL_RCC_PLLM_DIV_28
3201 * @arg @ref LL_RCC_PLLM_DIV_29
3202 * @arg @ref LL_RCC_PLLM_DIV_30
3203 * @arg @ref LL_RCC_PLLM_DIV_31
3204 * @arg @ref LL_RCC_PLLM_DIV_32
3205 * @arg @ref LL_RCC_PLLM_DIV_33
3206 * @arg @ref LL_RCC_PLLM_DIV_34
3207 * @arg @ref LL_RCC_PLLM_DIV_35
3208 * @arg @ref LL_RCC_PLLM_DIV_36
3209 * @arg @ref LL_RCC_PLLM_DIV_37
3210 * @arg @ref LL_RCC_PLLM_DIV_38
3211 * @arg @ref LL_RCC_PLLM_DIV_39
3212 * @arg @ref LL_RCC_PLLM_DIV_40
3213 * @arg @ref LL_RCC_PLLM_DIV_41
3214 * @arg @ref LL_RCC_PLLM_DIV_42
3215 * @arg @ref LL_RCC_PLLM_DIV_43
3216 * @arg @ref LL_RCC_PLLM_DIV_44
3217 * @arg @ref LL_RCC_PLLM_DIV_45
3218 * @arg @ref LL_RCC_PLLM_DIV_46
3219 * @arg @ref LL_RCC_PLLM_DIV_47
3220 * @arg @ref LL_RCC_PLLM_DIV_48
3221 * @arg @ref LL_RCC_PLLM_DIV_49
3222 * @arg @ref LL_RCC_PLLM_DIV_50
3223 * @arg @ref LL_RCC_PLLM_DIV_51
3224 * @arg @ref LL_RCC_PLLM_DIV_52
3225 * @arg @ref LL_RCC_PLLM_DIV_53
3226 * @arg @ref LL_RCC_PLLM_DIV_54
3227 * @arg @ref LL_RCC_PLLM_DIV_55
3228 * @arg @ref LL_RCC_PLLM_DIV_56
3229 * @arg @ref LL_RCC_PLLM_DIV_57
3230 * @arg @ref LL_RCC_PLLM_DIV_58
3231 * @arg @ref LL_RCC_PLLM_DIV_59
3232 * @arg @ref LL_RCC_PLLM_DIV_60
3233 * @arg @ref LL_RCC_PLLM_DIV_61
3234 * @arg @ref LL_RCC_PLLM_DIV_62
3235 * @arg @ref LL_RCC_PLLM_DIV_63
3236 * @param PLLN Between 50 and 432
3237 * @param PLLP This parameter can be one of the following values:
3238 * @arg @ref LL_RCC_PLLP_DIV_2
3239 * @arg @ref LL_RCC_PLLP_DIV_4
3240 * @arg @ref LL_RCC_PLLP_DIV_6
3241 * @arg @ref LL_RCC_PLLP_DIV_8
3242 * @retval None
3243 */
3244 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3245 {
3246 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3247 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
3248 }
3249
3250 /**
3251 * @brief Configure PLL used for 48Mhz domain clock
3252 * @note PLL Source and PLLM Divider can be written only when PLL,
3253 * PLLI2S and PLLSAI are disabled
3254 * @note PLLN/PLLQ can be written only when PLL is disabled
3255 * @note This can be selected for USB, RNG, SDMMC1
3256 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3257 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3258 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3259 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3260 * @param Source This parameter can be one of the following values:
3261 * @arg @ref LL_RCC_PLLSOURCE_HSI
3262 * @arg @ref LL_RCC_PLLSOURCE_HSE
3263 * @param PLLM This parameter can be one of the following values:
3264 * @arg @ref LL_RCC_PLLM_DIV_2
3265 * @arg @ref LL_RCC_PLLM_DIV_3
3266 * @arg @ref LL_RCC_PLLM_DIV_4
3267 * @arg @ref LL_RCC_PLLM_DIV_5
3268 * @arg @ref LL_RCC_PLLM_DIV_6
3269 * @arg @ref LL_RCC_PLLM_DIV_7
3270 * @arg @ref LL_RCC_PLLM_DIV_8
3271 * @arg @ref LL_RCC_PLLM_DIV_9
3272 * @arg @ref LL_RCC_PLLM_DIV_10
3273 * @arg @ref LL_RCC_PLLM_DIV_11
3274 * @arg @ref LL_RCC_PLLM_DIV_12
3275 * @arg @ref LL_RCC_PLLM_DIV_13
3276 * @arg @ref LL_RCC_PLLM_DIV_14
3277 * @arg @ref LL_RCC_PLLM_DIV_15
3278 * @arg @ref LL_RCC_PLLM_DIV_16
3279 * @arg @ref LL_RCC_PLLM_DIV_17
3280 * @arg @ref LL_RCC_PLLM_DIV_18
3281 * @arg @ref LL_RCC_PLLM_DIV_19
3282 * @arg @ref LL_RCC_PLLM_DIV_20
3283 * @arg @ref LL_RCC_PLLM_DIV_21
3284 * @arg @ref LL_RCC_PLLM_DIV_22
3285 * @arg @ref LL_RCC_PLLM_DIV_23
3286 * @arg @ref LL_RCC_PLLM_DIV_24
3287 * @arg @ref LL_RCC_PLLM_DIV_25
3288 * @arg @ref LL_RCC_PLLM_DIV_26
3289 * @arg @ref LL_RCC_PLLM_DIV_27
3290 * @arg @ref LL_RCC_PLLM_DIV_28
3291 * @arg @ref LL_RCC_PLLM_DIV_29
3292 * @arg @ref LL_RCC_PLLM_DIV_30
3293 * @arg @ref LL_RCC_PLLM_DIV_31
3294 * @arg @ref LL_RCC_PLLM_DIV_32
3295 * @arg @ref LL_RCC_PLLM_DIV_33
3296 * @arg @ref LL_RCC_PLLM_DIV_34
3297 * @arg @ref LL_RCC_PLLM_DIV_35
3298 * @arg @ref LL_RCC_PLLM_DIV_36
3299 * @arg @ref LL_RCC_PLLM_DIV_37
3300 * @arg @ref LL_RCC_PLLM_DIV_38
3301 * @arg @ref LL_RCC_PLLM_DIV_39
3302 * @arg @ref LL_RCC_PLLM_DIV_40
3303 * @arg @ref LL_RCC_PLLM_DIV_41
3304 * @arg @ref LL_RCC_PLLM_DIV_42
3305 * @arg @ref LL_RCC_PLLM_DIV_43
3306 * @arg @ref LL_RCC_PLLM_DIV_44
3307 * @arg @ref LL_RCC_PLLM_DIV_45
3308 * @arg @ref LL_RCC_PLLM_DIV_46
3309 * @arg @ref LL_RCC_PLLM_DIV_47
3310 * @arg @ref LL_RCC_PLLM_DIV_48
3311 * @arg @ref LL_RCC_PLLM_DIV_49
3312 * @arg @ref LL_RCC_PLLM_DIV_50
3313 * @arg @ref LL_RCC_PLLM_DIV_51
3314 * @arg @ref LL_RCC_PLLM_DIV_52
3315 * @arg @ref LL_RCC_PLLM_DIV_53
3316 * @arg @ref LL_RCC_PLLM_DIV_54
3317 * @arg @ref LL_RCC_PLLM_DIV_55
3318 * @arg @ref LL_RCC_PLLM_DIV_56
3319 * @arg @ref LL_RCC_PLLM_DIV_57
3320 * @arg @ref LL_RCC_PLLM_DIV_58
3321 * @arg @ref LL_RCC_PLLM_DIV_59
3322 * @arg @ref LL_RCC_PLLM_DIV_60
3323 * @arg @ref LL_RCC_PLLM_DIV_61
3324 * @arg @ref LL_RCC_PLLM_DIV_62
3325 * @arg @ref LL_RCC_PLLM_DIV_63
3326 * @param PLLN Between 50 and 432
3327 * @param PLLQ This parameter can be one of the following values:
3328 * @arg @ref LL_RCC_PLLQ_DIV_2
3329 * @arg @ref LL_RCC_PLLQ_DIV_3
3330 * @arg @ref LL_RCC_PLLQ_DIV_4
3331 * @arg @ref LL_RCC_PLLQ_DIV_5
3332 * @arg @ref LL_RCC_PLLQ_DIV_6
3333 * @arg @ref LL_RCC_PLLQ_DIV_7
3334 * @arg @ref LL_RCC_PLLQ_DIV_8
3335 * @arg @ref LL_RCC_PLLQ_DIV_9
3336 * @arg @ref LL_RCC_PLLQ_DIV_10
3337 * @arg @ref LL_RCC_PLLQ_DIV_11
3338 * @arg @ref LL_RCC_PLLQ_DIV_12
3339 * @arg @ref LL_RCC_PLLQ_DIV_13
3340 * @arg @ref LL_RCC_PLLQ_DIV_14
3341 * @arg @ref LL_RCC_PLLQ_DIV_15
3342 * @retval None
3343 */
3344 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3345 {
3346 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3347 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
3348 }
3349
3350 #if defined(DSI)
3351 /**
3352 * @brief Configure PLL used for DSI clock
3353 * @note PLL Source and PLLM Divider can be written only when PLL,
3354 * PLLI2S and PLLSAI are disabled
3355 * @note PLLN/PLLR can be written only when PLL is disabled
3356 * @note This can be selected for DSI
3357 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
3358 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
3359 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
3360 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
3361 * @param Source This parameter can be one of the following values:
3362 * @arg @ref LL_RCC_PLLSOURCE_HSI
3363 * @arg @ref LL_RCC_PLLSOURCE_HSE
3364 * @param PLLM This parameter can be one of the following values:
3365 * @arg @ref LL_RCC_PLLM_DIV_2
3366 * @arg @ref LL_RCC_PLLM_DIV_3
3367 * @arg @ref LL_RCC_PLLM_DIV_4
3368 * @arg @ref LL_RCC_PLLM_DIV_5
3369 * @arg @ref LL_RCC_PLLM_DIV_6
3370 * @arg @ref LL_RCC_PLLM_DIV_7
3371 * @arg @ref LL_RCC_PLLM_DIV_8
3372 * @arg @ref LL_RCC_PLLM_DIV_9
3373 * @arg @ref LL_RCC_PLLM_DIV_10
3374 * @arg @ref LL_RCC_PLLM_DIV_11
3375 * @arg @ref LL_RCC_PLLM_DIV_12
3376 * @arg @ref LL_RCC_PLLM_DIV_13
3377 * @arg @ref LL_RCC_PLLM_DIV_14
3378 * @arg @ref LL_RCC_PLLM_DIV_15
3379 * @arg @ref LL_RCC_PLLM_DIV_16
3380 * @arg @ref LL_RCC_PLLM_DIV_17
3381 * @arg @ref LL_RCC_PLLM_DIV_18
3382 * @arg @ref LL_RCC_PLLM_DIV_19
3383 * @arg @ref LL_RCC_PLLM_DIV_20
3384 * @arg @ref LL_RCC_PLLM_DIV_21
3385 * @arg @ref LL_RCC_PLLM_DIV_22
3386 * @arg @ref LL_RCC_PLLM_DIV_23
3387 * @arg @ref LL_RCC_PLLM_DIV_24
3388 * @arg @ref LL_RCC_PLLM_DIV_25
3389 * @arg @ref LL_RCC_PLLM_DIV_26
3390 * @arg @ref LL_RCC_PLLM_DIV_27
3391 * @arg @ref LL_RCC_PLLM_DIV_28
3392 * @arg @ref LL_RCC_PLLM_DIV_29
3393 * @arg @ref LL_RCC_PLLM_DIV_30
3394 * @arg @ref LL_RCC_PLLM_DIV_31
3395 * @arg @ref LL_RCC_PLLM_DIV_32
3396 * @arg @ref LL_RCC_PLLM_DIV_33
3397 * @arg @ref LL_RCC_PLLM_DIV_34
3398 * @arg @ref LL_RCC_PLLM_DIV_35
3399 * @arg @ref LL_RCC_PLLM_DIV_36
3400 * @arg @ref LL_RCC_PLLM_DIV_37
3401 * @arg @ref LL_RCC_PLLM_DIV_38
3402 * @arg @ref LL_RCC_PLLM_DIV_39
3403 * @arg @ref LL_RCC_PLLM_DIV_40
3404 * @arg @ref LL_RCC_PLLM_DIV_41
3405 * @arg @ref LL_RCC_PLLM_DIV_42
3406 * @arg @ref LL_RCC_PLLM_DIV_43
3407 * @arg @ref LL_RCC_PLLM_DIV_44
3408 * @arg @ref LL_RCC_PLLM_DIV_45
3409 * @arg @ref LL_RCC_PLLM_DIV_46
3410 * @arg @ref LL_RCC_PLLM_DIV_47
3411 * @arg @ref LL_RCC_PLLM_DIV_48
3412 * @arg @ref LL_RCC_PLLM_DIV_49
3413 * @arg @ref LL_RCC_PLLM_DIV_50
3414 * @arg @ref LL_RCC_PLLM_DIV_51
3415 * @arg @ref LL_RCC_PLLM_DIV_52
3416 * @arg @ref LL_RCC_PLLM_DIV_53
3417 * @arg @ref LL_RCC_PLLM_DIV_54
3418 * @arg @ref LL_RCC_PLLM_DIV_55
3419 * @arg @ref LL_RCC_PLLM_DIV_56
3420 * @arg @ref LL_RCC_PLLM_DIV_57
3421 * @arg @ref LL_RCC_PLLM_DIV_58
3422 * @arg @ref LL_RCC_PLLM_DIV_59
3423 * @arg @ref LL_RCC_PLLM_DIV_60
3424 * @arg @ref LL_RCC_PLLM_DIV_61
3425 * @arg @ref LL_RCC_PLLM_DIV_62
3426 * @arg @ref LL_RCC_PLLM_DIV_63
3427 * @param PLLN Between 50 and 432
3428 * @param PLLR This parameter can be one of the following values:
3429 * @arg @ref LL_RCC_PLLR_DIV_2
3430 * @arg @ref LL_RCC_PLLR_DIV_3
3431 * @arg @ref LL_RCC_PLLR_DIV_4
3432 * @arg @ref LL_RCC_PLLR_DIV_5
3433 * @arg @ref LL_RCC_PLLR_DIV_6
3434 * @arg @ref LL_RCC_PLLR_DIV_7
3435 * @retval None
3436 */
3437 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3438 {
3439 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3440 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
3441 }
3442 #endif /* DSI */
3443
3444 /**
3445 * @brief Configure PLL clock source
3446 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3447 * @param PLLSource This parameter can be one of the following values:
3448 * @arg @ref LL_RCC_PLLSOURCE_HSI
3449 * @arg @ref LL_RCC_PLLSOURCE_HSE
3450 * @retval None
3451 */
3452 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3453 {
3454 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3455 }
3456
3457 /**
3458 * @brief Get the oscillator used as PLL clock source.
3459 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3460 * @retval Returned value can be one of the following values:
3461 * @arg @ref LL_RCC_PLLSOURCE_HSI
3462 * @arg @ref LL_RCC_PLLSOURCE_HSE
3463 */
3464 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3465 {
3466 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3467 }
3468
3469 /**
3470 * @brief Get Main PLL multiplication factor for VCO
3471 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3472 * @retval Between 50 and 432
3473 */
3474 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3475 {
3476 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3477 }
3478
3479 /**
3480 * @brief Get Main PLL division factor for PLLP
3481 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3482 * @retval Returned value can be one of the following values:
3483 * @arg @ref LL_RCC_PLLP_DIV_2
3484 * @arg @ref LL_RCC_PLLP_DIV_4
3485 * @arg @ref LL_RCC_PLLP_DIV_6
3486 * @arg @ref LL_RCC_PLLP_DIV_8
3487 */
3488 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3489 {
3490 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3491 }
3492
3493 /**
3494 * @brief Get Main PLL division factor for PLLQ
3495 * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
3496 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3497 * @retval Returned value can be one of the following values:
3498 * @arg @ref LL_RCC_PLLQ_DIV_2
3499 * @arg @ref LL_RCC_PLLQ_DIV_3
3500 * @arg @ref LL_RCC_PLLQ_DIV_4
3501 * @arg @ref LL_RCC_PLLQ_DIV_5
3502 * @arg @ref LL_RCC_PLLQ_DIV_6
3503 * @arg @ref LL_RCC_PLLQ_DIV_7
3504 * @arg @ref LL_RCC_PLLQ_DIV_8
3505 * @arg @ref LL_RCC_PLLQ_DIV_9
3506 * @arg @ref LL_RCC_PLLQ_DIV_10
3507 * @arg @ref LL_RCC_PLLQ_DIV_11
3508 * @arg @ref LL_RCC_PLLQ_DIV_12
3509 * @arg @ref LL_RCC_PLLQ_DIV_13
3510 * @arg @ref LL_RCC_PLLQ_DIV_14
3511 * @arg @ref LL_RCC_PLLQ_DIV_15
3512 */
3513 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3514 {
3515 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3516 }
3517
3518 #if defined(RCC_PLLCFGR_PLLR)
3519 /**
3520 * @brief Get Main PLL division factor for PLLR
3521 * @note used for PLLCLK (system clock)
3522 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3523 * @retval Returned value can be one of the following values:
3524 * @arg @ref LL_RCC_PLLR_DIV_2
3525 * @arg @ref LL_RCC_PLLR_DIV_3
3526 * @arg @ref LL_RCC_PLLR_DIV_4
3527 * @arg @ref LL_RCC_PLLR_DIV_5
3528 * @arg @ref LL_RCC_PLLR_DIV_6
3529 * @arg @ref LL_RCC_PLLR_DIV_7
3530 */
3531 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3532 {
3533 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3534 }
3535 #endif /* RCC_PLLCFGR_PLLR */
3536
3537 /**
3538 * @brief Get Division factor for the main PLL and other PLL
3539 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3540 * @retval Returned value can be one of the following values:
3541 * @arg @ref LL_RCC_PLLM_DIV_2
3542 * @arg @ref LL_RCC_PLLM_DIV_3
3543 * @arg @ref LL_RCC_PLLM_DIV_4
3544 * @arg @ref LL_RCC_PLLM_DIV_5
3545 * @arg @ref LL_RCC_PLLM_DIV_6
3546 * @arg @ref LL_RCC_PLLM_DIV_7
3547 * @arg @ref LL_RCC_PLLM_DIV_8
3548 * @arg @ref LL_RCC_PLLM_DIV_9
3549 * @arg @ref LL_RCC_PLLM_DIV_10
3550 * @arg @ref LL_RCC_PLLM_DIV_11
3551 * @arg @ref LL_RCC_PLLM_DIV_12
3552 * @arg @ref LL_RCC_PLLM_DIV_13
3553 * @arg @ref LL_RCC_PLLM_DIV_14
3554 * @arg @ref LL_RCC_PLLM_DIV_15
3555 * @arg @ref LL_RCC_PLLM_DIV_16
3556 * @arg @ref LL_RCC_PLLM_DIV_17
3557 * @arg @ref LL_RCC_PLLM_DIV_18
3558 * @arg @ref LL_RCC_PLLM_DIV_19
3559 * @arg @ref LL_RCC_PLLM_DIV_20
3560 * @arg @ref LL_RCC_PLLM_DIV_21
3561 * @arg @ref LL_RCC_PLLM_DIV_22
3562 * @arg @ref LL_RCC_PLLM_DIV_23
3563 * @arg @ref LL_RCC_PLLM_DIV_24
3564 * @arg @ref LL_RCC_PLLM_DIV_25
3565 * @arg @ref LL_RCC_PLLM_DIV_26
3566 * @arg @ref LL_RCC_PLLM_DIV_27
3567 * @arg @ref LL_RCC_PLLM_DIV_28
3568 * @arg @ref LL_RCC_PLLM_DIV_29
3569 * @arg @ref LL_RCC_PLLM_DIV_30
3570 * @arg @ref LL_RCC_PLLM_DIV_31
3571 * @arg @ref LL_RCC_PLLM_DIV_32
3572 * @arg @ref LL_RCC_PLLM_DIV_33
3573 * @arg @ref LL_RCC_PLLM_DIV_34
3574 * @arg @ref LL_RCC_PLLM_DIV_35
3575 * @arg @ref LL_RCC_PLLM_DIV_36
3576 * @arg @ref LL_RCC_PLLM_DIV_37
3577 * @arg @ref LL_RCC_PLLM_DIV_38
3578 * @arg @ref LL_RCC_PLLM_DIV_39
3579 * @arg @ref LL_RCC_PLLM_DIV_40
3580 * @arg @ref LL_RCC_PLLM_DIV_41
3581 * @arg @ref LL_RCC_PLLM_DIV_42
3582 * @arg @ref LL_RCC_PLLM_DIV_43
3583 * @arg @ref LL_RCC_PLLM_DIV_44
3584 * @arg @ref LL_RCC_PLLM_DIV_45
3585 * @arg @ref LL_RCC_PLLM_DIV_46
3586 * @arg @ref LL_RCC_PLLM_DIV_47
3587 * @arg @ref LL_RCC_PLLM_DIV_48
3588 * @arg @ref LL_RCC_PLLM_DIV_49
3589 * @arg @ref LL_RCC_PLLM_DIV_50
3590 * @arg @ref LL_RCC_PLLM_DIV_51
3591 * @arg @ref LL_RCC_PLLM_DIV_52
3592 * @arg @ref LL_RCC_PLLM_DIV_53
3593 * @arg @ref LL_RCC_PLLM_DIV_54
3594 * @arg @ref LL_RCC_PLLM_DIV_55
3595 * @arg @ref LL_RCC_PLLM_DIV_56
3596 * @arg @ref LL_RCC_PLLM_DIV_57
3597 * @arg @ref LL_RCC_PLLM_DIV_58
3598 * @arg @ref LL_RCC_PLLM_DIV_59
3599 * @arg @ref LL_RCC_PLLM_DIV_60
3600 * @arg @ref LL_RCC_PLLM_DIV_61
3601 * @arg @ref LL_RCC_PLLM_DIV_62
3602 * @arg @ref LL_RCC_PLLM_DIV_63
3603 */
3604 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3605 {
3606 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3607 }
3608
3609 /**
3610 * @brief Configure Spread Spectrum used for PLL
3611 * @note These bits must be written before enabling PLL
3612 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
3613 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
3614 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
3615 * @param Mod Between Min_Data=0 and Max_Data=8191
3616 * @param Inc Between Min_Data=0 and Max_Data=32767
3617 * @param Sel This parameter can be one of the following values:
3618 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3619 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3620 * @retval None
3621 */
3622 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
3623 {
3624 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
3625 }
3626
3627 /**
3628 * @brief Get Spread Spectrum Modulation Period for PLL
3629 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
3630 * @retval Between Min_Data=0 and Max_Data=8191
3631 */
3632 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
3633 {
3634 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
3635 }
3636
3637 /**
3638 * @brief Get Spread Spectrum Incrementation Step for PLL
3639 * @note Must be written before enabling PLL
3640 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
3641 * @retval Between Min_Data=0 and Max_Data=32767
3642 */
3643 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
3644 {
3645 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
3646 }
3647
3648 /**
3649 * @brief Get Spread Spectrum Selection for PLL
3650 * @note Must be written before enabling PLL
3651 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
3652 * @retval Returned value can be one of the following values:
3653 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3654 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3655 */
3656 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
3657 {
3658 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
3659 }
3660
3661 /**
3662 * @brief Enable Spread Spectrum for PLL.
3663 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
3664 * @retval None
3665 */
3666 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
3667 {
3668 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3669 }
3670
3671 /**
3672 * @brief Disable Spread Spectrum for PLL.
3673 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
3674 * @retval None
3675 */
3676 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
3677 {
3678 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3679 }
3680
3681 /**
3682 * @}
3683 */
3684
3685 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
3686 * @{
3687 */
3688
3689 /**
3690 * @brief Enable PLLI2S
3691 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
3692 * @retval None
3693 */
3694 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
3695 {
3696 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
3697 }
3698
3699 /**
3700 * @brief Disable PLLI2S
3701 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
3702 * @retval None
3703 */
3704 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
3705 {
3706 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
3707 }
3708
3709 /**
3710 * @brief Check if PLLI2S Ready
3711 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
3712 * @retval State of bit (1 or 0).
3713 */
3714 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
3715 {
3716 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
3717 }
3718
3719 /**
3720 * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock
3721 * @note PLL Source and PLLM Divider can be written only when PLL,
3722 * PLLI2S and PLLSAI are disabled
3723 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
3724 * @note This can be selected for SAI1 and SAI2
3725 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
3726 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
3727 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
3728 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
3729 * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
3730 * @param Source This parameter can be one of the following values:
3731 * @arg @ref LL_RCC_PLLSOURCE_HSI
3732 * @arg @ref LL_RCC_PLLSOURCE_HSE
3733 * @param PLLM This parameter can be one of the following values:
3734 * @arg @ref LL_RCC_PLLM_DIV_2
3735 * @arg @ref LL_RCC_PLLM_DIV_3
3736 * @arg @ref LL_RCC_PLLM_DIV_4
3737 * @arg @ref LL_RCC_PLLM_DIV_5
3738 * @arg @ref LL_RCC_PLLM_DIV_6
3739 * @arg @ref LL_RCC_PLLM_DIV_7
3740 * @arg @ref LL_RCC_PLLM_DIV_8
3741 * @arg @ref LL_RCC_PLLM_DIV_9
3742 * @arg @ref LL_RCC_PLLM_DIV_10
3743 * @arg @ref LL_RCC_PLLM_DIV_11
3744 * @arg @ref LL_RCC_PLLM_DIV_12
3745 * @arg @ref LL_RCC_PLLM_DIV_13
3746 * @arg @ref LL_RCC_PLLM_DIV_14
3747 * @arg @ref LL_RCC_PLLM_DIV_15
3748 * @arg @ref LL_RCC_PLLM_DIV_16
3749 * @arg @ref LL_RCC_PLLM_DIV_17
3750 * @arg @ref LL_RCC_PLLM_DIV_18
3751 * @arg @ref LL_RCC_PLLM_DIV_19
3752 * @arg @ref LL_RCC_PLLM_DIV_20
3753 * @arg @ref LL_RCC_PLLM_DIV_21
3754 * @arg @ref LL_RCC_PLLM_DIV_22
3755 * @arg @ref LL_RCC_PLLM_DIV_23
3756 * @arg @ref LL_RCC_PLLM_DIV_24
3757 * @arg @ref LL_RCC_PLLM_DIV_25
3758 * @arg @ref LL_RCC_PLLM_DIV_26
3759 * @arg @ref LL_RCC_PLLM_DIV_27
3760 * @arg @ref LL_RCC_PLLM_DIV_28
3761 * @arg @ref LL_RCC_PLLM_DIV_29
3762 * @arg @ref LL_RCC_PLLM_DIV_30
3763 * @arg @ref LL_RCC_PLLM_DIV_31
3764 * @arg @ref LL_RCC_PLLM_DIV_32
3765 * @arg @ref LL_RCC_PLLM_DIV_33
3766 * @arg @ref LL_RCC_PLLM_DIV_34
3767 * @arg @ref LL_RCC_PLLM_DIV_35
3768 * @arg @ref LL_RCC_PLLM_DIV_36
3769 * @arg @ref LL_RCC_PLLM_DIV_37
3770 * @arg @ref LL_RCC_PLLM_DIV_38
3771 * @arg @ref LL_RCC_PLLM_DIV_39
3772 * @arg @ref LL_RCC_PLLM_DIV_40
3773 * @arg @ref LL_RCC_PLLM_DIV_41
3774 * @arg @ref LL_RCC_PLLM_DIV_42
3775 * @arg @ref LL_RCC_PLLM_DIV_43
3776 * @arg @ref LL_RCC_PLLM_DIV_44
3777 * @arg @ref LL_RCC_PLLM_DIV_45
3778 * @arg @ref LL_RCC_PLLM_DIV_46
3779 * @arg @ref LL_RCC_PLLM_DIV_47
3780 * @arg @ref LL_RCC_PLLM_DIV_48
3781 * @arg @ref LL_RCC_PLLM_DIV_49
3782 * @arg @ref LL_RCC_PLLM_DIV_50
3783 * @arg @ref LL_RCC_PLLM_DIV_51
3784 * @arg @ref LL_RCC_PLLM_DIV_52
3785 * @arg @ref LL_RCC_PLLM_DIV_53
3786 * @arg @ref LL_RCC_PLLM_DIV_54
3787 * @arg @ref LL_RCC_PLLM_DIV_55
3788 * @arg @ref LL_RCC_PLLM_DIV_56
3789 * @arg @ref LL_RCC_PLLM_DIV_57
3790 * @arg @ref LL_RCC_PLLM_DIV_58
3791 * @arg @ref LL_RCC_PLLM_DIV_59
3792 * @arg @ref LL_RCC_PLLM_DIV_60
3793 * @arg @ref LL_RCC_PLLM_DIV_61
3794 * @arg @ref LL_RCC_PLLM_DIV_62
3795 * @arg @ref LL_RCC_PLLM_DIV_63
3796 * @param PLLN Between 50 and 432
3797 * @param PLLQ This parameter can be one of the following values:
3798 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
3799 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
3800 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
3801 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
3802 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
3803 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
3804 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
3805 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
3806 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
3807 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
3808 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
3809 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
3810 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
3811 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
3812 * @param PLLDIVQ This parameter can be one of the following values:
3813 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
3814 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
3815 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
3816 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
3817 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
3818 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
3819 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
3820 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
3821 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
3822 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
3823 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
3824 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
3825 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
3826 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
3827 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
3828 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
3829 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
3830 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
3831 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
3832 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
3833 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
3834 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
3835 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
3836 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
3837 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
3838 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
3839 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
3840 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
3841 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
3842 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
3843 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
3844 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
3845 * @retval None
3846 */
3847 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
3848 {
3849 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3850 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
3851 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
3852 }
3853
3854 #if defined(SPDIFRX)
3855 /**
3856 * @brief Configure PLLI2S used for SPDIFRX domain clock
3857 * @note PLL Source and PLLM Divider can be written only when PLL,
3858 * PLLI2S and PLLSAI are disabled
3859 * @note PLLN/PLLP can be written only when PLLI2S is disabled
3860 * @note This can be selected for SPDIFRX
3861 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3862 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3863 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3864 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
3865 * @param Source This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_PLLSOURCE_HSI
3867 * @arg @ref LL_RCC_PLLSOURCE_HSE
3868 * @param PLLM This parameter can be one of the following values:
3869 * @arg @ref LL_RCC_PLLM_DIV_2
3870 * @arg @ref LL_RCC_PLLM_DIV_3
3871 * @arg @ref LL_RCC_PLLM_DIV_4
3872 * @arg @ref LL_RCC_PLLM_DIV_5
3873 * @arg @ref LL_RCC_PLLM_DIV_6
3874 * @arg @ref LL_RCC_PLLM_DIV_7
3875 * @arg @ref LL_RCC_PLLM_DIV_8
3876 * @arg @ref LL_RCC_PLLM_DIV_9
3877 * @arg @ref LL_RCC_PLLM_DIV_10
3878 * @arg @ref LL_RCC_PLLM_DIV_11
3879 * @arg @ref LL_RCC_PLLM_DIV_12
3880 * @arg @ref LL_RCC_PLLM_DIV_13
3881 * @arg @ref LL_RCC_PLLM_DIV_14
3882 * @arg @ref LL_RCC_PLLM_DIV_15
3883 * @arg @ref LL_RCC_PLLM_DIV_16
3884 * @arg @ref LL_RCC_PLLM_DIV_17
3885 * @arg @ref LL_RCC_PLLM_DIV_18
3886 * @arg @ref LL_RCC_PLLM_DIV_19
3887 * @arg @ref LL_RCC_PLLM_DIV_20
3888 * @arg @ref LL_RCC_PLLM_DIV_21
3889 * @arg @ref LL_RCC_PLLM_DIV_22
3890 * @arg @ref LL_RCC_PLLM_DIV_23
3891 * @arg @ref LL_RCC_PLLM_DIV_24
3892 * @arg @ref LL_RCC_PLLM_DIV_25
3893 * @arg @ref LL_RCC_PLLM_DIV_26
3894 * @arg @ref LL_RCC_PLLM_DIV_27
3895 * @arg @ref LL_RCC_PLLM_DIV_28
3896 * @arg @ref LL_RCC_PLLM_DIV_29
3897 * @arg @ref LL_RCC_PLLM_DIV_30
3898 * @arg @ref LL_RCC_PLLM_DIV_31
3899 * @arg @ref LL_RCC_PLLM_DIV_32
3900 * @arg @ref LL_RCC_PLLM_DIV_33
3901 * @arg @ref LL_RCC_PLLM_DIV_34
3902 * @arg @ref LL_RCC_PLLM_DIV_35
3903 * @arg @ref LL_RCC_PLLM_DIV_36
3904 * @arg @ref LL_RCC_PLLM_DIV_37
3905 * @arg @ref LL_RCC_PLLM_DIV_38
3906 * @arg @ref LL_RCC_PLLM_DIV_39
3907 * @arg @ref LL_RCC_PLLM_DIV_40
3908 * @arg @ref LL_RCC_PLLM_DIV_41
3909 * @arg @ref LL_RCC_PLLM_DIV_42
3910 * @arg @ref LL_RCC_PLLM_DIV_43
3911 * @arg @ref LL_RCC_PLLM_DIV_44
3912 * @arg @ref LL_RCC_PLLM_DIV_45
3913 * @arg @ref LL_RCC_PLLM_DIV_46
3914 * @arg @ref LL_RCC_PLLM_DIV_47
3915 * @arg @ref LL_RCC_PLLM_DIV_48
3916 * @arg @ref LL_RCC_PLLM_DIV_49
3917 * @arg @ref LL_RCC_PLLM_DIV_50
3918 * @arg @ref LL_RCC_PLLM_DIV_51
3919 * @arg @ref LL_RCC_PLLM_DIV_52
3920 * @arg @ref LL_RCC_PLLM_DIV_53
3921 * @arg @ref LL_RCC_PLLM_DIV_54
3922 * @arg @ref LL_RCC_PLLM_DIV_55
3923 * @arg @ref LL_RCC_PLLM_DIV_56
3924 * @arg @ref LL_RCC_PLLM_DIV_57
3925 * @arg @ref LL_RCC_PLLM_DIV_58
3926 * @arg @ref LL_RCC_PLLM_DIV_59
3927 * @arg @ref LL_RCC_PLLM_DIV_60
3928 * @arg @ref LL_RCC_PLLM_DIV_61
3929 * @arg @ref LL_RCC_PLLM_DIV_62
3930 * @arg @ref LL_RCC_PLLM_DIV_63
3931 * @param PLLN Between 50 and 432
3932 * @param PLLP This parameter can be one of the following values:
3933 * @arg @ref LL_RCC_PLLI2SP_DIV_2
3934 * @arg @ref LL_RCC_PLLI2SP_DIV_4
3935 * @arg @ref LL_RCC_PLLI2SP_DIV_6
3936 * @arg @ref LL_RCC_PLLI2SP_DIV_8
3937 * @retval None
3938 */
3939 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3940 {
3941 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3942 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
3943 }
3944 #endif /* SPDIFRX */
3945
3946 /**
3947 * @brief Configure PLLI2S used for I2S1 domain clock
3948 * @note PLL Source and PLLM Divider can be written only when PLL,
3949 * PLLI2S and PLLSAI are disabled
3950 * @note PLLN/PLLR can be written only when PLLI2S is disabled
3951 * @note This can be selected for I2S
3952 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
3953 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
3954 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
3955 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
3956 * @param Source This parameter can be one of the following values:
3957 * @arg @ref LL_RCC_PLLSOURCE_HSI
3958 * @arg @ref LL_RCC_PLLSOURCE_HSE
3959 * @param PLLM This parameter can be one of the following values:
3960 * @arg @ref LL_RCC_PLLM_DIV_2
3961 * @arg @ref LL_RCC_PLLM_DIV_3
3962 * @arg @ref LL_RCC_PLLM_DIV_4
3963 * @arg @ref LL_RCC_PLLM_DIV_5
3964 * @arg @ref LL_RCC_PLLM_DIV_6
3965 * @arg @ref LL_RCC_PLLM_DIV_7
3966 * @arg @ref LL_RCC_PLLM_DIV_8
3967 * @arg @ref LL_RCC_PLLM_DIV_9
3968 * @arg @ref LL_RCC_PLLM_DIV_10
3969 * @arg @ref LL_RCC_PLLM_DIV_11
3970 * @arg @ref LL_RCC_PLLM_DIV_12
3971 * @arg @ref LL_RCC_PLLM_DIV_13
3972 * @arg @ref LL_RCC_PLLM_DIV_14
3973 * @arg @ref LL_RCC_PLLM_DIV_15
3974 * @arg @ref LL_RCC_PLLM_DIV_16
3975 * @arg @ref LL_RCC_PLLM_DIV_17
3976 * @arg @ref LL_RCC_PLLM_DIV_18
3977 * @arg @ref LL_RCC_PLLM_DIV_19
3978 * @arg @ref LL_RCC_PLLM_DIV_20
3979 * @arg @ref LL_RCC_PLLM_DIV_21
3980 * @arg @ref LL_RCC_PLLM_DIV_22
3981 * @arg @ref LL_RCC_PLLM_DIV_23
3982 * @arg @ref LL_RCC_PLLM_DIV_24
3983 * @arg @ref LL_RCC_PLLM_DIV_25
3984 * @arg @ref LL_RCC_PLLM_DIV_26
3985 * @arg @ref LL_RCC_PLLM_DIV_27
3986 * @arg @ref LL_RCC_PLLM_DIV_28
3987 * @arg @ref LL_RCC_PLLM_DIV_29
3988 * @arg @ref LL_RCC_PLLM_DIV_30
3989 * @arg @ref LL_RCC_PLLM_DIV_31
3990 * @arg @ref LL_RCC_PLLM_DIV_32
3991 * @arg @ref LL_RCC_PLLM_DIV_33
3992 * @arg @ref LL_RCC_PLLM_DIV_34
3993 * @arg @ref LL_RCC_PLLM_DIV_35
3994 * @arg @ref LL_RCC_PLLM_DIV_36
3995 * @arg @ref LL_RCC_PLLM_DIV_37
3996 * @arg @ref LL_RCC_PLLM_DIV_38
3997 * @arg @ref LL_RCC_PLLM_DIV_39
3998 * @arg @ref LL_RCC_PLLM_DIV_40
3999 * @arg @ref LL_RCC_PLLM_DIV_41
4000 * @arg @ref LL_RCC_PLLM_DIV_42
4001 * @arg @ref LL_RCC_PLLM_DIV_43
4002 * @arg @ref LL_RCC_PLLM_DIV_44
4003 * @arg @ref LL_RCC_PLLM_DIV_45
4004 * @arg @ref LL_RCC_PLLM_DIV_46
4005 * @arg @ref LL_RCC_PLLM_DIV_47
4006 * @arg @ref LL_RCC_PLLM_DIV_48
4007 * @arg @ref LL_RCC_PLLM_DIV_49
4008 * @arg @ref LL_RCC_PLLM_DIV_50
4009 * @arg @ref LL_RCC_PLLM_DIV_51
4010 * @arg @ref LL_RCC_PLLM_DIV_52
4011 * @arg @ref LL_RCC_PLLM_DIV_53
4012 * @arg @ref LL_RCC_PLLM_DIV_54
4013 * @arg @ref LL_RCC_PLLM_DIV_55
4014 * @arg @ref LL_RCC_PLLM_DIV_56
4015 * @arg @ref LL_RCC_PLLM_DIV_57
4016 * @arg @ref LL_RCC_PLLM_DIV_58
4017 * @arg @ref LL_RCC_PLLM_DIV_59
4018 * @arg @ref LL_RCC_PLLM_DIV_60
4019 * @arg @ref LL_RCC_PLLM_DIV_61
4020 * @arg @ref LL_RCC_PLLM_DIV_62
4021 * @arg @ref LL_RCC_PLLM_DIV_63
4022 * @param PLLN Between 50 and 432
4023 * @param PLLR This parameter can be one of the following values:
4024 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4025 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4026 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4027 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4028 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4029 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4030 * @retval None
4031 */
4032 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4033 {
4034 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4035 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
4036 }
4037
4038 /**
4039 * @brief Get I2SPLL multiplication factor for VCO
4040 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
4041 * @retval Between 50 and 432
4042 */
4043 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
4044 {
4045 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
4046 }
4047
4048 /**
4049 * @brief Get I2SPLL division factor for PLLI2SQ
4050 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
4051 * @retval Returned value can be one of the following values:
4052 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
4053 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
4054 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
4055 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
4056 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
4057 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
4058 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
4059 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
4060 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
4061 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
4062 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
4063 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
4064 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
4065 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
4066 */
4067 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
4068 {
4069 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
4070 }
4071
4072 /**
4073 * @brief Get I2SPLL division factor for PLLI2SR
4074 * @note used for PLLI2SCLK (I2S clock)
4075 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
4076 * @retval Returned value can be one of the following values:
4077 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4078 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4079 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4080 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4081 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4082 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4083 */
4084 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
4085 {
4086 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
4087 }
4088
4089 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
4090 /**
4091 * @brief Get I2SPLL division factor for PLLI2SP
4092 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
4093 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
4094 * @retval Returned value can be one of the following values:
4095 * @arg @ref LL_RCC_PLLI2SP_DIV_2
4096 * @arg @ref LL_RCC_PLLI2SP_DIV_4
4097 * @arg @ref LL_RCC_PLLI2SP_DIV_6
4098 * @arg @ref LL_RCC_PLLI2SP_DIV_8
4099 */
4100 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
4101 {
4102 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
4103 }
4104 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
4105
4106 /**
4107 * @brief Get I2SPLL division factor for PLLI2SDIVQ
4108 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4109 * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
4110 * @retval Returned value can be one of the following values:
4111 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
4112 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
4113 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
4114 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
4115 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
4116 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
4117 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
4118 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
4119 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
4120 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
4121 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
4122 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
4123 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
4124 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
4125 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
4126 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
4127 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
4128 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
4129 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
4130 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
4131 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
4132 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
4133 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
4134 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
4135 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
4136 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
4137 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
4138 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
4139 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
4140 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
4141 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
4142 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
4143 */
4144 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
4145 {
4146 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
4147 }
4148
4149 /**
4150 * @}
4151 */
4152
4153 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
4154 * @{
4155 */
4156
4157 /**
4158 * @brief Enable PLLSAI
4159 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
4160 * @retval None
4161 */
4162 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
4163 {
4164 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
4165 }
4166
4167 /**
4168 * @brief Disable PLLSAI
4169 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
4170 * @retval None
4171 */
4172 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
4173 {
4174 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
4175 }
4176
4177 /**
4178 * @brief Check if PLLSAI Ready
4179 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
4180 * @retval State of bit (1 or 0).
4181 */
4182 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
4183 {
4184 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
4185 }
4186
4187 /**
4188 * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock
4189 * @note PLL Source and PLLM Divider can be written only when PLL,
4190 * PLLI2S and PLLSAI are disabled
4191 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
4192 * @note This can be selected for SAI1 and SAI2
4193 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
4194 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
4195 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
4196 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
4197 * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
4198 * @param Source This parameter can be one of the following values:
4199 * @arg @ref LL_RCC_PLLSOURCE_HSI
4200 * @arg @ref LL_RCC_PLLSOURCE_HSE
4201 * @param PLLM This parameter can be one of the following values:
4202 * @arg @ref LL_RCC_PLLM_DIV_2
4203 * @arg @ref LL_RCC_PLLM_DIV_3
4204 * @arg @ref LL_RCC_PLLM_DIV_4
4205 * @arg @ref LL_RCC_PLLM_DIV_5
4206 * @arg @ref LL_RCC_PLLM_DIV_6
4207 * @arg @ref LL_RCC_PLLM_DIV_7
4208 * @arg @ref LL_RCC_PLLM_DIV_8
4209 * @arg @ref LL_RCC_PLLM_DIV_9
4210 * @arg @ref LL_RCC_PLLM_DIV_10
4211 * @arg @ref LL_RCC_PLLM_DIV_11
4212 * @arg @ref LL_RCC_PLLM_DIV_12
4213 * @arg @ref LL_RCC_PLLM_DIV_13
4214 * @arg @ref LL_RCC_PLLM_DIV_14
4215 * @arg @ref LL_RCC_PLLM_DIV_15
4216 * @arg @ref LL_RCC_PLLM_DIV_16
4217 * @arg @ref LL_RCC_PLLM_DIV_17
4218 * @arg @ref LL_RCC_PLLM_DIV_18
4219 * @arg @ref LL_RCC_PLLM_DIV_19
4220 * @arg @ref LL_RCC_PLLM_DIV_20
4221 * @arg @ref LL_RCC_PLLM_DIV_21
4222 * @arg @ref LL_RCC_PLLM_DIV_22
4223 * @arg @ref LL_RCC_PLLM_DIV_23
4224 * @arg @ref LL_RCC_PLLM_DIV_24
4225 * @arg @ref LL_RCC_PLLM_DIV_25
4226 * @arg @ref LL_RCC_PLLM_DIV_26
4227 * @arg @ref LL_RCC_PLLM_DIV_27
4228 * @arg @ref LL_RCC_PLLM_DIV_28
4229 * @arg @ref LL_RCC_PLLM_DIV_29
4230 * @arg @ref LL_RCC_PLLM_DIV_30
4231 * @arg @ref LL_RCC_PLLM_DIV_31
4232 * @arg @ref LL_RCC_PLLM_DIV_32
4233 * @arg @ref LL_RCC_PLLM_DIV_33
4234 * @arg @ref LL_RCC_PLLM_DIV_34
4235 * @arg @ref LL_RCC_PLLM_DIV_35
4236 * @arg @ref LL_RCC_PLLM_DIV_36
4237 * @arg @ref LL_RCC_PLLM_DIV_37
4238 * @arg @ref LL_RCC_PLLM_DIV_38
4239 * @arg @ref LL_RCC_PLLM_DIV_39
4240 * @arg @ref LL_RCC_PLLM_DIV_40
4241 * @arg @ref LL_RCC_PLLM_DIV_41
4242 * @arg @ref LL_RCC_PLLM_DIV_42
4243 * @arg @ref LL_RCC_PLLM_DIV_43
4244 * @arg @ref LL_RCC_PLLM_DIV_44
4245 * @arg @ref LL_RCC_PLLM_DIV_45
4246 * @arg @ref LL_RCC_PLLM_DIV_46
4247 * @arg @ref LL_RCC_PLLM_DIV_47
4248 * @arg @ref LL_RCC_PLLM_DIV_48
4249 * @arg @ref LL_RCC_PLLM_DIV_49
4250 * @arg @ref LL_RCC_PLLM_DIV_50
4251 * @arg @ref LL_RCC_PLLM_DIV_51
4252 * @arg @ref LL_RCC_PLLM_DIV_52
4253 * @arg @ref LL_RCC_PLLM_DIV_53
4254 * @arg @ref LL_RCC_PLLM_DIV_54
4255 * @arg @ref LL_RCC_PLLM_DIV_55
4256 * @arg @ref LL_RCC_PLLM_DIV_56
4257 * @arg @ref LL_RCC_PLLM_DIV_57
4258 * @arg @ref LL_RCC_PLLM_DIV_58
4259 * @arg @ref LL_RCC_PLLM_DIV_59
4260 * @arg @ref LL_RCC_PLLM_DIV_60
4261 * @arg @ref LL_RCC_PLLM_DIV_61
4262 * @arg @ref LL_RCC_PLLM_DIV_62
4263 * @arg @ref LL_RCC_PLLM_DIV_63
4264 * @param PLLN Between 50 and 432
4265 * @param PLLQ This parameter can be one of the following values:
4266 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4267 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4268 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4269 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4270 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4271 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4272 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4273 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4274 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4275 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4276 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4277 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4278 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4279 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4280 * @param PLLDIVQ This parameter can be one of the following values:
4281 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4282 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4283 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4284 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4285 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4286 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4287 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4288 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4289 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4290 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4291 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4292 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4293 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4294 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4295 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4296 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4297 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4298 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4299 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4300 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4301 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4302 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4303 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4304 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4305 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4306 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4307 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4308 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4309 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4310 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4311 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4312 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4313 * @retval None
4314 */
4315 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
4316 {
4317 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4318 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
4319 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
4320 }
4321
4322 /**
4323 * @brief Configure PLLSAI used for 48Mhz domain clock
4324 * @note PLL Source and PLLM Divider can be written only when PLL,
4325 * PLLI2S and PLLSAI are disabled
4326 * @note PLLN/PLLP can be written only when PLLSAI is disabled
4327 * @note This can be selected for USB, RNG, SDMMC1
4328 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
4329 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
4330 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
4331 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
4332 * @param Source This parameter can be one of the following values:
4333 * @arg @ref LL_RCC_PLLSOURCE_HSI
4334 * @arg @ref LL_RCC_PLLSOURCE_HSE
4335 * @param PLLM This parameter can be one of the following values:
4336 * @arg @ref LL_RCC_PLLM_DIV_2
4337 * @arg @ref LL_RCC_PLLM_DIV_3
4338 * @arg @ref LL_RCC_PLLM_DIV_4
4339 * @arg @ref LL_RCC_PLLM_DIV_5
4340 * @arg @ref LL_RCC_PLLM_DIV_6
4341 * @arg @ref LL_RCC_PLLM_DIV_7
4342 * @arg @ref LL_RCC_PLLM_DIV_8
4343 * @arg @ref LL_RCC_PLLM_DIV_9
4344 * @arg @ref LL_RCC_PLLM_DIV_10
4345 * @arg @ref LL_RCC_PLLM_DIV_11
4346 * @arg @ref LL_RCC_PLLM_DIV_12
4347 * @arg @ref LL_RCC_PLLM_DIV_13
4348 * @arg @ref LL_RCC_PLLM_DIV_14
4349 * @arg @ref LL_RCC_PLLM_DIV_15
4350 * @arg @ref LL_RCC_PLLM_DIV_16
4351 * @arg @ref LL_RCC_PLLM_DIV_17
4352 * @arg @ref LL_RCC_PLLM_DIV_18
4353 * @arg @ref LL_RCC_PLLM_DIV_19
4354 * @arg @ref LL_RCC_PLLM_DIV_20
4355 * @arg @ref LL_RCC_PLLM_DIV_21
4356 * @arg @ref LL_RCC_PLLM_DIV_22
4357 * @arg @ref LL_RCC_PLLM_DIV_23
4358 * @arg @ref LL_RCC_PLLM_DIV_24
4359 * @arg @ref LL_RCC_PLLM_DIV_25
4360 * @arg @ref LL_RCC_PLLM_DIV_26
4361 * @arg @ref LL_RCC_PLLM_DIV_27
4362 * @arg @ref LL_RCC_PLLM_DIV_28
4363 * @arg @ref LL_RCC_PLLM_DIV_29
4364 * @arg @ref LL_RCC_PLLM_DIV_30
4365 * @arg @ref LL_RCC_PLLM_DIV_31
4366 * @arg @ref LL_RCC_PLLM_DIV_32
4367 * @arg @ref LL_RCC_PLLM_DIV_33
4368 * @arg @ref LL_RCC_PLLM_DIV_34
4369 * @arg @ref LL_RCC_PLLM_DIV_35
4370 * @arg @ref LL_RCC_PLLM_DIV_36
4371 * @arg @ref LL_RCC_PLLM_DIV_37
4372 * @arg @ref LL_RCC_PLLM_DIV_38
4373 * @arg @ref LL_RCC_PLLM_DIV_39
4374 * @arg @ref LL_RCC_PLLM_DIV_40
4375 * @arg @ref LL_RCC_PLLM_DIV_41
4376 * @arg @ref LL_RCC_PLLM_DIV_42
4377 * @arg @ref LL_RCC_PLLM_DIV_43
4378 * @arg @ref LL_RCC_PLLM_DIV_44
4379 * @arg @ref LL_RCC_PLLM_DIV_45
4380 * @arg @ref LL_RCC_PLLM_DIV_46
4381 * @arg @ref LL_RCC_PLLM_DIV_47
4382 * @arg @ref LL_RCC_PLLM_DIV_48
4383 * @arg @ref LL_RCC_PLLM_DIV_49
4384 * @arg @ref LL_RCC_PLLM_DIV_50
4385 * @arg @ref LL_RCC_PLLM_DIV_51
4386 * @arg @ref LL_RCC_PLLM_DIV_52
4387 * @arg @ref LL_RCC_PLLM_DIV_53
4388 * @arg @ref LL_RCC_PLLM_DIV_54
4389 * @arg @ref LL_RCC_PLLM_DIV_55
4390 * @arg @ref LL_RCC_PLLM_DIV_56
4391 * @arg @ref LL_RCC_PLLM_DIV_57
4392 * @arg @ref LL_RCC_PLLM_DIV_58
4393 * @arg @ref LL_RCC_PLLM_DIV_59
4394 * @arg @ref LL_RCC_PLLM_DIV_60
4395 * @arg @ref LL_RCC_PLLM_DIV_61
4396 * @arg @ref LL_RCC_PLLM_DIV_62
4397 * @arg @ref LL_RCC_PLLM_DIV_63
4398 * @param PLLN Between 50 and 432
4399 * @param PLLP This parameter can be one of the following values:
4400 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4401 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4402 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4403 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4404 * @retval None
4405 */
4406 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4407 {
4408 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4409 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
4410 }
4411
4412 #if defined(LTDC)
4413 /**
4414 * @brief Configure PLLSAI used for LTDC domain clock
4415 * @note PLL Source and PLLM Divider can be written only when PLL,
4416 * PLLI2S and PLLSAI are disabled
4417 * @note PLLN/PLLR can be written only when PLLSAI is disabled
4418 * @note This can be selected for LTDC
4419 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4420 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4421 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4422 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4423 * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
4424 * @param Source This parameter can be one of the following values:
4425 * @arg @ref LL_RCC_PLLSOURCE_HSI
4426 * @arg @ref LL_RCC_PLLSOURCE_HSE
4427 * @param PLLM This parameter can be one of the following values:
4428 * @arg @ref LL_RCC_PLLM_DIV_2
4429 * @arg @ref LL_RCC_PLLM_DIV_3
4430 * @arg @ref LL_RCC_PLLM_DIV_4
4431 * @arg @ref LL_RCC_PLLM_DIV_5
4432 * @arg @ref LL_RCC_PLLM_DIV_6
4433 * @arg @ref LL_RCC_PLLM_DIV_7
4434 * @arg @ref LL_RCC_PLLM_DIV_8
4435 * @arg @ref LL_RCC_PLLM_DIV_9
4436 * @arg @ref LL_RCC_PLLM_DIV_10
4437 * @arg @ref LL_RCC_PLLM_DIV_11
4438 * @arg @ref LL_RCC_PLLM_DIV_12
4439 * @arg @ref LL_RCC_PLLM_DIV_13
4440 * @arg @ref LL_RCC_PLLM_DIV_14
4441 * @arg @ref LL_RCC_PLLM_DIV_15
4442 * @arg @ref LL_RCC_PLLM_DIV_16
4443 * @arg @ref LL_RCC_PLLM_DIV_17
4444 * @arg @ref LL_RCC_PLLM_DIV_18
4445 * @arg @ref LL_RCC_PLLM_DIV_19
4446 * @arg @ref LL_RCC_PLLM_DIV_20
4447 * @arg @ref LL_RCC_PLLM_DIV_21
4448 * @arg @ref LL_RCC_PLLM_DIV_22
4449 * @arg @ref LL_RCC_PLLM_DIV_23
4450 * @arg @ref LL_RCC_PLLM_DIV_24
4451 * @arg @ref LL_RCC_PLLM_DIV_25
4452 * @arg @ref LL_RCC_PLLM_DIV_26
4453 * @arg @ref LL_RCC_PLLM_DIV_27
4454 * @arg @ref LL_RCC_PLLM_DIV_28
4455 * @arg @ref LL_RCC_PLLM_DIV_29
4456 * @arg @ref LL_RCC_PLLM_DIV_30
4457 * @arg @ref LL_RCC_PLLM_DIV_31
4458 * @arg @ref LL_RCC_PLLM_DIV_32
4459 * @arg @ref LL_RCC_PLLM_DIV_33
4460 * @arg @ref LL_RCC_PLLM_DIV_34
4461 * @arg @ref LL_RCC_PLLM_DIV_35
4462 * @arg @ref LL_RCC_PLLM_DIV_36
4463 * @arg @ref LL_RCC_PLLM_DIV_37
4464 * @arg @ref LL_RCC_PLLM_DIV_38
4465 * @arg @ref LL_RCC_PLLM_DIV_39
4466 * @arg @ref LL_RCC_PLLM_DIV_40
4467 * @arg @ref LL_RCC_PLLM_DIV_41
4468 * @arg @ref LL_RCC_PLLM_DIV_42
4469 * @arg @ref LL_RCC_PLLM_DIV_43
4470 * @arg @ref LL_RCC_PLLM_DIV_44
4471 * @arg @ref LL_RCC_PLLM_DIV_45
4472 * @arg @ref LL_RCC_PLLM_DIV_46
4473 * @arg @ref LL_RCC_PLLM_DIV_47
4474 * @arg @ref LL_RCC_PLLM_DIV_48
4475 * @arg @ref LL_RCC_PLLM_DIV_49
4476 * @arg @ref LL_RCC_PLLM_DIV_50
4477 * @arg @ref LL_RCC_PLLM_DIV_51
4478 * @arg @ref LL_RCC_PLLM_DIV_52
4479 * @arg @ref LL_RCC_PLLM_DIV_53
4480 * @arg @ref LL_RCC_PLLM_DIV_54
4481 * @arg @ref LL_RCC_PLLM_DIV_55
4482 * @arg @ref LL_RCC_PLLM_DIV_56
4483 * @arg @ref LL_RCC_PLLM_DIV_57
4484 * @arg @ref LL_RCC_PLLM_DIV_58
4485 * @arg @ref LL_RCC_PLLM_DIV_59
4486 * @arg @ref LL_RCC_PLLM_DIV_60
4487 * @arg @ref LL_RCC_PLLM_DIV_61
4488 * @arg @ref LL_RCC_PLLM_DIV_62
4489 * @arg @ref LL_RCC_PLLM_DIV_63
4490 * @param PLLN Between 50 and 432
4491 * @param PLLR This parameter can be one of the following values:
4492 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4493 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4494 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4495 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4496 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4497 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4498 * @param PLLDIVR This parameter can be one of the following values:
4499 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4500 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4501 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4502 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4503 * @retval None
4504 */
4505 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4506 {
4507 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4508 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
4509 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
4510 }
4511 #endif /* LTDC */
4512
4513 /**
4514 * @brief Get SAIPLL multiplication factor for VCO
4515 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
4516 * @retval Between 50 and 432
4517 */
4518 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
4519 {
4520 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
4521 }
4522
4523 /**
4524 * @brief Get SAIPLL division factor for PLLSAIQ
4525 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
4526 * @retval Returned value can be one of the following values:
4527 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4528 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4529 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4530 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4531 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4532 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4533 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4534 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4535 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4536 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4537 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4538 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4539 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4540 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4541 */
4542 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
4543 {
4544 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
4545 }
4546
4547 #if defined(RCC_PLLSAICFGR_PLLSAIR)
4548 /**
4549 * @brief Get SAIPLL division factor for PLLSAIR
4550 * @note used for PLLSAICLK (SAI clock)
4551 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
4552 * @retval Returned value can be one of the following values:
4553 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4554 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4555 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4556 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4557 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4558 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4559 */
4560 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
4561 {
4562 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
4563 }
4564 #endif /* RCC_PLLSAICFGR_PLLSAIR */
4565
4566 /**
4567 * @brief Get SAIPLL division factor for PLLSAIP
4568 * @note used for PLL48MCLK (48M domain clock)
4569 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
4570 * @retval Returned value can be one of the following values:
4571 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4572 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4573 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4574 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4575 */
4576 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
4577 {
4578 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
4579 }
4580
4581 /**
4582 * @brief Get SAIPLL division factor for PLLSAIDIVQ
4583 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4584 * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
4585 * @retval Returned value can be one of the following values:
4586 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4587 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4588 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4589 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4590 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4591 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4592 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4593 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4594 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4595 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4596 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4597 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4598 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4599 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4600 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4601 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4602 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4603 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4604 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4605 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4606 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4607 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4608 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4609 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4610 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4611 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4612 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4613 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4614 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4615 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4616 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4617 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4618 */
4619 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
4620 {
4621 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
4622 }
4623
4624 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
4625 /**
4626 * @brief Get SAIPLL division factor for PLLSAIDIVR
4627 * @note used for LTDC domain clock
4628 * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
4629 * @retval Returned value can be one of the following values:
4630 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4631 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4632 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4633 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4634 */
4635 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
4636 {
4637 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
4638 }
4639 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
4640
4641 /**
4642 * @}
4643 */
4644
4645 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
4646 * @{
4647 */
4648
4649 /**
4650 * @brief Clear LSI ready interrupt flag
4651 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
4652 * @retval None
4653 */
4654 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
4655 {
4656 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
4657 }
4658
4659 /**
4660 * @brief Clear LSE ready interrupt flag
4661 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
4662 * @retval None
4663 */
4664 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
4665 {
4666 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
4667 }
4668
4669 /**
4670 * @brief Clear HSI ready interrupt flag
4671 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
4672 * @retval None
4673 */
4674 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
4675 {
4676 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
4677 }
4678
4679 /**
4680 * @brief Clear HSE ready interrupt flag
4681 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
4682 * @retval None
4683 */
4684 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
4685 {
4686 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
4687 }
4688
4689 /**
4690 * @brief Clear PLL ready interrupt flag
4691 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
4692 * @retval None
4693 */
4694 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
4695 {
4696 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
4697 }
4698
4699 /**
4700 * @brief Clear PLLI2S ready interrupt flag
4701 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
4702 * @retval None
4703 */
4704 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
4705 {
4706 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
4707 }
4708
4709 /**
4710 * @brief Clear PLLSAI ready interrupt flag
4711 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
4712 * @retval None
4713 */
4714 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
4715 {
4716 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
4717 }
4718
4719 /**
4720 * @brief Clear Clock security system interrupt flag
4721 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
4722 * @retval None
4723 */
4724 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
4725 {
4726 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
4727 }
4728
4729 /**
4730 * @brief Check if LSI ready interrupt occurred or not
4731 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
4732 * @retval State of bit (1 or 0).
4733 */
4734 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
4735 {
4736 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
4737 }
4738
4739 /**
4740 * @brief Check if LSE ready interrupt occurred or not
4741 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
4742 * @retval State of bit (1 or 0).
4743 */
4744 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
4745 {
4746 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
4747 }
4748
4749 /**
4750 * @brief Check if HSI ready interrupt occurred or not
4751 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
4752 * @retval State of bit (1 or 0).
4753 */
4754 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
4755 {
4756 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
4757 }
4758
4759 /**
4760 * @brief Check if HSE ready interrupt occurred or not
4761 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
4762 * @retval State of bit (1 or 0).
4763 */
4764 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
4765 {
4766 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
4767 }
4768
4769 /**
4770 * @brief Check if PLL ready interrupt occurred or not
4771 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
4772 * @retval State of bit (1 or 0).
4773 */
4774 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
4775 {
4776 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
4777 }
4778
4779 /**
4780 * @brief Check if PLLI2S ready interrupt occurred or not
4781 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
4782 * @retval State of bit (1 or 0).
4783 */
4784 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
4785 {
4786 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
4787 }
4788
4789 /**
4790 * @brief Check if PLLSAI ready interrupt occurred or not
4791 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
4792 * @retval State of bit (1 or 0).
4793 */
4794 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
4795 {
4796 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
4797 }
4798
4799 /**
4800 * @brief Check if Clock security system interrupt occurred or not
4801 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
4802 * @retval State of bit (1 or 0).
4803 */
4804 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
4805 {
4806 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
4807 }
4808
4809 /**
4810 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4811 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4812 * @retval State of bit (1 or 0).
4813 */
4814 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4815 {
4816 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
4817 }
4818
4819 /**
4820 * @brief Check if RCC flag Low Power reset is set or not.
4821 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4822 * @retval State of bit (1 or 0).
4823 */
4824 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4825 {
4826 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
4827 }
4828
4829 /**
4830 * @brief Check if RCC flag Pin reset is set or not.
4831 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4832 * @retval State of bit (1 or 0).
4833 */
4834 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4835 {
4836 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
4837 }
4838
4839 /**
4840 * @brief Check if RCC flag POR/PDR reset is set or not.
4841 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
4842 * @retval State of bit (1 or 0).
4843 */
4844 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
4845 {
4846 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
4847 }
4848
4849 /**
4850 * @brief Check if RCC flag Software reset is set or not.
4851 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4852 * @retval State of bit (1 or 0).
4853 */
4854 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4855 {
4856 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
4857 }
4858
4859 /**
4860 * @brief Check if RCC flag Window Watchdog reset is set or not.
4861 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4862 * @retval State of bit (1 or 0).
4863 */
4864 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4865 {
4866 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
4867 }
4868
4869 /**
4870 * @brief Check if RCC flag BOR reset is set or not.
4871 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4872 * @retval State of bit (1 or 0).
4873 */
4874 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4875 {
4876 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
4877 }
4878
4879 /**
4880 * @brief Set RMVF bit to clear the reset flags.
4881 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4882 * @retval None
4883 */
4884 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4885 {
4886 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4887 }
4888
4889 /**
4890 * @}
4891 */
4892
4893 /** @defgroup RCC_LL_EF_IT_Management IT Management
4894 * @{
4895 */
4896
4897 /**
4898 * @brief Enable LSI ready interrupt
4899 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
4900 * @retval None
4901 */
4902 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
4903 {
4904 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4905 }
4906
4907 /**
4908 * @brief Enable LSE ready interrupt
4909 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
4910 * @retval None
4911 */
4912 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4913 {
4914 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4915 }
4916
4917 /**
4918 * @brief Enable HSI ready interrupt
4919 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
4920 * @retval None
4921 */
4922 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4923 {
4924 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4925 }
4926
4927 /**
4928 * @brief Enable HSE ready interrupt
4929 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
4930 * @retval None
4931 */
4932 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4933 {
4934 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
4935 }
4936
4937 /**
4938 * @brief Enable PLL ready interrupt
4939 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
4940 * @retval None
4941 */
4942 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4943 {
4944 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
4945 }
4946
4947 /**
4948 * @brief Enable PLLI2S ready interrupt
4949 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
4950 * @retval None
4951 */
4952 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
4953 {
4954 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
4955 }
4956
4957 /**
4958 * @brief Enable PLLSAI ready interrupt
4959 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
4960 * @retval None
4961 */
4962 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
4963 {
4964 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
4965 }
4966
4967 /**
4968 * @brief Disable LSI ready interrupt
4969 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
4970 * @retval None
4971 */
4972 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
4973 {
4974 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4975 }
4976
4977 /**
4978 * @brief Disable LSE ready interrupt
4979 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
4980 * @retval None
4981 */
4982 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4983 {
4984 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4985 }
4986
4987 /**
4988 * @brief Disable HSI ready interrupt
4989 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
4990 * @retval None
4991 */
4992 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4993 {
4994 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4995 }
4996
4997 /**
4998 * @brief Disable HSE ready interrupt
4999 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
5000 * @retval None
5001 */
5002 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5003 {
5004 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
5005 }
5006
5007 /**
5008 * @brief Disable PLL ready interrupt
5009 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
5010 * @retval None
5011 */
5012 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5013 {
5014 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
5015 }
5016
5017 /**
5018 * @brief Disable PLLI2S ready interrupt
5019 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
5020 * @retval None
5021 */
5022 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
5023 {
5024 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
5025 }
5026
5027 /**
5028 * @brief Disable PLLSAI ready interrupt
5029 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
5030 * @retval None
5031 */
5032 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
5033 {
5034 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
5035 }
5036
5037 /**
5038 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5039 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5040 * @retval State of bit (1 or 0).
5041 */
5042 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5043 {
5044 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
5045 }
5046
5047 /**
5048 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5049 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5050 * @retval State of bit (1 or 0).
5051 */
5052 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5053 {
5054 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
5055 }
5056
5057 /**
5058 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5059 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5060 * @retval State of bit (1 or 0).
5061 */
5062 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5063 {
5064 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
5065 }
5066
5067 /**
5068 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5069 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5070 * @retval State of bit (1 or 0).
5071 */
5072 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5073 {
5074 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
5075 }
5076
5077 /**
5078 * @brief Checks if PLL ready interrupt source is enabled or disabled.
5079 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
5080 * @retval State of bit (1 or 0).
5081 */
5082 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
5083 {
5084 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
5085 }
5086
5087 /**
5088 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
5089 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
5090 * @retval State of bit (1 or 0).
5091 */
5092 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
5093 {
5094 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
5095 }
5096
5097 /**
5098 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
5099 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
5100 * @retval State of bit (1 or 0).
5101 */
5102 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
5103 {
5104 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
5105 }
5106
5107 /**
5108 * @}
5109 */
5110
5111 #if defined(USE_FULL_LL_DRIVER)
5112 /** @defgroup RCC_LL_EF_Init De-initialization function
5113 * @{
5114 */
5115 ErrorStatus LL_RCC_DeInit(void);
5116 /**
5117 * @}
5118 */
5119
5120 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
5121 * @{
5122 */
5123 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
5124 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
5125 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
5126 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
5127 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
5128 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
5129 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
5130 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
5131 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
5132 #if defined(DFSDM1_Channel0)
5133 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
5134 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
5135 #endif /* DFSDM1_Channel0 */
5136 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
5137 #if defined(CEC)
5138 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
5139 #endif /* CEC */
5140 #if defined(LTDC)
5141 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
5142 #endif /* LTDC */
5143 #if defined(SPDIFRX)
5144 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
5145 #endif /* SPDIFRX */
5146 #if defined(DSI)
5147 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
5148 #endif /* DSI */
5149 /**
5150 * @}
5151 */
5152 #endif /* USE_FULL_LL_DRIVER */
5153
5154 /**
5155 * @}
5156 */
5157
5158 /**
5159 * @}
5160 */
5161
5162 #endif /* defined(RCC) */
5163
5164 /**
5165 * @}
5166 */
5167
5168 #ifdef __cplusplus
5169 }
5170 #endif
5171
5172 #endif /* __STM32F7xx_LL_RCC_H */
5173
5174 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/