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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_sdmmc.h
blob4e386989c003a12eb2714df83973b28f9884bbd6
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_sdmmc.h
4 * @author MCD Application Team
5 * @brief Header file of SDMMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_LL_SDMMC_H
22 #define __STM32F7xx_LL_SDMMC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30
31 /** @addtogroup STM32F7xx_Driver
32 * @{
33 */
34
35 /** @addtogroup SDMMC_LL
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
41 * @{
42 */
43
44 /**
45 * @brief SDMMC Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
50 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
51
52 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
53 enabled or disabled.
54 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
55
56 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
57 disabled when the bus is idle.
58 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
59
60 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
61 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
62
63 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
64 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
65
66 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
67 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
68
69 }SDMMC_InitTypeDef;
70
71
72 /**
73 * @brief SDMMC Command Control structure
74 */
75 typedef struct
76 {
77 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
78 to a card as part of a command message. If a command
79 contains an argument, it must be loaded into this register
80 before writing the command to the command register. */
81
82 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
83 Max_Data = 64 */
84
85 uint32_t Response; /*!< Specifies the SDMMC response type.
86 This parameter can be a value of @ref SDMMC_LL_Response_Type */
87
88 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
89 enabled or disabled.
90 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
91
92 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
93 is enabled or disabled.
94 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
95 }SDMMC_CmdInitTypeDef;
96
97
98 /**
99 * @brief SDMMC Data Control structure
100 */
101 typedef struct
102 {
103 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
104
105 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
106
107 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
108 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
109
110 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
111 is a read or write.
112 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
113
114 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
115 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
116
117 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
118 is enabled or disabled.
119 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
120 }SDMMC_DataInitTypeDef;
121
122 /**
123 * @}
124 */
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
128 * @{
129 */
130 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
131 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
132 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
133 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
134 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
135 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
136 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
137 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
138 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
139 number of transferred bytes does not match the block length */
140 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
141 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
142 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
143 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
144 command or if there was an attempt to access a locked card */
145 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
146 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
147 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
148 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
149 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
150 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
151 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
152 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
153 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
154 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
155 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
156 of erase sequence command was received */
157 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
158 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
159 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
160 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
161 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
162 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
163 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
164 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
165 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
166
167 /**
168 * @brief SDMMC Commands Index
169 */
170 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
171 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
172 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
173 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
174 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
175 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
176 operating condition register (OCR) content in the response on the CMD line. */
177 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
178 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
179 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
180 and asks the card whether card supports voltage. */
181 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
182 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
183 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
184 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
185 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
186 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
187 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
188 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
189 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
190 for SDHS and SDXC. */
191 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
192 fixed 512 bytes in case of SDHC and SDXC. */
193 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
194 STOP_TRANSMISSION command. */
195 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
196 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
197 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
198 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
199 fixed 512 bytes in case of SDHC and SDXC. */
200 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
201 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
202 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
203 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
204 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
205 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
206 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
207 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
208 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
209 system set by switch function command (CMD6). */
210 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
211 Reserved for each command system set by switch function command (CMD6). */
212 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
213 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
214 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
215 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
216 the SET_BLOCK_LEN command. */
217 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
218 than a standard command. */
219 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
220 for general purpose/application specific commands. */
221 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
222
223 /**
224 * @brief Following commands are SD Card Specific commands.
225 * SDMMC_APP_CMD should be sent before sending these commands.
226 */
227 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
228 widths are given in SCR register. */
229 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
230 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
231 32bit+CRC data block. */
232 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
233 send its operating condition register (OCR) content in the response on the CMD line. */
234 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
235 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
236 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
237 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
238
239 /**
240 * @brief Following commands are SD Card Specific security commands.
241 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
242 */
243 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
244 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
245 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
246 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
247 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
248 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
249 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
250 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
251 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
252 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
253 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
254
255 /**
256 * @brief Masks for errors Card Status R1 (OCR Register)
257 */
258 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
259 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
260 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
261 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
262 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
263 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
264 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
265 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
266 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
267 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
268 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
269 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
270 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
271 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
272 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
273 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
274 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
275 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
276 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
277 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
278
279 /**
280 * @brief Masks for R6 Response
281 */
282 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
283 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
284 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
285
286 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
287 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
288 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
289 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
290
291 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
292
293 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
294
295 #define SDMMC_ALLZERO ((uint32_t)0x00000000U)
296
297 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
298 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
299 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
300
301 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
302
303 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
304 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
305 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
306 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
307 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
308
309 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
310 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
311
312 /**
313 * @brief Command Class supported
314 */
315 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
316
317 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
318 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
319
320
321 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
322 * @{
323 */
324 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
325 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
326
327 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
328 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
329 /**
330 * @}
331 */
332
333 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
334 * @{
335 */
336 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
337 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
338
339 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
340 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
341 /**
342 * @}
343 */
344
345 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
346 * @{
347 */
348 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
349 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
350
351 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
352 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
353 /**
354 * @}
355 */
356
357 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
358 * @{
359 */
360 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
361 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
362 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
363
364 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
365 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
366 ((WIDE) == SDMMC_BUS_WIDE_8B))
367 /**
368 * @}
369 */
370
371 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
372 * @{
373 */
374 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
375 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
376
377 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
378 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
379 /**
380 * @}
381 */
382
383 /** @defgroup SDMMC_LL_Clock_Division Clock Division
384 * @{
385 */
386 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
387 /**
388 * @}
389 */
390
391 /** @defgroup SDMMC_LL_Command_Index Command Index
392 * @{
393 */
394 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
395 /**
396 * @}
397 */
398
399 /** @defgroup SDMMC_LL_Response_Type Response Type
400 * @{
401 */
402 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
403 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
404 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
405
406 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
407 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
408 ((RESPONSE) == SDMMC_RESPONSE_LONG))
409 /**
410 * @}
411 */
412
413 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
414 * @{
415 */
416 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
417 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
418 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
419
420 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
421 ((WAIT) == SDMMC_WAIT_IT) || \
422 ((WAIT) == SDMMC_WAIT_PEND))
423 /**
424 * @}
425 */
426
427 /** @defgroup SDMMC_LL_CPSM_State CPSM State
428 * @{
429 */
430 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
431 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
432
433 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
434 ((CPSM) == SDMMC_CPSM_ENABLE))
435 /**
436 * @}
437 */
438
439 /** @defgroup SDMMC_LL_Response_Registers Response Register
440 * @{
441 */
442 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
443 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
444 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
445 #define SDMMC_RESP4 ((uint32_t)0x0000000C)
446
447 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
448 ((RESP) == SDMMC_RESP2) || \
449 ((RESP) == SDMMC_RESP3) || \
450 ((RESP) == SDMMC_RESP4))
451 /**
452 * @}
453 */
454
455 /** @defgroup SDMMC_LL_Data_Length Data Lenght
456 * @{
457 */
458 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
459 /**
460 * @}
461 */
462
463 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
464 * @{
465 */
466 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
467 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
468 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
469 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
470 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
471 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
472 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
473 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
474 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
475 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
476 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
477 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
478 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
479 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
480 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
481
482 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
483 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
484 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
485 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
486 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
487 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
488 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
489 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
490 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
491 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
492 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
493 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
494 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
495 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
496 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
497 /**
498 * @}
499 */
500
501 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
502 * @{
503 */
504 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
505 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
506
507 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
508 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
509 /**
510 * @}
511 */
512
513 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
514 * @{
515 */
516 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
517 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
518
519 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
520 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
521 /**
522 * @}
523 */
524
525 /** @defgroup SDMMC_LL_DPSM_State DPSM State
526 * @{
527 */
528 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
529 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
530
531 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
532 ((DPSM) == SDMMC_DPSM_ENABLE))
533 /**
534 * @}
535 */
536
537 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
538 * @{
539 */
540 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
541 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
542
543 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
544 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
545 /**
546 * @}
547 */
548
549 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
550 * @{
551 */
552 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
553 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
554 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
555 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
556 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
557 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
558 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
559 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
560 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
561 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
562 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
563 #define SDMMC_IT_TXACT SDMMC_STA_TXACT
564 #define SDMMC_IT_RXACT SDMMC_STA_RXACT
565 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
566 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
567 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
568 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
569 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
570 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
571 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
572 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
573 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
574 /**
575 * @}
576 */
577
578 /** @defgroup SDMMC_LL_Flags Flags
579 * @{
580 */
581 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
582 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
583 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
584 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
585 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
586 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
587 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
588 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
589 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
590 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
591 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
592 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
593 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
594 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
595 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
596 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
597 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
598 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
599 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
600 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
601 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
602 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
603 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
604 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
605 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
606 SDMMC_FLAG_DBCKEND))
607 /**
608 * @}
609 */
610
611 /**
612 * @}
613 */
614
615 /* Exported macro ------------------------------------------------------------*/
616 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
617 * @{
618 */
619
620 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
621 * @brief SDMMC_LL registers bit address in the alias region
622 * @{
623 */
624 /* ---------------------- SDMMC registers bit mask --------------------------- */
625 /* --- CLKCR Register ---*/
626 /* CLKCR register clear mask */
627 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
628 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
629 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
630
631 /* --- DCTRL Register ---*/
632 /* SDMMC DCTRL Clear Mask */
633 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
634 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
635
636 /* --- CMD Register ---*/
637 /* CMD Register clear mask */
638 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
639 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
640 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
641
642 /* SDMMC Initialization Frequency (400KHz max) */
643 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
644
645 /* SDMMC Data Transfer Frequency (25MHz max) */
646 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
647
648 /**
649 * @}
650 */
651
652 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
653 * @brief macros to handle interrupts and specific clock configurations
654 * @{
655 */
656
657 /**
658 * @brief Enable the SDMMC device.
659 * @param __INSTANCE__ SDMMC Instance
660 * @retval None
661 */
662 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
663
664 /**
665 * @brief Disable the SDMMC device.
666 * @param __INSTANCE__ SDMMC Instance
667 * @retval None
668 */
669 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
670
671 /**
672 * @brief Enable the SDMMC DMA transfer.
673 * @param __INSTANCE__ SDMMC Instance
674 * @retval None
675 */
676 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
677 /**
678 * @brief Disable the SDMMC DMA transfer.
679 * @param __INSTANCE__ SDMMC Instance
680 * @retval None
681 */
682 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
683
684 /**
685 * @brief Enable the SDMMC device interrupt.
686 * @param __INSTANCE__ Pointer to SDMMC register base
687 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
688 * This parameter can be one or a combination of the following values:
689 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
690 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
691 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
692 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
693 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
694 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
695 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
696 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
697 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
698 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
699 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
700 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
701 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
702 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
703 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
704 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
705 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
706 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
707 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
708 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
709 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
710 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
711 * @retval None
712 */
713 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
714
715 /**
716 * @brief Disable the SDMMC device interrupt.
717 * @param __INSTANCE__ Pointer to SDMMC register base
718 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
719 * This parameter can be one or a combination of the following values:
720 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
721 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
722 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
723 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
724 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
725 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
726 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
727 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
728 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
729 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
730 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
731 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
732 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
733 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
734 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
735 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
736 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
737 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
738 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
739 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
740 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
741 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
742 * @retval None
743 */
744 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
745
746 /**
747 * @brief Checks whether the specified SDMMC flag is set or not.
748 * @param __INSTANCE__ Pointer to SDMMC register base
749 * @param __FLAG__ specifies the flag to check.
750 * This parameter can be one of the following values:
751 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
752 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
753 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
754 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
755 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
756 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
757 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
758 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
759 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
760 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
761 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
762 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
763 * @arg SDMMC_FLAG_RXACT: Data receive in progress
764 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
765 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
766 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
767 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
768 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
769 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
770 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
771 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
772 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
773 * @retval The new state of SDMMC_FLAG (SET or RESET).
774 */
775 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
776
777
778 /**
779 * @brief Clears the SDMMC pending flags.
780 * @param __INSTANCE__ Pointer to SDMMC register base
781 * @param __FLAG__ specifies the flag to clear.
782 * This parameter can be one or a combination of the following values:
783 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
784 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
785 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
786 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
787 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
788 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
789 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
790 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
791 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
792 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
793 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
794 * @retval None
795 */
796 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
797
798 /**
799 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
800 * @param __INSTANCE__ Pointer to SDMMC register base
801 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
802 * This parameter can be one of the following values:
803 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
804 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
805 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
806 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
807 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
808 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
809 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
810 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
811 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
812 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
813 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
814 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
815 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
816 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
817 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
818 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
819 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
820 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
821 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
822 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
823 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
824 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
825 * @retval The new state of SDMMC_IT (SET or RESET).
826 */
827 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
828
829 /**
830 * @brief Clears the SDMMC's interrupt pending bits.
831 * @param __INSTANCE__ Pointer to SDMMC register base
832 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
833 * This parameter can be one or a combination of the following values:
834 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
835 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
836 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
837 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
838 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
839 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
840 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
841 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
842 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
843 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
844 * @retval None
845 */
846 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
847
848 /**
849 * @brief Enable Start the SD I/O Read Wait operation.
850 * @param __INSTANCE__ Pointer to SDMMC register base
851 * @retval None
852 */
853 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
854
855 /**
856 * @brief Disable Start the SD I/O Read Wait operations.
857 * @param __INSTANCE__ Pointer to SDMMC register base
858 * @retval None
859 */
860 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
861
862 /**
863 * @brief Enable Start the SD I/O Read Wait operation.
864 * @param __INSTANCE__ Pointer to SDMMC register base
865 * @retval None
866 */
867 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
868
869 /**
870 * @brief Disable Stop the SD I/O Read Wait operations.
871 * @param __INSTANCE__ Pointer to SDMMC register base
872 * @retval None
873 */
874 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
875
876 /**
877 * @brief Enable the SD I/O Mode Operation.
878 * @param __INSTANCE__ Pointer to SDMMC register base
879 * @retval None
880 */
881 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
882
883 /**
884 * @brief Disable the SD I/O Mode Operation.
885 * @param __INSTANCE__ Pointer to SDMMC register base
886 * @retval None
887 */
888 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
889
890 /**
891 * @brief Enable the SD I/O Suspend command sending.
892 * @param __INSTANCE__ Pointer to SDMMC register base
893 * @retval None
894 */
895 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
896
897 /**
898 * @brief Disable the SD I/O Suspend command sending.
899 * @param __INSTANCE__ Pointer to SDMMC register base
900 * @retval None
901 */
902 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
903
904 /**
905 * @}
906 */
907
908 /**
909 * @}
910 */
911
912 /* Exported functions --------------------------------------------------------*/
913 /** @addtogroup SDMMC_LL_Exported_Functions
914 * @{
915 */
916
917 /* Initialization/de-initialization functions **********************************/
918 /** @addtogroup HAL_SDMMC_LL_Group1
919 * @{
920 */
921 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
922 /**
923 * @}
924 */
925
926 /* I/O operation functions *****************************************************/
927 /** @addtogroup HAL_SDMMC_LL_Group2
928 * @{
929 */
930 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
931 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
932 /**
933 * @}
934 */
935
936 /* Peripheral Control functions ************************************************/
937 /** @addtogroup HAL_SDMMC_LL_Group3
938 * @{
939 */
940 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
941 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
942 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
943
944 /* Command path state machine (CPSM) management functions */
945 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
946 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
947 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
948
949 /* Data path state machine (DPSM) management functions */
950 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
951 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
952 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
953
954 /* SDMMC Cards mode management functions */
955 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
956
957 /* SDMMC Commands management functions */
958 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
959 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
960 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
961 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
962 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
963 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
964 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
965 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
966 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
967 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
968 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
969 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
970 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
971 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
972 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
973 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
974 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
975 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
976 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
977 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
978 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
979 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
980 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
981 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
982 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
983
984 /**
985 * @}
986 */
987
988 /**
989 * @}
990 */
991
992 /**
993 * @}
994 */
995
996 /**
997 * @}
998 */
999
1000 #ifdef __cplusplus
1001 }
1002 #endif
1003
1004 #endif /* __STM32F7xx_LL_SDMMC_H */
1005
1006 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/