?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_adc.c
bloba0fde31dcd84447181f8a8519460616b95648616
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
7 * + Initialization and de-initialization functions
8 * + IO operation functions
9 * + State and errors functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### ADC Peripheral features #####
14 ==============================================================================
15 [..]
16 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
17 (#) Interrupt generation at the end of conversion, end of injected conversion,
18 and in case of analog watchdog or overrun events
19 (#) Single and continuous conversion modes.
20 (#) Scan mode for automatic conversion of channel 0 to channel x.
21 (#) Data alignment with in-built data coherency.
22 (#) Channel-wise programmable sampling time.
23 (#) External trigger option with configurable polarity for both regular and
24 injected conversion.
25 (#) Dual/Triple mode (on devices with 2 ADCs or more).
26 (#) Configurable DMA data storage in Dual/Triple ADC mode.
27 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
28 (#) ADC conversion type (refer to the datasheets).
29 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
30 slower speed.
31 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
32 (#) DMA request generation during regular channel conversion.
33
34
35 ##### How to use this driver #####
36 ==============================================================================
37 [..]
38 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
39 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
40 (##) ADC pins configuration
41 (+++) Enable the clock for the ADC GPIOs using the following function:
42 __HAL_RCC_GPIOx_CLK_ENABLE()
43 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
44 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
45 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
46 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
47 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
48 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
49 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
50 (+++) Configure and enable two DMA streams stream for managing data
51 transfer from peripheral to memory (output stream)
52 (+++) Associate the initialized DMA handle to the CRYP DMA handle
53 using __HAL_LINKDMA()
54 (+++) Configure the priority and enable the NVIC for the transfer complete
55 interrupt on the two DMA Streams. The output stream should have higher
56 priority than the input stream.
57
58 *** Configuration of ADC, groups regular/injected, channels parameters ***
59 ==============================================================================
60 [..]
61 (#) Configure the ADC parameters (resolution, data alignment, ...)
62 and regular group parameters (conversion trigger, sequencer, ...)
63 using function HAL_ADC_Init().
64
65 (#) Configure the channels for regular group parameters (channel number,
66 channel rank into sequencer, ..., into regular group)
67 using function HAL_ADC_ConfigChannel().
68
69 (#) Optionally, configure the injected group parameters (conversion trigger,
70 sequencer, ..., of injected group)
71 and the channels for injected group parameters (channel number,
72 channel rank into sequencer, ..., into injected group)
73 using function HAL_ADCEx_InjectedConfigChannel().
74
75 (#) Optionally, configure the analog watchdog parameters (channels
76 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
77
78 (#) Optionally, for devices with several ADC instances: configure the
79 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
80
81 *** Execution of ADC conversions ***
82 ==============================================================================
83 [..]
84 (#) ADC driver can be used among three modes: polling, interruption,
85 transfer by DMA.
86
87 *** Polling mode IO operation ***
88 =================================
89 [..]
90 (+) Start the ADC peripheral using HAL_ADC_Start()
91 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
92 user can specify the value of timeout according to his end application
93 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
94 (+) Stop the ADC peripheral using HAL_ADC_Stop()
95
96 *** Interrupt mode IO operation ***
97 ===================================
98 [..]
99 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
100 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
101 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
102 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
103 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
104 add his own code by customization of function pointer HAL_ADC_ErrorCallback
105 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
106
107 *** DMA mode IO operation ***
108 ==============================
109 [..]
110 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
111 of data to be transferred at each end of conversion
112 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
114 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
117
118 *** ADC HAL driver macros list ***
119 =============================================
120 [..]
121 Below the list of most used macros in ADC HAL driver.
122
123 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
124 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
125 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
126 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
127 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
128 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
129 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
130 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
131
132 *** Callback functions ***
133 ==============================
134 (@) Callback functions must be implemented in user program:
135 (+@) HAL_ADC_ErrorCallback()
136 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
137 (+@) HAL_ADC_ConvCpltCallback()
138 (+@) HAL_ADC_ConvHalfCpltCallback
139
140 (@) You can refer to the ADC HAL driver header file for more useful macros
141
142 *** Deinitialization of ADC ***
143 ==============================================================================
144 [..]
145 (#) Disable the ADC interface
146 (++) ADC clock can be hard reset and disabled at RCC top level.
147 (++) Hard reset of ADC peripherals
148 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
149 (++) ADC clock disable using the equivalent macro/functions as configuration step.
150 (+++) Example:
151 Into HAL_ADC_MspDeInit() (recommended code location) or with
152 other device clock parameters configuration:
153 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
154 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
155 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
156 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
157
158 (#) ADC pins configuration
159 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
160
161 (#) Optionally, in case of usage of ADC with interruptions:
162 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
163
164 (#) Optionally, in case of usage of DMA:
165 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
166 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
167
168 *** Callback registration ***
169 ==============================================================================
170 [..]
171
172 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
173 allows the user to configure dynamically the driver callbacks.
174 Use Functions @ref HAL_ADC_RegisterCallback()
175 to register an interrupt callback.
176 [..]
177
178 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
179 (+) ConvCpltCallback : ADC conversion complete callback
180 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
181 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
182 (+) ErrorCallback : ADC error callback
183 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
184 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
185 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
186 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
187 (+) EndOfSamplingCallback : ADC end of sampling callback
188 (+) MspInitCallback : ADC Msp Init callback
189 (+) MspDeInitCallback : ADC Msp DeInit callback
190 This function takes as parameters the HAL peripheral handle, the Callback ID
191 and a pointer to the user callback function.
192 [..]
193
194 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
195 weak function.
196 [..]
197
198 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
199 and the Callback ID.
200 This function allows to reset following callbacks:
201 (+) ConvCpltCallback : ADC conversion complete callback
202 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
203 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
204 (+) ErrorCallback : ADC error callback
205 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
206 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
207 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
208 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
209 (+) EndOfSamplingCallback : ADC end of sampling callback
210 (+) MspInitCallback : ADC Msp Init callback
211 (+) MspDeInitCallback : ADC Msp DeInit callback
212 [..]
213
214 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
215 all callbacks are set to the corresponding weak functions:
216 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
217 Exception done for MspInit and MspDeInit functions that are
218 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
219 these callbacks are null (not registered beforehand).
220 [..]
221
222 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
223 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
224 [..]
225
226 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
227 Exception done MspInit/MspDeInit functions that can be registered/unregistered
228 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
229 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
230 [..]
231
232 Then, the user first registers the MspInit/MspDeInit user callbacks
233 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
234 or @ref HAL_ADC_Init() function.
235 [..]
236
237 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
238 not defined, the callback registration feature is not available and all callbacks
239 are set to the corresponding weak functions.
240
241 @endverbatim
242 ******************************************************************************
243 * @attention
244 *
245 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
246 * All rights reserved.</center></h2>
247 *
248 * This software component is licensed by ST under BSD 3-Clause license,
249 * the "License"; You may not use this file except in compliance with the
250 * License. You may obtain a copy of the License at:
251 * opensource.org/licenses/BSD-3-Clause
252 *
253 ******************************************************************************
254 */
255
256 /* Includes ------------------------------------------------------------------*/
257 #include "stm32f7xx_hal.h"
258
259 /** @addtogroup STM32F7xx_HAL_Driver
260 * @{
261 */
262
263 /** @defgroup ADC ADC
264 * @brief ADC driver modules
265 * @{
266 */
267
268 #ifdef HAL_ADC_MODULE_ENABLED
269
270 /* Private typedef -----------------------------------------------------------*/
271 /* Private define ------------------------------------------------------------*/
272 /* Private macro -------------------------------------------------------------*/
273 /* Private variables ---------------------------------------------------------*/
274 /** @addtogroup ADC_Private_Functions
275 * @{
276 */
277 /* Private function prototypes -----------------------------------------------*/
278 static void ADC_Init(ADC_HandleTypeDef* hadc);
279 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
280 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
281 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
282 /**
283 * @}
284 */
285
286 /* Exported functions --------------------------------------------------------*/
287 /** @defgroup ADC_Exported_Functions ADC Exported Functions
288 * @{
289 */
290
291 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
292 * @brief Initialization and Configuration functions
293 *
294 @verbatim
295 ===============================================================================
296 ##### Initialization and de-initialization functions #####
297 ===============================================================================
298 [..] This section provides functions allowing to:
299 (+) Initialize and configure the ADC.
300 (+) De-initialize the ADC.
301
302 @endverbatim
303 * @{
304 */
305
306 /**
307 * @brief Initializes the ADCx peripheral according to the specified parameters
308 * in the ADC_InitStruct and initializes the ADC MSP.
309 *
310 * @note This function is used to configure the global features of the ADC (
311 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
312 * the rest of the configuration parameters are specific to the regular
313 * channels group (scan mode activation, continuous mode activation,
314 * External trigger source and edge, DMA continuous request after the
315 * last transfer and End of conversion selection).
316 *
317 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
318 * the configuration information for the specified ADC.
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
322 {
323 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
324
325 /* Check ADC handle */
326 if(hadc == NULL)
327 {
328 return HAL_ERROR;
329 }
330
331 /* Check the parameters */
332 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
333 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
334 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
335 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
336 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
337 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
338 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
339 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
340 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
341 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
342 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
343
344 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
345 {
346 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
347 }
348
349 if(hadc->State == HAL_ADC_STATE_RESET)
350 {
351 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
352 /* Init the ADC Callback settings */
353 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
354 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
355 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
356 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
357 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
358 if (hadc->MspInitCallback == NULL)
359 {
360 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
361 }
362
363 /* Init the low level hardware */
364 hadc->MspInitCallback(hadc);
365 #else
366 /* Init the low level hardware */
367 HAL_ADC_MspInit(hadc);
368 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
369
370 /* Initialize ADC error code */
371 ADC_CLEAR_ERRORCODE(hadc);
372
373 /* Allocate lock resource and initialize it */
374 hadc->Lock = HAL_UNLOCKED;
375 }
376
377 /* Configuration of ADC parameters if previous preliminary actions are */
378 /* correctly completed. */
379 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
380 {
381 /* Set ADC state */
382 ADC_STATE_CLR_SET(hadc->State,
383 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
384 HAL_ADC_STATE_BUSY_INTERNAL);
385
386 /* Set ADC parameters */
387 ADC_Init(hadc);
388
389 /* Set ADC error code to none */
390 ADC_CLEAR_ERRORCODE(hadc);
391
392 /* Set the ADC state */
393 ADC_STATE_CLR_SET(hadc->State,
394 HAL_ADC_STATE_BUSY_INTERNAL,
395 HAL_ADC_STATE_READY);
396 }
397 else
398 {
399 tmp_hal_status = HAL_ERROR;
400 }
401
402 /* Release Lock */
403 __HAL_UNLOCK(hadc);
404
405 /* Return function status */
406 return tmp_hal_status;
407 }
408
409 /**
410 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
411 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
412 * the configuration information for the specified ADC.
413 * @retval HAL status
414 */
415 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
416 {
417 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
418
419 /* Check ADC handle */
420 if(hadc == NULL)
421 {
422 return HAL_ERROR;
423 }
424
425 /* Check the parameters */
426 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
427
428 /* Set ADC state */
429 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
430
431 /* Stop potential conversion on going, on regular and injected groups */
432 /* Disable ADC peripheral */
433 __HAL_ADC_DISABLE(hadc);
434
435 /* Configuration of ADC parameters if previous preliminary actions are */
436 /* correctly completed. */
437 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
438 {
439 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
440 if (hadc->MspDeInitCallback == NULL)
441 {
442 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
443 }
444
445 /* DeInit the low level hardware: RCC clock, NVIC */
446 hadc->MspDeInitCallback(hadc);
447 #else
448 /* DeInit the low level hardware: RCC clock, NVIC */
449 HAL_ADC_MspDeInit(hadc);
450 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
451
452 /* Set ADC error code to none */
453 ADC_CLEAR_ERRORCODE(hadc);
454
455 /* Set ADC state */
456 hadc->State = HAL_ADC_STATE_RESET;
457 }
458
459 /* Process unlocked */
460 __HAL_UNLOCK(hadc);
461
462 /* Return function status */
463 return tmp_hal_status;
464 }
465
466 /**
467 * @brief Initializes the ADC MSP.
468 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
469 * the configuration information for the specified ADC.
470 * @retval None
471 */
472 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
473 {
474 /* Prevent unused argument(s) compilation warning */
475 UNUSED(hadc);
476 /* NOTE : This function Should not be modified, when the callback is needed,
477 the HAL_ADC_MspInit could be implemented in the user file
478 */
479 }
480
481 /**
482 * @brief DeInitializes the ADC MSP.
483 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
484 * the configuration information for the specified ADC.
485 * @retval None
486 */
487 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
488 {
489 /* Prevent unused argument(s) compilation warning */
490 UNUSED(hadc);
491 /* NOTE : This function Should not be modified, when the callback is needed,
492 the HAL_ADC_MspDeInit could be implemented in the user file
493 */
494 }
495
496 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
497 /**
498 * @brief Register a User ADC Callback
499 * To be used instead of the weak predefined callback
500 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
501 * the configuration information for the specified ADC.
502 * @param CallbackID ID of the callback to be registered
503 * This parameter can be one of the following values:
504 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
505 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
506 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
507 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
508 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
509 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
510 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
511 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
512 * @param pCallback pointer to the Callback function
513 * @retval HAL status
514 */
515 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
516 {
517 HAL_StatusTypeDef status = HAL_OK;
518
519 if (pCallback == NULL)
520 {
521 /* Update the error code */
522 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
523
524 return HAL_ERROR;
525 }
526
527 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
528 {
529 switch (CallbackID)
530 {
531 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
532 hadc->ConvCpltCallback = pCallback;
533 break;
534
535 case HAL_ADC_CONVERSION_HALF_CB_ID :
536 hadc->ConvHalfCpltCallback = pCallback;
537 break;
538
539 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
540 hadc->LevelOutOfWindowCallback = pCallback;
541 break;
542
543 case HAL_ADC_ERROR_CB_ID :
544 hadc->ErrorCallback = pCallback;
545 break;
546
547 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
548 hadc->InjectedConvCpltCallback = pCallback;
549 break;
550
551 case HAL_ADC_MSPINIT_CB_ID :
552 hadc->MspInitCallback = pCallback;
553 break;
554
555 case HAL_ADC_MSPDEINIT_CB_ID :
556 hadc->MspDeInitCallback = pCallback;
557 break;
558
559 default :
560 /* Update the error code */
561 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
562
563 /* Return error status */
564 status = HAL_ERROR;
565 break;
566 }
567 }
568 else if (HAL_ADC_STATE_RESET == hadc->State)
569 {
570 switch (CallbackID)
571 {
572 case HAL_ADC_MSPINIT_CB_ID :
573 hadc->MspInitCallback = pCallback;
574 break;
575
576 case HAL_ADC_MSPDEINIT_CB_ID :
577 hadc->MspDeInitCallback = pCallback;
578 break;
579
580 default :
581 /* Update the error code */
582 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
583
584 /* Return error status */
585 status = HAL_ERROR;
586 break;
587 }
588 }
589 else
590 {
591 /* Update the error code */
592 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
593
594 /* Return error status */
595 status = HAL_ERROR;
596 }
597
598 return status;
599 }
600
601 /**
602 * @brief Unregister a ADC Callback
603 * ADC callback is redirected to the weak predefined callback
604 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
605 * the configuration information for the specified ADC.
606 * @param CallbackID ID of the callback to be unregistered
607 * This parameter can be one of the following values:
608 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
609 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
610 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
611 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
612 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
613 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
614 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
615 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
616 * @retval HAL status
617 */
618 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
619 {
620 HAL_StatusTypeDef status = HAL_OK;
621
622 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
623 {
624 switch (CallbackID)
625 {
626 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
627 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
628 break;
629
630 case HAL_ADC_CONVERSION_HALF_CB_ID :
631 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
632 break;
633
634 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
635 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
636 break;
637
638 case HAL_ADC_ERROR_CB_ID :
639 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
640 break;
641
642 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
643 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
644 break;
645
646 case HAL_ADC_MSPINIT_CB_ID :
647 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
648 break;
649
650 case HAL_ADC_MSPDEINIT_CB_ID :
651 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
652 break;
653
654 default :
655 /* Update the error code */
656 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
657
658 /* Return error status */
659 status = HAL_ERROR;
660 break;
661 }
662 }
663 else if (HAL_ADC_STATE_RESET == hadc->State)
664 {
665 switch (CallbackID)
666 {
667 case HAL_ADC_MSPINIT_CB_ID :
668 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
669 break;
670
671 case HAL_ADC_MSPDEINIT_CB_ID :
672 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
673 break;
674
675 default :
676 /* Update the error code */
677 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
678
679 /* Return error status */
680 status = HAL_ERROR;
681 break;
682 }
683 }
684 else
685 {
686 /* Update the error code */
687 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
688
689 /* Return error status */
690 status = HAL_ERROR;
691 }
692
693 return status;
694 }
695
696 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
697
698
699 /**
700 * @}
701 */
702
703 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
704 * @brief IO operation functions
705 *
706 @verbatim
707 ===============================================================================
708 ##### IO operation functions #####
709 ===============================================================================
710 [..] This section provides functions allowing to:
711 (+) Start conversion of regular channel.
712 (+) Stop conversion of regular channel.
713 (+) Start conversion of regular channel and enable interrupt.
714 (+) Stop conversion of regular channel and disable interrupt.
715 (+) Start conversion of regular channel and enable DMA transfer.
716 (+) Stop conversion of regular channel and disable DMA transfer.
717 (+) Handle ADC interrupt request.
718
719 @endverbatim
720 * @{
721 */
722
723 /**
724 * @brief Enables ADC and starts conversion of the regular channels.
725 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
726 * the configuration information for the specified ADC.
727 * @retval HAL status
728 */
729 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
730 {
731 __IO uint32_t counter = 0;
732
733 /* Check the parameters */
734 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
735 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
736
737 /* Process locked */
738 __HAL_LOCK(hadc);
739
740 /* Enable the ADC peripheral */
741 /* Check if ADC peripheral is disabled in order to enable it and wait during
742 Tstab time the ADC's stabilization */
743 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
744 {
745 /* Enable the Peripheral */
746 __HAL_ADC_ENABLE(hadc);
747
748 /* Delay for ADC stabilization time */
749 /* Compute number of CPU cycles to wait for */
750 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
751 while(counter != 0)
752 {
753 counter--;
754 }
755 }
756
757 /* Start conversion if ADC is effectively enabled */
758 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
759 {
760 /* Set ADC state */
761 /* - Clear state bitfield related to regular group conversion results */
762 /* - Set state bitfield related to regular group operation */
763 ADC_STATE_CLR_SET(hadc->State,
764 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
765 HAL_ADC_STATE_REG_BUSY);
766
767 /* If conversions on group regular are also triggering group injected, */
768 /* update ADC state. */
769 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
770 {
771 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
772 }
773
774 /* State machine update: Check if an injected conversion is ongoing */
775 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
776 {
777 /* Reset ADC error code fields related to conversions on group regular */
778 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
779 }
780 else
781 {
782 /* Reset ADC all error code fields */
783 ADC_CLEAR_ERRORCODE(hadc);
784 }
785
786 /* Process unlocked */
787 /* Unlock before starting ADC conversions: in case of potential */
788 /* interruption, to let the process to ADC IRQ Handler. */
789 __HAL_UNLOCK(hadc);
790
791 /* Clear regular group conversion flag and overrun flag */
792 /* (To ensure of no unknown state from potential previous ADC operations) */
793 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
794
795 /* Check if Multimode enabled */
796 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
797 {
798 /* if no external trigger present enable software conversion of regular channels */
799 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
800 {
801 /* Enable the selected ADC software conversion for regular group */
802 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
803 }
804 }
805 else
806 {
807 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
808 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
809 {
810 /* Enable the selected ADC software conversion for regular group */
811 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
812 }
813
814 /* if dual mode is selected, ADC3 works independently. */
815 /* check if the mode selected is not triple */
816 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
817 {
818 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
819 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
820 {
821 /* Enable the selected ADC software conversion for regular group */
822 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
823 }
824 }
825 }
826 }
827
828 /* Return function status */
829 return HAL_OK;
830 }
831
832 /**
833 * @brief Disables ADC and stop conversion of regular channels.
834 *
835 * @note Caution: This function will stop also injected channels.
836 *
837 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
838 * the configuration information for the specified ADC.
839 *
840 * @retval HAL status.
841 */
842 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
843 {
844 /* Check the parameters */
845 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
846
847 /* Process locked */
848 __HAL_LOCK(hadc);
849
850 /* Stop potential conversion on going, on regular and injected groups */
851 /* Disable ADC peripheral */
852 __HAL_ADC_DISABLE(hadc);
853
854 /* Check if ADC is effectively disabled */
855 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
856 {
857 /* Set ADC state */
858 ADC_STATE_CLR_SET(hadc->State,
859 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
860 HAL_ADC_STATE_READY);
861 }
862
863 /* Process unlocked */
864 __HAL_UNLOCK(hadc);
865
866 /* Return function status */
867 return HAL_OK;
868 }
869
870 /**
871 * @brief Poll for regular conversion complete
872 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
873 * conversion) are cleared by this function.
874 * @note This function cannot be used in a particular setup: ADC configured
875 * in DMA mode and polling for end of each conversion (ADC init
876 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
877 * In this case, DMA resets the flag EOC and polling cannot be
878 * performed on each conversion. Nevertheless, polling can still
879 * be performed on the complete sequence.
880 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
881 * the configuration information for the specified ADC.
882 * @param Timeout Timeout value in millisecond.
883 * @retval HAL status
884 */
885 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
886 {
887 uint32_t tickstart = 0;
888
889 /* Verification that ADC configuration is compliant with polling for */
890 /* each conversion: */
891 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
892 /* several ranks and polling for end of each conversion. */
893 /* For code simplicity sake, this particular case is generalized to */
894 /* ADC configured in DMA mode and polling for end of each conversion. */
895 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
896 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
897 {
898 /* Update ADC state machine to error */
899 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
900
901 /* Process unlocked */
902 __HAL_UNLOCK(hadc);
903
904 return HAL_ERROR;
905 }
906
907 /* Get tick */
908 tickstart = HAL_GetTick();
909
910 /* Check End of conversion flag */
911 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
912 {
913 /* Check if timeout is disabled (set to infinite wait) */
914 if(Timeout != HAL_MAX_DELAY)
915 {
916 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
917 {
918 /* Update ADC state machine to timeout */
919 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
920
921 /* Process unlocked */
922 __HAL_UNLOCK(hadc);
923
924 return HAL_TIMEOUT;
925 }
926 }
927 }
928
929 /* Clear regular group conversion flag */
930 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
931
932 /* Update ADC state machine */
933 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
934
935 /* Determine whether any further conversion upcoming on group regular */
936 /* by external trigger, continuous mode or scan sequence on going. */
937 /* Note: On STM32F7, there is no independent flag of end of sequence. */
938 /* The test of scan sequence on going is done either with scan */
939 /* sequence disabled or with end of conversion flag set to */
940 /* of end of sequence. */
941 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
942 (hadc->Init.ContinuousConvMode == DISABLE) &&
943 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
944 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
945 {
946 /* Set ADC state */
947 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
948
949 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
950 {
951 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
952 }
953 }
954
955 /* Return ADC state */
956 return HAL_OK;
957 }
958
959 /**
960 * @brief Poll for conversion event
961 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
962 * the configuration information for the specified ADC.
963 * @param EventType the ADC event type.
964 * This parameter can be one of the following values:
965 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
966 * @arg ADC_OVR_EVENT: ADC Overrun event.
967 * @param Timeout Timeout value in millisecond.
968 * @retval HAL status
969 */
970 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
971 {
972 uint32_t tickstart = 0;
973
974 /* Check the parameters */
975 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
976 assert_param(IS_ADC_EVENT_TYPE(EventType));
977
978 /* Get tick */
979 tickstart = HAL_GetTick();
980
981 /* Check selected event flag */
982 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
983 {
984 /* Check for the Timeout */
985 if(Timeout != HAL_MAX_DELAY)
986 {
987 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
988 {
989 /* Update ADC state machine to timeout */
990 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
991
992 /* Process unlocked */
993 __HAL_UNLOCK(hadc);
994
995 return HAL_TIMEOUT;
996 }
997 }
998 }
999
1000 /* Analog watchdog (level out of window) event */
1001 if(EventType == ADC_AWD_EVENT)
1002 {
1003 /* Set ADC state */
1004 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1005
1006 /* Clear ADC analog watchdog flag */
1007 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1008 }
1009 /* Overrun event */
1010 else
1011 {
1012 /* Set ADC state */
1013 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1014 /* Set ADC error code to overrun */
1015 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1016
1017 /* Clear ADC overrun flag */
1018 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1019 }
1020
1021 /* Return ADC state */
1022 return HAL_OK;
1023 }
1024
1025
1026 /**
1027 * @brief Enables the interrupt and starts ADC conversion of regular channels.
1028 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1029 * the configuration information for the specified ADC.
1030 * @retval HAL status.
1031 */
1032 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1033 {
1034 __IO uint32_t counter = 0;
1035
1036 /* Check the parameters */
1037 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1038 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1039
1040 /* Process locked */
1041 __HAL_LOCK(hadc);
1042
1043 /* Enable the ADC peripheral */
1044 /* Check if ADC peripheral is disabled in order to enable it and wait during
1045 Tstab time the ADC's stabilization */
1046 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1047 {
1048 /* Enable the Peripheral */
1049 __HAL_ADC_ENABLE(hadc);
1050
1051 /* Delay for ADC stabilization time */
1052 /* Compute number of CPU cycles to wait for */
1053 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1054 while(counter != 0)
1055 {
1056 counter--;
1057 }
1058 }
1059
1060 /* Start conversion if ADC is effectively enabled */
1061 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1062 {
1063 /* Set ADC state */
1064 /* - Clear state bitfield related to regular group conversion results */
1065 /* - Set state bitfield related to regular group operation */
1066 ADC_STATE_CLR_SET(hadc->State,
1067 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1068 HAL_ADC_STATE_REG_BUSY);
1069
1070 /* If conversions on group regular are also triggering group injected, */
1071 /* update ADC state. */
1072 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1073 {
1074 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1075 }
1076
1077 /* State machine update: Check if an injected conversion is ongoing */
1078 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1079 {
1080 /* Reset ADC error code fields related to conversions on group regular */
1081 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1082 }
1083 else
1084 {
1085 /* Reset ADC all error code fields */
1086 ADC_CLEAR_ERRORCODE(hadc);
1087 }
1088
1089 /* Process unlocked */
1090 /* Unlock before starting ADC conversions: in case of potential */
1091 /* interruption, to let the process to ADC IRQ Handler. */
1092 __HAL_UNLOCK(hadc);
1093
1094 /* Clear regular group conversion flag and overrun flag */
1095 /* (To ensure of no unknown state from potential previous ADC operations) */
1096 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1097
1098 /* Enable end of conversion interrupt for regular group */
1099 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1100
1101 /* Check if Multimode enabled */
1102 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
1103 {
1104 /* if no external trigger present enable software conversion of regular channels */
1105 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1106 {
1107 /* Enable the selected ADC software conversion for regular group */
1108 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1109 }
1110 }
1111 else
1112 {
1113 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1114 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1115 {
1116 /* Enable the selected ADC software conversion for regular group */
1117 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1118 }
1119
1120 /* if dual mode is selected, ADC3 works independently. */
1121 /* check if the mode selected is not triple */
1122 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
1123 {
1124 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
1125 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1126 {
1127 /* Enable the selected ADC software conversion for regular group */
1128 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1129 }
1130 }
1131 }
1132 }
1133
1134 /* Return function status */
1135 return HAL_OK;
1136 }
1137
1138 /**
1139 * @brief Disables the interrupt and stop ADC conversion of regular channels.
1140 *
1141 * @note Caution: This function will stop also injected channels.
1142 *
1143 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1144 * the configuration information for the specified ADC.
1145 * @retval HAL status.
1146 */
1147 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1148 {
1149 /* Check the parameters */
1150 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1151
1152 /* Process locked */
1153 __HAL_LOCK(hadc);
1154
1155 /* Stop potential conversion on going, on regular and injected groups */
1156 /* Disable ADC peripheral */
1157 __HAL_ADC_DISABLE(hadc);
1158
1159 /* Check if ADC is effectively disabled */
1160 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1161 {
1162 /* Disable ADC end of conversion interrupt for regular group */
1163 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1164
1165 /* Set ADC state */
1166 ADC_STATE_CLR_SET(hadc->State,
1167 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1168 HAL_ADC_STATE_READY);
1169 }
1170
1171 /* Process unlocked */
1172 __HAL_UNLOCK(hadc);
1173
1174 /* Return function status */
1175 return HAL_OK;
1176 }
1177
1178 /**
1179 * @brief Handles ADC interrupt request
1180 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1181 * the configuration information for the specified ADC.
1182 * @retval None
1183 */
1184 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1185 {
1186 uint32_t tmp1 = 0, tmp2 = 0;
1187
1188 /* Check the parameters */
1189 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1190 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
1191 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
1192
1193 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
1194 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
1195 /* Check End of conversion flag for regular channels */
1196 if(tmp1 && tmp2)
1197 {
1198 /* Update state machine on conversion status if not in error state */
1199 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1200 {
1201 /* Set ADC state */
1202 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1203 }
1204
1205 /* Determine whether any further conversion upcoming on group regular */
1206 /* by external trigger, continuous mode or scan sequence on going. */
1207 /* Note: On STM32F7, there is no independent flag of end of sequence. */
1208 /* The test of scan sequence on going is done either with scan */
1209 /* sequence disabled or with end of conversion flag set to */
1210 /* of end of sequence. */
1211 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1212 (hadc->Init.ContinuousConvMode == DISABLE) &&
1213 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1214 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1215 {
1216 /* Disable ADC end of single conversion interrupt on group regular */
1217 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1218 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1219 /* by overrun IRQ process below. */
1220 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1221
1222 /* Set ADC state */
1223 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1224
1225 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1226 {
1227 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1228 }
1229 }
1230
1231 /* Conversion complete callback */
1232 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1233 hadc->ConvCpltCallback(hadc);
1234 #else
1235 HAL_ADC_ConvCpltCallback(hadc);
1236 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1237
1238 /* Clear regular group conversion flag */
1239 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1240 }
1241
1242 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
1243 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
1244 /* Check End of conversion flag for injected channels */
1245 if(tmp1 && tmp2)
1246 {
1247 /* Update state machine on conversion status if not in error state */
1248 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1249 {
1250 /* Set ADC state */
1251 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1252 }
1253
1254 /* Determine whether any further conversion upcoming on group injected */
1255 /* by external trigger, scan sequence on going or by automatic injected */
1256 /* conversion from group regular (same conditions as group regular */
1257 /* interruption disabling above). */
1258 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1259 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1260 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
1261 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1262 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1263 (hadc->Init.ContinuousConvMode == DISABLE))))
1264 {
1265 /* Disable ADC end of single conversion interrupt on group injected */
1266 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1267
1268 /* Set ADC state */
1269 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1270
1271 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1272 {
1273 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1274 }
1275 }
1276
1277 /* Conversion complete callback */
1278 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1279 hadc->InjectedConvCpltCallback(hadc);
1280 #else
1281 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1282 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1283
1284 /* Clear injected group conversion flag */
1285 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1286 }
1287
1288 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
1289 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
1290 /* Check Analog watchdog flag */
1291 if(tmp1 && tmp2)
1292 {
1293 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1294 {
1295 /* Set ADC state */
1296 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1297
1298 /* Level out of window callback */
1299 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1300 hadc->LevelOutOfWindowCallback(hadc);
1301 #else
1302 HAL_ADC_LevelOutOfWindowCallback(hadc);
1303 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1304
1305
1306 /* Clear the ADC analog watchdog flag */
1307 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1308 }
1309 }
1310
1311 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
1312 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
1313 /* Check Overrun flag */
1314 if(tmp1 && tmp2)
1315 {
1316 /* Note: On STM32F7, ADC overrun can be set through other parameters */
1317 /* refer to description of parameter "EOCSelection" for more */
1318 /* details. */
1319
1320 /* Set ADC error code to overrun */
1321 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1322
1323 /* Clear ADC overrun flag */
1324 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1325
1326 /* Error callback */
1327 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1328 hadc->ErrorCallback(hadc);
1329 #else
1330 HAL_ADC_ErrorCallback(hadc);
1331 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1332
1333 /* Clear the Overrun flag */
1334 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1335 }
1336 }
1337
1338 /**
1339 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
1340 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1341 * the configuration information for the specified ADC.
1342 * @param pData The destination Buffer address.
1343 * @param Length The length of data to be transferred from ADC peripheral to memory.
1344 * @retval HAL status
1345 */
1346 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1347 {
1348 __IO uint32_t counter = 0;
1349
1350 /* Check the parameters */
1351 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1352 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1353
1354 /* Process locked */
1355 __HAL_LOCK(hadc);
1356
1357 /* Enable the ADC peripheral */
1358 /* Check if ADC peripheral is disabled in order to enable it and wait during
1359 Tstab time the ADC's stabilization */
1360 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1361 {
1362 /* Enable the Peripheral */
1363 __HAL_ADC_ENABLE(hadc);
1364
1365 /* Delay for ADC stabilization time */
1366 /* Compute number of CPU cycles to wait for */
1367 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1368 while(counter != 0)
1369 {
1370 counter--;
1371 }
1372 }
1373
1374 /* Start conversion if ADC is effectively enabled */
1375 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1376 {
1377 /* Set ADC state */
1378 /* - Clear state bitfield related to regular group conversion results */
1379 /* - Set state bitfield related to regular group operation */
1380 ADC_STATE_CLR_SET(hadc->State,
1381 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1382 HAL_ADC_STATE_REG_BUSY);
1383
1384 /* If conversions on group regular are also triggering group injected, */
1385 /* update ADC state. */
1386 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1387 {
1388 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1389 }
1390
1391 /* State machine update: Check if an injected conversion is ongoing */
1392 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1393 {
1394 /* Reset ADC error code fields related to conversions on group regular */
1395 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1396 }
1397 else
1398 {
1399 /* Reset ADC all error code fields */
1400 ADC_CLEAR_ERRORCODE(hadc);
1401 }
1402
1403 /* Process unlocked */
1404 /* Unlock before starting ADC conversions: in case of potential */
1405 /* interruption, to let the process to ADC IRQ Handler. */
1406 __HAL_UNLOCK(hadc);
1407
1408 /* Set the DMA transfer complete callback */
1409 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1410
1411 /* Set the DMA half transfer complete callback */
1412 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1413
1414 /* Set the DMA error callback */
1415 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1416
1417
1418 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1419 /* start (in case of SW start): */
1420
1421 /* Clear regular group conversion flag and overrun flag */
1422 /* (To ensure of no unknown state from potential previous ADC operations) */
1423 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1424
1425 /* Enable ADC overrun interrupt */
1426 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1427
1428 /* Enable ADC DMA mode */
1429 hadc->Instance->CR2 |= ADC_CR2_DMA;
1430
1431 /* Start the DMA channel */
1432 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1433
1434 /* Check if Multimode enabled */
1435 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
1436 {
1437 /* if no external trigger present enable software conversion of regular channels */
1438 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1439 {
1440 /* Enable the selected ADC software conversion for regular group */
1441 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1442 }
1443 }
1444 else
1445 {
1446 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1447 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1448 {
1449 /* Enable the selected ADC software conversion for regular group */
1450 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1451 }
1452 /* if dual mode is selected, ADC3 works independently. */
1453 /* check if the mode selected is not triple */
1454 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
1455 {
1456 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
1457 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1458 {
1459 /* Enable the selected ADC software conversion for regular group */
1460 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1461 }
1462 }
1463 }
1464 }
1465
1466 /* Return function status */
1467 return HAL_OK;
1468 }
1469
1470 /**
1471 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
1472 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1473 * the configuration information for the specified ADC.
1474 * @retval HAL status
1475 */
1476 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1477 {
1478 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1479
1480 /* Check the parameters */
1481 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1482
1483 /* Process locked */
1484 __HAL_LOCK(hadc);
1485
1486 /* Stop potential conversion on going, on regular and injected groups */
1487 /* Disable ADC peripheral */
1488 __HAL_ADC_DISABLE(hadc);
1489
1490 /* Check if ADC is effectively disabled */
1491 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1492 {
1493 /* Disable the selected ADC DMA mode */
1494 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1495
1496 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1497 /* DMA transfer is on going) */
1498 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1499
1500 /* Disable ADC overrun interrupt */
1501 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1502
1503 /* Set ADC state */
1504 ADC_STATE_CLR_SET(hadc->State,
1505 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1506 HAL_ADC_STATE_READY);
1507 }
1508
1509 /* Process unlocked */
1510 __HAL_UNLOCK(hadc);
1511
1512 /* Return function status */
1513 return tmp_hal_status;
1514 }
1515
1516 /**
1517 * @brief Gets the converted value from data register of regular channel.
1518 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1519 * the configuration information for the specified ADC.
1520 * @retval Converted value
1521 */
1522 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1523 {
1524 /* Return the selected ADC converted value */
1525 return hadc->Instance->DR;
1526 }
1527
1528 /**
1529 * @brief Regular conversion complete callback in non blocking mode
1530 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1531 * the configuration information for the specified ADC.
1532 * @retval None
1533 */
1534 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1535 {
1536 /* Prevent unused argument(s) compilation warning */
1537 UNUSED(hadc);
1538 /* NOTE : This function Should not be modified, when the callback is needed,
1539 the HAL_ADC_ConvCpltCallback could be implemented in the user file
1540 */
1541 }
1542
1543 /**
1544 * @brief Regular conversion half DMA transfer callback in non blocking mode
1545 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1546 * the configuration information for the specified ADC.
1547 * @retval None
1548 */
1549 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1550 {
1551 /* Prevent unused argument(s) compilation warning */
1552 UNUSED(hadc);
1553 /* NOTE : This function Should not be modified, when the callback is needed,
1554 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
1555 */
1556 }
1557
1558 /**
1559 * @brief Analog watchdog callback in non blocking mode
1560 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1561 * the configuration information for the specified ADC.
1562 * @retval None
1563 */
1564 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1565 {
1566 /* Prevent unused argument(s) compilation warning */
1567 UNUSED(hadc);
1568 /* NOTE : This function Should not be modified, when the callback is needed,
1569 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1570 */
1571 }
1572
1573 /**
1574 * @brief Error ADC callback.
1575 * @note In case of error due to overrun when using ADC with DMA transfer
1576 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1577 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1578 * - If needed, restart a new ADC conversion using function
1579 * "HAL_ADC_Start_DMA()"
1580 * (this function is also clearing overrun flag)
1581 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1582 * the configuration information for the specified ADC.
1583 * @retval None
1584 */
1585 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1586 {
1587 /* Prevent unused argument(s) compilation warning */
1588 UNUSED(hadc);
1589 /* NOTE : This function Should not be modified, when the callback is needed,
1590 the HAL_ADC_ErrorCallback could be implemented in the user file
1591 */
1592 }
1593
1594 /**
1595 * @}
1596 */
1597
1598 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1599 * @brief Peripheral Control functions
1600 *
1601 @verbatim
1602 ===============================================================================
1603 ##### Peripheral Control functions #####
1604 ===============================================================================
1605 [..] This section provides functions allowing to:
1606 (+) Configure regular channels.
1607 (+) Configure injected channels.
1608 (+) Configure multimode.
1609 (+) Configure the analog watch dog.
1610
1611 @endverbatim
1612 * @{
1613 */
1614
1615 /**
1616 * @brief Configures for the selected ADC regular channel its corresponding
1617 * rank in the sequencer and its sample time.
1618 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1619 * the configuration information for the specified ADC.
1620 * @param sConfig ADC configuration structure.
1621 * @retval HAL status
1622 */
1623 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1624 {
1625 __IO uint32_t counter = 0;
1626
1627 /* Check the parameters */
1628 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1629 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1630 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1631
1632 /* Process locked */
1633 __HAL_LOCK(hadc);
1634
1635 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1636 if (sConfig->Channel > ADC_CHANNEL_9)
1637 {
1638 /* Clear the old sample time */
1639 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1640
1641 if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
1642 {
1643 /* Set the new sample time */
1644 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
1645 }
1646 else
1647 {
1648 /* Set the new sample time */
1649 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1650 }
1651 }
1652 else /* ADC_Channel include in ADC_Channel_[0..9] */
1653 {
1654 /* Clear the old sample time */
1655 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1656
1657 /* Set the new sample time */
1658 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1659 }
1660
1661 /* For Rank 1 to 6 */
1662 if (sConfig->Rank < 7)
1663 {
1664 /* Clear the old SQx bits for the selected rank */
1665 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1666
1667 /* Set the SQx bits for the selected rank */
1668 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1669 }
1670 /* For Rank 7 to 12 */
1671 else if (sConfig->Rank < 13)
1672 {
1673 /* Clear the old SQx bits for the selected rank */
1674 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1675
1676 /* Set the SQx bits for the selected rank */
1677 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1678 }
1679 /* For Rank 13 to 16 */
1680 else
1681 {
1682 /* Clear the old SQx bits for the selected rank */
1683 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1684
1685 /* Set the SQx bits for the selected rank */
1686 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1687 }
1688
1689 /* if ADC1 Channel_18 is selected enable VBAT Channel */
1690 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1691 {
1692 /* Enable the VBAT channel*/
1693 ADC->CCR |= ADC_CCR_VBATE;
1694 }
1695
1696 /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
1697 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1698 {
1699 /* Enable the TSVREFE channel*/
1700 ADC->CCR |= ADC_CCR_TSVREFE;
1701
1702 if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
1703 {
1704 /* Delay for temperature sensor stabilization time */
1705 /* Compute number of CPU cycles to wait for */
1706 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1707 while(counter != 0)
1708 {
1709 counter--;
1710 }
1711 }
1712 }
1713
1714 /* Process unlocked */
1715 __HAL_UNLOCK(hadc);
1716
1717 /* Return function status */
1718 return HAL_OK;
1719 }
1720
1721 /**
1722 * @brief Configures the analog watchdog.
1723 * @note Analog watchdog thresholds can be modified while ADC conversion
1724 * is on going.
1725 * In this case, some constraints must be taken into account:
1726 * the programmed threshold values are effective from the next
1727 * ADC EOC (end of unitary conversion).
1728 * Considering that registers write delay may happen due to
1729 * bus activity, this might cause an uncertainty on the
1730 * effective timing of the new programmed threshold values.
1731 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1732 * the configuration information for the specified ADC.
1733 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
1734 * that contains the configuration information of ADC analog watchdog.
1735 * @retval HAL status
1736 */
1737 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1738 {
1739 #ifdef USE_FULL_ASSERT
1740 uint32_t tmp = 0;
1741 #endif /* USE_FULL_ASSERT */
1742
1743 /* Check the parameters */
1744 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1745 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1746 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1747
1748 #ifdef USE_FULL_ASSERT
1749 tmp = ADC_GET_RESOLUTION(hadc);
1750 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1751 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1752 #endif /* USE_FULL_ASSERT */
1753
1754 /* Process locked */
1755 __HAL_LOCK(hadc);
1756
1757 if(AnalogWDGConfig->ITMode == ENABLE)
1758 {
1759 /* Enable the ADC Analog watchdog interrupt */
1760 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1761 }
1762 else
1763 {
1764 /* Disable the ADC Analog watchdog interrupt */
1765 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1766 }
1767
1768 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1769 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1770
1771 /* Set the analog watchdog enable mode */
1772 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1773
1774 /* Set the high threshold */
1775 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1776
1777 /* Set the low threshold */
1778 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1779
1780 /* Clear the Analog watchdog channel select bits */
1781 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1782
1783 /* Set the Analog watchdog channel */
1784 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1785
1786 /* Process unlocked */
1787 __HAL_UNLOCK(hadc);
1788
1789 /* Return function status */
1790 return HAL_OK;
1791 }
1792
1793 /**
1794 * @}
1795 */
1796
1797 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1798 * @brief ADC Peripheral State functions
1799 *
1800 @verbatim
1801 ===============================================================================
1802 ##### Peripheral State and errors functions #####
1803 ===============================================================================
1804 [..]
1805 This subsection provides functions allowing to
1806 (+) Check the ADC state
1807 (+) Check the ADC Error
1808
1809 @endverbatim
1810 * @{
1811 */
1812
1813 /**
1814 * @brief return the ADC state
1815 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1816 * the configuration information for the specified ADC.
1817 * @retval HAL state
1818 */
1819 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1820 {
1821 /* Return ADC state */
1822 return hadc->State;
1823 }
1824
1825 /**
1826 * @brief Return the ADC error code
1827 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1828 * the configuration information for the specified ADC.
1829 * @retval ADC Error Code
1830 */
1831 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1832 {
1833 return hadc->ErrorCode;
1834 }
1835
1836 /**
1837 * @}
1838 */
1839
1840 /**
1841 * @}
1842 */
1843
1844 /* Private functions ---------------------------------------------------------*/
1845
1846 /** @defgroup ADC_Private_Functions ADC Private Functions
1847 * @{
1848 */
1849
1850 /**
1851 * @brief Initializes the ADCx peripheral according to the specified parameters
1852 * in the ADC_InitStruct without initializing the ADC MSP.
1853 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1854 * the configuration information for the specified ADC.
1855 * @retval None
1856 */
1857 static void ADC_Init(ADC_HandleTypeDef* hadc)
1858 {
1859 /* Set ADC parameters */
1860 /* Set the ADC clock prescaler */
1861 ADC->CCR &= ~(ADC_CCR_ADCPRE);
1862 ADC->CCR |= hadc->Init.ClockPrescaler;
1863
1864 /* Set ADC scan mode */
1865 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1866 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1867
1868 /* Set ADC resolution */
1869 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1870 hadc->Instance->CR1 |= hadc->Init.Resolution;
1871
1872 /* Set ADC data alignment */
1873 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1874 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1875
1876 /* Enable external trigger if trigger selection is different of software */
1877 /* start. */
1878 /* Note: This configuration keeps the hardware feature of parameter */
1879 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1880 /* software start. */
1881 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1882 {
1883 /* Select external trigger to start conversion */
1884 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1885 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1886
1887 /* Select external trigger polarity */
1888 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1889 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1890 }
1891 else
1892 {
1893 /* Reset the external trigger */
1894 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1895 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1896 }
1897
1898 /* Enable or disable ADC continuous conversion mode */
1899 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1900 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
1901
1902 if(hadc->Init.DiscontinuousConvMode != DISABLE)
1903 {
1904 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1905
1906 /* Enable the selected ADC regular discontinuous mode */
1907 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1908
1909 /* Set the number of channels to be converted in discontinuous mode */
1910 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1911 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1912 }
1913 else
1914 {
1915 /* Disable the selected ADC regular discontinuous mode */
1916 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1917 }
1918
1919 /* Set ADC number of conversion */
1920 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1921 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1922
1923 /* Enable or disable ADC DMA continuous request */
1924 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1925 hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
1926
1927 /* Enable or disable ADC end of conversion selection */
1928 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1929 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1930 }
1931
1932 /**
1933 * @brief DMA transfer complete callback.
1934 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1935 * the configuration information for the specified DMA module.
1936 * @retval None
1937 */
1938 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1939 {
1940 /* Retrieve ADC handle corresponding to current DMA handle */
1941 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1942
1943 /* Update state machine on conversion status if not in error state */
1944 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
1945 {
1946 /* Update ADC state machine */
1947 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1948
1949 /* Determine whether any further conversion upcoming on group regular */
1950 /* by external trigger, continuous mode or scan sequence on going. */
1951 /* Note: On STM32F7, there is no independent flag of end of sequence. */
1952 /* The test of scan sequence on going is done either with scan */
1953 /* sequence disabled or with end of conversion flag set to */
1954 /* of end of sequence. */
1955 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1956 (hadc->Init.ContinuousConvMode == DISABLE) &&
1957 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1958 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1959 {
1960 /* Disable ADC end of single conversion interrupt on group regular */
1961 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1962 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1963 /* by overrun IRQ process below. */
1964 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1965
1966 /* Set ADC state */
1967 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1968
1969 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1970 {
1971 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1972 }
1973 }
1974
1975 /* Conversion complete callback */
1976 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1977 hadc->ConvCpltCallback(hadc);
1978 #else
1979 HAL_ADC_ConvCpltCallback(hadc);
1980 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1981 }
1982 else /* DMA and-or internal error occurred */
1983 {
1984 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
1985 {
1986 /* Call HAL ADC Error Callback function */
1987 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1988 hadc->ErrorCallback(hadc);
1989 #else
1990 HAL_ADC_ErrorCallback(hadc);
1991 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1992 }
1993 else
1994 {
1995 /* Call DMA error callback */
1996 hadc->DMA_Handle->XferErrorCallback(hdma);
1997 }
1998 }
1999 }
2000
2001 /**
2002 * @brief DMA half transfer complete callback.
2003 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2004 * the configuration information for the specified DMA module.
2005 * @retval None
2006 */
2007 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2008 {
2009 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2010 /* Half conversion callback */
2011 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2012 hadc->ConvHalfCpltCallback(hadc);
2013 #else
2014 HAL_ADC_ConvHalfCpltCallback(hadc);
2015 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2016 }
2017
2018 /**
2019 * @brief DMA error callback
2020 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2021 * the configuration information for the specified DMA module.
2022 * @retval None
2023 */
2024 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2025 {
2026 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2027 hadc->State= HAL_ADC_STATE_ERROR_DMA;
2028 /* Set ADC error code to DMA error */
2029 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
2030 /* Error callback */
2031 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2032 hadc->ErrorCallback(hadc);
2033 #else
2034 HAL_ADC_ErrorCallback(hadc);
2035 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2036 }
2037
2038 /**
2039 * @}
2040 */
2041
2042 /**
2043 * @}
2044 */
2045
2046 #endif /* HAL_ADC_MODULE_ENABLED */
2047 /**
2048 * @}
2049 */
2050
2051 /**
2052 * @}
2053 */
2054
2055 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/