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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_cryp.c
blob36892d6297ffd6db6bd788476145751003716537
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization, de-initialization, set config and get config functions
9 * + DES/TDES, AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
20
21 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
22 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
23 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
24 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
25 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
26 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
27 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
28 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
29 (+++) Configure and enable two DMA streams one for managing data transfer from
30 memory to peripheral (input stream) and another stream for managing data
31 transfer from peripheral to memory (output stream)
32 (+++) Associate the initialized DMA handle to the CRYP DMA handle
33 using __HAL_LINKDMA()
34 (+++) Configure the priority and enable the NVIC for the transfer complete
35 interrupt on the two DMA Streams. The output stream should have higher
36 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
37
38 (#)Initialize the CRYP according to the specified parameters :
39 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
40 (##) The key size: 128, 192 or 256.
41 (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
42 (##) The initialization vector (counter). It is not used in ECB mode.
43 (##) The key buffer used for encryption/decryption.
44 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
45 (##) The HeaderSize The size of header buffer in word.
46 (##) The B0 block is the first authentication block used only in AES CCM mode.
47
48 (#)Three processing (encryption/decryption) functions are available:
49 (##) Polling mode: encryption and decryption APIs are blocking functions
50 i.e. they process the data and wait till the processing is finished,
51 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
52 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
53 i.e. they process the data under interrupt,
54 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
55 (##) DMA mode: encryption and decryption APIs are not blocking functions
56 i.e. the data transfer is ensured by DMA,
57 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
58
59 (#)When the processing function is called at first time after HAL_CRYP_Init()
60 the CRYP peripheral is configured and processes the buffer in input.
61 At second call, no need to Initialize the CRYP, user have to get current configuration via
62 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
63 new parametres, finally user can start encryption/decryption.
64
65 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
66
67 [..]
68 The cryptographic processor supports following standards:
69 (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
70 (##)64-bit data block processing
71 (##) chaining modes supported :
72 (+++) Electronic Code Book(ECB)
73 (+++) Cipher Block Chaining (CBC)
74 (##) keys length supported :64-bit, 128-bit and 192-bit.
75 (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
76 (##)128-bit data block processing
77 (##) chaining modes supported :
78 (+++) Electronic Code Book(ECB)
79 (+++) Cipher Block Chaining (CBC)
80 (+++) Counter mode (CTR)
81 (+++) Galois/counter mode (GCM/GMAC)
82 (+++) Counter with Cipher Block Chaining-Message(CCM)
83 (##) keys length Supported :
84 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
85 (+++) for TinyAES IP: 128-bit and 256-bit
86
87 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
88 (#) Algorithm supported :
89 (##) Galois/counter mode (GCM)
90 (##) Galois message authentication code (GMAC) :is exactly the same as
91 GCM algorithm composed only by an header.
92 (#) Four phases are performed in GCM :
93 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
94 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
95 computation only.
96 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
97 encryption + data XORing. It works in a similar way for ciphertext (C).
98 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
99 (#) structure of message construction in GCM is defined as below :
100 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
101 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
102 this part of the message is only authenticated, not encrypted.
103 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
104 GCM standard specifies that ciphertext has same bit length as the plaintext.
105 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
106 (on 64 bits)
107
108 [..] This section describe The AES Counter with Cipher Block Chaining-Message
109 Authentication Code (CCM) supported by both CRYP1 IP:
110 (#) Specific parameters for CCM :
111
112 (##) B0 block : According to NIST Special Publication 800-38C,
113 The first block B0 is formatted as follows, where l(m) is encoded in
114 most-significant-byte first order(see below table 3)
115
116 (+++) Q: a bit string representation of the octet length of P (plaintext)
117 (+++) q The octet length of the binary representation of the octet length of the payload
118 (+++) A nonce (N), n The octet length of the where n+q=15.
119 (+++) Flags: most significant octet containing four flags for control information,
120 (+++) t The octet length of the MAC.
121 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
122 the associated data length expressed in bytes (a) defined as below:
123 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
124 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
125 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
126 (##) CTRx block : control blocks
127 (+++) Generation of CTR1 from first block B0 information :
128 equal to B0 with first 5 bits zeroed and most significant bits storing octet
129 length of P also zeroed, then incremented by one ( see below Table 4)
130 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
131
132 (#) Four phases are performed in CCM for CRYP1 IP:
133 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
134 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
135 computation only.
136 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
137 encryption + data XORing. It works in a similar way for ciphertext (C).
138 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
139
140 *** Callback registration ***
141 =============================================
142
143 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
144 allows the user to configure dynamically the driver callbacks.
145 Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
146 to register an interrupt callback.
147
148 Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
149 (+) InCpltCallback : Input FIFO transfer completed callback.
150 (+) OutCpltCallback : Output FIFO transfer completed callback.
151 (+) ErrorCallback : callback for error detection.
152 (+) MspInitCallback : CRYP MspInit.
153 (+) MspDeInitCallback : CRYP MspDeInit.
154 This function takes as parameters the HAL peripheral handle, the Callback ID
155 and a pointer to the user callback function.
156
157 Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
158 weak function.
159 @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
160 and the Callback ID.
161 This function allows to reset following callbacks:
162 (+) InCpltCallback : Input FIFO transfer completed callback.
163 (+) OutCpltCallback : Output FIFO transfer completed callback.
164 (+) ErrorCallback : callback for error detection.
165 (+) MspInitCallback : CRYP MspInit.
166 (+) MspDeInitCallback : CRYP MspDeInit.
167
168 By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
169 all callbacks are set to the corresponding weak functions :
170 examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
171 Exception done for MspInit and MspDeInit functions that are
172 reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
173 these callbacks are null (not registered beforehand).
174 if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
175 keep and use the user MspInit/MspDeInit functions (registered beforehand)
176
177 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
178 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
179 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
180 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
181 In that case first register the MspInit/MspDeInit user callbacks
182 using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
183 or @ref HAL_CRYP_Init() function.
184
185 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
186 not defined, the callback registration feature is not available and all callbacks
187 are set to the corresponding weak functions.
188
189 Table 1. Initial Counter Block (ICB)
190 +-------------------------------------------------------+
191 | Initialization vector (IV) | Counter |
192 |----------------|----------------|-----------|---------|
193 127 95 63 31 0
194
195
196 Bit Number Register Contents
197 ---------- --------------- -----------
198 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
199 95 ...64 CRYP_IV1L[31:0] B0[95:64]
200 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
201 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
202
203 Table 2. GCM last block definition
204
205 +-------------------------------------------------------------------+
206 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
207 |-----------|--------------------|-----------|----------------------|
208 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
209 |-----------|--------------------|-----------|----------------------|
210
211 Table 3. B0 block
212 Octet Number Contents
213 ------------ ---------
214 0 Flags
215 1 ... 15-q Nonce N
216 16-q ... 15 Q
217
218 the Flags field is formatted as follows:
219
220 Bit Number Contents
221 ---------- ----------------------
222 7 Reserved (always zero)
223 6 Adata
224 5 ... 3 (t-2)/2
225 2 ... 0 [q-1]3
226
227 Table 4. CTRx block
228 Bit Number Register Contents
229 ---------- --------------- -----------
230 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
231 bit 0 that is set to 1
232 95 ...64 CRYP_IV1L[31:0] B0[95:64]
233 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
234 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
235
236 @endverbatim
237 ******************************************************************************
238 * @attention
239 *
240 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
241 * All rights reserved.</center></h2>
242 *
243 * This software component is licensed by ST under BSD 3-Clause license,
244 * the "License"; You may not use this file except in compliance with the
245 * License. You may obtain a copy of the License at:
246 * opensource.org/licenses/BSD-3-Clause
247 *
248 ******************************************************************************
249 */
250
251 /* Includes ------------------------------------------------------------------*/
252 #include "stm32f7xx_hal.h"
253
254 /** @addtogroup STM32F7xx_HAL_Driver
255 * @{
256 */
257
258 #if defined (AES) || defined (CRYP)
259
260 /** @defgroup CRYP CRYP
261 * @brief CRYP HAL module driver.
262 * @{
263 */
264
265
266 #ifdef HAL_CRYP_MODULE_ENABLED
267
268 /* Private typedef -----------------------------------------------------------*/
269 /* Private define ------------------------------------------------------------*/
270 /** @addtogroup CRYP_Private_Defines
271 * @{
272 */
273 #define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
274 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
275 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
276
277 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
278 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
279
280 #if defined(AES)
281 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
282 #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
283 #define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
284 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
285 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
286 #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
287 #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
288 #define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
289 #else /* CRYP */
290 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
291 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
292 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
293 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
294 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
295 #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
296 #endif /* End CRYP or AES */
297
298 /* CTR1 information to use in CCM algorithm */
299 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
300 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
301 #define CRYP_CCM_CTR1_2 0x00000001U
302
303
304 /**
305 * @}
306 */
307
308
309 /* Private macro -------------------------------------------------------------*/
310 /** @addtogroup CRYP_Private_Macros
311 * @{
312 */
313
314 #if defined(CRYP)
315
316 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
317 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
318 }while(0)
319
320 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
321
322 #else /*AES*/
323 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
324 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
325 }while(0)
326 #endif /* End AES or CRYP*/
327
328
329 /**
330 * @}
331 */
332
333 /* Private struct -------------------------------------------------------------*/
334 /* Private variables ---------------------------------------------------------*/
335 /* Private function prototypes -----------------------------------------------*/
336 /** @addtogroup CRYP_Private_Functions_prototypes
337 * @{
338 */
339
340 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
341 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
342 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
343 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
344 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
345 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
346
347 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
348 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
349 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
350 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
351 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
352 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
353 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
354 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
355 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
356 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
357 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
358
359 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
360 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
363 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
364 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
365 #if defined (CRYP)
366 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
367
368 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
369
370 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
371 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
372 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
373 #else /*AES*/
374 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375 #endif /* End CRYP or AES */
376
377 /**
378 * @}
379 */
380
381 /* Exported functions ---------------------------------------------------------*/
382
383 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
384 * @{
385 */
386
387
388 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
389 * @brief Initialization and Configuration functions.
390 *
391 @verbatim
392 ========================================================================================
393 ##### Initialization, de-initialization and Set and Get configuration functions #####
394 ========================================================================================
395 [..] This section provides functions allowing to:
396 (+) Initialize the CRYP
397 (+) DeInitialize the CRYP
398 (+) Initialize the CRYP MSP
399 (+) DeInitialize the CRYP MSP
400 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
401 Parameters which are configured in This section are :
402 (+) Key size
403 (+) Data Type : 32,16, 8 or 1bit
404 (+) AlgoMode :
405 - for CRYP1 IP :
406 ECB and CBC in DES/TDES Standard
407 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
408 - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
409 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
410
411
412 @endverbatim
413 * @{
414 */
415
416
417 /**
418 * @brief Initializes the CRYP according to the specified
419 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
420 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
421 * the configuration information for CRYP module
422 * @retval HAL status
423 */
424 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
425 {
426 /* Check the CRYP handle allocation */
427 if(hcryp == NULL)
428 {
429 return HAL_ERROR;
430 }
431
432 /* Check parameters */
433 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
434 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
435 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
436
437 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
438 if(hcryp->State == HAL_CRYP_STATE_RESET)
439 {
440 /* Allocate lock resource and initialize it */
441 hcryp->Lock = HAL_UNLOCKED;
442
443 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
444 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
445 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
446
447 if(hcryp->MspInitCallback == NULL)
448 {
449 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
450 }
451
452 /* Init the low level hardware */
453 hcryp->MspInitCallback(hcryp);
454 }
455 #else
456 if(hcryp->State == HAL_CRYP_STATE_RESET)
457 {
458 /* Allocate lock resource and initialize it */
459 hcryp->Lock = HAL_UNLOCKED;
460
461 /* Init the low level hardware */
462 HAL_CRYP_MspInit(hcryp);
463 }
464 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
465
466 /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type and Algorithm */
467 #if defined (CRYP)
468
469 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
470
471 #else /*AES*/
472
473 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
474
475 #endif /* End AES or CRYP*/
476
477 /* Reset Error Code field */
478 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
479
480 /* Change the CRYP state */
481 hcryp->State = HAL_CRYP_STATE_READY;
482
483 /* Set the default CRYP phase */
484 hcryp->Phase = CRYP_PHASE_READY;
485
486 /* Return function status */
487 return HAL_OK;
488 }
489
490 /**
491 * @brief De-Initializes the CRYP peripheral.
492 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
493 * the configuration information for CRYP module
494 * @retval HAL status
495 */
496 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
497 {
498 /* Check the CRYP handle allocation */
499 if(hcryp == NULL)
500 {
501 return HAL_ERROR;
502 }
503
504 /* Set the default CRYP phase */
505 hcryp->Phase = CRYP_PHASE_READY;
506
507 /* Reset CrypInCount and CrypOutCount */
508 hcryp->CrypInCount = 0;
509 hcryp->CrypOutCount = 0;
510 hcryp->CrypHeaderCount =0;
511
512 /* Disable the CRYP peripheral clock */
513 __HAL_CRYP_DISABLE(hcryp);
514
515 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
516
517 if(hcryp->MspDeInitCallback == NULL)
518 {
519 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
520 }
521 /* DeInit the low level hardware */
522 hcryp->MspDeInitCallback(hcryp);
523
524 #else
525
526 /* DeInit the low level hardware: CLOCK, NVIC.*/
527 HAL_CRYP_MspDeInit(hcryp);
528
529 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
530
531 /* Change the CRYP state */
532 hcryp->State = HAL_CRYP_STATE_RESET;
533
534 /* Release Lock */
535 __HAL_UNLOCK(hcryp);
536
537 /* Return function status */
538 return HAL_OK;
539 }
540
541 /**
542 * @brief Configure the CRYP according to the specified
543 * parameters in the CRYP_ConfigTypeDef
544 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
545 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
546 * the configuration information for CRYP module
547 * @retval HAL status
548 */
549 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
550 {
551 /* Check the CRYP handle allocation */
552 if((hcryp == NULL)|| (pConf == NULL) )
553 {
554 return HAL_ERROR;
555 }
556
557 /* Check parameters */
558 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
559 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
560 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
561
562 if(hcryp->State == HAL_CRYP_STATE_READY)
563 {
564 /* Change the CRYP state */
565 hcryp->State = HAL_CRYP_STATE_BUSY;
566
567 /* Process locked */
568 __HAL_LOCK(hcryp);
569
570 /* Set CRYP parameters */
571 hcryp->Init.DataType = pConf->DataType;
572 hcryp->Init.pKey = pConf->pKey;
573 hcryp->Init.Algorithm = pConf->Algorithm;
574 hcryp->Init.KeySize = pConf->KeySize;
575 hcryp->Init.pInitVect = pConf->pInitVect;
576 hcryp->Init.Header = pConf->Header;
577 hcryp->Init.HeaderSize = pConf->HeaderSize;
578 hcryp->Init.B0 = pConf->B0;
579 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
580
581 /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
582 #if defined (CRYP)
583
584 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
585
586 #else /*AES*/
587 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
588
589 /*clear error flags*/
590 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR);
591
592 #endif /* End AES or CRYP */
593
594 /* Process Unlocked */
595 __HAL_UNLOCK(hcryp);
596
597 /* Reset Error Code field */
598 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
599
600 /* Change the CRYP state */
601 hcryp->State = HAL_CRYP_STATE_READY;
602
603 /* Set the default CRYP phase */
604 hcryp->Phase = CRYP_PHASE_READY;
605
606 /* Return function status */
607 return HAL_OK;
608 }
609 else
610 {
611 /* Process Unlocked */
612 __HAL_UNLOCK(hcryp);
613
614 /* Busy error code field */
615 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
616 return HAL_ERROR;
617 }
618 }
619
620 /**
621 * @brief Get CRYP Configuration parameters in associated handle.
622 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
623 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
624 * the configuration information for CRYP module
625 * @retval HAL status
626 */
627 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
628 {
629 /* Check the CRYP handle allocation */
630 if((hcryp == NULL)|| (pConf == NULL) )
631 {
632 return HAL_ERROR;
633 }
634
635 if(hcryp->State == HAL_CRYP_STATE_READY)
636 {
637 /* Change the CRYP state */
638 hcryp->State = HAL_CRYP_STATE_BUSY;
639
640 /* Process locked */
641 __HAL_LOCK(hcryp);
642
643 /* Get CRYP parameters */
644 pConf->DataType = hcryp->Init.DataType;
645 pConf->pKey = hcryp->Init.pKey;
646 pConf->Algorithm = hcryp->Init.Algorithm;
647 pConf->KeySize = hcryp->Init.KeySize ;
648 pConf->pInitVect = hcryp->Init.pInitVect;
649 pConf->Header = hcryp->Init.Header ;
650 pConf->HeaderSize = hcryp->Init.HeaderSize;
651 pConf->B0 = hcryp->Init.B0;
652 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
653
654 /* Process Unlocked */
655 __HAL_UNLOCK(hcryp);
656
657 /* Change the CRYP state */
658 hcryp->State = HAL_CRYP_STATE_READY;
659
660 /* Return function status */
661 return HAL_OK;
662 }
663 else
664 {
665 /* Process Unlocked */
666 __HAL_UNLOCK(hcryp);
667
668 /* Busy error code field */
669 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
670 return HAL_ERROR;
671 }
672 }
673 /**
674 * @brief Initializes the CRYP MSP.
675 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
676 * the configuration information for CRYP module
677 * @retval None
678 */
679 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
680 {
681 /* Prevent unused argument(s) compilation warning */
682 UNUSED(hcryp);
683
684 /* NOTE : This function Should not be modified, when the callback is needed,
685 the HAL_CRYP_MspInit could be implemented in the user file
686 */
687 }
688
689 /**
690 * @brief DeInitializes CRYP MSP.
691 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
692 * the configuration information for CRYP module
693 * @retval None
694 */
695 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
696 {
697 /* Prevent unused argument(s) compilation warning */
698 UNUSED(hcryp);
699
700 /* NOTE : This function Should not be modified, when the callback is needed,
701 the HAL_CRYP_MspDeInit could be implemented in the user file
702 */
703 }
704
705 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
706 /**
707 * @brief Register a User CRYP Callback
708 * To be used instead of the weak predefined callback
709 * @param hcryp cryp handle
710 * @param CallbackID ID of the callback to be registered
711 * This parameter can be one of the following values:
712 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
713 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
714 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
715 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
716 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
717 * @param pCallback pointer to the Callback function
718 * @retval status
719 */
720 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
721 {
722 HAL_StatusTypeDef status = HAL_OK;
723
724 if(pCallback == NULL)
725 {
726 /* Update the error code */
727 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
728
729 return HAL_ERROR;
730 }
731 /* Process locked */
732 __HAL_LOCK(hcryp);
733
734 if(hcryp->State == HAL_CRYP_STATE_READY)
735 {
736 switch (CallbackID)
737 {
738 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
739 hcryp->InCpltCallback = pCallback;
740 break;
741
742 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
743 hcryp->OutCpltCallback = pCallback;
744 break;
745
746 case HAL_CRYP_ERROR_CB_ID :
747 hcryp->ErrorCallback = pCallback;
748 break;
749
750 case HAL_CRYP_MSPINIT_CB_ID :
751 hcryp->MspInitCallback = pCallback;
752 break;
753
754 case HAL_CRYP_MSPDEINIT_CB_ID :
755 hcryp->MspDeInitCallback = pCallback;
756 break;
757
758 default :
759 /* Update the error code */
760 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
761 /* Return error status */
762 status = HAL_ERROR;
763 break;
764 }
765 }
766 else if(hcryp->State == HAL_CRYP_STATE_RESET)
767 {
768 switch (CallbackID)
769 {
770 case HAL_CRYP_MSPINIT_CB_ID :
771 hcryp->MspInitCallback = pCallback;
772 break;
773
774 case HAL_CRYP_MSPDEINIT_CB_ID :
775 hcryp->MspDeInitCallback = pCallback;
776 break;
777
778 default :
779 /* Update the error code */
780 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
781 /* Return error status */
782 status = HAL_ERROR;
783 break;
784 }
785 }
786 else
787 {
788 /* Update the error code */
789 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
790 /* Return error status */
791 status = HAL_ERROR;
792 }
793
794 /* Release Lock */
795 __HAL_UNLOCK(hcryp);
796
797 return status;
798 }
799
800 /**
801 * @brief Unregister an CRYP Callback
802 * CRYP callback is redirected to the weak predefined callback
803 * @param hcryp cryp handle
804 * @param CallbackID ID of the callback to be unregistered
805 * This parameter can be one of the following values:
806 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
807 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
808 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
809 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
810 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
811 * @retval status
812 */
813 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
814 {
815 HAL_StatusTypeDef status = HAL_OK;
816
817 /* Process locked */
818 __HAL_LOCK(hcryp);
819
820 if(hcryp->State == HAL_CRYP_STATE_READY)
821 {
822 switch (CallbackID)
823 {
824 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
825 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
826 break;
827
828 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
829 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
830 break;
831
832 case HAL_CRYP_ERROR_CB_ID :
833 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
834 break;
835
836 case HAL_CRYP_MSPINIT_CB_ID :
837 hcryp->MspInitCallback = HAL_CRYP_MspInit;
838 break;
839
840 case HAL_CRYP_MSPDEINIT_CB_ID :
841 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
842 break;
843
844 default :
845 /* Update the error code */
846 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
847 /* Return error status */
848 status = HAL_ERROR;
849 break;
850 }
851 }
852 else if(hcryp->State == HAL_CRYP_STATE_RESET)
853 {
854 switch (CallbackID)
855 {
856 case HAL_CRYP_MSPINIT_CB_ID :
857 hcryp->MspInitCallback = HAL_CRYP_MspInit;
858 break;
859
860 case HAL_CRYP_MSPDEINIT_CB_ID :
861 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
862 break;
863
864 default :
865 /* Update the error code */
866 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
867 /* Return error status */
868 status = HAL_ERROR;
869 break;
870 }
871 }
872 else
873 {
874 /* Update the error code */
875 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
876 /* Return error status */
877 status = HAL_ERROR;
878 }
879
880 /* Release Lock */
881 __HAL_UNLOCK(hcryp);
882
883 return status;
884 }
885 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
886 /**
887 * @}
888 */
889
890 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
891 * @brief processing functions.
892 *
893 @verbatim
894 ==============================================================================
895 ##### Encrypt Decrypt functions #####
896 ==============================================================================
897 [..] This section provides API allowing to Encrypt/Decrypt Data following
898 Standard DES/TDES or AES, and Algorithm configured by the user:
899 (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
900 - Electronic Code Book(ECB)
901 - Cipher Block Chaining (CBC)
902 (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
903 - Electronic Code Book(ECB)
904 - Cipher Block Chaining (CBC)
905 - Counter mode (CTR)
906 - Cipher Block Chaining (CBC)
907 - Counter mode (CTR)
908 - Galois/counter mode (GCM)
909 - Counter with Cipher Block Chaining-Message(CCM)
910 [..] Three processing functions are available:
911 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
912 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
913 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
914
915 @endverbatim
916 * @{
917 */
918
919
920 /**
921 * @brief Encryption mode.
922 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
923 * the configuration information for CRYP module
924 * @param Input: Pointer to the input buffer (plaintext)
925 * @param Size: Length of the plaintext buffer in word.
926 * @param Output: Pointer to the output buffer(ciphertext)
927 * @param Timeout: Specify Timeout value
928 * @retval HAL status
929 */
930 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
931 {
932 uint32_t algo;
933 HAL_StatusTypeDef status;
934
935 if(hcryp->State == HAL_CRYP_STATE_READY)
936 {
937 /* Change state Busy */
938 hcryp->State = HAL_CRYP_STATE_BUSY;
939
940 /* Process locked */
941 __HAL_LOCK(hcryp);
942
943 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
944 hcryp->CrypInCount = 0U;
945 hcryp->CrypOutCount = 0U;
946 hcryp->pCrypInBuffPtr = Input;
947 hcryp->pCrypOutBuffPtr = Output;
948
949 /* Calculate Size parameter in Byte*/
950 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
951 {
952 hcryp->Size = Size * 4U;
953 }
954 else
955 {
956 hcryp->Size = Size;
957 }
958
959 #if defined (CRYP)
960 /* Set Encryption operating mode*/
961 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
962
963 /* algo get algorithm selected */
964 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
965
966 switch(algo)
967 {
968 case CRYP_DES_ECB:
969 case CRYP_DES_CBC:
970 case CRYP_TDES_ECB:
971 case CRYP_TDES_CBC:
972
973 /*Set Key */
974 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
975 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
976 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
977 {
978 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
979 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
980 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
981 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
982 }
983
984 /*Set Initialization Vector (IV)*/
985 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
986 {
987 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
988 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
989 }
990
991 /* Flush FIFO */
992 HAL_CRYP_FIFO_FLUSH(hcryp);
993
994 /* Set the phase */
995 hcryp->Phase = CRYP_PHASE_PROCESS;
996
997 /* Statrt DES/TDES encryption process */
998 status = CRYP_TDES_Process(hcryp,Timeout);
999 break;
1000
1001 case CRYP_AES_ECB:
1002 case CRYP_AES_CBC:
1003 case CRYP_AES_CTR:
1004
1005 /* AES encryption */
1006 status = CRYP_AES_Encrypt(hcryp, Timeout);
1007 break;
1008
1009 case CRYP_AES_GCM:
1010
1011 /* AES GCM encryption */
1012 status = CRYP_AESGCM_Process(hcryp, Timeout);
1013
1014 break;
1015
1016 case CRYP_AES_CCM:
1017
1018 /* AES CCM encryption */
1019 status = CRYP_AESCCM_Process(hcryp,Timeout);
1020 break;
1021
1022 default:
1023 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1024 return HAL_ERROR;
1025 }
1026
1027 #else /*AES*/
1028
1029 /* Set the operating mode*/
1030 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1031
1032 /* algo get algorithm selected */
1033 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1034
1035 switch(algo)
1036 {
1037
1038 case CRYP_AES_ECB:
1039 case CRYP_AES_CBC:
1040 case CRYP_AES_CTR:
1041
1042 /* AES encryption */
1043 status = CRYP_AES_Encrypt(hcryp, Timeout);
1044 break;
1045
1046 case CRYP_AES_GCM_GMAC:
1047
1048 /* AES GCM encryption */
1049 status = CRYP_AESGCM_Process (hcryp,Timeout) ;
1050 break;
1051
1052 case CRYP_AES_CCM:
1053
1054 /* AES CCM encryption */
1055 status = CRYP_AESCCM_Process(hcryp,Timeout);
1056 break;
1057
1058 default:
1059 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1060 return HAL_ERROR;
1061 }
1062 #endif /*end AES or CRYP */
1063
1064 if (status == HAL_OK)
1065 {
1066 /* Change the CRYP peripheral state */
1067 hcryp->State = HAL_CRYP_STATE_READY;
1068
1069 /* Process unlocked */
1070 __HAL_UNLOCK(hcryp);
1071 }
1072 }
1073 else
1074 {
1075 /* Busy error code field */
1076 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1077 return HAL_ERROR;
1078 }
1079
1080 /* Return function status */
1081 return HAL_OK;
1082 }
1083
1084 /**
1085 * @brief Decryption mode.
1086 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1087 * the configuration information for CRYP module
1088 * @param Input: Pointer to the input buffer (ciphertext )
1089 * @param Size: Length of the plaintext buffer in word.
1090 * @param Output: Pointer to the output buffer(plaintext)
1091 * @param Timeout: Specify Timeout value
1092 * @retval HAL status
1093 */
1094 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
1095 {
1096 HAL_StatusTypeDef status;
1097 uint32_t algo;
1098
1099 if(hcryp->State == HAL_CRYP_STATE_READY)
1100 {
1101 /* Change state Busy */
1102 hcryp->State = HAL_CRYP_STATE_BUSY;
1103
1104 /* Process locked */
1105 __HAL_LOCK(hcryp);
1106
1107 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1108 hcryp->CrypInCount = 0U;
1109 hcryp->CrypOutCount = 0U;
1110 hcryp->pCrypInBuffPtr = Input;
1111 hcryp->pCrypOutBuffPtr = Output;
1112
1113 /* Calculate Size parameter in Byte*/
1114 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1115 {
1116 hcryp->Size = Size * 4U;
1117 }
1118 else
1119 {
1120 hcryp->Size = Size;
1121 }
1122
1123 #if defined (CRYP)
1124
1125 /* Set Decryption operating mode*/
1126 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1127
1128 /* algo get algorithm selected */
1129 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1130
1131 switch(algo)
1132 {
1133 case CRYP_DES_ECB:
1134 case CRYP_DES_CBC:
1135 case CRYP_TDES_ECB:
1136 case CRYP_TDES_CBC:
1137
1138 /*Set Key */
1139 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
1140 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
1141 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1142 {
1143 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
1144 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
1145 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
1146 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
1147 }
1148
1149 /*Set Initialization Vector (IV)*/
1150 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1151 {
1152 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1153 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1154 }
1155
1156 /* Flush FIFO */
1157 HAL_CRYP_FIFO_FLUSH(hcryp);
1158
1159 /* Set the phase */
1160 hcryp->Phase = CRYP_PHASE_PROCESS;
1161
1162 /* Start DES/TDES decryption process */
1163 status = CRYP_TDES_Process(hcryp, Timeout);
1164
1165 break;
1166
1167 case CRYP_AES_ECB:
1168 case CRYP_AES_CBC:
1169 case CRYP_AES_CTR:
1170
1171 /* AES decryption */
1172 status = CRYP_AES_Decrypt(hcryp, Timeout);
1173 break;
1174
1175 case CRYP_AES_GCM:
1176
1177 /* AES GCM decryption */
1178 status = CRYP_AESGCM_Process (hcryp, Timeout) ;
1179 break;
1180
1181 case CRYP_AES_CCM:
1182
1183 /* AES CCM decryption */
1184 status = CRYP_AESCCM_Process(hcryp, Timeout);
1185 break;
1186
1187 default:
1188 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1189 return HAL_ERROR;
1190 }
1191
1192 #else /*AES*/
1193
1194 /* Set Decryption operating mode*/
1195 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1196
1197 /* algo get algorithm selected */
1198 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1199
1200 switch(algo)
1201 {
1202
1203 case CRYP_AES_ECB:
1204 case CRYP_AES_CBC:
1205 case CRYP_AES_CTR:
1206
1207 /* AES decryption */
1208 status = CRYP_AES_Decrypt(hcryp, Timeout);
1209 break;
1210
1211 case CRYP_AES_GCM_GMAC:
1212
1213 /* AES GCM decryption */
1214 status = CRYP_AESGCM_Process (hcryp, Timeout) ;
1215 break;
1216
1217 case CRYP_AES_CCM:
1218
1219 /* AES CCM decryption */
1220 status = CRYP_AESCCM_Process(hcryp, Timeout);
1221 break;
1222
1223 default:
1224 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1225 return HAL_ERROR;
1226 }
1227 #endif /* End AES or CRYP */
1228
1229 if (status == HAL_OK)
1230 {
1231 /* Change the CRYP peripheral state */
1232 hcryp->State = HAL_CRYP_STATE_READY;
1233
1234 /* Process unlocked */
1235 __HAL_UNLOCK(hcryp);
1236 }
1237 }
1238 else
1239 {
1240 /* Busy error code field */
1241 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1242 return HAL_ERROR;
1243 }
1244
1245 /* Return function status */
1246 return HAL_OK;
1247 }
1248
1249 /**
1250 * @brief Encryption in interrupt mode.
1251 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1252 * the configuration information for CRYP module
1253 * @param Input: Pointer to the input buffer (plaintext)
1254 * @param Size: Length of the plaintext buffer in word
1255 * @param Output: Pointer to the output buffer(ciphertext)
1256 * @retval HAL status
1257 */
1258 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1259 {
1260 uint32_t algo;
1261 HAL_StatusTypeDef status = HAL_OK;
1262
1263 if(hcryp->State == HAL_CRYP_STATE_READY)
1264 {
1265 /* Change state Busy */
1266 hcryp->State = HAL_CRYP_STATE_BUSY;
1267
1268 /* Process locked */
1269 __HAL_LOCK(hcryp);
1270
1271 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1272 hcryp->CrypInCount = 0U;
1273 hcryp->CrypOutCount = 0U;
1274 hcryp->pCrypInBuffPtr = Input;
1275 hcryp->pCrypOutBuffPtr = Output;
1276
1277 /* Calculate Size parameter in Byte*/
1278 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1279 {
1280 hcryp->Size = Size * 4U;
1281 }
1282 else
1283 {
1284 hcryp->Size = Size;
1285 }
1286
1287 #if defined (CRYP)
1288
1289 /* Set encryption operating mode*/
1290 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1291
1292 /* algo get algorithm selected */
1293 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1294
1295 switch(algo)
1296 {
1297 case CRYP_DES_ECB:
1298 case CRYP_DES_CBC:
1299 case CRYP_TDES_ECB:
1300 case CRYP_TDES_CBC:
1301
1302 /*Set Key */
1303 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
1304 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
1305 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1306 {
1307 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
1308 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
1309 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
1310 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
1311 }
1312 /* Set the Initialization Vector*/
1313 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1314 {
1315 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1316 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1317 }
1318
1319 /* Flush FIFO */
1320 HAL_CRYP_FIFO_FLUSH(hcryp);
1321
1322 /* Set the phase */
1323 hcryp->Phase = CRYP_PHASE_PROCESS;
1324
1325 /* Enable interrupts */
1326 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1327
1328 /* Enable CRYP to start DES/TDES process*/
1329 __HAL_CRYP_ENABLE(hcryp);
1330 break;
1331
1332 case CRYP_AES_ECB:
1333 case CRYP_AES_CBC:
1334 case CRYP_AES_CTR:
1335
1336 status = CRYP_AES_Encrypt_IT(hcryp);
1337 break;
1338
1339 case CRYP_AES_GCM:
1340
1341 status = CRYP_AESGCM_Process_IT (hcryp) ;
1342 break;
1343
1344 case CRYP_AES_CCM:
1345
1346 status = CRYP_AESCCM_Process_IT(hcryp);
1347 break;
1348
1349 default:
1350 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1351 status = HAL_ERROR;
1352 break;
1353 }
1354
1355 #else /* AES */
1356
1357 /* Set encryption operating mode*/
1358 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1359
1360 /* algo get algorithm selected */
1361 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1362
1363 switch(algo)
1364 {
1365 case CRYP_AES_ECB:
1366 case CRYP_AES_CBC:
1367 case CRYP_AES_CTR:
1368
1369 /* AES encryption */
1370 status = CRYP_AES_Encrypt_IT(hcryp);
1371 break;
1372
1373 case CRYP_AES_GCM_GMAC:
1374
1375 /* AES GCM encryption */
1376 status = CRYP_AESGCM_Process_IT (hcryp) ;
1377 break;
1378
1379 case CRYP_AES_CCM:
1380
1381 /* AES CCM encryption */
1382 status = CRYP_AESCCM_Process_IT(hcryp);
1383 break;
1384
1385 default:
1386 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1387 status = HAL_ERROR;
1388 break;
1389 }
1390 #endif /*end AES or CRYP*/
1391
1392 }
1393 else
1394 {
1395 /* Busy error code field */
1396 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1397 status = HAL_ERROR;
1398 }
1399
1400 /* Return function status */
1401 return status;
1402 }
1403
1404 /**
1405 * @brief Decryption in itnterrupt mode.
1406 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1407 * the configuration information for CRYP module
1408 * @param Input: Pointer to the input buffer (ciphertext )
1409 * @param Size: Length of the plaintext buffer in word.
1410 * @param Output: Pointer to the output buffer(plaintext)
1411 * @retval HAL status
1412 */
1413 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1414 {
1415 uint32_t algo;
1416 HAL_StatusTypeDef status = HAL_OK;
1417
1418 if(hcryp->State == HAL_CRYP_STATE_READY)
1419 {
1420 /* Change state Busy */
1421 hcryp->State = HAL_CRYP_STATE_BUSY;
1422
1423 /* Process locked */
1424 __HAL_LOCK(hcryp);
1425
1426 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1427 hcryp->CrypInCount = 0U;
1428 hcryp->CrypOutCount = 0U;
1429 hcryp->pCrypInBuffPtr = Input;
1430 hcryp->pCrypOutBuffPtr = Output;
1431
1432 /* Calculate Size parameter in Byte*/
1433 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1434 {
1435 hcryp->Size = Size * 4U;
1436 }
1437 else
1438 {
1439 hcryp->Size = Size;
1440 }
1441
1442 #if defined (CRYP)
1443
1444 /* Set decryption operating mode*/
1445 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
1446
1447 /* algo get algorithm selected */
1448 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1449
1450 switch(algo)
1451 {
1452 case CRYP_DES_ECB:
1453 case CRYP_DES_CBC:
1454 case CRYP_TDES_ECB:
1455 case CRYP_TDES_CBC:
1456
1457 /*Set Key */
1458 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
1459 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
1460 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1461 {
1462 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
1463 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
1464 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
1465 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
1466 }
1467
1468 /* Set the Initialization Vector*/
1469 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1470 {
1471 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1472 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1473 }
1474 /* Flush FIFO */
1475 HAL_CRYP_FIFO_FLUSH(hcryp);
1476
1477 /* Set the phase */
1478 hcryp->Phase = CRYP_PHASE_PROCESS;
1479
1480 /* Enable interrupts */
1481 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1482
1483 /* Enable CRYP and start DES/TDES process*/
1484 __HAL_CRYP_ENABLE(hcryp);
1485
1486 break;
1487
1488 case CRYP_AES_ECB:
1489 case CRYP_AES_CBC:
1490 case CRYP_AES_CTR:
1491
1492 /* AES decryption */
1493 status = CRYP_AES_Decrypt_IT(hcryp);
1494 break;
1495
1496 case CRYP_AES_GCM:
1497
1498 /* AES GCM decryption */
1499 status = CRYP_AESGCM_Process_IT (hcryp) ;
1500 break;
1501
1502 case CRYP_AES_CCM:
1503
1504 /* AES CCMdecryption */
1505 status = CRYP_AESCCM_Process_IT(hcryp);
1506 break;
1507
1508 default:
1509 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1510 status = HAL_ERROR;
1511 break;
1512 }
1513
1514 #else /*AES*/
1515
1516 /* Set decryption operating mode*/
1517 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1518
1519 /* algo get algorithm selected */
1520 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1521
1522 switch(algo)
1523 {
1524 case CRYP_AES_ECB:
1525 case CRYP_AES_CBC:
1526 case CRYP_AES_CTR:
1527
1528 /* AES decryption */
1529 status = CRYP_AES_Decrypt_IT(hcryp);
1530 break;
1531
1532 case CRYP_AES_GCM_GMAC:
1533
1534 /* AES GCM decryption */
1535 status = CRYP_AESGCM_Process_IT (hcryp) ;
1536 break;
1537
1538 case CRYP_AES_CCM:
1539
1540 /* AES CCM decryption */
1541 status = CRYP_AESCCM_Process_IT(hcryp);
1542 break;
1543
1544 default:
1545 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1546 status = HAL_ERROR;
1547 break;
1548 }
1549 #endif /* End AES or CRYP */
1550
1551 }
1552 else
1553 {
1554 /* Busy error code field */
1555 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1556 status = HAL_ERROR;
1557 }
1558
1559 /* Return function status */
1560 return status;
1561 }
1562
1563 /**
1564 * @brief Encryption in DMA mode.
1565 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1566 * the configuration information for CRYP module
1567 * @param Input: Pointer to the input buffer (plaintext)
1568 * @param Size: Length of the plaintext buffer in word.
1569 * @param Output: Pointer to the output buffer(ciphertext)
1570 * @retval HAL status
1571 */
1572 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1573 {
1574 uint32_t algo;
1575 HAL_StatusTypeDef status = HAL_OK;
1576
1577 if(hcryp->State == HAL_CRYP_STATE_READY)
1578 {
1579 /* Change state Busy */
1580 hcryp->State = HAL_CRYP_STATE_BUSY;
1581
1582 /* Process locked */
1583 __HAL_LOCK(hcryp);
1584
1585 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1586 hcryp->CrypInCount = 0U;
1587 hcryp->CrypOutCount = 0U;
1588 hcryp->pCrypInBuffPtr = Input;
1589 hcryp->pCrypOutBuffPtr = Output;
1590
1591 /* Calculate Size parameter in Byte*/
1592 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1593 {
1594 hcryp->Size = Size * 4U;
1595 }
1596 else
1597 {
1598 hcryp->Size = Size;
1599 }
1600
1601 #if defined (CRYP)
1602
1603 /* Set encryption operating mode*/
1604 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1605
1606 /* algo get algorithm selected */
1607 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1608
1609 switch(algo)
1610 {
1611 case CRYP_DES_ECB:
1612 case CRYP_DES_CBC:
1613 case CRYP_TDES_ECB:
1614 case CRYP_TDES_CBC:
1615
1616 /*Set Key */
1617 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
1618 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
1619 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1620 {
1621 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
1622 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
1623 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
1624 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
1625 }
1626
1627 /* Set the Initialization Vector*/
1628 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1629 {
1630 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1631 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1632 }
1633
1634 /* Flush FIFO */
1635 HAL_CRYP_FIFO_FLUSH(hcryp);
1636
1637 /* Set the phase */
1638 hcryp->Phase = CRYP_PHASE_PROCESS;
1639
1640 /* Start DMA process transfer for DES/TDES */
1641 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1642 break;
1643
1644 case CRYP_AES_ECB:
1645 case CRYP_AES_CBC:
1646 case CRYP_AES_CTR:
1647
1648 /* Set the Key*/
1649 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1650
1651 /* Set the Initialization Vector IV */
1652 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1653 {
1654 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1655 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1656 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
1657 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
1658 }
1659 /* Set the phase */
1660 hcryp->Phase = CRYP_PHASE_PROCESS;
1661
1662 /* Start DMA process transfer for AES */
1663 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1664 break;
1665
1666 case CRYP_AES_GCM:
1667 /* AES GCM encryption */
1668 status = CRYP_AESGCM_Process_DMA (hcryp) ;
1669 break;
1670
1671 case CRYP_AES_CCM:
1672 /* AES CCM encryption */
1673 status = CRYP_AESCCM_Process_DMA(hcryp);
1674 break;
1675
1676 default:
1677 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1678 status = HAL_ERROR;
1679 break;
1680 }
1681
1682 #else /*AES*/
1683 /* Set encryption operating mode*/
1684 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1685
1686 /* algo get algorithm selected */
1687 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1688
1689 switch(algo)
1690 {
1691
1692 case CRYP_AES_ECB:
1693 case CRYP_AES_CBC:
1694 case CRYP_AES_CTR:
1695
1696 /* Set the Key*/
1697 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1698
1699 /* Set the Initialization Vector*/
1700 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1701 {
1702 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
1703 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
1704 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
1705 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
1706 }
1707
1708 /* Set the phase */
1709 hcryp->Phase = CRYP_PHASE_PROCESS;
1710
1711 /* Start DMA process transfer for AES */
1712 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1713 break;
1714
1715 case CRYP_AES_GCM_GMAC:
1716 /* AES GCM encryption */
1717 status = CRYP_AESGCM_Process_DMA (hcryp) ;
1718 break;
1719
1720 case CRYP_AES_CCM:
1721 /* AES CCM encryption */
1722 status = CRYP_AESCCM_Process_DMA(hcryp);
1723 break;
1724
1725 default:
1726 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1727 status = HAL_ERROR;
1728 break;
1729 }
1730 #endif /* End AES or CRYP */
1731
1732 }
1733 else
1734 {
1735 /* Busy error code field */
1736 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1737 status = HAL_ERROR;
1738 }
1739
1740 /* Return function status */
1741 return status;
1742 }
1743
1744 /**
1745 * @brief Decryption in DMA mode.
1746 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1747 * the configuration information for CRYP module
1748 * @param Input: Pointer to the input buffer (ciphertext )
1749 * @param Size: Length of the plaintext buffer in word
1750 * @param Output: Pointer to the output buffer(plaintext)
1751 * @retval HAL status
1752 */
1753 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1754 {
1755 uint32_t algo;
1756 HAL_StatusTypeDef status = HAL_OK;
1757
1758 if(hcryp->State == HAL_CRYP_STATE_READY)
1759 {
1760
1761 /* Change state Busy */
1762 hcryp->State = HAL_CRYP_STATE_BUSY;
1763
1764 /* Process locked */
1765 __HAL_LOCK(hcryp);
1766
1767 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1768 hcryp->CrypInCount = 0U;
1769 hcryp->CrypOutCount = 0U;
1770 hcryp->pCrypInBuffPtr = Input;
1771 hcryp->pCrypOutBuffPtr = Output;
1772
1773 /* Calculate Size parameter in Byte*/
1774 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1775 {
1776 hcryp->Size = Size * 4U;
1777 }
1778 else
1779 {
1780 hcryp->Size = Size;
1781 }
1782
1783 #if defined (CRYP)
1784
1785 /* Set decryption operating mode*/
1786 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1787
1788 /* algo get algorithm selected */
1789 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1790
1791 switch(algo)
1792 {
1793 case CRYP_DES_ECB:
1794 case CRYP_DES_CBC:
1795 case CRYP_TDES_ECB:
1796 case CRYP_TDES_CBC:
1797
1798 /*Set Key */
1799 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
1800 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
1801 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1802 {
1803 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
1804 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
1805 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
1806 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
1807 }
1808
1809 /* Set the Initialization Vector*/
1810 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1811 {
1812 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
1813 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
1814 }
1815
1816 /* Flush FIFO */
1817 HAL_CRYP_FIFO_FLUSH(hcryp);
1818
1819 /* Set the phase */
1820 hcryp->Phase = CRYP_PHASE_PROCESS;
1821
1822 /* Start DMA process transfer for DES/TDES */
1823 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1824 break;
1825
1826 case CRYP_AES_ECB:
1827 case CRYP_AES_CBC:
1828 case CRYP_AES_CTR:
1829
1830 /* AES decryption */
1831 status = CRYP_AES_Decrypt_DMA(hcryp);
1832 break;
1833
1834 case CRYP_AES_GCM:
1835 /* AES GCM decryption */
1836 status = CRYP_AESGCM_Process_DMA (hcryp) ;
1837 break;
1838
1839 case CRYP_AES_CCM:
1840 /* AES CCM decryption */
1841 status = CRYP_AESCCM_Process_DMA(hcryp);
1842 break;
1843
1844 default:
1845 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1846 status = HAL_ERROR;
1847 break;
1848 }
1849
1850 #else /*AES*/
1851
1852 /* Set decryption operating mode*/
1853 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1854
1855 /* algo get algorithm selected */
1856 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1857
1858 switch(algo)
1859 {
1860
1861 case CRYP_AES_ECB:
1862 case CRYP_AES_CBC:
1863 case CRYP_AES_CTR:
1864
1865 /* AES decryption */
1866 status = CRYP_AES_Decrypt_DMA(hcryp);
1867 break;
1868
1869 case CRYP_AES_GCM_GMAC:
1870 /* AES GCM decryption */
1871 status = CRYP_AESGCM_Process_DMA (hcryp) ;
1872 break;
1873
1874 case CRYP_AES_CCM:
1875 /* AES CCM decryption */
1876 status = CRYP_AESCCM_Process_DMA(hcryp);
1877 break;
1878
1879 default:
1880 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1881 status = HAL_ERROR;
1882 break;
1883 }
1884 #endif /* End AES or CRYP */
1885 }
1886 else
1887 {
1888 /* Busy error code field */
1889 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1890 status = HAL_ERROR;
1891 }
1892
1893 /* Return function status */
1894 return status;
1895 }
1896
1897 /**
1898 * @}
1899 */
1900
1901 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
1902 * @brief CRYP IRQ handler.
1903 *
1904 @verbatim
1905 ==============================================================================
1906 ##### CRYP IRQ handler management #####
1907 ==============================================================================
1908 [..] This section provides CRYP IRQ handler and callback functions.
1909 (+) HAL_CRYP_IRQHandler CRYP interrupt request
1910 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
1911 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
1912 (+) HAL_CRYP_ErrorCallback CRYP error callback
1913 (+) HAL_CRYP_GetState return the CRYP state
1914 (+) HAL_CRYP_GetError return the CRYP error code
1915 @endverbatim
1916 * @{
1917 */
1918
1919 /**
1920 * @brief This function handles cryptographic interrupt request.
1921 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1922 * the configuration information for CRYP module
1923 * @retval None
1924 */
1925 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
1926 {
1927
1928 #if defined (CRYP)
1929
1930 if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U))
1931 {
1932 if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1933 {
1934 CRYP_TDES_IT(hcryp); /* DES or TDES*/
1935 }
1936 else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
1937 {
1938 CRYP_AES_IT(hcryp); /*AES*/
1939 }
1940
1941 else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
1942 {
1943 /* if header phase */
1944 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
1945 {
1946 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
1947 }
1948 else /* if payload phase */
1949 {
1950 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
1951 }
1952 }
1953
1954 else
1955 {
1956 /* Nothing to do */
1957 }
1958 }
1959
1960 #else /*AES*/
1961 if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U))
1962 {
1963
1964 /* Clear computation complete flag */
1965 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
1966
1967 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
1968 {
1969
1970 /* if header phase */
1971 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
1972 {
1973 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
1974 }
1975 else /* if payload phase */
1976 {
1977 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
1978 }
1979 }
1980 else if(hcryp->Init.Algorithm == CRYP_AES_CCM)
1981 {
1982 /* if header phase */
1983 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount )
1984 {
1985 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
1986 }
1987 else /* if payload phase */
1988 {
1989 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
1990 }
1991 }
1992 else /* AES Algorithm ECB,CBC or CTR*/
1993 {
1994 CRYP_AES_IT(hcryp);
1995 }
1996 }
1997 /* Check if error occurred */
1998 if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
1999 {
2000 /* If write Error occurred */
2001 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
2002 {
2003 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2004 }
2005 /* If read Error occurred */
2006 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
2007 {
2008 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2009 }
2010 }
2011 #endif /* End AES or CRYP */
2012 }
2013
2014 /**
2015 * @brief Return the CRYP error code.
2016 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2017 * the configuration information for the CRYP IP
2018 * @retval CRYP error code
2019 */
2020 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2021 {
2022 return hcryp->ErrorCode;
2023 }
2024
2025 /**
2026 * @brief Returns the CRYP state.
2027 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2028 * the configuration information for CRYP module.
2029 * @retval HAL state
2030 */
2031 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2032 {
2033 return hcryp->State;
2034 }
2035
2036 /**
2037 * @brief Input FIFO transfer completed callback.
2038 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2039 * the configuration information for CRYP module.
2040 * @retval None
2041 */
2042 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2043 {
2044 /* Prevent unused argument(s) compilation warning */
2045 UNUSED(hcryp);
2046
2047 /* NOTE : This function Should not be modified, when the callback is needed,
2048 the HAL_CRYP_InCpltCallback could be implemented in the user file
2049 */
2050 }
2051
2052 /**
2053 * @brief Output FIFO transfer completed callback.
2054 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2055 * the configuration information for CRYP module.
2056 * @retval None
2057 */
2058 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2059 {
2060 /* Prevent unused argument(s) compilation warning */
2061 UNUSED(hcryp);
2062
2063 /* NOTE : This function Should not be modified, when the callback is needed,
2064 the HAL_CRYP_OutCpltCallback could be implemented in the user file
2065 */
2066 }
2067
2068 /**
2069 * @brief CRYP error callback.
2070 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2071 * the configuration information for CRYP module.
2072 * @retval None
2073 */
2074 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2075 {
2076 /* Prevent unused argument(s) compilation warning */
2077 UNUSED(hcryp);
2078
2079 /* NOTE : This function Should not be modified, when the callback is needed,
2080 the HAL_CRYP_ErrorCallback could be implemented in the user file
2081 */
2082 }
2083 /**
2084 * @}
2085 */
2086
2087 /* Private functions ---------------------------------------------------------*/
2088 /** @addtogroup CRYP_Private_Functions
2089 * @{
2090 */
2091
2092 #if defined (CRYP)
2093
2094 /**
2095 * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
2096 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2097 * the configuration information for CRYP module
2098 * @param Timeout: specify Timeout value
2099 * @retval HAL status
2100 */
2101 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2102 {
2103 uint32_t temp; /* Temporary CrypOutBuff */
2104 uint16_t incount; /* Temporary CrypInCount Value */
2105 uint16_t outcount; /* Temporary CrypOutCount Value */
2106
2107 /* Enable CRYP */
2108 __HAL_CRYP_ENABLE(hcryp);
2109 /*Temporary CrypOutCount Value*/
2110 outcount = hcryp->CrypOutCount;
2111
2112 /*Start processing*/
2113 while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
2114 {
2115 /* Temporary CrypInCount Value */
2116 incount = hcryp->CrypInCount;
2117 /* Write plain data and get cipher data */
2118 if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
2119 {
2120 /* Write the input block in the IN FIFO */
2121 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2122 hcryp->CrypInCount++;
2123 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2124 hcryp->CrypInCount++;
2125 }
2126
2127 /* Wait for OFNE flag to be raised */
2128 if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2129 {
2130 /* Disable the CRYP peripheral clock */
2131 __HAL_CRYP_DISABLE(hcryp);
2132
2133 /* Change state & errorCode*/
2134 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2135 hcryp->State = HAL_CRYP_STATE_READY;
2136
2137 /* Process unlocked */
2138 __HAL_UNLOCK(hcryp);
2139 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2140 /*Call registered error callback*/
2141 hcryp->ErrorCallback(hcryp);
2142 #else
2143 /*Call legacy weak error callback*/
2144 HAL_CRYP_ErrorCallback(hcryp);
2145 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2146 }
2147
2148 /*Temporary CrypOutCount Value*/
2149 outcount = hcryp->CrypOutCount;
2150
2151 if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
2152 {
2153 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2154 temp = hcryp->Instance->DOUT;
2155 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
2156 hcryp->CrypOutCount++;
2157 temp = hcryp->Instance->DOUT;
2158 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
2159 hcryp->CrypOutCount++;
2160 }
2161 /*Temporary CrypOutCount Value*/
2162 outcount = hcryp->CrypOutCount;
2163 }
2164 /* Disable CRYP */
2165 __HAL_CRYP_DISABLE(hcryp);
2166 /* Change the CRYP state */
2167 hcryp->State = HAL_CRYP_STATE_READY;
2168
2169 /* Return function status */
2170 return HAL_OK;
2171 }
2172
2173 /**
2174 * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
2175 * @note The function is called under interruption only, once
2176 * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
2177 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2178 * the configuration information for CRYP module.
2179 * @retval none
2180 */
2181 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2182 {
2183 uint32_t temp; /* Temporary CrypOutBuff */
2184
2185 if(hcryp->State == HAL_CRYP_STATE_BUSY)
2186 {
2187 if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
2188
2189 {
2190 /* Write input block in the IN FIFO */
2191 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2192 hcryp->CrypInCount++;
2193 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2194 hcryp->CrypInCount++;
2195
2196 if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
2197 {
2198 /* Disable interruption */
2199 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2200 /* Call the input data transfer complete callback */
2201 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2202 /*Call registered Input complete callback*/
2203 hcryp->InCpltCallback(hcryp);
2204 #else
2205 /*Call legacy weak Input complete callback*/
2206 HAL_CRYP_InCpltCallback(hcryp);
2207 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2208 }
2209 }
2210 if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
2211 {
2212 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2213 temp = hcryp->Instance->DOUT;
2214 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
2215 hcryp->CrypOutCount++;
2216 temp = hcryp->Instance->DOUT;
2217 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
2218 hcryp->CrypOutCount++;
2219 if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
2220 {
2221 /* Disable interruption */
2222 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2223
2224 /* Disable CRYP */
2225 __HAL_CRYP_DISABLE(hcryp);
2226
2227 /* Process unlocked */
2228 __HAL_UNLOCK(hcryp);
2229
2230 /* Change the CRYP state */
2231 hcryp->State = HAL_CRYP_STATE_READY;
2232 /* Call output transfer complete callback */
2233 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2234 /*Call registered Output complete callback*/
2235 hcryp->OutCpltCallback(hcryp);
2236 #else
2237 /*Call legacy weak Output complete callback*/
2238 HAL_CRYP_OutCpltCallback(hcryp);
2239 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2240 }
2241 }
2242 }
2243 else
2244 {
2245 /* Process unlocked */
2246 __HAL_UNLOCK(hcryp);
2247 /* Busy error code field */
2248 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2249 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2250 /*Call registered error callback*/
2251 hcryp->ErrorCallback(hcryp);
2252 #else
2253 /*Call legacy weak error callback*/
2254 HAL_CRYP_ErrorCallback(hcryp);
2255 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2256 }
2257 }
2258
2259 #endif /* CRYP */
2260
2261 /**
2262 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2263 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2264 * @param Timeout: specify Timeout value
2265 * @retval HAL status
2266 */
2267 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2268 {
2269 uint16_t outcount; /* Temporary CrypOutCount Value */
2270
2271 /* Set the Key*/
2272 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2273
2274 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2275 {
2276 /* Set the Initialization Vector*/
2277 #if defined (AES)
2278 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
2279 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
2280 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
2281 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
2282 #else /* CRYP */
2283 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
2284 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
2285 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
2286 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
2287 #endif /* End AES or CRYP */
2288 }
2289
2290 /* Set the phase */
2291 hcryp->Phase = CRYP_PHASE_PROCESS;
2292
2293 /* Enable CRYP */
2294 __HAL_CRYP_ENABLE(hcryp);
2295
2296 /*Temporary CrypOutCount Value*/
2297 outcount = hcryp->CrypOutCount;
2298
2299 while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
2300 {
2301 /* Write plain Ddta and get cipher data */
2302 CRYP_AES_ProcessData(hcryp,Timeout);
2303 /*Temporary CrypOutCount Value*/
2304 outcount = hcryp->CrypOutCount;
2305 }
2306
2307 /* Disable CRYP */
2308 __HAL_CRYP_DISABLE(hcryp);
2309
2310 /* Change the CRYP state */
2311 hcryp->State = HAL_CRYP_STATE_READY;
2312
2313 /* Return function status */
2314 return HAL_OK;
2315 }
2316
2317 /**
2318 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2319 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2320 * the configuration information for CRYP module
2321 * @retval HAL status
2322 */
2323 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2324 {
2325
2326 /* Set the Key*/
2327 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2328
2329 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2330 {
2331 /* Set the Initialization Vector*/
2332 #if defined (AES)
2333 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
2334 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
2335 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
2336 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
2337
2338 #else /* CRYP */
2339 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
2340 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
2341 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
2342 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
2343 #endif /* End AES or CRYP */
2344 }
2345 /* Set the phase */
2346 hcryp->Phase = CRYP_PHASE_PROCESS;
2347
2348 if(hcryp->Size != 0U)
2349 {
2350 #if defined (AES)
2351
2352 /* Enable computation complete flag and error interrupts */
2353 __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2354
2355 /* Enable CRYP */
2356 __HAL_CRYP_ENABLE(hcryp);
2357
2358 /* Write the input block in the IN FIFO */
2359 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2360 hcryp->CrypInCount++;
2361 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2362 hcryp->CrypInCount++;
2363 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2364 hcryp->CrypInCount++;
2365 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2366 hcryp->CrypInCount++;
2367
2368 #else /* CRYP */
2369
2370 /* Enable interrupts */
2371 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2372
2373 /* Enable CRYP */
2374 __HAL_CRYP_ENABLE(hcryp);
2375
2376 #endif /* End AES or CRYP */
2377 }
2378 else
2379 {
2380 /* Change the CRYP state */
2381 hcryp->State = HAL_CRYP_STATE_READY;
2382
2383 /* Process unlocked */
2384 __HAL_UNLOCK(hcryp);
2385 }
2386
2387 /* Return function status */
2388 return HAL_OK;
2389 }
2390
2391 /**
2392 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2393 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2394 * @param Timeout: Specify Timeout value
2395 * @retval HAL status
2396 */
2397 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
2398 {
2399 uint16_t outcount; /* Temporary CrypOutCount Value */
2400
2401 /* Key preparation for ECB/CBC */
2402 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2403 {
2404 #if defined (AES)
2405 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2406 {
2407 /* Set key preparation for decryption operating mode*/
2408 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2409
2410 /* Set the Key*/
2411 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2412
2413 /* Enable CRYP */
2414 __HAL_CRYP_ENABLE(hcryp);
2415
2416 /* Wait for CCF flag to be raised */
2417 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2418 {
2419 /* Disable the CRYP peripheral clock */
2420 __HAL_CRYP_DISABLE(hcryp);
2421
2422 /* Change state & error code*/
2423 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2424 hcryp->State = HAL_CRYP_STATE_READY;
2425
2426 /* Process unlocked */
2427 __HAL_UNLOCK(hcryp);
2428 return HAL_ERROR;
2429 }
2430 /* Clear CCF Flag */
2431 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2432
2433 /* Return to decryption operating mode(Mode 3)*/
2434 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2435 }
2436 else /*Mode 4 : decryption & Key preparation*/
2437 {
2438 /* Set the Key*/
2439 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2440
2441 /* Set decryption & Key preparation operating mode*/
2442 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2443 }
2444 #else /* CRYP */
2445 /* change ALGOMODE to key preparation for decryption*/
2446 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
2447
2448 /* Set the Key*/
2449 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2450
2451 /* Enable CRYP */
2452 __HAL_CRYP_ENABLE(hcryp);
2453
2454 /* Wait for BUSY flag to be raised */
2455 if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2456 {
2457 /* Disable the CRYP peripheral clock */
2458 __HAL_CRYP_DISABLE(hcryp);
2459
2460 /* Change state */
2461 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2462 hcryp->State = HAL_CRYP_STATE_READY;
2463
2464 /* Process unlocked */
2465 __HAL_UNLOCK(hcryp);
2466 return HAL_ERROR;
2467 }
2468 /* Turn back to ALGOMODE of the configuration */
2469 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
2470
2471 #endif /* End AES or CRYP */
2472 }
2473 else /*Algorithm CTR */
2474 {
2475 /* Set the Key*/
2476 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2477 }
2478
2479 /* Set IV */
2480 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2481 {
2482 /* Set the Initialization Vector*/
2483 #if defined (AES)
2484 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
2485 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
2486 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
2487 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
2488 #else /* CRYP */
2489 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
2490 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
2491 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
2492 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
2493 #endif /* End AES or CRYP */
2494 }
2495 /* Set the phase */
2496 hcryp->Phase = CRYP_PHASE_PROCESS;
2497
2498 /* Enable CRYP */
2499 __HAL_CRYP_ENABLE(hcryp);
2500
2501 /*Temporary CrypOutCount Value*/
2502 outcount = hcryp->CrypOutCount;
2503
2504 while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
2505 {
2506 /* Write plain data and get cipher data */
2507 CRYP_AES_ProcessData(hcryp,Timeout);
2508 /*Temporary CrypOutCount Value*/
2509 outcount = hcryp->CrypOutCount;
2510 }
2511
2512 /* Disable CRYP */
2513 __HAL_CRYP_DISABLE(hcryp);
2514
2515 /* Change the CRYP state */
2516 hcryp->State = HAL_CRYP_STATE_READY;
2517
2518 /* Return function status */
2519 return HAL_OK;
2520 }
2521 /**
2522 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2523 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2524 * the configuration information for CRYP module
2525 * @retval HAL status
2526 */
2527 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2528 {
2529 __IO uint32_t count = 0U;
2530
2531 /* Key preparation for ECB/CBC */
2532 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2533 {
2534 #if defined (AES)
2535 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2536 {
2537 /* Set key preparation for decryption operating mode*/
2538 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2539
2540 /* Set the Key*/
2541 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2542
2543 /* Enable CRYP */
2544 __HAL_CRYP_ENABLE(hcryp);
2545
2546 /* Wait for CCF flag to be raised */
2547 count = CRYP_TIMEOUT_KEYPREPARATION;
2548 do
2549 {
2550 count-- ;
2551 if(count == 0U)
2552 {
2553 /* Disable the CRYP peripheral clock */
2554 __HAL_CRYP_DISABLE(hcryp);
2555
2556 /* Change state */
2557 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2558 hcryp->State = HAL_CRYP_STATE_READY;
2559
2560 /* Process unlocked */
2561 __HAL_UNLOCK(hcryp);
2562 return HAL_ERROR;
2563 }
2564 }
2565 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2566
2567 /* Clear CCF Flag */
2568 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2569
2570 /* Return to decryption operating mode(Mode 3)*/
2571 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2572 }
2573 else /*Mode 4 : decryption & key preparation*/
2574 {
2575 /* Set the Key*/
2576 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2577
2578 /* Set decryption & key preparation operating mode*/
2579 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2580 }
2581 #else /* CRYP */
2582
2583 /* change ALGOMODE to key preparation for decryption*/
2584 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
2585
2586 /* Set the Key*/
2587 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2588
2589 /* Enable CRYP */
2590 __HAL_CRYP_ENABLE(hcryp);
2591
2592 /* Wait for BUSY flag to be raised */
2593 count = CRYP_TIMEOUT_KEYPREPARATION;
2594 do
2595 {
2596 count-- ;
2597 if(count == 0U)
2598 {
2599 /* Change state */
2600 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2601 hcryp->State = HAL_CRYP_STATE_READY;
2602
2603 /* Process unlocked */
2604 __HAL_UNLOCK(hcryp);
2605 return HAL_ERROR;
2606 }
2607 }
2608 while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2609
2610 /* Turn back to ALGOMODE of the configuration */
2611 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
2612
2613 #endif /* End AES or CRYP */
2614 }
2615
2616 else /*Algorithm CTR */
2617 {
2618 /* Set the Key*/
2619 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2620 }
2621
2622 /* Set IV */
2623 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2624 {
2625 /* Set the Initialization Vector*/
2626 #if defined (AES)
2627 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
2628 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
2629 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
2630 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
2631 #else /* CRYP */
2632 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
2633 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
2634 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
2635 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
2636 #endif /* End AES or CRYP */
2637 }
2638 /* Set the phase */
2639 hcryp->Phase = CRYP_PHASE_PROCESS;
2640 if(hcryp->Size != 0U)
2641 {
2642
2643 #if defined (AES)
2644
2645 /* Enable computation complete flag and error interrupts */
2646 __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2647
2648 /* Enable CRYP */
2649 __HAL_CRYP_ENABLE(hcryp);
2650
2651 /* Write the input block in the IN FIFO */
2652 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2653 hcryp->CrypInCount++;
2654 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2655 hcryp->CrypInCount++;
2656 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2657 hcryp->CrypInCount++;
2658 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2659 hcryp->CrypInCount++;
2660
2661 #else /* CRYP */
2662
2663 /* Enable interrupts */
2664 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2665
2666 /* Enable CRYP */
2667 __HAL_CRYP_ENABLE(hcryp);
2668
2669 #endif /* End AES or CRYP */
2670 }
2671 else
2672 {
2673 /* Process locked */
2674 __HAL_UNLOCK(hcryp);
2675
2676 /* Change the CRYP state */
2677 hcryp->State = HAL_CRYP_STATE_READY;
2678 }
2679
2680 /* Return function status */
2681 return HAL_OK;
2682 }
2683 /**
2684 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2685 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2686 * the configuration information for CRYP module
2687 * @retval HAL status
2688 */
2689 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2690 {
2691 __IO uint32_t count = 0U;
2692
2693 /* Key preparation for ECB/CBC */
2694 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2695 {
2696 #if defined (AES)
2697 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2698 {
2699 /* Set key preparation for decryption operating mode*/
2700 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2701
2702 /* Set the Key*/
2703 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2704
2705 /* Enable CRYP */
2706 __HAL_CRYP_ENABLE(hcryp);
2707
2708 /* Wait for CCF flag to be raised */
2709 count = CRYP_TIMEOUT_KEYPREPARATION;
2710 do
2711 {
2712 count-- ;
2713 if(count == 0U)
2714 {
2715 /* Disable the CRYP peripheral clock */
2716 __HAL_CRYP_DISABLE(hcryp);
2717
2718 /* Change state */
2719 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2720 hcryp->State = HAL_CRYP_STATE_READY;
2721
2722 /* Process unlocked */
2723 __HAL_UNLOCK(hcryp);
2724 return HAL_ERROR;
2725 }
2726 }
2727 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2728
2729 /* Clear CCF Flag */
2730 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2731
2732 /* Return to decryption operating mode(Mode 3)*/
2733 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2734 }
2735 else /*Mode 4 : decryption & key preparation*/
2736 {
2737 /* Set the Key*/
2738 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2739
2740 /* Set decryption & Key preparation operating mode*/
2741 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2742 }
2743 #else /* CRYP */
2744 /* change ALGOMODE to key preparation for decryption*/
2745 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
2746
2747 /* Set the Key*/
2748 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2749
2750 /* Enable CRYP */
2751 __HAL_CRYP_ENABLE(hcryp);
2752
2753 /* Wait for BUSY flag to be raised */
2754 count = CRYP_TIMEOUT_KEYPREPARATION;
2755 do
2756 {
2757 count-- ;
2758 if(count == 0U)
2759 {
2760 /* Disable the CRYP peripheral clock */
2761 __HAL_CRYP_DISABLE(hcryp);
2762
2763 /* Change state */
2764 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2765 hcryp->State = HAL_CRYP_STATE_READY;
2766
2767 /* Process unlocked */
2768 __HAL_UNLOCK(hcryp);
2769 return HAL_ERROR;
2770 }
2771 }
2772 while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2773
2774 /* Turn back to ALGOMODE of the configuration */
2775 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
2776
2777 #endif /* End AES or CRYP */
2778 }
2779 else /*Algorithm CTR */
2780 {
2781 /* Set the Key*/
2782 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2783 }
2784
2785 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2786 {
2787 /* Set the Initialization Vector*/
2788 #if defined (AES)
2789 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
2790 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
2791 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
2792 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
2793 #else /* CRYP */
2794 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
2795 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
2796 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
2797 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
2798 #endif /* End AES or CRYP */
2799 }
2800 /* Set the phase */
2801 hcryp->Phase = CRYP_PHASE_PROCESS;
2802
2803 if(hcryp->Size != 0U)
2804 {
2805 /* Set the input and output addresses and start DMA transfer */
2806 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
2807 }
2808 else
2809 {
2810 /* Process unlocked */
2811 __HAL_UNLOCK(hcryp);
2812
2813 /* Change the CRYP state */
2814 hcryp->State = HAL_CRYP_STATE_READY;
2815 }
2816
2817 /* Return function status */
2818 return HAL_OK;
2819 }
2820
2821
2822 /**
2823 * @brief DMA CRYP input data process complete callback.
2824 * @param hdma: DMA handle
2825 * @retval None
2826 */
2827 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
2828 {
2829 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2830
2831 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
2832 in the DMACR register */
2833 #if defined (CRYP)
2834 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
2835
2836 #else /* AES */
2837 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
2838
2839 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
2840 if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
2841 {
2842 /* Clear CCF flag */
2843 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
2844
2845 /* Change the CRYP state to ready */
2846 hcryp->State = HAL_CRYP_STATE_READY;
2847
2848 /* Process Unlocked */
2849 __HAL_UNLOCK(hcryp);
2850 }
2851 #endif /* End AES or CRYP */
2852
2853 /* Call input data transfer complete callback */
2854 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2855 /*Call registered Input complete callback*/
2856 hcryp->InCpltCallback(hcryp);
2857 #else
2858 /*Call legacy weak Input complete callback*/
2859 HAL_CRYP_InCpltCallback(hcryp);
2860 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2861 }
2862
2863 /**
2864 * @brief DMA CRYP output data process complete callback.
2865 * @param hdma: DMA handle
2866 * @retval None
2867 */
2868 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
2869 {
2870 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2871
2872 /* Disable the DMA transfer for output FIFO request by resetting
2873 the DOEN bit in the DMACR register */
2874
2875 #if defined (CRYP)
2876
2877 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
2878 if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
2879 {
2880 /* Disable CRYP (not allowed in GCM)*/
2881 __HAL_CRYP_DISABLE(hcryp);
2882 }
2883 #else /* AES */
2884
2885 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
2886
2887 /* Clear CCF flag */
2888 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
2889
2890 if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
2891 {
2892 /* Disable CRYP (not allowed in GCM)*/
2893 __HAL_CRYP_DISABLE(hcryp);
2894 }
2895 #endif /* End AES or CRYP */
2896
2897 /* Change the CRYP state to ready */
2898 hcryp->State = HAL_CRYP_STATE_READY;
2899
2900 /* Process unlocked */
2901 __HAL_UNLOCK(hcryp);
2902 /* Call output data transfer complete callback */
2903 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2904 /*Call registered Output complete callback*/
2905 hcryp->OutCpltCallback(hcryp);
2906 #else
2907 /*Call legacy weak Output complete callback*/
2908 HAL_CRYP_OutCpltCallback(hcryp);
2909 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2910 }
2911
2912 /**
2913 * @brief DMA CRYP communication error callback.
2914 * @param hdma: DMA handle
2915 * @retval None
2916 */
2917 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
2918 {
2919 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2920
2921 /* Change the CRYP peripheral state */
2922 hcryp->State= HAL_CRYP_STATE_READY;
2923
2924 /* DMA error code field */
2925 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2926
2927 #if defined (AES)
2928
2929 /* Clear CCF flag */
2930 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
2931
2932 #endif /* AES */
2933
2934 /* Call error callback */
2935 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2936 /*Call registered error callback*/
2937 hcryp->ErrorCallback(hcryp);
2938 #else
2939 /*Call legacy weak error callback*/
2940 HAL_CRYP_ErrorCallback(hcryp);
2941 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2942 }
2943
2944 /**
2945 * @brief Set the DMA configuration and start the DMA transfer
2946 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2947 * the configuration information for CRYP module
2948 * @param inputaddr: address of the input buffer
2949 * @param Size: size of the input buffer, must be a multiple of 16.
2950 * @param outputaddr: address of the output buffer
2951 * @retval None
2952 */
2953 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2954 {
2955 /* Set the CRYP DMA transfer complete callback */
2956 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
2957
2958 /* Set the DMA input error callback */
2959 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
2960
2961 /* Set the CRYP DMA transfer complete callback */
2962 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
2963
2964 /* Set the DMA output error callback */
2965 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
2966
2967 #if defined (CRYP)
2968
2969 /* Enable CRYP */
2970 __HAL_CRYP_ENABLE(hcryp);
2971
2972 /* Enable the input DMA Stream */
2973 if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
2974 {
2975 /* DMA error code field */
2976 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2977
2978 /* Call error callback */
2979 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2980 /*Call registered error callback*/
2981 hcryp->ErrorCallback(hcryp);
2982 #else
2983 /*Call legacy weak error callback*/
2984 HAL_CRYP_ErrorCallback(hcryp);
2985 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2986 }
2987 /* Enable the output DMA Stream */
2988 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
2989 {
2990 /* DMA error code field */
2991 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2992
2993 /* Call error callback */
2994 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2995 /*Call registered error callback*/
2996 hcryp->ErrorCallback(hcryp);
2997 #else
2998 /*Call legacy weak error callback*/
2999 HAL_CRYP_ErrorCallback(hcryp);
3000 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3001 }
3002 /* Enable In/Out DMA request */
3003 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3004
3005 #else /* AES */
3006
3007 if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3008 {
3009 /* Enable CRYP (not allowed in GCM & CCM)*/
3010 __HAL_CRYP_ENABLE(hcryp);
3011 }
3012
3013 /* Enable the DMA input stream */
3014 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK)
3015 {
3016 /* DMA error code field */
3017 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3018
3019 /* Call error callback */
3020 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3021 /*Call registered error callback*/
3022 hcryp->ErrorCallback(hcryp);
3023 #else
3024 /*Call legacy weak error callback*/
3025 HAL_CRYP_ErrorCallback(hcryp);
3026 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3027 }
3028 /* Enable the DMA output stream */
3029 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK)
3030 {
3031 /* DMA error code field */
3032 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3033
3034 /* Call error callback */
3035 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3036 /*Call registered error callback*/
3037 hcryp->ErrorCallback(hcryp);
3038 #else
3039 /*Call legacy weak error callback*/
3040 HAL_CRYP_ErrorCallback(hcryp);
3041 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3042 }
3043 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3044 /* Enable In and Out DMA requests */
3045 if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3046 {
3047 /* Enable only In DMA requests for CCM*/
3048 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN ));
3049 }
3050 else
3051 {
3052 /* Enable In and Out DMA requests */
3053 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3054 }
3055 #endif /* End AES or CRYP */
3056 }
3057
3058 /**
3059 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3060 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3061 * the configuration information for CRYP module
3062 * @param Timeout: Specify Timeout value
3063 * @retval None
3064 */
3065 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3066 {
3067
3068 uint32_t temp; /* Temporary CrypOutBuff */
3069 #if defined (CRYP)
3070 uint16_t incount; /* Temporary CrypInCount Value */
3071 uint16_t outcount; /* Temporary CrypOutCount Value */
3072 #endif
3073
3074 #if defined (CRYP)
3075
3076 /*Temporary CrypOutCount Value*/
3077 incount = hcryp->CrypInCount;
3078
3079 if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
3080 {
3081 /* Write the input block in the IN FIFO */
3082 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3083 hcryp->CrypInCount++;
3084 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3085 hcryp->CrypInCount++;
3086 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3087 hcryp->CrypInCount++;
3088 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3089 hcryp->CrypInCount++;
3090 }
3091
3092 /* Wait for OFNE flag to be raised */
3093 if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3094 {
3095 /* Disable the CRYP peripheral clock */
3096 __HAL_CRYP_DISABLE(hcryp);
3097
3098 /* Change state & error code*/
3099 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3100 hcryp->State = HAL_CRYP_STATE_READY;
3101
3102 /* Process unlocked */
3103 __HAL_UNLOCK(hcryp);
3104 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3105 /*Call registered error callback*/
3106 hcryp->ErrorCallback(hcryp);
3107 #else
3108 /*Call legacy weak error callback*/
3109 HAL_CRYP_ErrorCallback(hcryp);
3110 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3111 }
3112
3113 /*Temporary CrypOutCount Value*/
3114 outcount = hcryp->CrypOutCount;
3115
3116 if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
3117 {
3118 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3119 temp = hcryp->Instance->DOUT;
3120 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3121 hcryp->CrypOutCount++;
3122 temp = hcryp->Instance->DOUT;
3123 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3124 hcryp->CrypOutCount++;
3125 temp = hcryp->Instance->DOUT;
3126 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3127 hcryp->CrypOutCount++;
3128 temp = hcryp->Instance->DOUT;
3129 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3130 hcryp->CrypOutCount++;
3131 }
3132
3133 #else /* AES */
3134
3135 /* Write the input block in the IN FIFO */
3136 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3137 hcryp->CrypInCount++;
3138 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3139 hcryp->CrypInCount++;
3140 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3141 hcryp->CrypInCount++;
3142 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3143 hcryp->CrypInCount++;
3144
3145 /* Wait for CCF flag to be raised */
3146 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3147 {
3148 /* Disable the CRYP peripheral clock */
3149 __HAL_CRYP_DISABLE(hcryp);
3150
3151 /* Change state */
3152 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3153 hcryp->State = HAL_CRYP_STATE_READY;
3154
3155 /* Process unlocked */
3156 __HAL_UNLOCK(hcryp);
3157 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3158 /*Call registered error callback*/
3159 hcryp->ErrorCallback(hcryp);
3160 #else
3161 /*Call legacy weak error callback*/
3162 HAL_CRYP_ErrorCallback(hcryp);
3163 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3164 }
3165
3166 /* Clear CCF Flag */
3167 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3168
3169 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3170 temp = hcryp->Instance->DOUTR;
3171 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
3172 hcryp->CrypOutCount++;
3173 temp = hcryp->Instance->DOUTR;
3174 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
3175 hcryp->CrypOutCount++;
3176 temp = hcryp->Instance->DOUTR;
3177 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
3178 hcryp->CrypOutCount++;
3179 temp = hcryp->Instance->DOUTR;
3180 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3181 hcryp->CrypOutCount++;
3182
3183 #endif /* End AES or CRYP */
3184 }
3185
3186 /**
3187 * @brief Handle CRYP block input/output data handling under interruption.
3188 * @note The function is called under interruption only, once
3189 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3190 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3191 * the configuration information for CRYP module.
3192 * @retval HAL status
3193 */
3194 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3195 {
3196 uint32_t temp; /* Temporary CrypOutBuff */
3197 #if defined (CRYP)
3198 uint16_t incount; /* Temporary CrypInCount Value */
3199 uint16_t outcount; /* Temporary CrypOutCount Value */
3200 #endif
3201
3202 if(hcryp->State == HAL_CRYP_STATE_BUSY)
3203 {
3204 #if defined (CRYP)
3205
3206 /*Temporary CrypOutCount Value*/
3207 incount = hcryp->CrypInCount;
3208 if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
3209 {
3210 /* Write the input block in the IN FIFO */
3211 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3212 hcryp->CrypInCount++;
3213 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3214 hcryp->CrypInCount++;
3215 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3216 hcryp->CrypInCount++;
3217 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3218 hcryp->CrypInCount++;
3219 if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
3220 {
3221 /* Disable interrupts */
3222 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3223
3224 /* Call the input data transfer complete callback */
3225 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3226 /*Call registered Input complete callback*/
3227 hcryp->InCpltCallback(hcryp);
3228 #else
3229 /*Call legacy weak Input complete callback*/
3230 HAL_CRYP_InCpltCallback(hcryp);
3231 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3232 }
3233 }
3234 /*Temporary CrypOutCount Value*/
3235 outcount = hcryp->CrypOutCount;
3236
3237 if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
3238 {
3239 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3240 temp = hcryp->Instance->DOUT;
3241 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3242 hcryp->CrypOutCount++;
3243 temp = hcryp->Instance->DOUT;
3244 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3245 hcryp->CrypOutCount++;
3246 temp = hcryp->Instance->DOUT;
3247 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3248 hcryp->CrypOutCount++;
3249 temp = hcryp->Instance->DOUT;
3250 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3251 hcryp->CrypOutCount++;
3252 if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
3253 {
3254 /* Disable interrupts */
3255 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3256
3257 /* Change the CRYP state */
3258 hcryp->State = HAL_CRYP_STATE_READY;
3259
3260 /* Disable CRYP */
3261 __HAL_CRYP_DISABLE(hcryp);
3262
3263 /* Process unlocked */
3264 __HAL_UNLOCK(hcryp);
3265
3266 /* Call Output transfer complete callback */
3267 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3268 /*Call registered Output complete callback*/
3269 hcryp->OutCpltCallback(hcryp);
3270 #else
3271 /*Call legacy weak Output complete callback*/
3272 HAL_CRYP_OutCpltCallback(hcryp);
3273 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3274 }
3275 }
3276
3277 #else /*AES*/
3278
3279 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3280 temp = hcryp->Instance->DOUTR;
3281 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
3282 hcryp->CrypOutCount++;
3283 temp = hcryp->Instance->DOUTR;
3284 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
3285 hcryp->CrypOutCount++;
3286 temp = hcryp->Instance->DOUTR;
3287 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
3288 hcryp->CrypOutCount++;
3289 temp = hcryp->Instance->DOUTR;
3290 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3291 hcryp->CrypOutCount++;
3292
3293 if(hcryp->CrypOutCount == (hcryp->Size/4U))
3294 {
3295 /* Disable Computation Complete flag and errors interrupts */
3296 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
3297
3298 /* Change the CRYP state */
3299 hcryp->State = HAL_CRYP_STATE_READY;
3300
3301 /* Disable CRYP */
3302 __HAL_CRYP_DISABLE(hcryp);
3303
3304 /* Process Unlocked */
3305 __HAL_UNLOCK(hcryp);
3306
3307 /* Call Output transfer complete callback */
3308 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3309 /*Call registered Output complete callback*/
3310 hcryp->OutCpltCallback(hcryp);
3311 #else
3312 /*Call legacy weak Output complete callback*/
3313 HAL_CRYP_OutCpltCallback(hcryp);
3314 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3315 }
3316 else
3317 {
3318 /* Write the input block in the IN FIFO */
3319 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3320 hcryp->CrypInCount++;
3321 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3322 hcryp->CrypInCount++;
3323 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3324 hcryp->CrypInCount++;
3325 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3326 hcryp->CrypInCount++;
3327
3328 if(hcryp->CrypInCount == (hcryp->Size/4U))
3329 {
3330 /* Call Input transfer complete callback */
3331 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3332 /*Call registered Input complete callback*/
3333 hcryp->InCpltCallback(hcryp);
3334 #else
3335 /*Call legacy weak Input complete callback*/
3336 HAL_CRYP_InCpltCallback(hcryp);
3337 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3338 }
3339 }
3340 #endif /* End AES or CRYP */
3341
3342 }
3343 else
3344 {
3345 /* Busy error code field */
3346 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3347 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3348 /*Call registered error callback*/
3349 hcryp->ErrorCallback(hcryp);
3350 #else
3351 /*Call legacy weak error callback*/
3352 HAL_CRYP_ErrorCallback(hcryp);
3353 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3354 }
3355 }
3356
3357 /**
3358 * @brief Writes Key in Key registers.
3359 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3360 * the configuration information for CRYP module
3361 * @param KeySize: Size of Key
3362 * @retval None
3363 */
3364 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3365 {
3366 #if defined (CRYP)
3367
3368 switch(KeySize)
3369 {
3370 case CRYP_KEYSIZE_256B:
3371 hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
3372 hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
3373 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
3374 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
3375 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
3376 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
3377 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
3378 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
3379 break;
3380 case CRYP_KEYSIZE_192B:
3381 hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
3382 hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
3383 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
3384 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
3385 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
3386 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
3387 break;
3388 case CRYP_KEYSIZE_128B:
3389 hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
3390 hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
3391 hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
3392 hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
3393
3394 break;
3395 default:
3396 break;
3397 }
3398 #else /*AES*/
3399 switch(KeySize)
3400 {
3401 case CRYP_KEYSIZE_256B:
3402 hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey);
3403 hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1);
3404 hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2);
3405 hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3);
3406 hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4);
3407 hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5);
3408 hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6);
3409 hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7);
3410 break;
3411 case CRYP_KEYSIZE_128B:
3412 hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey);
3413 hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1);
3414 hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2);
3415 hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3);
3416
3417 break;
3418 default:
3419 break;
3420 }
3421 #endif /* End AES or CRYP */
3422 }
3423
3424
3425 /**
3426 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3427 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3428 * the configuration information for CRYP module
3429 * @param Timeout: Timeout duration
3430 * @retval HAL status
3431 */
3432 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3433 {
3434 uint32_t tickstart;
3435 uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ;
3436 uint16_t outcount; /* Temporary CrypOutCount Value */
3437
3438 /* Reset CrypHeaderCount */
3439 hcryp->CrypHeaderCount = 0U;
3440
3441 /****************************** Init phase **********************************/
3442
3443 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
3444
3445 /* Set the key */
3446 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3447
3448 #if defined(CRYP)
3449
3450 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3451 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
3452 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
3453 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
3454 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
3455
3456 /* Enable the CRYP peripheral */
3457 __HAL_CRYP_ENABLE(hcryp);
3458
3459 /* Get tick */
3460 tickstart = HAL_GetTick();
3461
3462 /*Wait for the CRYPEN bit to be cleared*/
3463 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3464 {
3465 /* Check for the Timeout */
3466 if(Timeout != HAL_MAX_DELAY)
3467 {
3468 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
3469 {
3470 /* Disable the CRYP peripheral clock */
3471 __HAL_CRYP_DISABLE(hcryp);
3472
3473 /* Change state */
3474 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3475 hcryp->State = HAL_CRYP_STATE_READY;
3476
3477 /* Process unlocked */
3478 __HAL_UNLOCK(hcryp);
3479 return HAL_ERROR;
3480 }
3481 }
3482 }
3483
3484 #else /* AES */
3485 /* Workaround 1 : only AES.
3486 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3487 enabling the IP, datatype different from 32 bits can be configured.*/
3488 /* Select DATATYPE 32 */
3489 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3490
3491 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3492 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
3493 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
3494 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
3495 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
3496
3497 /* Enable the CRYP peripheral */
3498 __HAL_CRYP_ENABLE(hcryp);
3499
3500 /* just wait for hash computation */
3501 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3502 {
3503 /* Change state */
3504 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3505 hcryp->State = HAL_CRYP_STATE_READY;
3506
3507 /* Process unlocked & return error */
3508 __HAL_UNLOCK(hcryp);
3509 return HAL_ERROR;
3510 }
3511 /* Clear CCF flag */
3512 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3513
3514 #endif /* End AES or CRYP */
3515
3516 /************************ Header phase *************************************/
3517
3518 if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3519 {
3520 return HAL_ERROR;
3521 }
3522
3523 /*************************Payload phase ************************************/
3524
3525 /* Set the phase */
3526 hcryp->Phase = CRYP_PHASE_PROCESS;
3527
3528 #if defined(CRYP)
3529
3530 /* Disable the CRYP peripheral */
3531 __HAL_CRYP_DISABLE(hcryp);
3532
3533 /* Select payload phase once the header phase is performed */
3534 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3535
3536 /* Enable the CRYP peripheral */
3537 __HAL_CRYP_ENABLE(hcryp);
3538
3539 #else /* AES */
3540
3541 /* Select payload phase once the header phase is performed */
3542 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3543
3544 #endif /* End AES or CRYP */
3545
3546 if ((hcryp->Size % 16U) != 0U)
3547 {
3548 /* recalculate wordsize */
3549 wordsize = ((wordsize/4U)*4U) ;
3550 }
3551
3552 /* Get tick */
3553 tickstart = HAL_GetTick();
3554 /*Temporary CrypOutCount Value*/
3555 outcount = hcryp->CrypOutCount;
3556
3557 /* Write input data and get output Data */
3558 while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3559 {
3560 /* Write plain data and get cipher data */
3561 CRYP_AES_ProcessData(hcryp,Timeout);
3562
3563 /*Temporary CrypOutCount Value*/
3564 outcount = hcryp->CrypOutCount;
3565
3566 /* Check for the Timeout */
3567 if(Timeout != HAL_MAX_DELAY)
3568 {
3569 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
3570 {
3571 /* Disable the CRYP peripheral clock */
3572 __HAL_CRYP_DISABLE(hcryp);
3573
3574 /* Change state & error code */
3575 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3576 hcryp->State = HAL_CRYP_STATE_READY;
3577
3578 /* Process unlocked */
3579 __HAL_UNLOCK(hcryp);
3580 return HAL_ERROR;
3581 }
3582 }
3583 }
3584
3585 if ((hcryp->Size % 16U) != 0U)
3586 {
3587 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3588 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3589 is selected, then the TAG message will be wrong.*/
3590 CRYP_Workaround(hcryp,Timeout);
3591 }
3592
3593 /* Return function status */
3594 return HAL_OK;
3595 }
3596
3597 /**
3598 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3599 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3600 * the configuration information for CRYP module
3601 * @retval HAL status
3602 */
3603 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3604 {
3605 __IO uint32_t count = 0U;
3606 #if defined(AES)
3607 uint32_t loopcounter;
3608 uint32_t lastwordsize;
3609 uint32_t npblb;
3610 #endif /* AES */
3611
3612 /* Reset CrypHeaderCount */
3613 hcryp->CrypHeaderCount =0U;
3614
3615 /******************************* Init phase *********************************/
3616
3617 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
3618
3619 /* Set the key */
3620 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3621
3622 #if defined(CRYP)
3623 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3624 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
3625 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
3626 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
3627 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
3628
3629 /* Enable the CRYP peripheral */
3630 __HAL_CRYP_ENABLE(hcryp);
3631
3632 /*Wait for the CRYPEN bit to be cleared*/
3633 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3634 do
3635 {
3636 count-- ;
3637 if(count == 0U)
3638 {
3639 /* Disable the CRYP peripheral clock */
3640 __HAL_CRYP_DISABLE(hcryp);
3641
3642 /* Change state */
3643 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3644 hcryp->State = HAL_CRYP_STATE_READY;
3645
3646 /* Process unlocked */
3647 __HAL_UNLOCK(hcryp);
3648 return HAL_ERROR;
3649 }
3650 }
3651 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3652
3653 #else /* AES */
3654
3655 /* Workaround 1 : only AES
3656 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3657 enabling the IP, datatype different from 32 bits can be configured.*/
3658 /* Select DATATYPE 32 */
3659 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3660
3661 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3662 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
3663 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
3664 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
3665 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
3666
3667 /* Enable the CRYP peripheral */
3668 __HAL_CRYP_ENABLE(hcryp);
3669
3670 /* just wait for hash computation */
3671 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3672 do
3673 {
3674 count-- ;
3675 if(count == 0U)
3676 {
3677 /* Disable the CRYP peripheral clock */
3678 __HAL_CRYP_DISABLE(hcryp);
3679
3680 /* Change state */
3681 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3682 hcryp->State = HAL_CRYP_STATE_READY;
3683
3684 /* Process unlocked */
3685 __HAL_UNLOCK(hcryp);
3686 return HAL_ERROR;
3687 }
3688 }
3689 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3690
3691 /* Clear CCF flag */
3692 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3693
3694 #endif /* End AES or CRYP */
3695
3696 /***************************** Header phase *********************************/
3697
3698 #if defined(CRYP)
3699
3700 /* Select header phase */
3701 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3702
3703 /* Enable interrupts */
3704 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
3705
3706 /* Enable CRYP */
3707 __HAL_CRYP_ENABLE(hcryp);
3708
3709 #else /* AES */
3710
3711 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
3712 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
3713
3714 /* Select header phase */
3715 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3716
3717 /* Enable computation complete flag and error interrupts */
3718 __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3719
3720 /* Enable the CRYP peripheral */
3721 __HAL_CRYP_ENABLE(hcryp);
3722
3723 if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
3724 {
3725 /* Set the phase */
3726 hcryp->Phase = CRYP_PHASE_PROCESS;
3727
3728 /* Select payload phase once the header phase is performed */
3729 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
3730
3731 /* Write the payload Input block in the IN FIFO */
3732 if(hcryp->Size == 0U)
3733 {
3734 /* Disable interrupts */
3735 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
3736
3737 /* Change the CRYP state */
3738 hcryp->State = HAL_CRYP_STATE_READY;
3739
3740 /* Process unlocked */
3741 __HAL_UNLOCK(hcryp);
3742 }
3743 else if (hcryp->Size >= 16U)
3744 {
3745 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3746 hcryp->CrypInCount++;
3747 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3748 hcryp->CrypInCount++;
3749 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3750 hcryp->CrypInCount++;
3751 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3752 hcryp->CrypInCount++;
3753 if(hcryp->CrypInCount == ( hcryp->Size/4U))
3754 {
3755 /* Call Input transfer complete callback */
3756 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3757 /*Call registered Input complete callback*/
3758 hcryp->InCpltCallback(hcryp);
3759 #else
3760 /*Call legacy weak Input complete callback*/
3761 HAL_CRYP_InCpltCallback(hcryp);
3762 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3763 }
3764 }
3765 else /* Size < 16Bytes : first block is the last block*/
3766 {
3767 /* Workaround not implemented*/
3768 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
3769 Workaround is implemented in polling mode, so if last block of
3770 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
3771
3772 /* Compute the number of padding bytes in last block of payload */
3773 npblb = 16U- (uint32_t)(hcryp->Size);
3774
3775 /* Number of valid words (lastwordsize) in last block */
3776 if ((npblb % 4U) ==0U)
3777 {
3778 lastwordsize = (16U-npblb)/4U;
3779 }
3780 else
3781 {
3782 lastwordsize = ((16U-npblb)/4U) +1U;
3783 }
3784
3785 /* last block optionally pad the data with zeros*/
3786 for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
3787 {
3788 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
3789 hcryp->CrypInCount++;
3790 }
3791 while(loopcounter < 4U )
3792 {
3793 /* pad the data with zeros to have a complete block */
3794 hcryp->Instance->DINR = 0x0U;
3795 loopcounter++;
3796 }
3797 }
3798 }
3799 else if ((hcryp->Init.HeaderSize) < 4U)
3800 {
3801 for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
3802 {
3803 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
3804 hcryp->CrypHeaderCount++ ;
3805 }
3806 while(loopcounter < 4U )
3807 {
3808 /* pad the data with zeros to have a complete block */
3809 hcryp->Instance->DINR = 0x0U;
3810 loopcounter++;
3811 }
3812 /* Set the phase */
3813 hcryp->Phase = CRYP_PHASE_PROCESS;
3814
3815 /* Select payload phase once the header phase is performed */
3816 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3817
3818 /* Call Input transfer complete callback */
3819 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3820 /*Call registered Input complete callback*/
3821 hcryp->InCpltCallback(hcryp);
3822 #else
3823 /*Call legacy weak Input complete callback*/
3824 HAL_CRYP_InCpltCallback(hcryp);
3825 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3826 }
3827 else if ((hcryp->Init.HeaderSize) >= 4U)
3828 {
3829 /* Write the input block in the IN FIFO */
3830 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
3831 hcryp->CrypHeaderCount++;
3832 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
3833 hcryp->CrypHeaderCount++;
3834 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
3835 hcryp->CrypHeaderCount++;
3836 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
3837 hcryp->CrypHeaderCount++;
3838 }
3839 else
3840 {
3841 /* Nothing to do */
3842 }
3843
3844 #endif /* End AES or CRYP */
3845
3846 /* Return function status */
3847 return HAL_OK;
3848 }
3849
3850
3851 /**
3852 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
3853 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3854 * the configuration information for CRYP module
3855 * @retval HAL status
3856 */
3857 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
3858 {
3859 __IO uint32_t count = 0U;
3860 uint32_t wordsize;
3861
3862 /* Reset CrypHeaderCount */
3863 hcryp->CrypHeaderCount = 0U;
3864
3865 /*************************** Init phase ************************************/
3866
3867 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
3868
3869 /* Set the key */
3870 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3871
3872 #if defined(CRYP)
3873 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3874 hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
3875 hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
3876 hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
3877 hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
3878
3879 /* Enable the CRYP peripheral */
3880 __HAL_CRYP_ENABLE(hcryp);
3881
3882 /*Wait for the CRYPEN bit to be cleared*/
3883 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3884 do
3885 {
3886 count-- ;
3887 if(count == 0U)
3888 {
3889 /* Disable the CRYP peripheral clock */
3890 __HAL_CRYP_DISABLE(hcryp);
3891
3892 /* Change state */
3893 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3894 hcryp->State = HAL_CRYP_STATE_READY;
3895
3896 /* Process unlocked */
3897 __HAL_UNLOCK(hcryp);
3898 return HAL_ERROR;
3899 }
3900 }
3901 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3902
3903 #else /* AES */
3904
3905 /*Workaround 1 : only AES
3906 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3907 enabling the IP, datatype different from 32 bits can be configured.*/
3908 /* Select DATATYPE 32 */
3909 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3910
3911 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3912 hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
3913 hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
3914 hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
3915 hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
3916
3917 /* Enable the CRYP peripheral */
3918 __HAL_CRYP_ENABLE(hcryp);
3919
3920 /* just wait for hash computation */
3921 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3922 do
3923 {
3924 count-- ;
3925 if(count == 0U)
3926 {
3927 /* Disable the CRYP peripheral clock */
3928 __HAL_CRYP_DISABLE(hcryp);
3929
3930 /* Change state */
3931 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3932 hcryp->State = HAL_CRYP_STATE_READY;
3933
3934 /* Process unlocked */
3935 __HAL_UNLOCK(hcryp);
3936 return HAL_ERROR;
3937 }
3938 }
3939 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3940
3941 /* Clear CCF flag */
3942 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3943
3944 #endif /* End AES or CRYP */
3945
3946 /************************ Header phase *************************************/
3947
3948 if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
3949 {
3950 return HAL_ERROR;
3951 }
3952
3953 /************************ Payload phase ************************************/
3954
3955 /* Set the phase */
3956 hcryp->Phase = CRYP_PHASE_PROCESS;
3957
3958 #if defined(CRYP)
3959
3960 /* Disable the CRYP peripheral */
3961 __HAL_CRYP_DISABLE(hcryp);
3962
3963 #endif /* CRYP */
3964
3965 /* Select payload phase once the header phase is performed */
3966 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3967
3968 if(hcryp->Size != 0U)
3969 {
3970 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
3971 Workaround is implemented in polling mode, so if last block of
3972 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
3973 /* Set the input and output addresses and start DMA transfer */
3974 if ((hcryp->Size % 16U) == 0U)
3975 {
3976 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3977 }
3978 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
3979 {
3980 wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ;
3981
3982 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
3983 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3984 }
3985 }
3986 else
3987 {
3988 /* Process unLocked */
3989 __HAL_UNLOCK(hcryp);
3990
3991 /* Change the CRYP state and phase */
3992 hcryp->State = HAL_CRYP_STATE_READY;
3993 }
3994
3995 /* Return function status */
3996 return HAL_OK;
3997 }
3998
3999
4000 /**
4001 * @brief AES CCM encryption/decryption processing in polling mode
4002 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4003 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4004 * the configuration information for CRYP module
4005 * @param Timeout: Timeout duration
4006 * @retval HAL status
4007 */
4008 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4009 {
4010 uint32_t tickstart;
4011 uint32_t wordsize= (uint32_t)(hcryp->Size)/4U;
4012 uint16_t outcount; /* Temporary CrypOutCount Value */
4013 #if defined(AES)
4014 uint32_t loopcounter;
4015 uint32_t npblb;
4016 uint32_t lastwordsize;
4017 #endif /* AES */
4018
4019 /* Reset CrypHeaderCount */
4020 hcryp->CrypHeaderCount = 0U;
4021
4022 #if defined(CRYP)
4023
4024 /********************** Init phase ******************************************/
4025
4026 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
4027
4028 /* Set the key */
4029 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4030
4031 /* Set the initialization vector (IV) with CTR1 information */
4032 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4033 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4034 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4035 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
4036
4037
4038 /* Enable the CRYP peripheral */
4039 __HAL_CRYP_ENABLE(hcryp);
4040
4041 /*Write B0 packet into CRYP_DIN Register*/
4042 if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
4043 {
4044 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
4045 hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
4046 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
4047 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
4048 }
4049 else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
4050 {
4051 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
4052 hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
4053 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
4054 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
4055 }
4056 else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
4057 {
4058 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
4059 hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
4060 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
4061 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
4062 }
4063 else
4064 {
4065 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
4066 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
4067 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
4068 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
4069 }
4070 /* Get tick */
4071 tickstart = HAL_GetTick();
4072
4073 /*Wait for the CRYPEN bit to be cleared*/
4074 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4075 {
4076 /* Check for the Timeout */
4077 if(Timeout != HAL_MAX_DELAY)
4078 {
4079 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
4080 {
4081 /* Disable the CRYP peripheral clock */
4082 __HAL_CRYP_DISABLE(hcryp);
4083
4084 /* Change state */
4085 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4086 hcryp->State = HAL_CRYP_STATE_READY;
4087
4088 /* Process unlocked */
4089 __HAL_UNLOCK(hcryp);
4090 return HAL_ERROR;
4091 }
4092 }
4093 }
4094 #else /* AES */
4095 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4096 /* Select header phase */
4097 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4098
4099 /* configured encryption mode */
4100 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4101
4102 /* Set the key */
4103 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4104
4105 /* Set the initialization vector with zero values*/
4106 hcryp->Instance->IVR3 = 0U;
4107 hcryp->Instance->IVR2 = 0U;
4108 hcryp->Instance->IVR1 = 0U;
4109 hcryp->Instance->IVR0 = 0U;
4110
4111 /* Enable the CRYP peripheral */
4112 __HAL_CRYP_ENABLE(hcryp);
4113
4114 /*Write the B0 packet into CRYP_DIN*/
4115 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
4116 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
4117 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
4118 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
4119
4120 /* wait until the end of computation */
4121 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4122 {
4123 /* Change state */
4124 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4125 hcryp->State = HAL_CRYP_STATE_READY;
4126
4127 /* Process unlocked & return error */
4128 __HAL_UNLOCK(hcryp);
4129 return HAL_ERROR;
4130 }
4131 /* Clear CCF flag */
4132 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4133
4134 /* Set the phase */
4135 hcryp->Phase = CRYP_PHASE_PROCESS;
4136
4137 /* From that point the whole message must be processed, first the Header then the payload.
4138 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4139
4140 if (hcryp->Init.HeaderSize != 0U)
4141 {
4142 if ((hcryp->Init.HeaderSize %4U )== 0U)
4143 {
4144 /* HeaderSize %4, no padding */
4145 for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
4146 {
4147 /* Write the Input block in the Data Input register */
4148 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4149 hcryp->CrypHeaderCount++ ;
4150 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4151 hcryp->CrypHeaderCount++ ;
4152 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4153 hcryp->CrypHeaderCount++ ;
4154 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4155 hcryp->CrypHeaderCount++ ;
4156
4157 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4158 {
4159 /* Disable the CRYP peripheral clock */
4160 __HAL_CRYP_DISABLE(hcryp);
4161
4162 /* Change state */
4163 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4164 hcryp->State = HAL_CRYP_STATE_READY;
4165
4166 /* Process unlocked */
4167 __HAL_UNLOCK(hcryp);
4168 return HAL_ERROR;
4169 }
4170 /* Clear CCF Flag */
4171 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4172 }
4173 }
4174 else
4175 {
4176 /*Write Header block in the IN FIFO without last block */
4177 for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
4178 {
4179 /* Write the input block in the data input register */
4180 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4181 hcryp->CrypHeaderCount++ ;
4182 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4183 hcryp->CrypHeaderCount++ ;
4184 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4185 hcryp->CrypHeaderCount++ ;
4186 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4187 hcryp->CrypHeaderCount++ ;
4188
4189 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4190 {
4191 /* Disable the CRYP peripheral clock */
4192 __HAL_CRYP_DISABLE(hcryp);
4193
4194 /* Change state */
4195 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4196 hcryp->State = HAL_CRYP_STATE_READY;
4197
4198 /* Process unlocked */
4199 __HAL_UNLOCK(hcryp);
4200 return HAL_ERROR;
4201 }
4202 /* Clear CCF Flag */
4203 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4204 }
4205 /* Last block optionally pad the data with zeros*/
4206 for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
4207 {
4208 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4209 hcryp->CrypHeaderCount++ ;
4210 }
4211 while(loopcounter <4U )
4212 {
4213 /* Pad the data with zeros to have a complete block */
4214 hcryp->Instance->DINR = 0x0U;
4215 loopcounter++;
4216 }
4217
4218 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4219 {
4220 /* Disable the CRYP peripheral clock */
4221 __HAL_CRYP_DISABLE(hcryp);
4222
4223 /* Change state */
4224 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4225 hcryp->State = HAL_CRYP_STATE_READY;
4226
4227 /* Process unlocked */
4228 __HAL_UNLOCK(hcryp);
4229 return HAL_ERROR;
4230 }
4231 /* Clear CCF flag */
4232 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4233 }
4234 }
4235 /* Then the payload: cleartext payload (not the ciphertext payload).
4236 Write input Data, no output Data to get */
4237 if (hcryp->Size != 0U)
4238 {
4239 if ((hcryp->Size % 16U) != 0U)
4240 {
4241 /* recalculate wordsize */
4242 wordsize = ((wordsize/4U)*4U) ;
4243 }
4244
4245 /* Get tick */
4246 tickstart = HAL_GetTick();
4247 /*Temporary CrypOutCount Value*/
4248 outcount = hcryp->CrypOutCount;
4249
4250 while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4251 {
4252 /* Write plain data and get cipher data */
4253 CRYP_AES_ProcessData(hcryp,Timeout);
4254
4255 /*Temporary CrypOutCount Value*/
4256 outcount = hcryp->CrypOutCount;
4257
4258 /* Check for the Timeout */
4259 if(Timeout != HAL_MAX_DELAY)
4260 {
4261 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
4262 {
4263 /* Disable the CRYP peripheral clock */
4264 __HAL_CRYP_DISABLE(hcryp);
4265
4266 /* Change state */
4267 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4268 hcryp->State = HAL_CRYP_STATE_READY;
4269
4270 /* Process unlocked */
4271 __HAL_UNLOCK(hcryp);
4272 return HAL_ERROR;
4273 }
4274 }
4275 }
4276
4277 if ((hcryp->Size % 16U) != 0U)
4278 {
4279 /* Compute the number of padding bytes in last block of payload */
4280 npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
4281
4282 /* Number of valid words (lastwordsize) in last block */
4283 if ((npblb%4U) ==0U)
4284 {
4285 lastwordsize = (16U-npblb)/4U;
4286 }
4287 else
4288 {
4289 lastwordsize = ((16U-npblb)/4U) +1U;
4290 }
4291 /* Last block optionally pad the data with zeros*/
4292 for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++)
4293 {
4294 /* Write the last input block in the IN FIFO */
4295 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4296 hcryp->CrypInCount++;
4297 }
4298 while(loopcounter < 4U)
4299 {
4300 /* Pad the data with zeros to have a complete block */
4301 hcryp->Instance->DINR = 0U;
4302 loopcounter++;
4303 }
4304 /* Wait for CCF flag to be raised */
4305 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4306 {
4307 /* Disable the CRYP peripheral clock */
4308 __HAL_CRYP_DISABLE(hcryp);
4309
4310 /* Change state */
4311 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4312 hcryp->State = HAL_CRYP_STATE_READY;
4313
4314 /* Process unlocked */
4315 __HAL_UNLOCK(hcryp);
4316 return HAL_ERROR;
4317 }
4318 /* Clear CCF flag */
4319 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4320
4321 }
4322 }
4323 #endif /* End AES or CRYP */
4324
4325 #if defined(CRYP)
4326
4327 /************************* Header phase *************************************/
4328 /* Header block(B1) : associated data length expressed in bytes concatenated
4329 with Associated Data (A)*/
4330
4331 if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4332 {
4333 return HAL_ERROR;
4334 }
4335
4336 /********************** Payload phase ***************************************/
4337
4338 /* Set the phase */
4339 hcryp->Phase = CRYP_PHASE_PROCESS;
4340
4341 /* Disable the CRYP peripheral */
4342 __HAL_CRYP_DISABLE(hcryp);
4343
4344 /* Select payload phase once the header phase is performed */
4345 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4346
4347 /* Enable the CRYP peripheral */
4348 __HAL_CRYP_ENABLE(hcryp);
4349
4350 if ((hcryp->Size % 16U) != 0U)
4351 {
4352 /* recalculate wordsize */
4353 wordsize = ((wordsize/4U)*4U) ;
4354 }
4355 /* Get tick */
4356 tickstart = HAL_GetTick();
4357 /*Temporary CrypOutCount Value*/
4358 outcount = hcryp->CrypOutCount;
4359
4360 /* Write input data and get output data */
4361 while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4362 {
4363 /* Write plain data and get cipher data */
4364 CRYP_AES_ProcessData(hcryp,Timeout);
4365
4366 /* Check for the Timeout */
4367 if(Timeout != HAL_MAX_DELAY)
4368 {
4369 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
4370 {
4371 /* Disable the CRYP peripheral clock */
4372 __HAL_CRYP_DISABLE(hcryp);
4373
4374 /* Change state */
4375 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4376 hcryp->State = HAL_CRYP_STATE_READY;
4377
4378 /* Process unlocked */
4379 __HAL_UNLOCK(hcryp);
4380 return HAL_ERROR;
4381 }
4382 }
4383 }
4384
4385 if ((hcryp->Size % 16U) != 0U)
4386 {
4387 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4388 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4389 is selected, then the TAG message will be wrong.*/
4390 CRYP_Workaround(hcryp,Timeout);
4391 }
4392 #endif /* CRYP */
4393
4394 /* Return function status */
4395 return HAL_OK;
4396 }
4397
4398 /**
4399 * @brief AES CCM encryption/decryption process in interrupt mode
4400 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4401 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4402 * the configuration information for CRYP module
4403 * @retval HAL status
4404 */
4405 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4406 {
4407 #if defined(CRYP)
4408 __IO uint32_t count = 0U;
4409 #endif /* CRYP */
4410
4411 /* Reset CrypHeaderCount */
4412 hcryp->CrypHeaderCount = 0U;
4413
4414 #if defined(CRYP)
4415
4416 /************ Init phase ************/
4417
4418 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
4419
4420 /* Set the key */
4421 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4422
4423 /* Set the initialization vector (IV) with CTR1 information */
4424 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4425 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4426 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4427 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
4428
4429 /* Enable the CRYP peripheral */
4430 __HAL_CRYP_ENABLE(hcryp);
4431
4432 /*Write the B0 packet into CRYP_DIN Register*/
4433 if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
4434 {
4435 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
4436 hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
4437 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
4438 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
4439 }
4440 else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
4441 {
4442 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
4443 hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
4444 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
4445 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
4446 }
4447 else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
4448 {
4449 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
4450 hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
4451 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
4452 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
4453 }
4454 else
4455 {
4456 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
4457 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
4458 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
4459 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
4460 }
4461 /*Wait for the CRYPEN bit to be cleared*/
4462 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4463 do
4464 {
4465 count-- ;
4466 if(count == 0U)
4467 {
4468 /* Disable the CRYP peripheral clock */
4469 __HAL_CRYP_DISABLE(hcryp);
4470
4471 /* Change state */
4472 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4473 hcryp->State = HAL_CRYP_STATE_READY;
4474
4475 /* Process unlocked */
4476 __HAL_UNLOCK(hcryp);
4477 return HAL_ERROR;
4478 }
4479 }
4480 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4481
4482 /* Select header phase */
4483 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4484
4485 /* Enable interrupts */
4486 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4487
4488 /* Enable CRYP */
4489 __HAL_CRYP_ENABLE(hcryp);
4490
4491 #else /* AES */
4492
4493 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4494 /* Select header phase */
4495 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4496
4497 /* configured mode and encryption mode */
4498 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4499
4500 /* Set the key */
4501 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4502
4503 /* Set the initialization vector with zero values*/
4504 hcryp->Instance->IVR3 = 0U;
4505 hcryp->Instance->IVR2 = 0U;
4506 hcryp->Instance->IVR1 = 0U;
4507 hcryp->Instance->IVR0 = 0U;
4508
4509 /* Enable interrupts */
4510 __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4511 /* Enable the CRYP peripheral */
4512 __HAL_CRYP_ENABLE(hcryp);
4513
4514 /*Write the B0 packet into CRYP_DIN*/
4515 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
4516 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
4517 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
4518 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
4519
4520 #endif /* End AES or CRYP */
4521
4522 /* Return function status */
4523 return HAL_OK;
4524 }
4525 /**
4526 * @brief AES CCM encryption/decryption process in DMA mode
4527 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4528 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4529 * the configuration information for CRYP module
4530 * @retval HAL status
4531 */
4532 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4533 {
4534 uint32_t wordsize;
4535 __IO uint32_t count = 0U;
4536
4537 /* Reset CrypHeaderCount */
4538 hcryp->CrypHeaderCount = 0U;
4539
4540 #if defined(CRYP)
4541
4542 /************************** Init phase **************************************/
4543
4544 CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
4545
4546 /* Set the key */
4547 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4548
4549 /* Set the initialization vector (IV) with CTR1 information */
4550 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4551 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4552 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4553 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
4554
4555 /* Enable the CRYP peripheral */
4556 __HAL_CRYP_ENABLE(hcryp);
4557
4558 /*Write the B0 packet into CRYP_DIN Register*/
4559 if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
4560 {
4561 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
4562 hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
4563 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
4564 hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
4565 }
4566 else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
4567 {
4568 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
4569 hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
4570 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
4571 hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
4572 }
4573 else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
4574 {
4575 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
4576 hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
4577 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
4578 hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
4579 }
4580 else
4581 {
4582 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
4583 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
4584 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
4585 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
4586 }
4587
4588 /*Wait for the CRYPEN bit to be cleared*/
4589 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4590 do
4591 {
4592 count-- ;
4593 if(count == 0U)
4594 {
4595 /* Disable the CRYP peripheral clock */
4596 __HAL_CRYP_DISABLE(hcryp);
4597
4598 /* Change state */
4599 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4600 hcryp->State = HAL_CRYP_STATE_READY;
4601
4602 /* Process unlocked */
4603 __HAL_UNLOCK(hcryp);
4604 return HAL_ERROR;
4605 }
4606 }
4607 while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4608
4609 #else /* AES */
4610
4611 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4612 /* Select header phase */
4613 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4614
4615 /* configured CCM chaining mode and encryption mode */
4616 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4617
4618 /* Set the key */
4619 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4620
4621 /* Set the initialization vector with zero values*/
4622 hcryp->Instance->IVR3 = 0U;
4623 hcryp->Instance->IVR2 = 0U;
4624 hcryp->Instance->IVR1 = 0U;
4625 hcryp->Instance->IVR0 = 0U;
4626
4627 /* Enable the CRYP peripheral */
4628 __HAL_CRYP_ENABLE(hcryp);
4629
4630 /*Write the B0 packet into CRYP_DIN*/
4631 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
4632 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
4633 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
4634 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
4635
4636 /* wait until the end of computation */
4637 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4638 do
4639 {
4640 count-- ;
4641 if(count == 0U)
4642 {
4643 /* Disable the CRYP peripheral clock */
4644 __HAL_CRYP_DISABLE(hcryp);
4645
4646 /* Change state */
4647 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4648 hcryp->State = HAL_CRYP_STATE_READY;
4649
4650 /* Process Unlocked */
4651 __HAL_UNLOCK(hcryp);
4652 return HAL_ERROR;
4653 }
4654 }
4655 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4656
4657 /* Clear CCF flag */
4658 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4659
4660 #endif /* AES */
4661
4662 /********************* Header phase *****************************************/
4663
4664 if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4665 {
4666 return HAL_ERROR;
4667 }
4668
4669 /******************** Payload phase *****************************************/
4670
4671 /* Set the phase */
4672 hcryp->Phase = CRYP_PHASE_PROCESS;
4673
4674 #if defined(CRYP)
4675
4676 /* Disable the CRYP peripheral */
4677 __HAL_CRYP_DISABLE(hcryp);
4678
4679 /* Select payload phase once the header phase is performed */
4680 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4681
4682 #endif /* CRYP */
4683
4684 if(hcryp->Size != 0U)
4685 {
4686 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
4687 Workaround is implemented in polling mode, so if last block of
4688 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
4689 /* Set the input and output addresses and start DMA transfer */
4690 if ((hcryp->Size % 16U) == 0U)
4691 {
4692 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
4693 }
4694 else
4695 {
4696 wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ;
4697
4698 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
4699 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
4700 }
4701 }
4702 else /*Size = 0*/
4703 {
4704 /* Process unlocked */
4705 __HAL_UNLOCK(hcryp);
4706
4707 /* Change the CRYP state and phase */
4708 hcryp->State = HAL_CRYP_STATE_READY;
4709 }
4710
4711 /* Return function status */
4712 return HAL_OK;
4713 }
4714
4715 /**
4716 * @brief Sets the payload phase in iterrupt mode
4717 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4718 * the configuration information for CRYP module
4719 * @retval state
4720 */
4721 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
4722 {
4723 uint32_t loopcounter;
4724 uint32_t temp; /* Temporary CrypOutBuff */
4725 uint32_t lastwordsize;
4726 uint32_t npblb;
4727 #if defined(AES)
4728 uint16_t outcount; /* Temporary CrypOutCount Value */
4729 #endif /* AES */
4730
4731 /***************************** Payload phase *******************************/
4732
4733 #if defined(CRYP)
4734 if(hcryp->Size == 0U)
4735 {
4736 /* Disable interrupts */
4737 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
4738
4739 /* Process unlocked */
4740 __HAL_UNLOCK(hcryp);
4741
4742 /* Change the CRYP state */
4743 hcryp->State = HAL_CRYP_STATE_READY;
4744 }
4745
4746 else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
4747 {
4748 /* Write the input block in the IN FIFO */
4749 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4750 hcryp->CrypInCount++;
4751 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4752 hcryp->CrypInCount++;
4753 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4754 hcryp->CrypInCount++;
4755 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4756 hcryp->CrypInCount++;
4757 if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U))
4758 {
4759 /* Disable interrupts */
4760 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
4761
4762 /* Call the input data transfer complete callback */
4763 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4764 /*Call registered Input complete callback*/
4765 hcryp->InCpltCallback(hcryp);
4766 #else
4767 /*Call legacy weak Input complete callback*/
4768 HAL_CRYP_InCpltCallback(hcryp);
4769 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4770 }
4771 if(hcryp->CrypOutCount < (hcryp->Size/4U))
4772 {
4773 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
4774 temp = hcryp->Instance->DOUT;
4775 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
4776 hcryp->CrypOutCount++;
4777 temp = hcryp->Instance->DOUT;
4778 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
4779 hcryp->CrypOutCount++;
4780 temp = hcryp->Instance->DOUT;
4781 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
4782 hcryp->CrypOutCount++;
4783 temp = hcryp->Instance->DOUT;
4784 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
4785 hcryp->CrypOutCount++;
4786 if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U))
4787 {
4788 /* Disable interrupts */
4789 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
4790
4791 /* Change the CRYP state */
4792 hcryp->State = HAL_CRYP_STATE_READY;
4793
4794 /* Disable CRYP */
4795 __HAL_CRYP_DISABLE(hcryp);
4796
4797 /* Process unlocked */
4798 __HAL_UNLOCK(hcryp);
4799
4800 /* Call output transfer complete callback */
4801 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4802 /*Call registered Output complete callback*/
4803 hcryp->OutCpltCallback(hcryp);
4804 #else
4805 /*Call legacy weak Output complete callback*/
4806 HAL_CRYP_OutCpltCallback(hcryp);
4807 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4808 }
4809 }
4810 }
4811 else if ((hcryp->Size %16U )!= 0U)
4812 {
4813 /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
4814 Workaround is implemented in polling mode, so if last block of
4815 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
4816
4817 /* Compute the number of padding bytes in last block of payload */
4818 npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
4819
4820 /* Number of valid words (lastwordsize) in last block */
4821 if ((npblb%4U) ==0U)
4822 {
4823 lastwordsize = (16U-npblb)/4U;
4824 }
4825 else
4826 {
4827 lastwordsize = ((16U-npblb)/4U) +1U;
4828 }
4829
4830 /* Last block optionally pad the data with zeros*/
4831 for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
4832 {
4833 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4834 hcryp->CrypInCount++;
4835 }
4836 while(loopcounter < 4U )
4837 {
4838 /* Pad the data with zeros to have a complete block */
4839 hcryp->Instance->DIN = 0x0U;
4840 loopcounter++;
4841 }
4842 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
4843
4844 if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
4845 {
4846 for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
4847 {
4848 /* Read the output block from the output FIFO and put them in temporary buffer */
4849 temp= hcryp->Instance->DOUT;
4850
4851 /*get CrypOutBuff from temporary buffer */
4852 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
4853 hcryp->CrypOutCount++;
4854 }
4855 }
4856 if(hcryp->CrypOutCount >= (hcryp->Size/4U))
4857 {
4858 /* Disable interrupts */
4859 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
4860
4861 /* Change the CRYP peripheral state */
4862 hcryp->State = HAL_CRYP_STATE_READY;
4863
4864 /* Process unlocked */
4865 __HAL_UNLOCK(hcryp);
4866
4867 /* Call output transfer complete callback */
4868 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4869 /*Call registered Output complete callback*/
4870 hcryp->OutCpltCallback(hcryp);
4871 #else
4872 /*Call legacy weak Output complete callback*/
4873 HAL_CRYP_OutCpltCallback(hcryp);
4874 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4875 }
4876 }
4877 else
4878 {
4879 /* Nothing to do */
4880 }
4881 #else /* AES */
4882
4883 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
4884 temp = hcryp->Instance->DOUTR;
4885 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
4886 hcryp->CrypOutCount++;
4887 temp = hcryp->Instance->DOUTR;
4888 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
4889 hcryp->CrypOutCount++;
4890 temp = hcryp->Instance->DOUTR;
4891 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
4892 hcryp->CrypOutCount++;
4893 temp = hcryp->Instance->DOUTR;
4894 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
4895 hcryp->CrypOutCount++;
4896 /*Temporary CrypOutCount Value*/
4897 outcount = hcryp->CrypOutCount;
4898
4899 if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) )
4900 {
4901 /* Disable computation complete flag and errors interrupts */
4902 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
4903
4904 /* Change the CRYP state */
4905 hcryp->State = HAL_CRYP_STATE_READY;
4906
4907 /* Process unlocked */
4908 __HAL_UNLOCK(hcryp);
4909
4910 /* Call output transfer complete callback */
4911 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4912 /*Call registered Output complete callback*/
4913 hcryp->OutCpltCallback(hcryp);
4914 #else
4915 /*Call legacy weak Output complete callback*/
4916 HAL_CRYP_OutCpltCallback(hcryp);
4917 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4918 }
4919
4920 else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
4921 {
4922 /* Write the input block in the IN FIFO */
4923 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4924 hcryp->CrypInCount++;
4925 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4926 hcryp->CrypInCount++;
4927 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4928 hcryp->CrypInCount++;
4929 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4930 hcryp->CrypInCount++;
4931 if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
4932 {
4933 /* Call Input transfer complete callback */
4934 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4935 /*Call registered Input complete callback*/
4936 hcryp->InCpltCallback(hcryp);
4937 #else
4938 /*Call legacy weak Input complete callback*/
4939 HAL_CRYP_InCpltCallback(hcryp);
4940 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4941 }
4942 }
4943 else /* Last block of payload < 128bit*/
4944 {
4945 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
4946 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
4947 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
4948
4949 /* Compute the number of padding bytes in last block of payload */
4950 npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
4951
4952 /* Number of valid words (lastwordsize) in last block */
4953 if ((npblb%4U) ==0U)
4954 {
4955 lastwordsize = (16U-npblb)/4U;
4956 }
4957 else
4958 {
4959 lastwordsize = ((16U-npblb)/4U) +1U;
4960 }
4961
4962 /* Last block optionally pad the data with zeros*/
4963 for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
4964 {
4965 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
4966 hcryp->CrypInCount++;
4967 }
4968 while(loopcounter < 4U )
4969 {
4970 /* pad the data with zeros to have a complete block */
4971 hcryp->Instance->DINR = 0x0U;
4972 loopcounter++;
4973 }
4974 }
4975 #endif /* AES */
4976
4977 }
4978
4979
4980 /**
4981 * @brief Sets the header phase in polling mode
4982 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4983 * the configuration information for CRYP module(Header & HeaderSize)
4984 * @param Timeout: Timeout value
4985 * @retval state
4986 */
4987 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4988 {
4989 uint32_t loopcounter;
4990
4991 /***************************** Header phase for GCM/GMAC or CCM *********************************/
4992
4993 if((hcryp->Init.HeaderSize != 0U))
4994 {
4995
4996 #if defined(CRYP)
4997
4998 /* Select header phase */
4999 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5000
5001 /* Enable the CRYP peripheral */
5002 __HAL_CRYP_ENABLE(hcryp);
5003
5004 if ((hcryp->Init.HeaderSize %4U )== 0U)
5005 {
5006 /* HeaderSize %4, no padding */
5007 for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
5008 {
5009 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5010 hcryp->CrypHeaderCount++ ;
5011 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5012 hcryp->CrypHeaderCount++ ;
5013 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5014 hcryp->CrypHeaderCount++ ;
5015 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5016 hcryp->CrypHeaderCount++ ;
5017
5018 /* Wait for IFEM to be raised */
5019 if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5020 {
5021 /* Disable the CRYP peripheral clock */
5022 __HAL_CRYP_DISABLE(hcryp);
5023
5024 /* Change state */
5025 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5026 hcryp->State = HAL_CRYP_STATE_READY;
5027
5028 /* Process unlocked */
5029 __HAL_UNLOCK(hcryp);
5030 return HAL_ERROR;
5031 }
5032 }
5033 }
5034 else
5035 {
5036 /*Write header block in the IN FIFO without last block */
5037 for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
5038 {
5039 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5040 hcryp->CrypHeaderCount++ ;
5041 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5042 hcryp->CrypHeaderCount++ ;
5043 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5044 hcryp->CrypHeaderCount++ ;
5045 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5046 hcryp->CrypHeaderCount++ ;
5047
5048 /* Wait for IFEM to be raised */
5049 if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5050 {
5051 /* Disable the CRYP peripheral clock */
5052 __HAL_CRYP_DISABLE(hcryp);
5053
5054 /* Change state */
5055 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5056 hcryp->State = HAL_CRYP_STATE_READY;
5057
5058 /* Process unlocked */
5059 __HAL_UNLOCK(hcryp);
5060 return HAL_ERROR;
5061 }
5062 }
5063 /* Last block optionally pad the data with zeros*/
5064 for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
5065 {
5066 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5067 hcryp->CrypHeaderCount++ ;
5068 }
5069 while(loopcounter <4U )
5070 {
5071 /* pad the data with zeros to have a complete block */
5072 hcryp->Instance->DIN = 0x0U;
5073 loopcounter++;
5074 }
5075 /* Wait for CCF IFEM to be raised */
5076 if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5077 {
5078 /* Disable the CRYP peripheral clock */
5079 __HAL_CRYP_DISABLE(hcryp);
5080
5081 /* Change state */
5082 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5083 hcryp->State = HAL_CRYP_STATE_READY;
5084
5085 /* Process unlocked */
5086 __HAL_UNLOCK(hcryp);
5087 return HAL_ERROR;
5088 }
5089 }
5090 /* Wait until the complete message has been processed */
5091 if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5092 {
5093 /* Disable the CRYP peripheral clock */
5094 __HAL_CRYP_DISABLE(hcryp);
5095
5096 /* Change state */
5097 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5098 hcryp->State = HAL_CRYP_STATE_READY;
5099
5100 /* Process unlocked & return error */
5101 __HAL_UNLOCK(hcryp);
5102 return HAL_ERROR;
5103 }
5104
5105 #else /* AES */
5106
5107 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5108 {
5109 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5110 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5111
5112 /* Select header phase */
5113 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5114
5115 /* Enable the CRYP peripheral */
5116 __HAL_CRYP_ENABLE(hcryp);
5117
5118 }
5119 if ((hcryp->Init.HeaderSize %4U )== 0U)
5120 {
5121 /* HeaderSize %4, no padding */
5122 for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U)
5123 {
5124 /* Write the input block in the data input register */
5125 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5126 hcryp->CrypHeaderCount++ ;
5127 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5128 hcryp->CrypHeaderCount++ ;
5129 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5130 hcryp->CrypHeaderCount++ ;
5131 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5132 hcryp->CrypHeaderCount++ ;
5133
5134 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5135 {
5136 /* Disable the CRYP peripheral clock */
5137 __HAL_CRYP_DISABLE(hcryp);
5138
5139 /* Change state */
5140 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5141 hcryp->State = HAL_CRYP_STATE_READY;
5142
5143 /* Process unlocked */
5144 __HAL_UNLOCK(hcryp);
5145 return HAL_ERROR;
5146 }
5147 /* Clear CCF flag */
5148 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5149 }
5150 }
5151 else
5152 {
5153 /*Write header block in the IN FIFO without last block */
5154 for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
5155 {
5156 /* Write the input block in the data input register */
5157 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5158 hcryp->CrypHeaderCount++ ;
5159 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5160 hcryp->CrypHeaderCount++ ;
5161 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5162 hcryp->CrypHeaderCount++ ;
5163 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5164 hcryp->CrypHeaderCount++ ;
5165
5166 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5167 {
5168 /* Disable the CRYP peripheral clock */
5169 __HAL_CRYP_DISABLE(hcryp);
5170
5171 /* Change state */
5172 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5173 hcryp->State = HAL_CRYP_STATE_READY;
5174
5175 /* Process unlocked */
5176 __HAL_UNLOCK(hcryp);
5177 return HAL_ERROR;
5178 }
5179 /* Clear CCF flag */
5180 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5181 }
5182 /* Last block optionally pad the data with zeros*/
5183 for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
5184 {
5185 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5186 hcryp->CrypHeaderCount++ ;
5187 }
5188 while(loopcounter < 4U )
5189 {
5190 /*Pad the data with zeros to have a complete block */
5191 hcryp->Instance->DINR = 0x0U;
5192 loopcounter++;
5193 }
5194
5195 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5196 {
5197 /* Disable the CRYP peripheral clock */
5198 __HAL_CRYP_DISABLE(hcryp);
5199
5200 /* Change state */
5201 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5202 hcryp->State = HAL_CRYP_STATE_READY;
5203
5204 /* Process unlocked */
5205 __HAL_UNLOCK(hcryp);
5206 return HAL_ERROR;
5207 }
5208 /* Clear CCF flag */
5209 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5210 }
5211 #endif /* End AES or CRYP */
5212 }
5213 else
5214 {
5215 #if defined(AES)
5216 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5217 {
5218 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5219 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5220
5221 /* Select header phase */
5222 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5223
5224 /* Enable the CRYP peripheral */
5225 __HAL_CRYP_ENABLE(hcryp);
5226 }
5227 #endif /* AES */
5228 }
5229 /* Return function status */
5230 return HAL_OK;
5231 }
5232
5233 /**
5234 * @brief Sets the header phase when using DMA in process
5235 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5236 * the configuration information for CRYP module(Header & HeaderSize)
5237 * @retval None
5238 */
5239 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5240 {
5241 __IO uint32_t count = 0U;
5242 uint32_t loopcounter;
5243
5244 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5245 if((hcryp->Init.HeaderSize != 0U))
5246 {
5247
5248 #if defined(CRYP)
5249
5250 /* Select header phase */
5251 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5252
5253 /* Enable the CRYP peripheral */
5254 __HAL_CRYP_ENABLE(hcryp);
5255
5256 if ((hcryp->Init.HeaderSize %4U )== 0U)
5257 {
5258 /* HeaderSize %4, no padding */
5259 for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
5260 {
5261 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5262 hcryp->CrypHeaderCount++ ;
5263 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5264 hcryp->CrypHeaderCount++ ;
5265 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5266 hcryp->CrypHeaderCount++ ;
5267 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5268 hcryp->CrypHeaderCount++ ;
5269
5270 /* Wait for IFEM to be raised */
5271 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5272 do
5273 {
5274 count-- ;
5275 if(count == 0U)
5276 {
5277 /* Disable the CRYP peripheral clock */
5278 __HAL_CRYP_DISABLE(hcryp);
5279
5280 /* Change state */
5281 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5282 hcryp->State = HAL_CRYP_STATE_READY;
5283
5284 /* Process unlocked */
5285 __HAL_UNLOCK(hcryp);
5286 return HAL_ERROR;
5287 }
5288 }
5289 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5290 }
5291 }
5292 else
5293 {
5294 /*Write header block in the IN FIFO without last block */
5295 for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
5296 {
5297 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5298 hcryp->CrypHeaderCount++ ;
5299 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5300 hcryp->CrypHeaderCount++ ;
5301 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5302 hcryp->CrypHeaderCount++ ;
5303 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5304 hcryp->CrypHeaderCount++ ;
5305
5306 /* Wait for IFEM to be raised */
5307 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5308 do
5309 {
5310 count-- ;
5311 if(count == 0U)
5312 {
5313 /* Disable the CRYP peripheral clock */
5314 __HAL_CRYP_DISABLE(hcryp);
5315
5316 /* Change state */
5317 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5318 hcryp->State = HAL_CRYP_STATE_READY;
5319
5320 /* Process unlocked */
5321 __HAL_UNLOCK(hcryp);
5322 return HAL_ERROR;
5323 }
5324 }
5325 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5326 }
5327 /* Last block optionally pad the data with zeros*/
5328 for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
5329 {
5330 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5331 hcryp->CrypHeaderCount++ ;
5332 }
5333 while(loopcounter < 4U )
5334 {
5335 /* Pad the data with zeros to have a complete block */
5336 hcryp->Instance->DIN = 0x0U;
5337 loopcounter++;
5338 }
5339 /* Wait for IFEM to be raised */
5340 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5341 do
5342 {
5343 count-- ;
5344 if(count == 0U)
5345 {
5346 /* Disable the CRYP peripheral clock */
5347 __HAL_CRYP_DISABLE(hcryp);
5348
5349 /* Change state */
5350 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5351 hcryp->State = HAL_CRYP_STATE_READY;
5352
5353 /* Process unlocked */
5354 __HAL_UNLOCK(hcryp);
5355 return HAL_ERROR;
5356 }
5357 }
5358 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5359 }
5360 /* Wait until the complete message has been processed */
5361 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5362 do
5363 {
5364 count-- ;
5365 if(count == 0U)
5366 {
5367 /* Disable the CRYP peripheral clock */
5368 __HAL_CRYP_DISABLE(hcryp);
5369
5370 /* Change state */
5371 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5372 hcryp->State = HAL_CRYP_STATE_READY;
5373
5374 /* Process unlocked */
5375 __HAL_UNLOCK(hcryp);
5376 return HAL_ERROR;
5377 }
5378 }
5379 while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
5380
5381 #else /* AES */
5382
5383 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5384 {
5385 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5386 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5387
5388 /* Select header phase */
5389 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5390
5391 /* Enable the CRYP peripheral */
5392 __HAL_CRYP_ENABLE(hcryp);
5393 }
5394 if ((hcryp->Init.HeaderSize %4U )== 0U)
5395 {
5396 /* HeaderSize %4, no padding */
5397 for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
5398 {
5399 /* Write the input block in the data input register */
5400 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5401 hcryp->CrypHeaderCount++ ;
5402 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5403 hcryp->CrypHeaderCount++ ;
5404 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5405 hcryp->CrypHeaderCount++ ;
5406 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5407 hcryp->CrypHeaderCount++ ;
5408
5409 /*Wait on CCF flag*/
5410 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5411 do
5412 {
5413 count-- ;
5414 if(count == 0U)
5415 {
5416 /* Disable the CRYP peripheral clock */
5417 __HAL_CRYP_DISABLE(hcryp);
5418
5419 /* Change state */
5420 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5421 hcryp->State = HAL_CRYP_STATE_READY;
5422
5423 /* Process unlocked */
5424 __HAL_UNLOCK(hcryp);
5425 return HAL_ERROR;
5426 }
5427 }
5428 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5429
5430 /* Clear CCF flag */
5431 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5432 }
5433 }
5434 else
5435 {
5436 /*Write header block in the IN FIFO without last block */
5437 for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
5438 {
5439 /* Write the Input block in the Data Input register */
5440 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5441 hcryp->CrypHeaderCount++ ;
5442 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5443 hcryp->CrypHeaderCount++ ;
5444 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5445 hcryp->CrypHeaderCount++ ;
5446 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5447 hcryp->CrypHeaderCount++ ;
5448
5449 /*Wait on CCF flag*/
5450 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5451 do
5452 {
5453 count-- ;
5454 if(count == 0U)
5455 {
5456 /* Disable the CRYP peripheral clock */
5457 __HAL_CRYP_DISABLE(hcryp);
5458
5459 /* Change state */
5460 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5461 hcryp->State = HAL_CRYP_STATE_READY;
5462
5463 /* Process unlocked */
5464 __HAL_UNLOCK(hcryp);
5465 return HAL_ERROR;
5466 }
5467 }
5468 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5469
5470 /* Clear CCF flag */
5471 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5472 }
5473 /* Last block optionally pad the data with zeros*/
5474 for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
5475 {
5476 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5477 hcryp->CrypHeaderCount++ ;
5478 }
5479 while(loopcounter <4U )
5480 {
5481 /* Pad the data with zeros to have a complete block */
5482 hcryp->Instance->DINR = 0x0U;
5483 loopcounter++;
5484 }
5485
5486 /*Wait on CCF flag*/
5487 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5488 do
5489 {
5490 count-- ;
5491 if(count == 0U)
5492 {
5493 /* Disable the CRYP peripheral clock */
5494 __HAL_CRYP_DISABLE(hcryp);
5495
5496 /* Change state */
5497 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5498 hcryp->State = HAL_CRYP_STATE_READY;
5499
5500 /* Process unlocked */
5501 __HAL_UNLOCK(hcryp);
5502 return HAL_ERROR;
5503 }
5504 }
5505 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5506
5507 /* Clear CCF flag */
5508 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5509 }
5510 #endif /* End AES or CRYP */
5511 }
5512 else
5513 {
5514 #if defined(AES)
5515 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5516 {
5517 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5518 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5519
5520 /* Select header phase */
5521 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5522
5523 /* Enable the CRYP peripheral */
5524 __HAL_CRYP_ENABLE(hcryp);
5525 }
5526 #endif /* AES */
5527 }
5528 /* Return function status */
5529 return HAL_OK;
5530 }
5531
5532 /**
5533 * @brief Sets the header phase in interrupt mode
5534 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5535 * the configuration information for CRYP module(Header & HeaderSize)
5536 * @retval None
5537 */
5538 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
5539 {
5540 uint32_t loopcounter;
5541 #if defined(AES)
5542 uint32_t lastwordsize;
5543 uint32_t npblb;
5544 #endif
5545 /***************************** Header phase *********************************/
5546
5547 #if defined(CRYP)
5548 if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
5549 {
5550 /* Disable interrupts */
5551 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
5552
5553 /* Disable the CRYP peripheral */
5554 __HAL_CRYP_DISABLE(hcryp);
5555
5556 /* Set the phase */
5557 hcryp->Phase = CRYP_PHASE_PROCESS;
5558
5559 /* Select payload phase once the header phase is performed */
5560 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5561
5562 /* Enable Interrupts */
5563 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
5564
5565 /* Enable the CRYP peripheral */
5566 __HAL_CRYP_ENABLE(hcryp);
5567 }
5568 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
5569
5570 { /* HeaderSize %4, no padding */
5571 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
5572 hcryp->CrypHeaderCount++ ;
5573 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5574 hcryp->CrypHeaderCount++ ;
5575 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5576 hcryp->CrypHeaderCount++ ;
5577 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5578 hcryp->CrypHeaderCount++ ;
5579 }
5580 else
5581 {
5582 /* Last block optionally pad the data with zeros*/
5583 for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
5584 {
5585 hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
5586 hcryp->CrypHeaderCount++ ;
5587 }
5588 while(loopcounter <4U )
5589 {
5590 /* Pad the data with zeros to have a complete block */
5591 hcryp->Instance->DIN = 0x0U;
5592 loopcounter++;
5593 }
5594 }
5595 #else /* AES */
5596
5597 if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
5598 {
5599 /* Set the phase */
5600 hcryp->Phase = CRYP_PHASE_PROCESS;
5601
5602 /* Payload phase not supported in CCM AES2 */
5603 if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5604 {
5605 /* Select payload phase once the header phase is performed */
5606 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
5607 }
5608 if(hcryp->Init.Algorithm == CRYP_AES_CCM)
5609 {
5610 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
5611 hcryp->CrypHeaderCount++;
5612 }
5613 /* Write the payload Input block in the IN FIFO */
5614 if(hcryp->Size == 0U)
5615 {
5616 /* Disable interrupts */
5617 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
5618
5619 /* Change the CRYP state */
5620 hcryp->State = HAL_CRYP_STATE_READY;
5621
5622 /* Process unlocked */
5623 __HAL_UNLOCK(hcryp);
5624 }
5625 else if (hcryp->Size >= 16U)
5626 {
5627 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5628 hcryp->CrypInCount++;
5629 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5630 hcryp->CrypInCount++;
5631 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5632 hcryp->CrypInCount++;
5633 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5634 hcryp->CrypInCount++;
5635
5636 if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U))
5637 {
5638 /* Call the input data transfer complete callback */
5639 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5640 /*Call registered Input complete callback*/
5641 hcryp->InCpltCallback(hcryp);
5642 #else
5643 /*Call legacy weak Input complete callback*/
5644 HAL_CRYP_InCpltCallback(hcryp);
5645 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5646 }
5647 }
5648 else /* Size < 4 words : first block is the last block*/
5649 {
5650 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5651 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
5652 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
5653
5654 /* Compute the number of padding bytes in last block of payload */
5655 npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
5656
5657 /* Number of valid words (lastwordsize) in last block */
5658 if ((npblb % 4U) ==0U)
5659 {
5660 lastwordsize = (16U-npblb)/4U;
5661 }
5662 else
5663 {
5664 lastwordsize = ((16U-npblb)/4U) +1U;
5665 }
5666
5667 /* Last block optionally pad the data with zeros*/
5668 for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5669 {
5670 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5671 hcryp->CrypInCount++;
5672 }
5673 while(loopcounter <4U )
5674 {
5675 /* Pad the data with zeros to have a complete block */
5676 hcryp->Instance->DINR = 0x0U;
5677 loopcounter++;
5678 }
5679 }
5680 }
5681 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
5682 {
5683 /* Write the input block in the IN FIFO */
5684 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
5685 hcryp->CrypHeaderCount++;
5686 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
5687 hcryp->CrypHeaderCount++;
5688 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
5689 hcryp->CrypHeaderCount++;
5690 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
5691 hcryp->CrypHeaderCount++;
5692 }
5693 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
5694 {
5695 /* Last block optionally pad the data with zeros*/
5696 for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
5697 {
5698 hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5699 hcryp->CrypHeaderCount++ ;
5700 }
5701 while(loopcounter <4U )
5702 {
5703 /* pad the data with zeros to have a complete block */
5704 hcryp->Instance->DINR = 0x0U;
5705 loopcounter++;
5706 }
5707 }
5708 #endif /* End AES or CRYP */
5709 }
5710
5711
5712 /**
5713 * @brief Workaround used for GCM/CCM mode.
5714 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5715 * the configuration information for CRYP module
5716 * @param Timeout: specify Timeout value
5717 * @retval None
5718 */
5719 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
5720 {
5721 uint32_t lastwordsize;
5722 uint32_t npblb;
5723 #if defined(CRYP)
5724 uint32_t iv1temp;
5725 uint32_t temp[4] = {0};
5726 uint32_t temp2[4]= {0};
5727 #endif /* CRYP */
5728 uint32_t intermediate_data[4]={0};
5729 uint32_t index;
5730
5731 /* Compute the number of padding bytes in last block of payload */
5732 npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
5733
5734 /* Number of valid words (lastwordsize) in last block */
5735 if ((npblb%4U) ==0U)
5736 { lastwordsize = (16U-npblb)/4U;
5737 }
5738 else
5739 {lastwordsize = ((16U-npblb)/4U) +1U;
5740 }
5741
5742 #if defined(CRYP)
5743
5744 /* Workaround 2, case GCM encryption */
5745 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
5746 {
5747 if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
5748 {/*Workaround in order to properly compute authentication tags while doing
5749 a GCM encryption with the last block of payload size inferior to 128 bits*/
5750 /* Disable CRYP to start the final phase */
5751 __HAL_CRYP_DISABLE(hcryp);
5752
5753 /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
5754 by 1 and reinsert the result in CRYP_IV1R register*/
5755 hcryp->Instance->IV1RR = 0x5U;
5756 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
5757
5758 /* Enable CRYP to start the final phase */
5759 __HAL_CRYP_ENABLE(hcryp);
5760 }
5761 /* Last block optionally pad the data with zeros*/
5762 for(index=0; index < lastwordsize; index ++)
5763 {
5764 /* Write the last input block in the IN FIFO */
5765 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5766 hcryp->CrypInCount++;
5767 }
5768 while(index < 4U)
5769 {
5770 /* Pad the data with zeros to have a complete block */
5771 hcryp->Instance->DIN = 0U;
5772 index++;
5773 }
5774 /* Wait for OFNE flag to be raised */
5775 if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
5776 {
5777 /* Disable the CRYP peripheral clock */
5778 __HAL_CRYP_DISABLE(hcryp);
5779
5780 /* Change state */
5781 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5782 hcryp->State = HAL_CRYP_STATE_READY;
5783
5784 /* Process Unlocked */
5785 __HAL_UNLOCK(hcryp);
5786 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5787 /*Call registered error callback*/
5788 hcryp->ErrorCallback(hcryp);
5789 #else
5790 /*Call legacy weak error callback*/
5791 HAL_CRYP_ErrorCallback(hcryp);
5792 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5793 }
5794 if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
5795 {
5796 for(index=0U; index< 4U;index++)
5797 {
5798 /* Read the output block from the output FIFO */
5799 intermediate_data[index] = hcryp->Instance->DOUT;
5800
5801 /* Intermediate data buffer to be used in for the workaround*/
5802 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
5803 hcryp->CrypOutCount++;
5804 }
5805 }
5806
5807 if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
5808 {
5809 /*workaround in order to properly compute authentication tags while doing
5810 a GCM encryption with the last block of payload size inferior to 128 bits*/
5811 /* Change the AES mode to GCM mode and Select Final phase */
5812 /* configured CHMOD GCM */
5813 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
5814
5815 /* configured final phase */
5816 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
5817
5818 for (index=0U; index < lastwordsize; index ++)
5819 {
5820 /*Write the intermediate_data in the IN FIFO */
5821 hcryp->Instance->DIN=intermediate_data[index];
5822 }
5823 while(index < 4U)
5824 {
5825 /* Pad the data with zeros to have a complete block */
5826 hcryp->Instance->DIN = 0x0U;
5827 index++;
5828 }
5829 /* Wait for OFNE flag to be raised */
5830 if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
5831 {
5832 /* Disable the CRYP peripheral clock */
5833 __HAL_CRYP_DISABLE(hcryp);
5834
5835 /* Change state */
5836 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5837 hcryp->State = HAL_CRYP_STATE_READY;
5838
5839 /* Process unlocked */
5840 __HAL_UNLOCK(hcryp);
5841 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5842 /*Call registered error callback*/
5843 hcryp->ErrorCallback(hcryp);
5844 #else
5845 /*Call legacy weak error callback*/
5846 HAL_CRYP_ErrorCallback(hcryp);
5847 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5848 }
5849
5850 if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
5851 {
5852 for( index=0U; index< 4U;index++)
5853 {
5854 intermediate_data[index]=hcryp->Instance->DOUT;
5855 }
5856 }
5857 }
5858 } /* End of GCM encryption */
5859 else{ /* Workaround 2, case CCM decryption, in order to properly compute
5860 authentication tags while doing a CCM decryption with the last block
5861 of payload size inferior to 128 bits*/
5862
5863 if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
5864 {
5865 iv1temp = hcryp->Instance->CSGCMCCM7R;
5866
5867 /* Disable CRYP to start the final phase */
5868 __HAL_CRYP_DISABLE(hcryp);
5869
5870 temp[0]= hcryp->Instance->CSGCMCCM0R;
5871 temp[1]= hcryp->Instance->CSGCMCCM1R;
5872 temp[2]= hcryp->Instance->CSGCMCCM2R;
5873 temp[3]= hcryp->Instance->CSGCMCCM3R;
5874
5875 hcryp->Instance->IV1RR= iv1temp;
5876
5877 /* Configured CHMOD CTR */
5878 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
5879
5880 /* Enable CRYP to start the final phase */
5881 __HAL_CRYP_ENABLE(hcryp);
5882 }
5883 /* Last block optionally pad the data with zeros*/
5884 for(index=0; index < lastwordsize; index ++)
5885 {
5886 /* Write the last Input block in the IN FIFO */
5887 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
5888 hcryp->CrypInCount++;
5889 }
5890 while(index < 4U)
5891 {
5892 /* Pad the data with zeros to have a complete block */
5893 hcryp->Instance->DIN = 0U;
5894 index++;
5895 }
5896 /* Wait for OFNE flag to be raised */
5897 if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
5898 {
5899 /* Disable the CRYP peripheral clock */
5900 __HAL_CRYP_DISABLE(hcryp);
5901
5902 /* Change state */
5903 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5904 hcryp->State = HAL_CRYP_STATE_READY;
5905
5906 /* Process Unlocked */
5907 __HAL_UNLOCK(hcryp);
5908 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5909 /*Call registered error callback*/
5910 hcryp->ErrorCallback(hcryp);
5911 #else
5912 /*Call legacy weak error callback*/
5913 HAL_CRYP_ErrorCallback(hcryp);
5914 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5915 }
5916
5917 if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
5918 {
5919 for(index=0U; index< 4U;index++)
5920 {
5921 /* Read the Output block from the Output FIFO */
5922 intermediate_data[index] = hcryp->Instance->DOUT;
5923
5924 /*intermediate data buffer to be used in for the workaround*/
5925 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
5926 hcryp->CrypOutCount++;
5927 }
5928 }
5929
5930 if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
5931 {
5932 temp2[0]= hcryp->Instance->CSGCMCCM0R;
5933 temp2[1]= hcryp->Instance->CSGCMCCM1R;
5934 temp2[2]= hcryp->Instance->CSGCMCCM2R;
5935 temp2[3]= hcryp->Instance->CSGCMCCM3R;
5936
5937 /* configured CHMOD CCM */
5938 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
5939
5940 /* configured Header phase */
5941 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
5942
5943 /*set to zero the bits corresponding to the padded bits*/
5944 for(index = lastwordsize; index<4U; index ++)
5945 {
5946 intermediate_data[index] =0U;
5947 }
5948 if ((npblb %4U)==1U)
5949 {
5950 intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
5951 }
5952 if ((npblb %4U)==2U)
5953 {
5954 intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
5955 }
5956 if ((npblb %4U)==3U)
5957 {
5958 intermediate_data[lastwordsize-1U] &= 0xFF000000U;
5959 }
5960 for(index=0U; index < 4U ; index ++)
5961 {
5962 intermediate_data[index] ^= temp[index];
5963 intermediate_data[index] ^= temp2[index];
5964 }
5965 for(index = 0U; index < 4U; index ++)
5966 {
5967 /* Write the last Input block in the IN FIFO */
5968 hcryp->Instance->DIN = intermediate_data[index] ;
5969 }
5970
5971 /* Wait for BUSY flag to be raised */
5972 if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5973 {
5974 /* Disable the CRYP peripheral clock */
5975 __HAL_CRYP_DISABLE(hcryp);
5976
5977 /* Change state */
5978 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5979 hcryp->State = HAL_CRYP_STATE_READY;
5980
5981 /* Process Unlocked */
5982 __HAL_UNLOCK(hcryp);
5983 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5984 /*Call registered error callback*/
5985 hcryp->ErrorCallback(hcryp);
5986 #else
5987 /*Call legacy weak error callback*/
5988 HAL_CRYP_ErrorCallback(hcryp);
5989 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5990 }
5991 }
5992 } /* End of CCM WKA*/
5993
5994 /* Process Unlocked */
5995 __HAL_UNLOCK(hcryp);
5996
5997 #else /* AES */
5998
5999 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6000 the last block of paylaod, which size is inferior to 128 bits */
6001
6002 if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6003 {
6004 /* configured CHMOD CTR */
6005 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6006 }
6007 /* last block optionally pad the data with zeros*/
6008 for(index = 0U; index < lastwordsize; index ++)
6009 {
6010 /* Write the last Input block in the IN FIFO */
6011 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
6012 hcryp->CrypInCount++;
6013 }
6014 while(index < 4U)
6015 {
6016 /* pad the data with zeros to have a complete block */
6017 hcryp->Instance->DINR = 0U;
6018 index++;
6019 }
6020 /* Wait for CCF flag to be raised */
6021 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6022 {
6023 hcryp->State = HAL_CRYP_STATE_READY;
6024 __HAL_UNLOCK(hcryp);
6025 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6026 /*Call registered error callback*/
6027 hcryp->ErrorCallback(hcryp);
6028 #else
6029 /*Call legacy weak error callback*/
6030 HAL_CRYP_ErrorCallback(hcryp);
6031 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6032 }
6033
6034 /* Clear CCF Flag */
6035 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6036
6037 for(index = 0U; index< 4U;index++)
6038 {
6039 /* Read the Output block from the Output FIFO */
6040 intermediate_data[index] = hcryp->Instance->DOUTR;
6041
6042 /*intermediate data buffer to be used in the workaround*/
6043 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
6044 hcryp->CrypOutCount++;
6045 }
6046
6047 if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6048 {
6049 /* configured CHMOD GCM */
6050 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6051
6052 /* Select final phase */
6053 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6054
6055 /*Write the intermediate_data in the IN FIFO */
6056 for(index = 0U; index < lastwordsize; index ++)
6057 {
6058 hcryp->Instance->DINR = intermediate_data[index];
6059 }
6060 while(index < 4U)
6061 {
6062 /* pad the data with zeros to have a complete block */
6063 hcryp->Instance->DINR = 0U;
6064 index++;
6065 }
6066 /* Wait for CCF flag to be raised */
6067 if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6068 {
6069 /* Disable the CRYP peripheral clock */
6070 __HAL_CRYP_DISABLE(hcryp);
6071
6072 /* Change state */
6073 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6074 hcryp->State = HAL_CRYP_STATE_READY;
6075
6076 /* Process Unlocked */
6077 __HAL_UNLOCK(hcryp);
6078 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6079 /*Call registered error callback*/
6080 hcryp->ErrorCallback(hcryp);
6081 #else
6082 /*Call legacy weak error callback*/
6083 HAL_CRYP_ErrorCallback(hcryp);
6084 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6085 }
6086 /* Clear CCF Flag */
6087 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6088
6089 for( index = 0U; index< 4U;index++)
6090 {
6091 intermediate_data[index]=hcryp->Instance->DOUTR;
6092 }
6093 }/*End of Workaround 2*/
6094
6095 #endif /* End AES or CRYP */
6096 }
6097
6098 #if defined (CRYP)
6099
6100 /**
6101 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
6102 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6103 * the configuration information for CRYP module.
6104 * @param Timeout: Timeout duration.
6105 * @retval HAL status
6106 */
6107 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6108 {
6109 uint32_t tickstart;
6110
6111 /* Get timeout */
6112 tickstart = HAL_GetTick();
6113
6114 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
6115 {
6116 /* Check for the Timeout */
6117 if(Timeout != HAL_MAX_DELAY)
6118 {
6119 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
6120 {
6121 return HAL_ERROR;
6122 }
6123 }
6124 }
6125 return HAL_OK;
6126 }
6127
6128 /**
6129 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
6130 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6131 * the configuration information for CRYP module.
6132 * @param Timeout: Timeout duration.
6133 * @retval HAL status
6134 */
6135 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6136 {
6137 uint32_t tickstart;
6138
6139 /* Get timeout */
6140 tickstart = HAL_GetTick();
6141
6142 while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
6143 {
6144 /* Check for the Timeout */
6145 if(Timeout != HAL_MAX_DELAY)
6146 {
6147 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
6148 {
6149 return HAL_ERROR;
6150 }
6151 }
6152 }
6153 return HAL_OK;
6154 }
6155
6156
6157 /**
6158 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
6159 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6160 * the configuration information for CRYP module.
6161 * @param Timeout: Timeout duration.
6162 * @retval HAL status
6163 */
6164 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6165 {
6166 uint32_t tickstart;
6167
6168 /* Get timeout */
6169 tickstart = HAL_GetTick();
6170
6171 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
6172 {
6173 /* Check for the Timeout */
6174 if(Timeout != HAL_MAX_DELAY)
6175 {
6176 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
6177 {
6178 return HAL_ERROR;
6179 }
6180 }
6181 }
6182 return HAL_OK;
6183 }
6184
6185 #else /* AES */
6186
6187 /**
6188 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
6189 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6190 * the configuration information for CRYP module.
6191 * @param Timeout: Timeout duration.
6192 * @retval HAL status
6193 */
6194 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6195 {
6196 uint32_t tickstart;
6197
6198 /* Get timeout */
6199 tickstart = HAL_GetTick();
6200
6201 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
6202 {
6203 /* Check for the Timeout */
6204 if(Timeout != HAL_MAX_DELAY)
6205 {
6206 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) )
6207 {
6208 return HAL_ERROR;
6209 }
6210 }
6211 }
6212 return HAL_OK;
6213 }
6214
6215 #endif /* End AES or CRYP */
6216
6217
6218 /**
6219 * @}
6220 */
6221
6222
6223
6224 /**
6225 * @}
6226 */
6227
6228 /**
6229 * @}
6230 */
6231
6232 #endif /* HAL_CRYP_MODULE_ENABLED */
6233
6234
6235 /**
6236 * @}
6237 */
6238 #endif /* TinyAES or CRYP*/
6239 /**
6240 * @}
6241 */
6242
6243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/