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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_dma2d.c
blobc08a4b9a626a58296d3c81de14c5aace2ead1d3c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @brief DMA2D HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DMA2D peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#) Program the required configuration through the following parameters:
19 the transfer mode, the output color mode and the output offset using
20 HAL_DMA2D_Init() function.
21
22 (#) Program the required configuration through the following parameters:
23 the input color mode, the input color, the input alpha value, the alpha mode,
24 the red/blue swap mode, the inverted alpha mode and the input offset using
25 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
26
27 *** Polling mode IO operation ***
28 =================================
29 [..]
30 (#) Configure pdata parameter (explained hereafter), destination and data length
31 and enable the transfer using HAL_DMA2D_Start().
32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
33 user can specify the value of timeout according to his end application.
34
35 *** Interrupt mode IO operation ***
36 ===================================
37 [..]
38 (#) Configure pdata parameter, destination and data length and enable
39 the transfer using HAL_DMA2D_Start_IT().
40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
42 add his own function by customization of function pointer XferCpltCallback (member
43 of DMA2D handle structure).
44 (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
45 XferErrorCallback.
46
47 -@- In Register-to-Memory transfer mode, pdata parameter is the register
48 color, in Memory-to-memory or Memory-to-Memory with pixel format
49 conversion pdata is the source address.
50
51 -@- Configure the foreground source address, the background source address,
52 the destination and data length then Enable the transfer using
53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
54 in interrupt mode.
55
56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
57 are used if the memory to memory with blending transfer mode is selected.
58
59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
61
62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
63
64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
67 HAL_DMA2D_DisableDeadTime().
68
69 (#) The transfer can be suspended, resumed and aborted using the following
70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
71
72 (#) The CLUT loading can be suspended, resumed and aborted using the following
73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
74 HAL_DMA2D_CLUTLoading_Abort().
75
76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
77
78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
79
80 *** DMA2D HAL driver macros list ***
81 =============================================
82 [..]
83 Below the list of most used macros in DMA2D HAL driver :
84
85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
91
92 *** Callback registration ***
93 ===================================
94 [..]
95 (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
96 allows the user to configure dynamically the driver callbacks.
97 Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
98
99 (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
100 (+) XferCpltCallback : callback for transfer complete.
101 (+) XferErrorCallback : callback for transfer error.
102 (+) LineEventCallback : callback for line event.
103 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
104 (+) MspInitCallback : DMA2D MspInit.
105 (+) MspDeInitCallback : DMA2D MspDeInit.
106 This function takes as parameters the HAL peripheral handle, the Callback ID
107 and a pointer to the user callback function.
108
109 (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
110 weak (surcharged) function.
111 @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
112 and the Callback ID.
113 This function allows to reset following callbacks:
114 (+) XferCpltCallback : callback for transfer complete.
115 (+) XferErrorCallback : callback for transfer error.
116 (+) LineEventCallback : callback for line event.
117 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
118 (+) MspInitCallback : DMA2D MspInit.
119 (+) MspDeInitCallback : DMA2D MspDeInit.
120
121 (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
122 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
123 examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
124 Exception done for MspInit and MspDeInit callbacks that are respectively
125 reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
126 and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
127 If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
128 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
129
130 Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
131 as weak (surcharged) functions. They must be defined by the user to be resorted to.
132
133 Callbacks can be registered/unregistered in READY state only.
134 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
135 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
136 during the Init/DeInit.
137 In that case first register the MspInit/MspDeInit user callbacks
138 using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
139 or @ref HAL_DMA2D_Init function.
140
141 When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
142 not defined, the callback registering feature is not available
143 and weak (surcharged) callbacks are used.
144
145 [..]
146 (@) You can refer to the DMA2D HAL driver header file for more useful macros
147
148 @endverbatim
149 ******************************************************************************
150 * @attention
151 *
152 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
153 * All rights reserved.</center></h2>
154 *
155 * This software component is licensed by ST under BSD 3-Clause license,
156 * the "License"; You may not use this file except in compliance with the
157 * License. You may obtain a copy of the License at:
158 * opensource.org/licenses/BSD-3-Clause
159 *
160 ******************************************************************************
161 */
162
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32f7xx_hal.h"
165
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168
169 /** @addtogroup STM32F7xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup DMA2D DMA2D
174 * @brief DMA2D HAL module driver
175 * @{
176 */
177
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181 * @{
182 */
183
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185 * @{
186 */
187 #define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
188 #define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202 * @{
203 */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
205 /**
206 * @}
207 */
208
209 /* Private functions ---------------------------------------------------------*/
210 /* Exported functions --------------------------------------------------------*/
211 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
212 * @{
213 */
214
215 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
216 * @brief Initialization and Configuration functions
217 *
218 @verbatim
219 ===============================================================================
220 ##### Initialization and Configuration functions #####
221 ===============================================================================
222 [..] This section provides functions allowing to:
223 (+) Initialize and configure the DMA2D
224 (+) De-initialize the DMA2D
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the DMA2D according to the specified
232 * parameters in the DMA2D_InitTypeDef and create the associated handle.
233 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
234 * the configuration information for the DMA2D.
235 * @retval HAL status
236 */
237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
238 {
239 /* Check the DMA2D peripheral state */
240 if(hdma2d == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
247 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
248 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
249 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
250 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
251 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
252 assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
253 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
254
255 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
256 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
257 {
258 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
259 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
260 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
261 if(hdma2d->MspInitCallback == NULL)
262 {
263 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
264 }
265
266 /* Init the low level hardware */
267 hdma2d->MspInitCallback(hdma2d);
268 }
269 #else
270 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
271 {
272 /* Allocate lock resource and initialize it */
273 hdma2d->Lock = HAL_UNLOCKED;
274 /* Init the low level hardware */
275 HAL_DMA2D_MspInit(hdma2d);
276 }
277 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
278
279 /* Change DMA2D peripheral state */
280 hdma2d->State = HAL_DMA2D_STATE_BUSY;
281
282 /* DMA2D CR register configuration -------------------------------------------*/
283 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
284
285 /* DMA2D OPFCCR register configuration ---------------------------------------*/
286 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
287
288 /* DMA2D OOR register configuration ------------------------------------------*/
289 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
290 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
291 /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
292 MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
293 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
294
295
296 /* Update error code */
297 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
298
299 /* Initialize the DMA2D state*/
300 hdma2d->State = HAL_DMA2D_STATE_READY;
301
302 return HAL_OK;
303 }
304
305 /**
306 * @brief Deinitializes the DMA2D peripheral registers to their default reset
307 * values.
308 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
309 * the configuration information for the DMA2D.
310 * @retval None
311 */
312
313 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
314 {
315
316 /* Check the DMA2D peripheral state */
317 if(hdma2d == NULL)
318 {
319 return HAL_ERROR;
320 }
321
322 /* Before aborting any DMA2D transfer or CLUT loading, check
323 first whether or not DMA2D clock is enabled */
324 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
325 {
326 /* Abort DMA2D transfer if any */
327 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
328 {
329 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
330 {
331 /* Issue when aborting DMA2D transfer */
332 return HAL_ERROR;
333 }
334 }
335 else
336 {
337 /* Abort background CLUT loading if any */
338 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
339 {
340 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
341 {
342 /* Issue when aborting background CLUT loading */
343 return HAL_ERROR;
344 }
345 }
346 else
347 {
348 /* Abort foreground CLUT loading if any */
349 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
350 {
351 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
352 {
353 /* Issue when aborting foreground CLUT loading */
354 return HAL_ERROR;
355 }
356 }
357 }
358 }
359 }
360
361 /* Reset DMA2D control registers*/
362 hdma2d->Instance->CR = 0U;
363 hdma2d->Instance->IFCR = 0x3FU;
364 hdma2d->Instance->FGOR = 0U;
365 hdma2d->Instance->BGOR = 0U;
366 hdma2d->Instance->FGPFCCR = 0U;
367 hdma2d->Instance->BGPFCCR = 0U;
368 hdma2d->Instance->OPFCCR = 0U;
369
370 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
371
372 if(hdma2d->MspDeInitCallback == NULL)
373 {
374 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
375 }
376
377 /* DeInit the low level hardware */
378 hdma2d->MspDeInitCallback(hdma2d);
379
380 #else
381 /* Carry on with de-initialization of low level hardware */
382 HAL_DMA2D_MspDeInit(hdma2d);
383 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
384
385 /* Update error code */
386 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
387
388 /* Initialize the DMA2D state*/
389 hdma2d->State = HAL_DMA2D_STATE_RESET;
390
391 /* Release Lock */
392 __HAL_UNLOCK(hdma2d);
393
394 return HAL_OK;
395 }
396
397 /**
398 * @brief Initializes the DMA2D MSP.
399 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
400 * the configuration information for the DMA2D.
401 * @retval None
402 */
403 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
404 {
405 /* Prevent unused argument(s) compilation warning */
406 UNUSED(hdma2d);
407
408 /* NOTE : This function should not be modified; when the callback is needed,
409 the HAL_DMA2D_MspInit can be implemented in the user file.
410 */
411 }
412
413 /**
414 * @brief DeInitializes the DMA2D MSP.
415 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
416 * the configuration information for the DMA2D.
417 * @retval None
418 */
419 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
420 {
421 /* Prevent unused argument(s) compilation warning */
422 UNUSED(hdma2d);
423
424 /* NOTE : This function should not be modified; when the callback is needed,
425 the HAL_DMA2D_MspDeInit can be implemented in the user file.
426 */
427 }
428
429 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
430 /**
431 * @brief Register a User DMA2D Callback
432 * To be used instead of the weak (surcharged) predefined callback
433 * @param hdma2d DMA2D handle
434 * @param CallbackID ID of the callback to be registered
435 * This parameter can be one of the following values:
436 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
437 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
438 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
439 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
440 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
441 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
442 * @param pCallback pointer to the Callback function
443 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
444 * @retval status
445 */
446 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
447 {
448 HAL_StatusTypeDef status = HAL_OK;
449
450 if(pCallback == NULL)
451 {
452 /* Update the error code */
453 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
454 return HAL_ERROR;
455 }
456 /* Process locked */
457 __HAL_LOCK(hdma2d);
458
459 if(HAL_DMA2D_STATE_READY == hdma2d->State)
460 {
461 switch (CallbackID)
462 {
463 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
464 hdma2d->XferCpltCallback = pCallback;
465 break;
466
467 case HAL_DMA2D_TRANSFERERROR_CB_ID :
468 hdma2d->XferErrorCallback = pCallback;
469 break;
470
471 case HAL_DMA2D_LINEEVENT_CB_ID :
472 hdma2d->LineEventCallback = pCallback;
473 break;
474
475 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
476 hdma2d->CLUTLoadingCpltCallback = pCallback;
477 break;
478
479 case HAL_DMA2D_MSPINIT_CB_ID :
480 hdma2d->MspInitCallback = pCallback;
481 break;
482
483 case HAL_DMA2D_MSPDEINIT_CB_ID :
484 hdma2d->MspDeInitCallback = pCallback;
485 break;
486
487 default :
488 /* Update the error code */
489 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
490 /* update return status */
491 status = HAL_ERROR;
492 break;
493 }
494 }
495 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
496 {
497 switch (CallbackID)
498 {
499 case HAL_DMA2D_MSPINIT_CB_ID :
500 hdma2d->MspInitCallback = pCallback;
501 break;
502
503 case HAL_DMA2D_MSPDEINIT_CB_ID :
504 hdma2d->MspDeInitCallback = pCallback;
505 break;
506
507 default :
508 /* Update the error code */
509 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
510 /* update return status */
511 status = HAL_ERROR;
512 break;
513 }
514 }
515 else
516 {
517 /* Update the error code */
518 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
519 /* update return status */
520 status = HAL_ERROR;
521 }
522
523 /* Release Lock */
524 __HAL_UNLOCK(hdma2d);
525 return status;
526 }
527
528 /**
529 * @brief Unregister a DMA2D Callback
530 * DMA2D Callback is redirected to the weak (surcharged) predefined callback
531 * @param hdma2d DMA2D handle
532 * @param CallbackID ID of the callback to be unregistered
533 * This parameter can be one of the following values:
534 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
535 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
536 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
537 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
538 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
539 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
540 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
541 * @retval status
542 */
543 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
544 {
545 HAL_StatusTypeDef status = HAL_OK;
546
547 /* Process locked */
548 __HAL_LOCK(hdma2d);
549
550 if(HAL_DMA2D_STATE_READY == hdma2d->State)
551 {
552 switch (CallbackID)
553 {
554 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
555 hdma2d->XferCpltCallback = NULL;
556 break;
557
558 case HAL_DMA2D_TRANSFERERROR_CB_ID :
559 hdma2d->XferErrorCallback = NULL;
560 break;
561
562 case HAL_DMA2D_LINEEVENT_CB_ID :
563 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
564 break;
565
566 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
567 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
568 break;
569
570 case HAL_DMA2D_MSPINIT_CB_ID :
571 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
572 break;
573
574 case HAL_DMA2D_MSPDEINIT_CB_ID :
575 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
576 break;
577
578 default :
579 /* Update the error code */
580 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
581 /* update return status */
582 status = HAL_ERROR;
583 break;
584 }
585 }
586 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
587 {
588 switch (CallbackID)
589 {
590 case HAL_DMA2D_MSPINIT_CB_ID :
591 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
592 break;
593
594 case HAL_DMA2D_MSPDEINIT_CB_ID :
595 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
596 break;
597
598 default :
599 /* Update the error code */
600 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
601 /* update return status */
602 status = HAL_ERROR;
603 break;
604 }
605 }
606 else
607 {
608 /* Update the error code */
609 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
610 /* update return status */
611 status = HAL_ERROR;
612 }
613
614 /* Release Lock */
615 __HAL_UNLOCK(hdma2d);
616 return status;
617 }
618 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
619
620 /**
621 * @}
622 */
623
624
625 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
626 * @brief IO operation functions
627 *
628 @verbatim
629 ===============================================================================
630 ##### IO operation functions #####
631 ===============================================================================
632 [..] This section provides functions allowing to:
633 (+) Configure the pdata, destination address and data size then
634 start the DMA2D transfer.
635 (+) Configure the source for foreground and background, destination address
636 and data size then start a MultiBuffer DMA2D transfer.
637 (+) Configure the pdata, destination address and data size then
638 start the DMA2D transfer with interrupt.
639 (+) Configure the source for foreground and background, destination address
640 and data size then start a MultiBuffer DMA2D transfer with interrupt.
641 (+) Abort DMA2D transfer.
642 (+) Suspend DMA2D transfer.
643 (+) Resume DMA2D transfer.
644 (+) Enable CLUT transfer.
645 (+) Configure CLUT loading then start transfer in polling mode.
646 (+) Configure CLUT loading then start transfer in interrupt mode.
647 (+) Abort DMA2D CLUT loading.
648 (+) Suspend DMA2D CLUT loading.
649 (+) Resume DMA2D CLUT loading.
650 (+) Poll for transfer complete.
651 (+) handle DMA2D interrupt request.
652 (+) Transfer watermark callback.
653 (+) CLUT Transfer Complete callback.
654
655
656 @endverbatim
657 * @{
658 */
659
660 /**
661 * @brief Start the DMA2D Transfer.
662 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
663 * the configuration information for the DMA2D.
664 * @param pdata Configure the source memory Buffer address if
665 * Memory-to-Memory or Memory-to-Memory with pixel format
666 * conversion mode is selected, or configure
667 * the color value if Register-to-Memory mode is selected.
668 * @param DstAddress The destination memory Buffer address.
669 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
670 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
671 * @retval HAL status
672 */
673 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
674 {
675 /* Check the parameters */
676 assert_param(IS_DMA2D_LINE(Height));
677 assert_param(IS_DMA2D_PIXEL(Width));
678
679 /* Process locked */
680 __HAL_LOCK(hdma2d);
681
682 /* Change DMA2D peripheral state */
683 hdma2d->State = HAL_DMA2D_STATE_BUSY;
684
685 /* Configure the source, destination address and the data size */
686 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
687
688 /* Enable the Peripheral */
689 __HAL_DMA2D_ENABLE(hdma2d);
690
691 return HAL_OK;
692 }
693
694 /**
695 * @brief Start the DMA2D Transfer with interrupt enabled.
696 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
697 * the configuration information for the DMA2D.
698 * @param pdata Configure the source memory Buffer address if
699 * the Memory-to-Memory or Memory-to-Memory with pixel format
700 * conversion mode is selected, or configure
701 * the color value if Register-to-Memory mode is selected.
702 * @param DstAddress The destination memory Buffer address.
703 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
704 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
705 * @retval HAL status
706 */
707 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
708 {
709 /* Check the parameters */
710 assert_param(IS_DMA2D_LINE(Height));
711 assert_param(IS_DMA2D_PIXEL(Width));
712
713 /* Process locked */
714 __HAL_LOCK(hdma2d);
715
716 /* Change DMA2D peripheral state */
717 hdma2d->State = HAL_DMA2D_STATE_BUSY;
718
719 /* Configure the source, destination address and the data size */
720 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
721
722 /* Enable the transfer complete, transfer error and configuration error interrupts */
723 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
724
725 /* Enable the Peripheral */
726 __HAL_DMA2D_ENABLE(hdma2d);
727
728 return HAL_OK;
729 }
730
731 /**
732 * @brief Start the multi-source DMA2D Transfer.
733 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
734 * the configuration information for the DMA2D.
735 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
736 * @param SrcAddress2 The source memory Buffer address for the background layer.
737 * @param DstAddress The destination memory Buffer address.
738 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
739 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
740 * @retval HAL status
741 */
742 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
743 {
744 /* Check the parameters */
745 assert_param(IS_DMA2D_LINE(Height));
746 assert_param(IS_DMA2D_PIXEL(Width));
747
748 /* Process locked */
749 __HAL_LOCK(hdma2d);
750
751 /* Change DMA2D peripheral state */
752 hdma2d->State = HAL_DMA2D_STATE_BUSY;
753
754 /* Configure DMA2D Stream source2 address */
755 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
756
757 /* Configure the source, destination address and the data size */
758 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
759
760 /* Enable the Peripheral */
761 __HAL_DMA2D_ENABLE(hdma2d);
762
763 return HAL_OK;
764 }
765
766 /**
767 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
768 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
769 * the configuration information for the DMA2D.
770 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
771 * @param SrcAddress2 The source memory Buffer address for the background layer.
772 * @param DstAddress The destination memory Buffer address.
773 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
774 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
775 * @retval HAL status
776 */
777 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
778 {
779 /* Check the parameters */
780 assert_param(IS_DMA2D_LINE(Height));
781 assert_param(IS_DMA2D_PIXEL(Width));
782
783 /* Process locked */
784 __HAL_LOCK(hdma2d);
785
786 /* Change DMA2D peripheral state */
787 hdma2d->State = HAL_DMA2D_STATE_BUSY;
788
789 /* Configure DMA2D Stream source2 address */
790 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
791
792 /* Configure the source, destination address and the data size */
793 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
794
795 /* Enable the transfer complete, transfer error and configuration error interrupts */
796 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
797
798 /* Enable the Peripheral */
799 __HAL_DMA2D_ENABLE(hdma2d);
800
801 return HAL_OK;
802 }
803
804 /**
805 * @brief Abort the DMA2D Transfer.
806 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
807 * the configuration information for the DMA2D.
808 * @retval HAL status
809 */
810 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
811 {
812 uint32_t tickstart;
813
814 /* Abort the DMA2D transfer */
815 /* START bit is reset to make sure not to set it again, in the event the HW clears it
816 between the register read and the register write by the CPU (writing 0 has no
817 effect on START bitvalue) */
818 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
819
820 /* Get tick */
821 tickstart = HAL_GetTick();
822
823 /* Check if the DMA2D is effectively disabled */
824 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
825 {
826 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
827 {
828 /* Update error code */
829 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
830
831 /* Change the DMA2D state */
832 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
833
834 /* Process Unlocked */
835 __HAL_UNLOCK(hdma2d);
836
837 return HAL_TIMEOUT;
838 }
839 }
840
841 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
842 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
843
844 /* Change the DMA2D state*/
845 hdma2d->State = HAL_DMA2D_STATE_READY;
846
847 /* Process Unlocked */
848 __HAL_UNLOCK(hdma2d);
849
850 return HAL_OK;
851 }
852
853 /**
854 * @brief Suspend the DMA2D Transfer.
855 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
856 * the configuration information for the DMA2D.
857 * @retval HAL status
858 */
859 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
860 {
861 uint32_t tickstart;
862
863 /* Suspend the DMA2D transfer */
864 /* START bit is reset to make sure not to set it again, in the event the HW clears it
865 between the register read and the register write by the CPU (writing 0 has no
866 effect on START bitvalue). */
867 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
868
869 /* Get tick */
870 tickstart = HAL_GetTick();
871
872 /* Check if the DMA2D is effectively suspended */
873 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
874 {
875 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
876 {
877 /* Update error code */
878 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
879
880 /* Change the DMA2D state */
881 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
882
883 return HAL_TIMEOUT;
884 }
885 }
886
887 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
888 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
889 {
890 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
891 }
892 else
893 {
894 /* Make sure SUSP bit is cleared since it is meaningless
895 when no tranfer is on-going */
896 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
897 }
898
899 return HAL_OK;
900 }
901
902 /**
903 * @brief Resume the DMA2D Transfer.
904 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
905 * the configuration information for the DMA2D.
906 * @retval HAL status
907 */
908 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
909 {
910 /* Check the SUSP and START bits */
911 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
912 {
913 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
914 hdma2d->State = HAL_DMA2D_STATE_BUSY;
915 }
916
917 /* Resume the DMA2D transfer */
918 /* START bit is reset to make sure not to set it again, in the event the HW clears it
919 between the register read and the register write by the CPU (writing 0 has no
920 effect on START bitvalue). */
921 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
922
923 return HAL_OK;
924 }
925
926
927 /**
928 * @brief Enable the DMA2D CLUT Transfer.
929 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
930 * the configuration information for the DMA2D.
931 * @param LayerIdx DMA2D Layer index.
932 * This parameter can be one of the following values:
933 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
934 * @retval HAL status
935 */
936 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
937 {
938 /* Check the parameters */
939 assert_param(IS_DMA2D_LAYER(LayerIdx));
940
941 /* Process locked */
942 __HAL_LOCK(hdma2d);
943
944 /* Change DMA2D peripheral state */
945 hdma2d->State = HAL_DMA2D_STATE_BUSY;
946
947 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
948 {
949 /* Enable the background CLUT loading */
950 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
951 }
952 else
953 {
954 /* Enable the foreground CLUT loading */
955 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
956 }
957
958 return HAL_OK;
959 }
960
961
962 /**
963 * @brief Start DMA2D CLUT Loading.
964 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
965 * the configuration information for the DMA2D.
966 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
967 * the configuration information for the color look up table.
968 * @param LayerIdx DMA2D Layer index.
969 * This parameter can be one of the following values:
970 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
971 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
972 * @retval HAL status
973 */
974 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
975 {
976 /* Check the parameters */
977 assert_param(IS_DMA2D_LAYER(LayerIdx));
978 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
979 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
980
981 /* Process locked */
982 __HAL_LOCK(hdma2d);
983
984 /* Change DMA2D peripheral state */
985 hdma2d->State = HAL_DMA2D_STATE_BUSY;
986
987 /* Configure the CLUT of the background DMA2D layer */
988 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
989 {
990 /* Write background CLUT memory address */
991 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
992
993 /* Write background CLUT size and CLUT color mode */
994 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
995 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
996
997 /* Enable the CLUT loading for the background */
998 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
999 }
1000 /* Configure the CLUT of the foreground DMA2D layer */
1001 else
1002 {
1003 /* Write foreground CLUT memory address */
1004 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1005
1006 /* Write foreground CLUT size and CLUT color mode */
1007 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1008 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1009
1010 /* Enable the CLUT loading for the foreground */
1011 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1012 }
1013
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1019 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1020 * the configuration information for the DMA2D.
1021 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1022 * the configuration information for the color look up table.
1023 * @param LayerIdx DMA2D Layer index.
1024 * This parameter can be one of the following values:
1025 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1026 * @retval HAL status
1027 */
1028 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1029 {
1030 /* Check the parameters */
1031 assert_param(IS_DMA2D_LAYER(LayerIdx));
1032 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1033 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1034
1035 /* Process locked */
1036 __HAL_LOCK(hdma2d);
1037
1038 /* Change DMA2D peripheral state */
1039 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1040
1041 /* Configure the CLUT of the background DMA2D layer */
1042 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1043 {
1044 /* Write background CLUT memory address */
1045 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1046
1047 /* Write background CLUT size and CLUT color mode */
1048 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1049 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1050
1051 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1052 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1053
1054 /* Enable the CLUT loading for the background */
1055 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1056 }
1057 /* Configure the CLUT of the foreground DMA2D layer */
1058 else
1059 {
1060 /* Write foreground CLUT memory address */
1061 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1062
1063 /* Write foreground CLUT size and CLUT color mode */
1064 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1065 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1066
1067 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1068 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1069
1070 /* Enable the CLUT loading for the foreground */
1071 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1072 }
1073
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @brief Abort the DMA2D CLUT loading.
1079 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1080 * the configuration information for the DMA2D.
1081 * @param LayerIdx DMA2D Layer index.
1082 * This parameter can be one of the following values:
1083 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1084 * @retval HAL status
1085 */
1086 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1087 {
1088 uint32_t tickstart;
1089 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1090
1091 /* Abort the CLUT loading */
1092 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1093
1094 /* If foreground CLUT loading is considered, update local variables */
1095 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1096 {
1097 reg = &(hdma2d->Instance->FGPFCCR);
1098 }
1099
1100
1101 /* Get tick */
1102 tickstart = HAL_GetTick();
1103
1104 /* Check if the CLUT loading is aborted */
1105 while((*reg & DMA2D_BGPFCCR_START) != 0U)
1106 {
1107 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
1108 {
1109 /* Update error code */
1110 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1111
1112 /* Change the DMA2D state */
1113 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1114
1115 /* Process Unlocked */
1116 __HAL_UNLOCK(hdma2d);
1117
1118 return HAL_TIMEOUT;
1119 }
1120 }
1121
1122 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1123 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1124
1125 /* Change the DMA2D state*/
1126 hdma2d->State = HAL_DMA2D_STATE_READY;
1127
1128 /* Process Unlocked */
1129 __HAL_UNLOCK(hdma2d);
1130
1131 return HAL_OK;
1132 }
1133
1134 /**
1135 * @brief Suspend the DMA2D CLUT loading.
1136 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1137 * the configuration information for the DMA2D.
1138 * @param LayerIdx DMA2D Layer index.
1139 * This parameter can be one of the following values:
1140 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1141 * @retval HAL status
1142 */
1143 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1144 {
1145 uint32_t tickstart;
1146 uint32_t loadsuspended;
1147 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1148
1149 /* Suspend the CLUT loading */
1150 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1151
1152 /* If foreground CLUT loading is considered, update local variables */
1153 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1154 {
1155 reg = &(hdma2d->Instance->FGPFCCR);
1156 }
1157
1158 /* Get tick */
1159 tickstart = HAL_GetTick();
1160
1161 /* Check if the CLUT loading is suspended */
1162 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1163 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1164 while (loadsuspended == 0UL)
1165 {
1166 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
1167 {
1168 /* Update error code */
1169 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1170
1171 /* Change the DMA2D state */
1172 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1173
1174 return HAL_TIMEOUT;
1175 }
1176 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1177 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1178 }
1179
1180 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1181 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1182 {
1183 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1184 }
1185 else
1186 {
1187 /* Make sure SUSP bit is cleared since it is meaningless
1188 when no tranfer is on-going */
1189 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1190 }
1191
1192 return HAL_OK;
1193 }
1194
1195 /**
1196 * @brief Resume the DMA2D CLUT loading.
1197 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1198 * the configuration information for the DMA2D.
1199 * @param LayerIdx DMA2D Layer index.
1200 * This parameter can be one of the following values:
1201 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1202 * @retval HAL status
1203 */
1204 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1205 {
1206 /* Check the SUSP and START bits for background or foreground CLUT loading */
1207 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1208 {
1209 /* Background CLUT loading suspension check */
1210 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1211 {
1212 if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1213 {
1214 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1215 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1216 }
1217 }
1218 }
1219 else
1220 {
1221 /* Foreground CLUT loading suspension check */
1222 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1223 {
1224 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1225 {
1226 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1227 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1228 }
1229 }
1230 }
1231
1232 /* Resume the CLUT loading */
1233 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1234
1235 return HAL_OK;
1236 }
1237
1238
1239 /**
1240
1241 * @brief Polling for transfer complete or CLUT loading.
1242 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1243 * the configuration information for the DMA2D.
1244 * @param Timeout Timeout duration
1245 * @retval HAL status
1246 */
1247 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1248 {
1249 uint32_t tickstart;
1250 uint32_t layer_start;
1251 __IO uint32_t isrflags = 0x0U;
1252
1253 /* Polling for DMA2D transfer */
1254 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1255 {
1256 /* Get tick */
1257 tickstart = HAL_GetTick();
1258
1259 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1260 {
1261 isrflags = READ_REG(hdma2d->Instance->ISR);
1262 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1263 {
1264 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1265 {
1266 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1267 }
1268 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1269 {
1270 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1271 }
1272 /* Clear the transfer and configuration error flags */
1273 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1274
1275 /* Change DMA2D state */
1276 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1277
1278 /* Process unlocked */
1279 __HAL_UNLOCK(hdma2d);
1280
1281 return HAL_ERROR;
1282 }
1283 /* Check for the Timeout */
1284 if(Timeout != HAL_MAX_DELAY)
1285 {
1286 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1287 {
1288 /* Update error code */
1289 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1290
1291 /* Change the DMA2D state */
1292 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1293
1294 /* Process unlocked */
1295 __HAL_UNLOCK(hdma2d);
1296
1297 return HAL_TIMEOUT;
1298 }
1299 }
1300 }
1301 }
1302 /* Polling for CLUT loading (foreground or background) */
1303 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1304 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1305 if (layer_start != 0U)
1306 {
1307 /* Get tick */
1308 tickstart = HAL_GetTick();
1309
1310 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1311 {
1312 isrflags = READ_REG(hdma2d->Instance->ISR);
1313 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1314 {
1315 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1316 {
1317 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1318 }
1319 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1320 {
1321 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1322 }
1323 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1324 {
1325 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1326 }
1327 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1328 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1329
1330 /* Change DMA2D state */
1331 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1332
1333 /* Process unlocked */
1334 __HAL_UNLOCK(hdma2d);
1335
1336 return HAL_ERROR;
1337 }
1338 /* Check for the Timeout */
1339 if(Timeout != HAL_MAX_DELAY)
1340 {
1341 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1342 {
1343 /* Update error code */
1344 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1345
1346 /* Change the DMA2D state */
1347 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1348
1349 /* Process unlocked */
1350 __HAL_UNLOCK(hdma2d);
1351
1352 return HAL_TIMEOUT;
1353 }
1354 }
1355 }
1356 }
1357
1358 /* Clear the transfer complete and CLUT loading flags */
1359 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1360
1361 /* Change DMA2D state */
1362 hdma2d->State = HAL_DMA2D_STATE_READY;
1363
1364 /* Process unlocked */
1365 __HAL_UNLOCK(hdma2d);
1366
1367 return HAL_OK;
1368 }
1369 /**
1370 * @brief Handle DMA2D interrupt request.
1371 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1372 * the configuration information for the DMA2D.
1373 * @retval HAL status
1374 */
1375 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1376 {
1377 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1378 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1379
1380 /* Transfer Error Interrupt management ***************************************/
1381 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1382 {
1383 if ((crflags & DMA2D_IT_TE) != 0U)
1384 {
1385 /* Disable the transfer Error interrupt */
1386 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1387
1388 /* Update error code */
1389 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1390
1391 /* Clear the transfer error flag */
1392 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1393
1394 /* Change DMA2D state */
1395 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1396
1397 /* Process Unlocked */
1398 __HAL_UNLOCK(hdma2d);
1399
1400 if(hdma2d->XferErrorCallback != NULL)
1401 {
1402 /* Transfer error Callback */
1403 hdma2d->XferErrorCallback(hdma2d);
1404 }
1405 }
1406 }
1407 /* Configuration Error Interrupt management **********************************/
1408 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1409 {
1410 if ((crflags & DMA2D_IT_CE) != 0U)
1411 {
1412 /* Disable the Configuration Error interrupt */
1413 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1414
1415 /* Clear the Configuration error flag */
1416 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1417
1418 /* Update error code */
1419 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1420
1421 /* Change DMA2D state */
1422 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1423
1424 /* Process Unlocked */
1425 __HAL_UNLOCK(hdma2d);
1426
1427 if(hdma2d->XferErrorCallback != NULL)
1428 {
1429 /* Transfer error Callback */
1430 hdma2d->XferErrorCallback(hdma2d);
1431 }
1432 }
1433 }
1434 /* CLUT access Error Interrupt management ***********************************/
1435 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1436 {
1437 if ((crflags & DMA2D_IT_CAE) != 0U)
1438 {
1439 /* Disable the CLUT access error interrupt */
1440 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1441
1442 /* Clear the CLUT access error flag */
1443 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1444
1445 /* Update error code */
1446 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1447
1448 /* Change DMA2D state */
1449 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1450
1451 /* Process Unlocked */
1452 __HAL_UNLOCK(hdma2d);
1453
1454 if(hdma2d->XferErrorCallback != NULL)
1455 {
1456 /* Transfer error Callback */
1457 hdma2d->XferErrorCallback(hdma2d);
1458 }
1459 }
1460 }
1461 /* Transfer watermark Interrupt management **********************************/
1462 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1463 {
1464 if ((crflags & DMA2D_IT_TW) != 0U)
1465 {
1466 /* Disable the transfer watermark interrupt */
1467 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1468
1469 /* Clear the transfer watermark flag */
1470 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1471
1472 /* Transfer watermark Callback */
1473 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1474 hdma2d->LineEventCallback(hdma2d);
1475 #else
1476 HAL_DMA2D_LineEventCallback(hdma2d);
1477 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1478
1479 }
1480 }
1481 /* Transfer Complete Interrupt management ************************************/
1482 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1483 {
1484 if ((crflags & DMA2D_IT_TC) != 0U)
1485 {
1486 /* Disable the transfer complete interrupt */
1487 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1488
1489 /* Clear the transfer complete flag */
1490 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1491
1492 /* Update error code */
1493 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1494
1495 /* Change DMA2D state */
1496 hdma2d->State = HAL_DMA2D_STATE_READY;
1497
1498 /* Process Unlocked */
1499 __HAL_UNLOCK(hdma2d);
1500
1501 if(hdma2d->XferCpltCallback != NULL)
1502 {
1503 /* Transfer complete Callback */
1504 hdma2d->XferCpltCallback(hdma2d);
1505 }
1506 }
1507 }
1508 /* CLUT Transfer Complete Interrupt management ******************************/
1509 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1510 {
1511 if ((crflags & DMA2D_IT_CTC) != 0U)
1512 {
1513 /* Disable the CLUT transfer complete interrupt */
1514 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1515
1516 /* Clear the CLUT transfer complete flag */
1517 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1518
1519 /* Update error code */
1520 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1521
1522 /* Change DMA2D state */
1523 hdma2d->State = HAL_DMA2D_STATE_READY;
1524
1525 /* Process Unlocked */
1526 __HAL_UNLOCK(hdma2d);
1527
1528 /* CLUT Transfer complete Callback */
1529 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1530 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1531 #else
1532 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1533 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1534 }
1535 }
1536
1537 }
1538
1539 /**
1540 * @brief Transfer watermark callback.
1541 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1542 * the configuration information for the DMA2D.
1543 * @retval None
1544 */
1545 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1546 {
1547 /* Prevent unused argument(s) compilation warning */
1548 UNUSED(hdma2d);
1549
1550 /* NOTE : This function should not be modified; when the callback is needed,
1551 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1552 */
1553 }
1554
1555 /**
1556 * @brief CLUT Transfer Complete callback.
1557 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1558 * the configuration information for the DMA2D.
1559 * @retval None
1560 */
1561 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1562 {
1563 /* Prevent unused argument(s) compilation warning */
1564 UNUSED(hdma2d);
1565
1566 /* NOTE : This function should not be modified; when the callback is needed,
1567 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1568 */
1569 }
1570
1571 /**
1572 * @}
1573 */
1574
1575 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1576 * @brief Peripheral Control functions
1577 *
1578 @verbatim
1579 ===============================================================================
1580 ##### Peripheral Control functions #####
1581 ===============================================================================
1582 [..] This section provides functions allowing to:
1583 (+) Configure the DMA2D foreground or background layer parameters.
1584 (+) Configure the DMA2D CLUT transfer.
1585 (+) Configure the line watermark
1586 (+) Configure the dead time value.
1587 (+) Enable or disable the dead time value functionality.
1588
1589
1590 @endverbatim
1591 * @{
1592 */
1593
1594 /**
1595 * @brief Configure the DMA2D Layer according to the specified
1596 * parameters in the DMA2D_HandleTypeDef.
1597 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1598 * the configuration information for the DMA2D.
1599 * @param LayerIdx DMA2D Layer index.
1600 * This parameter can be one of the following values:
1601 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1602 * @retval HAL status
1603 */
1604 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1605 {
1606 DMA2D_LayerCfgTypeDef *pLayerCfg;
1607 uint32_t regMask, regValue;
1608
1609 /* Check the parameters */
1610 assert_param(IS_DMA2D_LAYER(LayerIdx));
1611 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1612 if(hdma2d->Init.Mode != DMA2D_R2M)
1613 {
1614 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1615 if(hdma2d->Init.Mode != DMA2D_M2M)
1616 {
1617 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1618 }
1619 }
1620 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1621 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1622 assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1623 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1624
1625 /* Process locked */
1626 __HAL_LOCK(hdma2d);
1627
1628 /* Change DMA2D peripheral state */
1629 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1630
1631 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1632
1633 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1634 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1635 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
1636 (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1637 regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1638 #else
1639 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
1640 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
1641 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1642
1643
1644 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1645 {
1646 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1647 }
1648 else
1649 {
1650 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1651 }
1652
1653 /* Configure the background DMA2D layer */
1654 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1655 {
1656 /* Write DMA2D BGPFCCR register */
1657 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1658
1659 /* DMA2D BGOR register configuration -------------------------------------*/
1660 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1661
1662 /* DMA2D BGCOLR register configuration -------------------------------------*/
1663 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1664 {
1665 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1666 }
1667 }
1668 /* Configure the foreground DMA2D layer */
1669 else
1670 {
1671
1672
1673 /* Write DMA2D FGPFCCR register */
1674 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1675
1676 /* DMA2D FGOR register configuration -------------------------------------*/
1677 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1678
1679 /* DMA2D FGCOLR register configuration -------------------------------------*/
1680 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1681 {
1682 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1683 }
1684 }
1685 /* Initialize the DMA2D state*/
1686 hdma2d->State = HAL_DMA2D_STATE_READY;
1687
1688 /* Process unlocked */
1689 __HAL_UNLOCK(hdma2d);
1690
1691 return HAL_OK;
1692 }
1693
1694 /**
1695 * @brief Configure the DMA2D CLUT Transfer.
1696 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1697 * the configuration information for the DMA2D.
1698 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1699 * the configuration information for the color look up table.
1700 * @param LayerIdx DMA2D Layer index.
1701 * This parameter can be one of the following values:
1702 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1703 * @retval HAL status
1704 */
1705 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1706 {
1707 /* Check the parameters */
1708 assert_param(IS_DMA2D_LAYER(LayerIdx));
1709 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1710 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1711
1712 /* Process locked */
1713 __HAL_LOCK(hdma2d);
1714
1715 /* Change DMA2D peripheral state */
1716 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1717
1718 /* Configure the CLUT of the background DMA2D layer */
1719 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1720 {
1721 /* Write background CLUT memory address */
1722 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1723
1724 /* Write background CLUT size and CLUT color mode */
1725 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1726 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1727 }
1728 /* Configure the CLUT of the foreground DMA2D layer */
1729 else
1730 {
1731 /* Write foreground CLUT memory address */
1732 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1733
1734 /* Write foreground CLUT size and CLUT color mode */
1735 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1736 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1737 }
1738
1739 /* Set the DMA2D state to Ready*/
1740 hdma2d->State = HAL_DMA2D_STATE_READY;
1741
1742 /* Process unlocked */
1743 __HAL_UNLOCK(hdma2d);
1744
1745 return HAL_OK;
1746 }
1747
1748
1749 /**
1750 * @brief Configure the line watermark.
1751 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1752 * the configuration information for the DMA2D.
1753 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
1754 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1755 * @note The transfer watermark interrupt is disabled once it has occurred.
1756 * @retval HAL status
1757 */
1758
1759 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1760 {
1761 /* Check the parameters */
1762 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1763
1764 if (Line > DMA2D_LWR_LW)
1765 {
1766 return HAL_ERROR;
1767 }
1768 else
1769 {
1770 /* Process locked */
1771 __HAL_LOCK(hdma2d);
1772
1773 /* Change DMA2D peripheral state */
1774 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1775
1776 /* Sets the Line watermark configuration */
1777 WRITE_REG(hdma2d->Instance->LWR, Line);
1778
1779 /* Enable the Line interrupt */
1780 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1781
1782 /* Initialize the DMA2D state*/
1783 hdma2d->State = HAL_DMA2D_STATE_READY;
1784
1785 /* Process unlocked */
1786 __HAL_UNLOCK(hdma2d);
1787
1788 return HAL_OK;
1789 }
1790 }
1791
1792 /**
1793 * @brief Enable DMA2D dead time feature.
1794 * @param hdma2d DMA2D handle.
1795 * @retval HAL status
1796 */
1797 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1798 {
1799 /* Process Locked */
1800 __HAL_LOCK(hdma2d);
1801
1802 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1803
1804 /* Set DMA2D_AMTCR EN bit */
1805 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1806
1807 hdma2d->State = HAL_DMA2D_STATE_READY;
1808
1809 /* Process Unlocked */
1810 __HAL_UNLOCK(hdma2d);
1811
1812 return HAL_OK;
1813 }
1814
1815 /**
1816 * @brief Disable DMA2D dead time feature.
1817 * @param hdma2d DMA2D handle.
1818 * @retval HAL status
1819 */
1820 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1821 {
1822 /* Process Locked */
1823 __HAL_LOCK(hdma2d);
1824
1825 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1826
1827 /* Clear DMA2D_AMTCR EN bit */
1828 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1829
1830 hdma2d->State = HAL_DMA2D_STATE_READY;
1831
1832 /* Process Unlocked */
1833 __HAL_UNLOCK(hdma2d);
1834
1835 return HAL_OK;
1836 }
1837
1838 /**
1839 * @brief Configure dead time.
1840 * @note The dead time value represents the guaranteed minimum number of cycles between
1841 * two consecutive transactions on the AHB bus.
1842 * @param hdma2d DMA2D handle.
1843 * @param DeadTime dead time value.
1844 * @retval HAL status
1845 */
1846 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1847 {
1848 /* Process Locked */
1849 __HAL_LOCK(hdma2d);
1850
1851 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1852
1853 /* Set DMA2D_AMTCR DT field */
1854 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
1855
1856 hdma2d->State = HAL_DMA2D_STATE_READY;
1857
1858 /* Process Unlocked */
1859 __HAL_UNLOCK(hdma2d);
1860
1861 return HAL_OK;
1862 }
1863
1864 /**
1865 * @}
1866 */
1867
1868
1869 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
1870 * @brief Peripheral State functions
1871 *
1872 @verbatim
1873 ===============================================================================
1874 ##### Peripheral State and Errors functions #####
1875 ===============================================================================
1876 [..]
1877 This subsection provides functions allowing to:
1878 (+) Get the DMA2D state
1879 (+) Get the DMA2D error code
1880
1881 @endverbatim
1882 * @{
1883 */
1884
1885 /**
1886 * @brief Return the DMA2D state
1887 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1888 * the configuration information for the DMA2D.
1889 * @retval HAL state
1890 */
1891 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1892 {
1893 return hdma2d->State;
1894 }
1895
1896 /**
1897 * @brief Return the DMA2D error code
1898 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1899 * the configuration information for DMA2D.
1900 * @retval DMA2D Error Code
1901 */
1902 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
1903 {
1904 return hdma2d->ErrorCode;
1905 }
1906
1907 /**
1908 * @}
1909 */
1910
1911 /**
1912 * @}
1913 */
1914
1915
1916 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
1917 * @{
1918 */
1919
1920 /**
1921 * @brief Set the DMA2D transfer parameters.
1922 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1923 * the configuration information for the specified DMA2D.
1924 * @param pdata The source memory Buffer address
1925 * @param DstAddress The destination memory Buffer address
1926 * @param Width The width of data to be transferred from source to destination.
1927 * @param Height The height of data to be transferred from source to destination.
1928 * @retval HAL status
1929 */
1930 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
1931 {
1932 uint32_t tmp;
1933 uint32_t tmp1;
1934 uint32_t tmp2;
1935 uint32_t tmp3;
1936 uint32_t tmp4;
1937
1938 /* Configure DMA2D data size */
1939 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
1940
1941 /* Configure DMA2D destination address */
1942 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
1943
1944 /* Register to memory DMA2D mode selected */
1945 if (hdma2d->Init.Mode == DMA2D_R2M)
1946 {
1947 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1948 tmp2 = pdata & DMA2D_OCOLR_RED_1;
1949 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1950 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1951
1952 /* Prepare the value to be written to the OCOLR register according to the color mode */
1953 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
1954 {
1955 tmp = (tmp3 | tmp2 | tmp1| tmp4);
1956 }
1957 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
1958 {
1959 tmp = (tmp3 | tmp2 | tmp4);
1960 }
1961 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
1962 {
1963 tmp2 = (tmp2 >> 19U);
1964 tmp3 = (tmp3 >> 10U);
1965 tmp4 = (tmp4 >> 3U );
1966 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
1967 }
1968 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
1969 {
1970 tmp1 = (tmp1 >> 31U);
1971 tmp2 = (tmp2 >> 19U);
1972 tmp3 = (tmp3 >> 11U);
1973 tmp4 = (tmp4 >> 3U );
1974 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
1975 }
1976 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
1977 {
1978 tmp1 = (tmp1 >> 28U);
1979 tmp2 = (tmp2 >> 20U);
1980 tmp3 = (tmp3 >> 12U);
1981 tmp4 = (tmp4 >> 4U );
1982 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
1983 }
1984 /* Write to DMA2D OCOLR register */
1985 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
1986 }
1987 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
1988 {
1989 /* Configure DMA2D source address */
1990 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
1991 }
1992 }
1993
1994 /**
1995 * @}
1996 */
1997
1998 /**
1999 * @}
2000 */
2001
2002 /**
2003 * @}
2004 */
2005 #endif /* DMA2D */
2006 #endif /* HAL_DMA2D_MODULE_ENABLED */
2007
2008 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/