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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_dsi.c
bloba01a6defd3d5f005bf44be68f129d3409e53516e
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dsi.c
4 * @author MCD Application Team
5 * @brief DSI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DSI peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
18 PLL parameters, number of lanes and TX Escape clock divider.
19 (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
20 command mode.
21 (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
22 (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
23 (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
24 (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
25 Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
26 to write DSI short packets, long packets and to read DSI packets.
27
28 (#) The DSI Host Offers two Low power modes :
29 (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
30 It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
31 and @ref HAL_DSI_ExitULPMData()
32
33 (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
34 It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
35 and @ref HAL_DSI_ExitULPM()
36
37 (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
38 When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
39 the error code by calling function @ref HAL_DSI_GetError()
40
41 (#) To control DSI state you can use the following function: HAL_DSI_GetState()
42
43 *** DSI HAL driver macros list ***
44 =============================================
45 [..]
46 Below the list of most used macros in DSI HAL driver.
47
48 (+) __HAL_DSI_ENABLE: Enable the DSI Host.
49 (+) __HAL_DSI_DISABLE: Disable the DSI Host.
50 (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
51 (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
52 (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
53 (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
54 (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
55 (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
56 (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
57 (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
58 (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
59 (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
60 (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
61
62
63
64 *** Callback registration ***
65 =============================================
66
67 The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
68 allows the user to configure dynamically the driver callbacks.
69 Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
70
71 Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
72 (+) TearingEffectCallback : DSI Tearing Effect Callback.
73 (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
74 (+) ErrorCallback : DSI Error Callback
75 (+) MspInitCallback : DSI MspInit.
76 (+) MspDeInitCallback : DSI MspDeInit.
77 This function takes as parameters the HAL peripheral handle, the Callback ID
78 and a pointer to the user callback function.
79
80 Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
81 weak function.
82 @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
83 and the Callback ID.
84 This function allows to reset following callbacks:
85 (+) TearingEffectCallback : DSI Tearing Effect Callback.
86 (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
87 (+) ErrorCallback : DSI Error Callback
88 (+) MspInitCallback : DSI MspInit.
89 (+) MspDeInitCallback : DSI MspDeInit.
90
91 By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
92 all callbacks are set to the corresponding weak functions:
93 examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
94 Exception done for MspInit and MspDeInit functions that are
95 reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
96 these callbacks are null (not registered beforehand).
97 if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
98 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
99
100 Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
101 Exception done MspInit/MspDeInit that can be registered/unregistered
102 in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
103 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
104 In that case first register the MspInit/MspDeInit user callbacks
105 using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
106 or HAL_DSI_Init function.
107
108 When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
109 not defined, the callback registration feature is not available and all callbacks
110 are set to the corresponding weak functions.
111
112 [..]
113 (@) You can refer to the DSI HAL driver header file for more useful macros
114
115 @endverbatim
116 ******************************************************************************
117 * @attention
118 *
119 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
120 * All rights reserved.</center></h2>
121 *
122 * This software component is licensed by ST under BSD 3-Clause license,
123 * the "License"; You may not use this file except in compliance with the
124 * License. You may obtain a copy of the License at:
125 * opensource.org/licenses/BSD-3-Clause
126 *
127 ******************************************************************************
128 */
129
130 /* Includes ------------------------------------------------------------------*/
131 #include "stm32f7xx_hal.h"
132
133 /** @addtogroup STM32F7xx_HAL_Driver
134 * @{
135 */
136
137 #ifdef HAL_DSI_MODULE_ENABLED
138
139 #if defined(DSI)
140
141 /** @addtogroup DSI
142 * @{
143 */
144
145 /* Private types -------------------------------------------------------------*/
146 /* Private defines -----------------------------------------------------------*/
147 /** @addtogroup DSI_Private_Constants
148 * @{
149 */
150 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
151
152 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
153 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
154 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
155 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
156 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
157 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
158 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
159 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
160 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
161 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
162 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
163 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
164 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
165 /**
166 * @}
167 */
168
169 /* Private variables ---------------------------------------------------------*/
170 /* Private constants ---------------------------------------------------------*/
171 /* Private macros ------------------------------------------------------------*/
172 /* Private function prototypes -----------------------------------------------*/
173 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
174 uint32_t Data1);
175
176 static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
177 uint32_t ChannelID,
178 uint32_t Mode,
179 uint32_t Param1,
180 uint32_t Param2);
181
182 /* Private functions ---------------------------------------------------------*/
183 /**
184 * @brief Generic DSI packet header configuration
185 * @param DSIx Pointer to DSI register base
186 * @param ChannelID Virtual channel ID of the header packet
187 * @param DataType Packet data type of the header packet
188 * This parameter can be any value of :
189 * @ref DSI_SHORT_WRITE_PKT_Data_Type
190 * or @ref DSI_LONG_WRITE_PKT_Data_Type
191 * or @ref DSI_SHORT_READ_PKT_Data_Type
192 * or DSI_MAX_RETURN_PKT_SIZE
193 * @param Data0 Word count LSB
194 * @param Data1 Word count MSB
195 * @retval None
196 */
197 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
198 uint32_t ChannelID,
199 uint32_t DataType,
200 uint32_t Data0,
201 uint32_t Data1)
202 {
203 /* Update the DSI packet header with new information */
204 DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
205 }
206
207 /**
208 * @brief write short DCS or short Generic command
209 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
210 * the configuration information for the DSI.
211 * @param ChannelID Virtual channel ID.
212 * @param Mode DSI short packet data type.
213 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
214 * @param Param1 DSC command or first generic parameter.
215 * This parameter can be any value of @ref DSI_DCS_Command or a
216 * generic command code.
217 * @param Param2 DSC parameter or second generic parameter.
218 * @retval HAL status
219 */
220 static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
221 uint32_t ChannelID,
222 uint32_t Mode,
223 uint32_t Param1,
224 uint32_t Param2)
225 {
226 uint32_t tickstart;
227
228 /* Get tick */
229 tickstart = HAL_GetTick();
230
231 /* Wait for Command FIFO Empty */
232 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
233 {
234 /* Check for the Timeout */
235 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
236 {
237 return HAL_TIMEOUT;
238 }
239 }
240
241 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
242 /* Update the DSI packet header with new information */
243 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
244
245 return HAL_OK;
246 }
247
248 /* Exported functions --------------------------------------------------------*/
249 /** @addtogroup DSI_Exported_Functions
250 * @{
251 */
252
253 /** @defgroup DSI_Group1 Initialization and Configuration functions
254 * @brief Initialization and Configuration functions
255 *
256 @verbatim
257 ===============================================================================
258 ##### Initialization and Configuration functions #####
259 ===============================================================================
260 [..] This section provides functions allowing to:
261 (+) Initialize and configure the DSI
262 (+) De-initialize the DSI
263
264 @endverbatim
265 * @{
266 */
267
268 /**
269 * @brief Initializes the DSI according to the specified
270 * parameters in the DSI_InitTypeDef and create the associated handle.
271 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
272 * the configuration information for the DSI.
273 * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
274 * the PLL Clock structure definition for the DSI.
275 * @retval HAL status
276 */
277 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
278 {
279 uint32_t tickstart;
280 uint32_t unitIntervalx4;
281 uint32_t tempIDF;
282
283 /* Check the DSI handle allocation */
284 if (hdsi == NULL)
285 {
286 return HAL_ERROR;
287 }
288
289 /* Check function parameters */
290 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
291 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
292 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
293 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
294 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
295
296 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
297 if (hdsi->State == HAL_DSI_STATE_RESET)
298 {
299 /* Reset the DSI callback to the legacy weak callbacks */
300 hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
301 hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
302 hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
303
304 if (hdsi->MspInitCallback == NULL)
305 {
306 hdsi->MspInitCallback = HAL_DSI_MspInit;
307 }
308 /* Initialize the low level hardware */
309 hdsi->MspInitCallback(hdsi);
310 }
311 #else
312 if (hdsi->State == HAL_DSI_STATE_RESET)
313 {
314 /* Initialize the low level hardware */
315 HAL_DSI_MspInit(hdsi);
316 }
317 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
318
319 /* Change DSI peripheral state */
320 hdsi->State = HAL_DSI_STATE_BUSY;
321
322 /**************** Turn on the regulator and enable the DSI PLL ****************/
323
324 /* Enable the regulator */
325 __HAL_DSI_REG_ENABLE(hdsi);
326
327 /* Get tick */
328 tickstart = HAL_GetTick();
329
330 /* Wait until the regulator is ready */
331 while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
332 {
333 /* Check for the Timeout */
334 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
335 {
336 return HAL_TIMEOUT;
337 }
338 }
339
340 /* Set the PLL division factors */
341 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
342 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
343
344 /* Enable the DSI PLL */
345 __HAL_DSI_PLL_ENABLE(hdsi);
346
347 /* Get tick */
348 tickstart = HAL_GetTick();
349
350 /* Wait for the lock of the PLL */
351 while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
352 {
353 /* Check for the Timeout */
354 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
355 {
356 return HAL_TIMEOUT;
357 }
358 }
359
360 /*************************** Set the PHY parameters ***************************/
361
362 /* D-PHY clock and digital enable*/
363 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
364
365 /* Clock lane configuration */
366 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
367 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
368
369 /* Configure the number of active data lanes */
370 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
371 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
372
373 /************************ Set the DSI clock parameters ************************/
374
375 /* Set the TX escape clock division factor */
376 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
377 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
378
379 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
380 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
381 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
382 tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
383 unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
384
385 /* Set the bit period in high-speed mode */
386 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
387 hdsi->Instance->WPCR[0U] |= unitIntervalx4;
388
389 /****************************** Error management *****************************/
390
391 /* Disable all error interrupts and reset the Error Mask */
392 hdsi->Instance->IER[0U] = 0U;
393 hdsi->Instance->IER[1U] = 0U;
394 hdsi->ErrorMsk = 0U;
395
396 /* Initialise the error code */
397 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
398
399 /* Initialize the DSI state*/
400 hdsi->State = HAL_DSI_STATE_READY;
401
402 return HAL_OK;
403 }
404
405 /**
406 * @brief De-initializes the DSI peripheral registers to their default reset
407 * values.
408 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
409 * the configuration information for the DSI.
410 * @retval HAL status
411 */
412 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
413 {
414 /* Check the DSI handle allocation */
415 if (hdsi == NULL)
416 {
417 return HAL_ERROR;
418 }
419
420 /* Change DSI peripheral state */
421 hdsi->State = HAL_DSI_STATE_BUSY;
422
423 /* Disable the DSI wrapper */
424 __HAL_DSI_WRAPPER_DISABLE(hdsi);
425
426 /* Disable the DSI host */
427 __HAL_DSI_DISABLE(hdsi);
428
429 /* D-PHY clock and digital disable */
430 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
431
432 /* Turn off the DSI PLL */
433 __HAL_DSI_PLL_DISABLE(hdsi);
434
435 /* Disable the regulator */
436 __HAL_DSI_REG_DISABLE(hdsi);
437
438 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
439 if (hdsi->MspDeInitCallback == NULL)
440 {
441 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
442 }
443 /* DeInit the low level hardware */
444 hdsi->MspDeInitCallback(hdsi);
445 #else
446 /* DeInit the low level hardware */
447 HAL_DSI_MspDeInit(hdsi);
448 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
449
450 /* Initialise the error code */
451 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
452
453 /* Initialize the DSI state*/
454 hdsi->State = HAL_DSI_STATE_RESET;
455
456 /* Release Lock */
457 __HAL_UNLOCK(hdsi);
458
459 return HAL_OK;
460 }
461
462 /**
463 * @brief Enable the error monitor flags
464 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
465 * the configuration information for the DSI.
466 * @param ActiveErrors indicates which error interrupts will be enabled.
467 * This parameter can be any combination of @ref DSI_Error_Data_Type.
468 * @retval HAL status
469 */
470 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
471 {
472 /* Process locked */
473 __HAL_LOCK(hdsi);
474
475 hdsi->Instance->IER[0U] = 0U;
476 hdsi->Instance->IER[1U] = 0U;
477
478 /* Store active errors to the handle */
479 hdsi->ErrorMsk = ActiveErrors;
480
481 if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
482 {
483 /* Enable the interrupt generation on selected errors */
484 hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
485 }
486
487 if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
488 {
489 /* Enable the interrupt generation on selected errors */
490 hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
491 }
492
493 if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
494 {
495 /* Enable the interrupt generation on selected errors */
496 hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
497 }
498
499 if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
500 {
501 /* Enable the interrupt generation on selected errors */
502 hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
503 }
504
505 if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
506 {
507 /* Enable the interrupt generation on selected errors */
508 hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
509 }
510
511 if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
512 {
513 /* Enable the interrupt generation on selected errors */
514 hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
515 }
516
517 if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
518 {
519 /* Enable the interrupt generation on selected errors */
520 hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
521 }
522
523 if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
524 {
525 /* Enable the interrupt generation on selected errors */
526 hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
527 }
528
529 if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
530 {
531 /* Enable the interrupt generation on selected errors */
532 hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
533 }
534
535 if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
536 {
537 /* Enable the interrupt generation on selected errors */
538 hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
539 }
540
541 /* Process Unlocked */
542 __HAL_UNLOCK(hdsi);
543
544 return HAL_OK;
545 }
546
547 /**
548 * @brief Initializes the DSI MSP.
549 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
550 * the configuration information for the DSI.
551 * @retval None
552 */
553 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
554 {
555 /* Prevent unused argument(s) compilation warning */
556 UNUSED(hdsi);
557 /* NOTE : This function Should not be modified, when the callback is needed,
558 the HAL_DSI_MspInit could be implemented in the user file
559 */
560 }
561
562 /**
563 * @brief De-initializes the DSI MSP.
564 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
565 * the configuration information for the DSI.
566 * @retval None
567 */
568 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
569 {
570 /* Prevent unused argument(s) compilation warning */
571 UNUSED(hdsi);
572 /* NOTE : This function Should not be modified, when the callback is needed,
573 the HAL_DSI_MspDeInit could be implemented in the user file
574 */
575 }
576
577 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
578 /**
579 * @brief Register a User DSI Callback
580 * To be used instead of the weak predefined callback
581 * @param hdsi dsi handle
582 * @param CallbackID ID of the callback to be registered
583 * This parameter can be one of the following values:
584 * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
585 * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
586 * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
587 * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
588 * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
589 * @param pCallback pointer to the Callback function
590 * @retval status
591 */
592 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
593 pDSI_CallbackTypeDef pCallback)
594 {
595 HAL_StatusTypeDef status = HAL_OK;
596
597 if (pCallback == NULL)
598 {
599 /* Update the error code */
600 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
601
602 return HAL_ERROR;
603 }
604 /* Process locked */
605 __HAL_LOCK(hdsi);
606
607 if (hdsi->State == HAL_DSI_STATE_READY)
608 {
609 switch (CallbackID)
610 {
611 case HAL_DSI_TEARING_EFFECT_CB_ID :
612 hdsi->TearingEffectCallback = pCallback;
613 break;
614
615 case HAL_DSI_ENDOF_REFRESH_CB_ID :
616 hdsi->EndOfRefreshCallback = pCallback;
617 break;
618
619 case HAL_DSI_ERROR_CB_ID :
620 hdsi->ErrorCallback = pCallback;
621 break;
622
623 case HAL_DSI_MSPINIT_CB_ID :
624 hdsi->MspInitCallback = pCallback;
625 break;
626
627 case HAL_DSI_MSPDEINIT_CB_ID :
628 hdsi->MspDeInitCallback = pCallback;
629 break;
630
631 default :
632 /* Update the error code */
633 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
634 /* Return error status */
635 status = HAL_ERROR;
636 break;
637 }
638 }
639 else if (hdsi->State == HAL_DSI_STATE_RESET)
640 {
641 switch (CallbackID)
642 {
643 case HAL_DSI_MSPINIT_CB_ID :
644 hdsi->MspInitCallback = pCallback;
645 break;
646
647 case HAL_DSI_MSPDEINIT_CB_ID :
648 hdsi->MspDeInitCallback = pCallback;
649 break;
650
651 default :
652 /* Update the error code */
653 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
654 /* Return error status */
655 status = HAL_ERROR;
656 break;
657 }
658 }
659 else
660 {
661 /* Update the error code */
662 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
663 /* Return error status */
664 status = HAL_ERROR;
665 }
666
667 /* Release Lock */
668 __HAL_UNLOCK(hdsi);
669
670 return status;
671 }
672
673 /**
674 * @brief Unregister a DSI Callback
675 * DSI callabck is redirected to the weak predefined callback
676 * @param hdsi dsi handle
677 * @param CallbackID ID of the callback to be unregistered
678 * This parameter can be one of the following values:
679 * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
680 * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
681 * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
682 * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
683 * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
684 * @retval status
685 */
686 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
687 {
688 HAL_StatusTypeDef status = HAL_OK;
689
690 /* Process locked */
691 __HAL_LOCK(hdsi);
692
693 if (hdsi->State == HAL_DSI_STATE_READY)
694 {
695 switch (CallbackID)
696 {
697 case HAL_DSI_TEARING_EFFECT_CB_ID :
698 hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
699 break;
700
701 case HAL_DSI_ENDOF_REFRESH_CB_ID :
702 hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
703 break;
704
705 case HAL_DSI_ERROR_CB_ID :
706 hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
707 break;
708
709 case HAL_DSI_MSPINIT_CB_ID :
710 hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
711 break;
712
713 case HAL_DSI_MSPDEINIT_CB_ID :
714 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
715 break;
716
717 default :
718 /* Update the error code */
719 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
720 /* Return error status */
721 status = HAL_ERROR;
722 break;
723 }
724 }
725 else if (hdsi->State == HAL_DSI_STATE_RESET)
726 {
727 switch (CallbackID)
728 {
729 case HAL_DSI_MSPINIT_CB_ID :
730 hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
731 break;
732
733 case HAL_DSI_MSPDEINIT_CB_ID :
734 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
735 break;
736
737 default :
738 /* Update the error code */
739 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
740 /* Return error status */
741 status = HAL_ERROR;
742 break;
743 }
744 }
745 else
746 {
747 /* Update the error code */
748 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
749 /* Return error status */
750 status = HAL_ERROR;
751 }
752
753 /* Release Lock */
754 __HAL_UNLOCK(hdsi);
755
756 return status;
757 }
758 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
759
760 /**
761 * @}
762 */
763
764 /** @defgroup DSI_Group2 IO operation functions
765 * @brief IO operation functions
766 *
767 @verbatim
768 ===============================================================================
769 ##### IO operation functions #####
770 ===============================================================================
771 [..] This section provides function allowing to:
772 (+) Handle DSI interrupt request
773
774 @endverbatim
775 * @{
776 */
777 /**
778 * @brief Handles DSI interrupt request.
779 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
780 * the configuration information for the DSI.
781 * @retval HAL status
782 */
783 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
784 {
785 uint32_t ErrorStatus0, ErrorStatus1;
786
787 /* Tearing Effect Interrupt management ***************************************/
788 if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
789 {
790 if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
791 {
792 /* Clear the Tearing Effect Interrupt Flag */
793 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
794
795 /* Tearing Effect Callback */
796 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
797 /*Call registered Tearing Effect callback */
798 hdsi->TearingEffectCallback(hdsi);
799 #else
800 /*Call legacy Tearing Effect callback*/
801 HAL_DSI_TearingEffectCallback(hdsi);
802 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
803 }
804 }
805
806 /* End of Refresh Interrupt management ***************************************/
807 if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
808 {
809 if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
810 {
811 /* Clear the End of Refresh Interrupt Flag */
812 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
813
814 /* End of Refresh Callback */
815 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
816 /*Call registered End of refresh callback */
817 hdsi->EndOfRefreshCallback(hdsi);
818 #else
819 /*Call Legacy End of refresh callback */
820 HAL_DSI_EndOfRefreshCallback(hdsi);
821 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
822 }
823 }
824
825 /* Error Interrupts management ***********************************************/
826 if (hdsi->ErrorMsk != 0U)
827 {
828 ErrorStatus0 = hdsi->Instance->ISR[0U];
829 ErrorStatus0 &= hdsi->Instance->IER[0U];
830 ErrorStatus1 = hdsi->Instance->ISR[1U];
831 ErrorStatus1 &= hdsi->Instance->IER[1U];
832
833 if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
834 {
835 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
836 }
837
838 if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
839 {
840 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
841 }
842
843 if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
844 {
845 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
846 }
847
848 if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
849 {
850 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
851 }
852
853 if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
854 {
855 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
856 }
857
858 if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
859 {
860 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
861 }
862
863 if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
864 {
865 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
866 }
867
868 if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
869 {
870 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
871 }
872
873 if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
874 {
875 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
876 }
877
878 if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
879 {
880 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
881 }
882
883 /* Check only selected errors */
884 if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
885 {
886 /* DSI error interrupt callback */
887 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
888 /*Call registered Error callback */
889 hdsi->ErrorCallback(hdsi);
890 #else
891 /*Call Legacy Error callback */
892 HAL_DSI_ErrorCallback(hdsi);
893 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
894 }
895 }
896 }
897
898 /**
899 * @brief Tearing Effect DSI callback.
900 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
901 * the configuration information for the DSI.
902 * @retval None
903 */
904 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
905 {
906 /* Prevent unused argument(s) compilation warning */
907 UNUSED(hdsi);
908 /* NOTE : This function Should not be modified, when the callback is needed,
909 the HAL_DSI_TearingEffectCallback could be implemented in the user file
910 */
911 }
912
913 /**
914 * @brief End of Refresh DSI callback.
915 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
916 * the configuration information for the DSI.
917 * @retval None
918 */
919 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
920 {
921 /* Prevent unused argument(s) compilation warning */
922 UNUSED(hdsi);
923 /* NOTE : This function Should not be modified, when the callback is needed,
924 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
925 */
926 }
927
928 /**
929 * @brief Operation Error DSI callback.
930 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
931 * the configuration information for the DSI.
932 * @retval None
933 */
934 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
935 {
936 /* Prevent unused argument(s) compilation warning */
937 UNUSED(hdsi);
938 /* NOTE : This function Should not be modified, when the callback is needed,
939 the HAL_DSI_ErrorCallback could be implemented in the user file
940 */
941 }
942
943 /**
944 * @}
945 */
946
947 /** @defgroup DSI_Group3 Peripheral Control functions
948 * @brief Peripheral Control functions
949 *
950 @verbatim
951 ===============================================================================
952 ##### Peripheral Control functions #####
953 ===============================================================================
954 [..] This section provides functions allowing to:
955 (+) Configure the Generic interface read-back Virtual Channel ID
956 (+) Select video mode and configure the corresponding parameters
957 (+) Configure command transmission mode: High-speed or Low-power
958 (+) Configure the flow control
959 (+) Configure the DSI PHY timer
960 (+) Configure the DSI HOST timeout
961 (+) Configure the DSI HOST timeout
962 (+) Start/Stop the DSI module
963 (+) Refresh the display in command mode
964 (+) Controls the display color mode in Video mode
965 (+) Control the display shutdown in Video mode
966 (+) write short DCS or short Generic command
967 (+) write long DCS or long Generic command
968 (+) Read command (DCS or generic)
969 (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
970 (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
971 (+) Start/Stop test pattern generation
972 (+) Slew-Rate And Delay Tuning
973 (+) Low-Power Reception Filter Tuning
974 (+) Activate an additional current path on all lanes to meet the SDDTx parameter
975 (+) Custom lane pins configuration
976 (+) Set custom timing for the PHY
977 (+) Force the Clock/Data Lane in TX Stop Mode
978 (+) Force LP Receiver in Low-Power Mode
979 (+) Force Data Lanes in RX Mode after a BTA
980 (+) Enable a pull-down on the lanes to prevent from floating states when unused
981 (+) Switch off the contention detection on data lanes
982
983 @endverbatim
984 * @{
985 */
986
987 /**
988 * @brief Configure the Generic interface read-back Virtual Channel ID.
989 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
990 * the configuration information for the DSI.
991 * @param VirtualChannelID Virtual channel ID
992 * @retval HAL status
993 */
994 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
995 {
996 /* Process locked */
997 __HAL_LOCK(hdsi);
998
999 /* Update the GVCID register */
1000 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
1001 hdsi->Instance->GVCIDR |= VirtualChannelID;
1002
1003 /* Process unlocked */
1004 __HAL_UNLOCK(hdsi);
1005
1006 return HAL_OK;
1007 }
1008
1009 /**
1010 * @brief Select video mode and configure the corresponding parameters
1011 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1012 * the configuration information for the DSI.
1013 * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
1014 * the DSI video mode configuration parameters
1015 * @retval HAL status
1016 */
1017 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
1018 {
1019 /* Process locked */
1020 __HAL_LOCK(hdsi);
1021
1022 /* Check the parameters */
1023 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
1024 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
1025 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
1026 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
1027 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
1028 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
1029 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
1030 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
1031 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
1032 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
1033 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
1034 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
1035 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
1036 /* Check the LooselyPacked variant only in 18-bit mode */
1037 if (VidCfg->ColorCoding == DSI_RGB666)
1038 {
1039 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
1040 }
1041
1042 /* Select video mode by resetting CMDM and DSIM bits */
1043 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
1044 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
1045
1046 /* Configure the video mode transmission type */
1047 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
1048 hdsi->Instance->VMCR |= VidCfg->Mode;
1049
1050 /* Configure the video packet size */
1051 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
1052 hdsi->Instance->VPCR |= VidCfg->PacketSize;
1053
1054 /* Set the chunks number to be transmitted through the DSI link */
1055 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
1056 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
1057
1058 /* Set the size of the null packet */
1059 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
1060 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
1061
1062 /* Select the virtual channel for the LTDC interface traffic */
1063 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
1064 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
1065
1066 /* Configure the polarity of control signals */
1067 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
1068 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
1069
1070 /* Select the color coding for the host */
1071 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
1072 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
1073
1074 /* Select the color coding for the wrapper */
1075 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
1076 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
1077
1078 /* Enable/disable the loosely packed variant to 18-bit configuration */
1079 if (VidCfg->ColorCoding == DSI_RGB666)
1080 {
1081 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
1082 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
1083 }
1084
1085 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
1086 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
1087 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
1088
1089 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
1090 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
1091 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
1092
1093 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
1094 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
1095 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
1096
1097 /* Set the Vertical Synchronization Active (VSA) */
1098 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
1099 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
1100
1101 /* Set the Vertical Back Porch (VBP)*/
1102 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
1103 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
1104
1105 /* Set the Vertical Front Porch (VFP)*/
1106 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
1107 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
1108
1109 /* Set the Vertical Active period*/
1110 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
1111 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
1112
1113 /* Configure the command transmission mode */
1114 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
1115 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
1116
1117 /* Low power largest packet size */
1118 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
1119 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
1120
1121 /* Low power VACT largest packet size */
1122 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
1123 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
1124
1125 /* Enable LP transition in HFP period */
1126 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
1127 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
1128
1129 /* Enable LP transition in HBP period */
1130 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
1131 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
1132
1133 /* Enable LP transition in VACT period */
1134 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
1135 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
1136
1137 /* Enable LP transition in VFP period */
1138 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
1139 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
1140
1141 /* Enable LP transition in VBP period */
1142 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
1143 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
1144
1145 /* Enable LP transition in vertical sync period */
1146 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
1147 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
1148
1149 /* Enable the request for an acknowledge response at the end of a frame */
1150 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
1151 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
1152
1153 /* Process unlocked */
1154 __HAL_UNLOCK(hdsi);
1155
1156 return HAL_OK;
1157 }
1158
1159 /**
1160 * @brief Select adapted command mode and configure the corresponding parameters
1161 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1162 * the configuration information for the DSI.
1163 * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
1164 * the DSI command mode configuration parameters
1165 * @retval HAL status
1166 */
1167 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
1168 {
1169 /* Process locked */
1170 __HAL_LOCK(hdsi);
1171
1172 /* Check the parameters */
1173 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
1174 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
1175 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
1176 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
1177 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
1178 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
1179 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
1180 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
1181 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
1182
1183 /* Select command mode by setting CMDM and DSIM bits */
1184 hdsi->Instance->MCR |= DSI_MCR_CMDM;
1185 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
1186 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
1187
1188 /* Select the virtual channel for the LTDC interface traffic */
1189 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
1190 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
1191
1192 /* Configure the polarity of control signals */
1193 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
1194 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
1195
1196 /* Select the color coding for the host */
1197 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
1198 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
1199
1200 /* Select the color coding for the wrapper */
1201 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
1202 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
1203
1204 /* Configure the maximum allowed size for write memory command */
1205 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
1206 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
1207
1208 /* Configure the tearing effect source and polarity and select the refresh mode */
1209 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
1210 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
1211 CmdCfg->VSyncPol);
1212
1213 /* Configure the tearing effect acknowledge request */
1214 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
1215 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
1216
1217 /* Enable the Tearing Effect interrupt */
1218 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
1219
1220 /* Enable the End of Refresh interrupt */
1221 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
1222
1223 /* Process unlocked */
1224 __HAL_UNLOCK(hdsi);
1225
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Configure command transmission mode: High-speed or Low-power
1231 * and enable/disable acknowledge request after packet transmission
1232 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1233 * the configuration information for the DSI.
1234 * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
1235 * the DSI command transmission mode configuration parameters
1236 * @retval HAL status
1237 */
1238 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
1239 {
1240 /* Process locked */
1241 __HAL_LOCK(hdsi);
1242
1243 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
1244 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
1245 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
1246 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
1247 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
1248 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
1249 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
1250 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
1251 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
1252 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
1253 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
1254 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
1255 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
1256
1257 /* Select High-speed or Low-power for command transmission */
1258 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
1259 DSI_CMCR_GSW1TX | \
1260 DSI_CMCR_GSW2TX | \
1261 DSI_CMCR_GSR0TX | \
1262 DSI_CMCR_GSR1TX | \
1263 DSI_CMCR_GSR2TX | \
1264 DSI_CMCR_GLWTX | \
1265 DSI_CMCR_DSW0TX | \
1266 DSI_CMCR_DSW1TX | \
1267 DSI_CMCR_DSR0TX | \
1268 DSI_CMCR_DLWTX | \
1269 DSI_CMCR_MRDPS);
1270 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \
1271 LPCmd->LPGenShortWriteOneP | \
1272 LPCmd->LPGenShortWriteTwoP | \
1273 LPCmd->LPGenShortReadNoP | \
1274 LPCmd->LPGenShortReadOneP | \
1275 LPCmd->LPGenShortReadTwoP | \
1276 LPCmd->LPGenLongWrite | \
1277 LPCmd->LPDcsShortWriteNoP | \
1278 LPCmd->LPDcsShortWriteOneP | \
1279 LPCmd->LPDcsShortReadNoP | \
1280 LPCmd->LPDcsLongWrite | \
1281 LPCmd->LPMaxReadPacket);
1282
1283 /* Configure the acknowledge request after each packet transmission */
1284 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
1285 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
1286
1287 /* Process unlocked */
1288 __HAL_UNLOCK(hdsi);
1289
1290 return HAL_OK;
1291 }
1292
1293 /**
1294 * @brief Configure the flow control parameters
1295 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1296 * the configuration information for the DSI.
1297 * @param FlowControl flow control feature(s) to be enabled.
1298 * This parameter can be any combination of @ref DSI_FlowControl.
1299 * @retval HAL status
1300 */
1301 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
1302 {
1303 /* Process locked */
1304 __HAL_LOCK(hdsi);
1305
1306 /* Check the parameters */
1307 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
1308
1309 /* Set the DSI Host Protocol Configuration Register */
1310 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
1311 hdsi->Instance->PCR |= FlowControl;
1312
1313 /* Process unlocked */
1314 __HAL_UNLOCK(hdsi);
1315
1316 return HAL_OK;
1317 }
1318
1319 /**
1320 * @brief Configure the DSI PHY timer parameters
1321 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1322 * the configuration information for the DSI.
1323 * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
1324 * the DSI PHY timing parameters
1325 * @retval HAL status
1326 */
1327 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
1328 {
1329 uint32_t maxTime;
1330 /* Process locked */
1331 __HAL_LOCK(hdsi);
1332
1333 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
1334 PhyTimers->ClockLaneHS2LPTime;
1335
1336 /* Clock lane timer configuration */
1337
1338 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
1339 High-Speed transmission.
1340 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
1341 to Low-Power and from Low-Power to High-Speed.
1342 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
1343 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
1344
1345 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
1346 */
1347 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
1348 hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
1349
1350 /* Data lane timer configuration */
1351 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
1352 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
1353 PhyTimers->DataLaneHS2LPTime) << 24U));
1354
1355 /* Configure the wait period to request HS transmission after a stop state */
1356 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
1357 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
1358
1359 /* Process unlocked */
1360 __HAL_UNLOCK(hdsi);
1361
1362 return HAL_OK;
1363 }
1364
1365 /**
1366 * @brief Configure the DSI HOST timeout parameters
1367 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1368 * the configuration information for the DSI.
1369 * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
1370 * the DSI host timeout parameters
1371 * @retval HAL status
1372 */
1373 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
1374 {
1375 /* Process locked */
1376 __HAL_LOCK(hdsi);
1377
1378 /* Set the timeout clock division factor */
1379 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
1380 hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
1381
1382 /* High-speed transmission timeout */
1383 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
1384 hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
1385
1386 /* Low-power reception timeout */
1387 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
1388 hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
1389
1390 /* High-speed read timeout */
1391 hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
1392 hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
1393
1394 /* Low-power read timeout */
1395 hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
1396 hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
1397
1398 /* High-speed write timeout */
1399 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
1400 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
1401
1402 /* High-speed write presp mode */
1403 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
1404 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
1405
1406 /* Low-speed write timeout */
1407 hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
1408 hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
1409
1410 /* BTA timeout */
1411 hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
1412 hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
1413
1414 /* Process unlocked */
1415 __HAL_UNLOCK(hdsi);
1416
1417 return HAL_OK;
1418 }
1419
1420 /**
1421 * @brief Start the DSI module
1422 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1423 * the configuration information for the DSI.
1424 * @retval HAL status
1425 */
1426 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1427 {
1428 /* Process locked */
1429 __HAL_LOCK(hdsi);
1430
1431 /* Enable the DSI host */
1432 __HAL_DSI_ENABLE(hdsi);
1433
1434 /* Enable the DSI wrapper */
1435 __HAL_DSI_WRAPPER_ENABLE(hdsi);
1436
1437 /* Process unlocked */
1438 __HAL_UNLOCK(hdsi);
1439
1440 return HAL_OK;
1441 }
1442
1443 /**
1444 * @brief Stop the DSI module
1445 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1446 * the configuration information for the DSI.
1447 * @retval HAL status
1448 */
1449 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1450 {
1451 /* Process locked */
1452 __HAL_LOCK(hdsi);
1453
1454 /* Disable the DSI host */
1455 __HAL_DSI_DISABLE(hdsi);
1456
1457 /* Disable the DSI wrapper */
1458 __HAL_DSI_WRAPPER_DISABLE(hdsi);
1459
1460 /* Process unlocked */
1461 __HAL_UNLOCK(hdsi);
1462
1463 return HAL_OK;
1464 }
1465
1466 /**
1467 * @brief Refresh the display in command mode
1468 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1469 * the configuration information for the DSI.
1470 * @retval HAL status
1471 */
1472 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1473 {
1474 /* Process locked */
1475 __HAL_LOCK(hdsi);
1476
1477 /* Update the display */
1478 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
1479
1480 /* Process unlocked */
1481 __HAL_UNLOCK(hdsi);
1482
1483 return HAL_OK;
1484 }
1485
1486 /**
1487 * @brief Controls the display color mode in Video mode
1488 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1489 * the configuration information for the DSI.
1490 * @param ColorMode Color mode (full or 8-colors).
1491 * This parameter can be any value of @ref DSI_Color_Mode
1492 * @retval HAL status
1493 */
1494 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1495 {
1496 /* Process locked */
1497 __HAL_LOCK(hdsi);
1498
1499 /* Check the parameters */
1500 assert_param(IS_DSI_COLOR_MODE(ColorMode));
1501
1502 /* Update the display color mode */
1503 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1504 hdsi->Instance->WCR |= ColorMode;
1505
1506 /* Process unlocked */
1507 __HAL_UNLOCK(hdsi);
1508
1509 return HAL_OK;
1510 }
1511
1512 /**
1513 * @brief Control the display shutdown in Video mode
1514 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1515 * the configuration information for the DSI.
1516 * @param Shutdown Shut-down (Display-ON or Display-OFF).
1517 * This parameter can be any value of @ref DSI_ShutDown
1518 * @retval HAL status
1519 */
1520 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1521 {
1522 /* Process locked */
1523 __HAL_LOCK(hdsi);
1524
1525 /* Check the parameters */
1526 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1527
1528 /* Update the display Shutdown */
1529 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1530 hdsi->Instance->WCR |= Shutdown;
1531
1532 /* Process unlocked */
1533 __HAL_UNLOCK(hdsi);
1534
1535 return HAL_OK;
1536 }
1537
1538 /**
1539 * @brief write short DCS or short Generic command
1540 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1541 * the configuration information for the DSI.
1542 * @param ChannelID Virtual channel ID.
1543 * @param Mode DSI short packet data type.
1544 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
1545 * @param Param1 DSC command or first generic parameter.
1546 * This parameter can be any value of @ref DSI_DCS_Command or a
1547 * generic command code.
1548 * @param Param2 DSC parameter or second generic parameter.
1549 * @retval HAL status
1550 */
1551 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1552 uint32_t ChannelID,
1553 uint32_t Mode,
1554 uint32_t Param1,
1555 uint32_t Param2)
1556 {
1557 HAL_StatusTypeDef status;
1558 /* Check the parameters */
1559 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1560
1561 /* Process locked */
1562 __HAL_LOCK(hdsi);
1563
1564 status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
1565
1566 /* Process unlocked */
1567 __HAL_UNLOCK(hdsi);
1568
1569 return status;
1570 }
1571
1572 /**
1573 * @brief write long DCS or long Generic command
1574 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1575 * the configuration information for the DSI.
1576 * @param ChannelID Virtual channel ID.
1577 * @param Mode DSI long packet data type.
1578 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
1579 * @param NbParams Number of parameters.
1580 * @param Param1 DSC command or first generic parameter.
1581 * This parameter can be any value of @ref DSI_DCS_Command or a
1582 * generic command code
1583 * @param ParametersTable Pointer to parameter values table.
1584 * @retval HAL status
1585 */
1586 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1587 uint32_t ChannelID,
1588 uint32_t Mode,
1589 uint32_t NbParams,
1590 uint32_t Param1,
1591 uint8_t *ParametersTable)
1592 {
1593 uint32_t uicounter, nbBytes, count;
1594 uint32_t tickstart;
1595 uint32_t fifoword;
1596 uint8_t *pparams = ParametersTable;
1597
1598 /* Process locked */
1599 __HAL_LOCK(hdsi);
1600
1601 /* Check the parameters */
1602 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1603
1604 /* Get tick */
1605 tickstart = HAL_GetTick();
1606
1607 /* Wait for Command FIFO Empty */
1608 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
1609 {
1610 /* Check for the Timeout */
1611 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1612 {
1613 /* Process Unlocked */
1614 __HAL_UNLOCK(hdsi);
1615
1616 return HAL_TIMEOUT;
1617 }
1618 }
1619
1620 /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
1621 fifoword = Param1;
1622 nbBytes = (NbParams < 3U) ? NbParams : 3U;
1623
1624 for (count = 0U; count < nbBytes; count++)
1625 {
1626 fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
1627 }
1628 hdsi->Instance->GPDR = fifoword;
1629
1630 uicounter = NbParams - nbBytes;
1631 pparams += nbBytes;
1632 /* Set the Next parameters on the write FIFO command*/
1633 while (uicounter != 0U)
1634 {
1635 nbBytes = (uicounter < 4U) ? uicounter : 4U;
1636 fifoword = 0U;
1637 for (count = 0U; count < nbBytes; count++)
1638 {
1639 fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
1640 }
1641 hdsi->Instance->GPDR = fifoword;
1642
1643 uicounter -= nbBytes;
1644 pparams += nbBytes;
1645 }
1646
1647 /* Configure the packet to send a long DCS command */
1648 DSI_ConfigPacketHeader(hdsi->Instance,
1649 ChannelID,
1650 Mode,
1651 ((NbParams + 1U) & 0x00FFU),
1652 (((NbParams + 1U) & 0xFF00U) >> 8U));
1653
1654 /* Process unlocked */
1655 __HAL_UNLOCK(hdsi);
1656
1657 return HAL_OK;
1658 }
1659
1660 /**
1661 * @brief Read command (DCS or generic)
1662 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1663 * the configuration information for the DSI.
1664 * @param ChannelNbr Virtual channel ID
1665 * @param Array pointer to a buffer to store the payload of a read back operation.
1666 * @param Size Data size to be read (in byte).
1667 * @param Mode DSI read packet data type.
1668 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
1669 * @param DCSCmd DCS get/read command.
1670 * @param ParametersTable Pointer to parameter values table.
1671 * @retval HAL status
1672 */
1673 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1674 uint32_t ChannelNbr,
1675 uint8_t *Array,
1676 uint32_t Size,
1677 uint32_t Mode,
1678 uint32_t DCSCmd,
1679 uint8_t *ParametersTable)
1680 {
1681 uint32_t tickstart;
1682 uint8_t *pdata = Array;
1683 uint32_t datasize = Size;
1684 uint32_t fifoword;
1685 uint32_t nbbytes;
1686 uint32_t count;
1687
1688 /* Process locked */
1689 __HAL_LOCK(hdsi);
1690
1691 /* Check the parameters */
1692 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1693
1694 if (datasize > 2U)
1695 {
1696 /* set max return packet size */
1697 if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
1698 (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
1699 {
1700 /* Process Unlocked */
1701 __HAL_UNLOCK(hdsi);
1702
1703 return HAL_ERROR;
1704 }
1705 }
1706
1707 /* Configure the packet to read command */
1708 if (Mode == DSI_DCS_SHORT_PKT_READ)
1709 {
1710 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
1711 }
1712 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1713 {
1714 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
1715 }
1716 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1717 {
1718 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
1719 }
1720 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1721 {
1722 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
1723 }
1724 else
1725 {
1726 /* Process Unlocked */
1727 __HAL_UNLOCK(hdsi);
1728
1729 return HAL_ERROR;
1730 }
1731
1732 /* Get tick */
1733 tickstart = HAL_GetTick();
1734
1735 /* If DSI fifo is not empty, read requested bytes */
1736 while (((int32_t)(datasize)) > 0)
1737 {
1738 if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
1739 {
1740 fifoword = hdsi->Instance->GPDR;
1741 nbbytes = (datasize < 4U) ? datasize : 4U;
1742
1743 for (count = 0U; count < nbbytes; count++)
1744 {
1745 *pdata = (uint8_t)(fifoword >> (8U * count));
1746 pdata++;
1747 datasize--;
1748 }
1749 }
1750
1751 /* Check for the Timeout */
1752 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1753 {
1754 /* Process Unlocked */
1755 __HAL_UNLOCK(hdsi);
1756
1757 return HAL_TIMEOUT;
1758 }
1759 }
1760
1761 /* Process unlocked */
1762 __HAL_UNLOCK(hdsi);
1763
1764 return HAL_OK;
1765 }
1766
1767 /**
1768 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1769 * (only data lanes are in ULPM)
1770 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1771 * the configuration information for the DSI.
1772 * @retval HAL status
1773 */
1774 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1775 {
1776 uint32_t tickstart;
1777
1778 /* Process locked */
1779 __HAL_LOCK(hdsi);
1780
1781 /* ULPS Request on Data Lanes */
1782 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
1783
1784 /* Get tick */
1785 tickstart = HAL_GetTick();
1786
1787 /* Wait until the D-PHY active lanes enter into ULPM */
1788 if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1789 {
1790 while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
1791 {
1792 /* Check for the Timeout */
1793 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1794 {
1795 /* Process Unlocked */
1796 __HAL_UNLOCK(hdsi);
1797
1798 return HAL_TIMEOUT;
1799 }
1800 }
1801 }
1802 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1803 {
1804 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
1805 {
1806 /* Check for the Timeout */
1807 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1808 {
1809 /* Process Unlocked */
1810 __HAL_UNLOCK(hdsi);
1811
1812 return HAL_TIMEOUT;
1813 }
1814 }
1815 }
1816 else
1817 {
1818 /* Process unlocked */
1819 __HAL_UNLOCK(hdsi);
1820
1821 return HAL_ERROR;
1822 }
1823
1824 /* Process unlocked */
1825 __HAL_UNLOCK(hdsi);
1826
1827 return HAL_OK;
1828 }
1829
1830 /**
1831 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1832 * (only data lanes are in ULPM)
1833 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1834 * the configuration information for the DSI.
1835 * @retval HAL status
1836 */
1837 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1838 {
1839 uint32_t tickstart;
1840
1841 /* Process locked */
1842 __HAL_LOCK(hdsi);
1843
1844 /* Exit ULPS on Data Lanes */
1845 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
1846
1847 /* Get tick */
1848 tickstart = HAL_GetTick();
1849
1850 /* Wait until all active lanes exit ULPM */
1851 if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1852 {
1853 while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1854 {
1855 /* Check for the Timeout */
1856 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1857 {
1858 /* Process Unlocked */
1859 __HAL_UNLOCK(hdsi);
1860
1861 return HAL_TIMEOUT;
1862 }
1863 }
1864 }
1865 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1866 {
1867 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
1868 {
1869 /* Check for the Timeout */
1870 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1871 {
1872 /* Process Unlocked */
1873 __HAL_UNLOCK(hdsi);
1874
1875 return HAL_TIMEOUT;
1876 }
1877 }
1878 }
1879 else
1880 {
1881 /* Process unlocked */
1882 __HAL_UNLOCK(hdsi);
1883
1884 return HAL_ERROR;
1885 }
1886
1887 /* wait for 1 ms*/
1888 HAL_Delay(1U);
1889
1890 /* De-assert the ULPM requests and the ULPM exit bits */
1891 hdsi->Instance->PUCR = 0U;
1892
1893 /* Process unlocked */
1894 __HAL_UNLOCK(hdsi);
1895
1896 return HAL_OK;
1897 }
1898
1899 /**
1900 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1901 * (both data and clock lanes are in ULPM)
1902 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1903 * the configuration information for the DSI.
1904 * @retval HAL status
1905 */
1906 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1907 {
1908 uint32_t tickstart;
1909
1910 /* Process locked */
1911 __HAL_LOCK(hdsi);
1912
1913 /* Clock lane configuration: no more HS request */
1914 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1915
1916 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1917 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1918
1919 /* ULPS Request on Clock and Data Lanes */
1920 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
1921
1922 /* Get tick */
1923 tickstart = HAL_GetTick();
1924
1925 /* Wait until all active lanes exit ULPM */
1926 if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1927 {
1928 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
1929 {
1930 /* Check for the Timeout */
1931 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1932 {
1933 /* Process Unlocked */
1934 __HAL_UNLOCK(hdsi);
1935
1936 return HAL_TIMEOUT;
1937 }
1938 }
1939 }
1940 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1941 {
1942 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
1943 {
1944 /* Check for the Timeout */
1945 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1946 {
1947 /* Process Unlocked */
1948 __HAL_UNLOCK(hdsi);
1949
1950 return HAL_TIMEOUT;
1951 }
1952 }
1953 }
1954 else
1955 {
1956 /* Process unlocked */
1957 __HAL_UNLOCK(hdsi);
1958
1959 return HAL_ERROR;
1960 }
1961
1962 /* Turn off the DSI PLL */
1963 __HAL_DSI_PLL_DISABLE(hdsi);
1964
1965 /* Process unlocked */
1966 __HAL_UNLOCK(hdsi);
1967
1968 return HAL_OK;
1969 }
1970
1971 /**
1972 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1973 * (both data and clock lanes are in ULPM)
1974 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1975 * the configuration information for the DSI.
1976 * @retval HAL status
1977 */
1978 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
1979 {
1980 uint32_t tickstart;
1981
1982 /* Process locked */
1983 __HAL_LOCK(hdsi);
1984
1985 /* Turn on the DSI PLL */
1986 __HAL_DSI_PLL_ENABLE(hdsi);
1987
1988 /* Get tick */
1989 tickstart = HAL_GetTick();
1990
1991 /* Wait for the lock of the PLL */
1992 while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
1993 {
1994 /* Check for the Timeout */
1995 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1996 {
1997 /* Process Unlocked */
1998 __HAL_UNLOCK(hdsi);
1999
2000 return HAL_TIMEOUT;
2001 }
2002 }
2003
2004 /* Exit ULPS on Clock and Data Lanes */
2005 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
2006
2007 /* Get tick */
2008 tickstart = HAL_GetTick();
2009
2010 /* Wait until all active lanes exit ULPM */
2011 if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
2012 {
2013 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
2014 {
2015 /* Check for the Timeout */
2016 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
2017 {
2018 /* Process Unlocked */
2019 __HAL_UNLOCK(hdsi);
2020
2021 return HAL_TIMEOUT;
2022 }
2023 }
2024 }
2025 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
2026 {
2027 while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
2028 DSI_PSR_UANC))
2029 {
2030 /* Check for the Timeout */
2031 if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
2032 {
2033 /* Process Unlocked */
2034 __HAL_UNLOCK(hdsi);
2035
2036 return HAL_TIMEOUT;
2037 }
2038 }
2039 }
2040 else
2041 {
2042 /* Process unlocked */
2043 __HAL_UNLOCK(hdsi);
2044
2045 return HAL_ERROR;
2046 }
2047
2048 /* wait for 1 ms */
2049 HAL_Delay(1U);
2050
2051 /* De-assert the ULPM requests and the ULPM exit bits */
2052 hdsi->Instance->PUCR = 0U;
2053
2054 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
2055 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
2056
2057 /* Restore clock lane configuration to HS */
2058 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
2059
2060 /* Process unlocked */
2061 __HAL_UNLOCK(hdsi);
2062
2063 return HAL_OK;
2064 }
2065
2066 /**
2067 * @brief Start test pattern generation
2068 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2069 * the configuration information for the DSI.
2070 * @param Mode Pattern generator mode
2071 * This parameter can be one of the following values:
2072 * 0 : Color bars (horizontal or vertical)
2073 * 1 : BER pattern (vertical only)
2074 * @param Orientation Pattern generator orientation
2075 * This parameter can be one of the following values:
2076 * 0 : Vertical color bars
2077 * 1 : Horizontal color bars
2078 * @retval HAL status
2079 */
2080 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
2081 {
2082 /* Process locked */
2083 __HAL_LOCK(hdsi);
2084
2085 /* Configure pattern generator mode and orientation */
2086 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
2087 hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
2088
2089 /* Enable pattern generator by setting PGE bit */
2090 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
2091
2092 /* Process unlocked */
2093 __HAL_UNLOCK(hdsi);
2094
2095 return HAL_OK;
2096 }
2097
2098 /**
2099 * @brief Stop test pattern generation
2100 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2101 * the configuration information for the DSI.
2102 * @retval HAL status
2103 */
2104 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
2105 {
2106 /* Process locked */
2107 __HAL_LOCK(hdsi);
2108
2109 /* Disable pattern generator by clearing PGE bit */
2110 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
2111
2112 /* Process unlocked */
2113 __HAL_UNLOCK(hdsi);
2114
2115 return HAL_OK;
2116 }
2117
2118 /**
2119 * @brief Set Slew-Rate And Delay Tuning
2120 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2121 * the configuration information for the DSI.
2122 * @param CommDelay Communication delay to be adjusted.
2123 * This parameter can be any value of @ref DSI_Communication_Delay
2124 * @param Lane select between clock or data lanes.
2125 * This parameter can be any value of @ref DSI_Lane_Group
2126 * @param Value Custom value of the slew-rate or delay
2127 * @retval HAL status
2128 */
2129 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
2130 uint32_t Value)
2131 {
2132 /* Process locked */
2133 __HAL_LOCK(hdsi);
2134
2135 /* Check function parameters */
2136 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
2137 assert_param(IS_DSI_LANE_GROUP(Lane));
2138
2139 switch (CommDelay)
2140 {
2141 case DSI_SLEW_RATE_HSTX:
2142 if (Lane == DSI_CLOCK_LANE)
2143 {
2144 /* High-Speed Transmission Slew Rate Control on Clock Lane */
2145 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
2146 hdsi->Instance->WPCR[1U] |= Value << 16U;
2147 }
2148 else if (Lane == DSI_DATA_LANES)
2149 {
2150 /* High-Speed Transmission Slew Rate Control on Data Lanes */
2151 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
2152 hdsi->Instance->WPCR[1U] |= Value << 18U;
2153 }
2154 else
2155 {
2156 /* Process unlocked */
2157 __HAL_UNLOCK(hdsi);
2158
2159 return HAL_ERROR;
2160 }
2161 break;
2162 case DSI_SLEW_RATE_LPTX:
2163 if (Lane == DSI_CLOCK_LANE)
2164 {
2165 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
2166 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
2167 hdsi->Instance->WPCR[1U] |= Value << 6U;
2168 }
2169 else if (Lane == DSI_DATA_LANES)
2170 {
2171 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
2172 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
2173 hdsi->Instance->WPCR[1U] |= Value << 8U;
2174 }
2175 else
2176 {
2177 /* Process unlocked */
2178 __HAL_UNLOCK(hdsi);
2179
2180 return HAL_ERROR;
2181 }
2182 break;
2183 case DSI_HS_DELAY:
2184 if (Lane == DSI_CLOCK_LANE)
2185 {
2186 /* High-Speed Transmission Delay on Clock Lane */
2187 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
2188 hdsi->Instance->WPCR[1U] |= Value;
2189 }
2190 else if (Lane == DSI_DATA_LANES)
2191 {
2192 /* High-Speed Transmission Delay on Data Lanes */
2193 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
2194 hdsi->Instance->WPCR[1U] |= Value << 2U;
2195 }
2196 else
2197 {
2198 /* Process unlocked */
2199 __HAL_UNLOCK(hdsi);
2200
2201 return HAL_ERROR;
2202 }
2203 break;
2204 default:
2205 break;
2206 }
2207
2208 /* Process unlocked */
2209 __HAL_UNLOCK(hdsi);
2210
2211 return HAL_OK;
2212 }
2213
2214 /**
2215 * @brief Low-Power Reception Filter Tuning
2216 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2217 * the configuration information for the DSI.
2218 * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
2219 * @retval HAL status
2220 */
2221 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
2222 {
2223 /* Process locked */
2224 __HAL_LOCK(hdsi);
2225
2226 /* Low-Power RX low-pass Filtering Tuning */
2227 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
2228 hdsi->Instance->WPCR[1U] |= Frequency << 25U;
2229
2230 /* Process unlocked */
2231 __HAL_UNLOCK(hdsi);
2232
2233 return HAL_OK;
2234 }
2235
2236 /**
2237 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
2238 * defined in the MIPI D-PHY specification
2239 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2240 * the configuration information for the DSI.
2241 * @param State ENABLE or DISABLE
2242 * @retval HAL status
2243 */
2244 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
2245 {
2246 /* Process locked */
2247 __HAL_LOCK(hdsi);
2248
2249 /* Check function parameters */
2250 assert_param(IS_FUNCTIONAL_STATE(State));
2251
2252 /* Activate/Disactivate additional current path on all lanes */
2253 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
2254 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
2255
2256 /* Process unlocked */
2257 __HAL_UNLOCK(hdsi);
2258
2259 return HAL_OK;
2260 }
2261
2262 /**
2263 * @brief Custom lane pins configuration
2264 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2265 * the configuration information for the DSI.
2266 * @param CustomLane Function to be applyed on selected lane.
2267 * This parameter can be any value of @ref DSI_CustomLane
2268 * @param Lane select between clock or data lane 0 or data lane 1.
2269 * This parameter can be any value of @ref DSI_Lane_Select
2270 * @param State ENABLE or DISABLE
2271 * @retval HAL status
2272 */
2273 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
2274 FunctionalState State)
2275 {
2276 /* Process locked */
2277 __HAL_LOCK(hdsi);
2278
2279 /* Check function parameters */
2280 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
2281 assert_param(IS_DSI_LANE(Lane));
2282 assert_param(IS_FUNCTIONAL_STATE(State));
2283
2284 switch (CustomLane)
2285 {
2286 case DSI_SWAP_LANE_PINS:
2287 if (Lane == DSI_CLK_LANE)
2288 {
2289 /* Swap pins on clock lane */
2290 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
2291 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
2292 }
2293 else if (Lane == DSI_DATA_LANE0)
2294 {
2295 /* Swap pins on data lane 0 */
2296 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
2297 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
2298 }
2299 else if (Lane == DSI_DATA_LANE1)
2300 {
2301 /* Swap pins on data lane 1 */
2302 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
2303 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
2304 }
2305 else
2306 {
2307 /* Process unlocked */
2308 __HAL_UNLOCK(hdsi);
2309
2310 return HAL_ERROR;
2311 }
2312 break;
2313 case DSI_INVERT_HS_SIGNAL:
2314 if (Lane == DSI_CLK_LANE)
2315 {
2316 /* Invert HS signal on clock lane */
2317 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
2318 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
2319 }
2320 else if (Lane == DSI_DATA_LANE0)
2321 {
2322 /* Invert HS signal on data lane 0 */
2323 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
2324 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
2325 }
2326 else if (Lane == DSI_DATA_LANE1)
2327 {
2328 /* Invert HS signal on data lane 1 */
2329 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
2330 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
2331 }
2332 else
2333 {
2334 /* Process unlocked */
2335 __HAL_UNLOCK(hdsi);
2336
2337 return HAL_ERROR;
2338 }
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 /* Process unlocked */
2345 __HAL_UNLOCK(hdsi);
2346
2347 return HAL_OK;
2348 }
2349
2350 /**
2351 * @brief Set custom timing for the PHY
2352 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2353 * the configuration information for the DSI.
2354 * @param Timing PHY timing to be adjusted.
2355 * This parameter can be any value of @ref DSI_PHY_Timing
2356 * @param State ENABLE or DISABLE
2357 * @param Value Custom value of the timing
2358 * @retval HAL status
2359 */
2360 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
2361 {
2362 /* Process locked */
2363 __HAL_LOCK(hdsi);
2364
2365 /* Check function parameters */
2366 assert_param(IS_DSI_PHY_TIMING(Timing));
2367 assert_param(IS_FUNCTIONAL_STATE(State));
2368
2369 switch (Timing)
2370 {
2371 case DSI_TCLK_POST:
2372 /* Enable/Disable custom timing setting */
2373 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
2374 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
2375
2376 if (State != DISABLE)
2377 {
2378 /* Set custom value */
2379 hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
2380 hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
2381 }
2382
2383 break;
2384 case DSI_TLPX_CLK:
2385 /* Enable/Disable custom timing setting */
2386 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
2387 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
2388
2389 if (State != DISABLE)
2390 {
2391 /* Set custom value */
2392 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
2393 hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
2394 }
2395
2396 break;
2397 case DSI_THS_EXIT:
2398 /* Enable/Disable custom timing setting */
2399 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
2400 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
2401
2402 if (State != DISABLE)
2403 {
2404 /* Set custom value */
2405 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
2406 hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
2407 }
2408
2409 break;
2410 case DSI_TLPX_DATA:
2411 /* Enable/Disable custom timing setting */
2412 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
2413 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
2414
2415 if (State != DISABLE)
2416 {
2417 /* Set custom value */
2418 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
2419 hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
2420 }
2421
2422 break;
2423 case DSI_THS_ZERO:
2424 /* Enable/Disable custom timing setting */
2425 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
2426 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
2427
2428 if (State != DISABLE)
2429 {
2430 /* Set custom value */
2431 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
2432 hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
2433 }
2434
2435 break;
2436 case DSI_THS_TRAIL:
2437 /* Enable/Disable custom timing setting */
2438 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
2439 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
2440
2441 if (State != DISABLE)
2442 {
2443 /* Set custom value */
2444 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
2445 hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
2446 }
2447
2448 break;
2449 case DSI_THS_PREPARE:
2450 /* Enable/Disable custom timing setting */
2451 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
2452 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
2453
2454 if (State != DISABLE)
2455 {
2456 /* Set custom value */
2457 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
2458 hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
2459 }
2460
2461 break;
2462 case DSI_TCLK_ZERO:
2463 /* Enable/Disable custom timing setting */
2464 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
2465 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
2466
2467 if (State != DISABLE)
2468 {
2469 /* Set custom value */
2470 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
2471 hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
2472 }
2473
2474 break;
2475 case DSI_TCLK_PREPARE:
2476 /* Enable/Disable custom timing setting */
2477 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
2478 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
2479
2480 if (State != DISABLE)
2481 {
2482 /* Set custom value */
2483 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
2484 hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
2485 }
2486
2487 break;
2488 default:
2489 break;
2490 }
2491
2492 /* Process unlocked */
2493 __HAL_UNLOCK(hdsi);
2494
2495 return HAL_OK;
2496 }
2497
2498 /**
2499 * @brief Force the Clock/Data Lane in TX Stop Mode
2500 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2501 * the configuration information for the DSI.
2502 * @param Lane select between clock or data lanes.
2503 * This parameter can be any value of @ref DSI_Lane_Group
2504 * @param State ENABLE or DISABLE
2505 * @retval HAL status
2506 */
2507 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2508 {
2509 /* Process locked */
2510 __HAL_LOCK(hdsi);
2511
2512 /* Check function parameters */
2513 assert_param(IS_DSI_LANE_GROUP(Lane));
2514 assert_param(IS_FUNCTIONAL_STATE(State));
2515
2516 if (Lane == DSI_CLOCK_LANE)
2517 {
2518 /* Force/Unforce the Clock Lane in TX Stop Mode */
2519 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
2520 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
2521 }
2522 else if (Lane == DSI_DATA_LANES)
2523 {
2524 /* Force/Unforce the Data Lanes in TX Stop Mode */
2525 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
2526 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
2527 }
2528 else
2529 {
2530 /* Process unlocked */
2531 __HAL_UNLOCK(hdsi);
2532
2533 return HAL_ERROR;
2534 }
2535
2536 /* Process unlocked */
2537 __HAL_UNLOCK(hdsi);
2538
2539 return HAL_OK;
2540 }
2541
2542 /**
2543 * @brief Force LP Receiver in Low-Power Mode
2544 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2545 * the configuration information for the DSI.
2546 * @param State ENABLE or DISABLE
2547 * @retval HAL status
2548 */
2549 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2550 {
2551 /* Process locked */
2552 __HAL_LOCK(hdsi);
2553
2554 /* Check function parameters */
2555 assert_param(IS_FUNCTIONAL_STATE(State));
2556
2557 /* Force/Unforce LP Receiver in Low-Power Mode */
2558 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
2559 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
2560
2561 /* Process unlocked */
2562 __HAL_UNLOCK(hdsi);
2563
2564 return HAL_OK;
2565 }
2566
2567 /**
2568 * @brief Force Data Lanes in RX Mode after a BTA
2569 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2570 * the configuration information for the DSI.
2571 * @param State ENABLE or DISABLE
2572 * @retval HAL status
2573 */
2574 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2575 {
2576 /* Process locked */
2577 __HAL_LOCK(hdsi);
2578
2579 /* Check function parameters */
2580 assert_param(IS_FUNCTIONAL_STATE(State));
2581
2582 /* Force Data Lanes in RX Mode */
2583 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
2584 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
2585
2586 /* Process unlocked */
2587 __HAL_UNLOCK(hdsi);
2588
2589 return HAL_OK;
2590 }
2591
2592 /**
2593 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
2594 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2595 * the configuration information for the DSI.
2596 * @param State ENABLE or DISABLE
2597 * @retval HAL status
2598 */
2599 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2600 {
2601 /* Process locked */
2602 __HAL_LOCK(hdsi);
2603
2604 /* Check function parameters */
2605 assert_param(IS_FUNCTIONAL_STATE(State));
2606
2607 /* Enable/Disable pull-down on lanes */
2608 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
2609 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
2610
2611 /* Process unlocked */
2612 __HAL_UNLOCK(hdsi);
2613
2614 return HAL_OK;
2615 }
2616
2617 /**
2618 * @brief Switch off the contention detection on data lanes
2619 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2620 * the configuration information for the DSI.
2621 * @param State ENABLE or DISABLE
2622 * @retval HAL status
2623 */
2624 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2625 {
2626 /* Process locked */
2627 __HAL_LOCK(hdsi);
2628
2629 /* Check function parameters */
2630 assert_param(IS_FUNCTIONAL_STATE(State));
2631
2632 /* Contention Detection on Data Lanes OFF */
2633 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
2634 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
2635
2636 /* Process unlocked */
2637 __HAL_UNLOCK(hdsi);
2638
2639 return HAL_OK;
2640 }
2641
2642 /**
2643 * @}
2644 */
2645
2646 /** @defgroup DSI_Group4 Peripheral State and Errors functions
2647 * @brief Peripheral State and Errors functions
2648 *
2649 @verbatim
2650 ===============================================================================
2651 ##### Peripheral State and Errors functions #####
2652 ===============================================================================
2653 [..]
2654 This subsection provides functions allowing to
2655 (+) Check the DSI state.
2656 (+) Get error code.
2657
2658 @endverbatim
2659 * @{
2660 */
2661
2662 /**
2663 * @brief Return the DSI state
2664 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2665 * the configuration information for the DSI.
2666 * @retval HAL state
2667 */
2668 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2669 {
2670 return hdsi->State;
2671 }
2672
2673 /**
2674 * @brief Return the DSI error code
2675 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2676 * the configuration information for the DSI.
2677 * @retval DSI Error Code
2678 */
2679 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
2680 {
2681 /* Get the error code */
2682 return hdsi->ErrorCode;
2683 }
2684
2685 /**
2686 * @}
2687 */
2688
2689 /**
2690 * @}
2691 */
2692
2693 /**
2694 * @}
2695 */
2696
2697 #endif /* DSI */
2698
2699 #endif /* HAL_DSI_MODULE_ENABLED */
2700
2701 /**
2702 * @}
2703 */
2704
2705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/