?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_eth.c
blob0dea1145c56e1989bbe1c6d49aaf484d09cf250b
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_eth.c
4 * @author MCD Application Team
5 * @brief ETH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Ethernet (ETH) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#)Declare a ETH_HandleTypeDef handle structure, for example:
19 ETH_HandleTypeDef heth;
20
21 (#)Fill parameters of Init structure in heth handle
22
23 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
24
25 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
26 (##) Enable the Ethernet interface clock using
27 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
28 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
29 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
30
31 (##) Initialize the related GPIO clocks
32 (##) Configure Ethernet pin-out
33 (##) Configure Ethernet NVIC interrupt (IT mode)
34
35 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
36 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
37 (##) HAL_ETH_DMARxDescListInit(); for Reception process
38
39 (#)Enable MAC and DMA transmission and reception:
40 (##) HAL_ETH_Start();
41
42 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
43 the frame to MAC TX FIFO:
44 (##) HAL_ETH_TransmitFrame();
45
46 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
47 frame parameters
48 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
49
50 (#) Get a received frame when an ETH RX interrupt occurs:
51 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
52
53 (#) Communicate with external PHY device:
54 (##) Read a specific register from the PHY
55 HAL_ETH_ReadPHYRegister();
56 (##) Write data to a specific RHY register:
57 HAL_ETH_WritePHYRegister();
58
59 (#) Configure the Ethernet MAC after ETH peripheral initialization
60 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
61
62 (#) Configure the Ethernet DMA after ETH peripheral initialization
63 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
64
65 *** Callback registration ***
66 =============================================
67
68 The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
69 allows the user to configure dynamically the driver callbacks.
70 Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
71
72 Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
73 (+) TxCpltCallback : Tx Complete Callback.
74 (+) RxCpltCallback : Rx Complete Callback.
75 (+) DMAErrorCallback : DMA Error Callback.
76 (+) MspInitCallback : MspInit Callback.
77 (+) MspDeInitCallback: MspDeInit Callback.
78
79 This function takes as parameters the HAL peripheral handle, the Callback ID
80 and a pointer to the user callback function.
81
82 Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
83 weak function.
84 @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (+) TxCpltCallback : Tx Complete Callback.
88 (+) RxCpltCallback : Rx Complete Callback.
89 (+) DMAErrorCallback : DMA Error Callback.
90 (+) MspInitCallback : MspInit Callback.
91 (+) MspDeInitCallback: MspDeInit Callback.
92
93 By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
94 all callbacks are set to the corresponding weak functions:
95 examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
96 Exception done for MspInit and MspDeInit functions that are
97 reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
98 these callbacks are null (not registered beforehand).
99 if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
100 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
101
102 Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
103 Exception done MspInit/MspDeInit that can be registered/unregistered
104 in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
105 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
106 In that case first register the MspInit/MspDeInit user callbacks
107 using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
108 or HAL_ETH_Init function.
109
110 When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
111 not defined, the callback registration feature is not available and all callbacks
112 are set to the corresponding weak functions.
113
114 @endverbatim
115 ******************************************************************************
116 * @attention
117 *
118 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
119 * All rights reserved.</center></h2>
120 *
121 * This software component is licensed by ST under BSD 3-Clause license,
122 * the "License"; You may not use this file except in compliance with the
123 * License. You may obtain a copy of the License at:
124 * opensource.org/licenses/BSD-3-Clause
125 *
126 ******************************************************************************
127 */
128
129 /* Includes ------------------------------------------------------------------*/
130 #include "stm32f7xx_hal.h"
131
132 /** @addtogroup STM32F7xx_HAL_Driver
133 * @{
134 */
135
136 /** @defgroup ETH ETH
137 * @brief ETH HAL module driver
138 * @{
139 */
140
141 #ifdef HAL_ETH_MODULE_ENABLED
142 #if defined (ETH)
143
144 /* Private typedef -----------------------------------------------------------*/
145 /* Private define ------------------------------------------------------------*/
146 /** @defgroup ETH_Private_Constants ETH Private Constants
147 * @{
148 */
149 #define ETH_TIMEOUT_SWRESET ((uint32_t)500)
150 #define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
151 #define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
152
153 /**
154 * @}
155 */
156 /* Private macro -------------------------------------------------------------*/
157 /* Private variables ---------------------------------------------------------*/
158 /* Private function prototypes -----------------------------------------------*/
159 /** @defgroup ETH_Private_Functions ETH Private Functions
160 * @{
161 */
162 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
163 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
164 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
165 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
166 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
167 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
168 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
169 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
170 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
171 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
172 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
173 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
174 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
175 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
176
177 /**
178 * @}
179 */
180 /* Private functions ---------------------------------------------------------*/
181
182 /** @defgroup ETH_Exported_Functions ETH Exported Functions
183 * @{
184 */
185
186 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
187 * @brief Initialization and Configuration functions
188 *
189 @verbatim
190 ===============================================================================
191 ##### Initialization and de-initialization functions #####
192 ===============================================================================
193 [..] This section provides functions allowing to:
194 (+) Initialize and configure the Ethernet peripheral
195 (+) De-initialize the Ethernet peripheral
196
197 @endverbatim
198 * @{
199 */
200
201 /**
202 * @brief Initializes the Ethernet MAC and DMA according to default
203 * parameters.
204 * @param heth pointer to a ETH_HandleTypeDef structure that contains
205 * the configuration information for ETHERNET module
206 * @retval HAL status
207 */
208 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
209 {
210 uint32_t tempreg = 0, phyreg = 0;
211 uint32_t hclk = 60000000;
212 uint32_t tickstart = 0;
213 uint32_t err = ETH_SUCCESS;
214
215 /* Check the ETH peripheral state */
216 if(heth == NULL)
217 {
218 return HAL_ERROR;
219 }
220
221 /* Check parameters */
222 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
223 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
224 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
225 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
226
227 if(heth->State == HAL_ETH_STATE_RESET)
228 {
229 /* Allocate lock resource and initialize it */
230 heth->Lock = HAL_UNLOCKED;
231 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
232 ETH_InitCallbacksToDefault(heth);
233
234 if(heth->MspInitCallback == NULL)
235 {
236 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
237 heth->MspInitCallback = HAL_ETH_MspInit;
238 }
239 heth->MspInitCallback(heth);
240
241 #else
242 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
243 HAL_ETH_MspInit(heth);
244 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
245 }
246
247 /* Enable SYSCFG Clock */
248 __HAL_RCC_SYSCFG_CLK_ENABLE();
249
250 /* Select MII or RMII Mode*/
251 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
252 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
253
254 /* Ethernet Software reset */
255 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
256 /* After reset all the registers holds their respective reset values */
257 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
258
259 /* Get tick */
260 tickstart = HAL_GetTick();
261
262 /* Wait for software reset */
263 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
264 {
265 /* Check for the Timeout */
266 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
267 {
268 heth->State= HAL_ETH_STATE_TIMEOUT;
269
270 /* Process Unlocked */
271 __HAL_UNLOCK(heth);
272
273 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
274 not available, please check your external PHY or the IO configuration */
275
276 return HAL_TIMEOUT;
277 }
278 }
279
280 /*-------------------------------- MAC Initialization ----------------------*/
281 /* Get the ETHERNET MACMIIAR value */
282 tempreg = (heth->Instance)->MACMIIAR;
283 /* Clear CSR Clock Range CR[2:0] bits */
284 tempreg &= ETH_MACMIIAR_CR_MASK;
285
286 /* Get hclk frequency value */
287 hclk = HAL_RCC_GetHCLKFreq();
288
289 /* Set CR bits depending on hclk value */
290 if((hclk >= 20000000)&&(hclk < 35000000))
291 {
292 /* CSR Clock Range between 20-35 MHz */
293 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
294 }
295 else if((hclk >= 35000000)&&(hclk < 60000000))
296 {
297 /* CSR Clock Range between 35-60 MHz */
298 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
299 }
300 else if((hclk >= 60000000)&&(hclk < 100000000))
301 {
302 /* CSR Clock Range between 60-100 MHz */
303 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
304 }
305 else if((hclk >= 100000000)&&(hclk < 150000000))
306 {
307 /* CSR Clock Range between 100-150 MHz */
308 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
309 }
310 else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
311 {
312 /* CSR Clock Range between 150-216 MHz */
313 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
314 }
315
316 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
317 (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
318
319 /*-------------------- PHY initialization and configuration ----------------*/
320 /* Put the PHY in reset mode */
321 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
322 {
323 /* In case of write timeout */
324 err = ETH_ERROR;
325
326 /* Config MAC and DMA */
327 ETH_MACDMAConfig(heth, err);
328
329 /* Set the ETH peripheral state to READY */
330 heth->State = HAL_ETH_STATE_READY;
331
332 /* Return HAL_ERROR */
333 return HAL_ERROR;
334 }
335
336 /* Delay to assure PHY reset */
337 HAL_Delay(PHY_RESET_DELAY);
338
339 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
340 {
341 /* Get tick */
342 tickstart = HAL_GetTick();
343
344 /* We wait for linked status */
345 do
346 {
347 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
348
349 /* Check for the Timeout */
350 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
351 {
352 /* In case of write timeout */
353 err = ETH_ERROR;
354
355 /* Config MAC and DMA */
356 ETH_MACDMAConfig(heth, err);
357
358 heth->State= HAL_ETH_STATE_READY;
359
360 /* Process Unlocked */
361 __HAL_UNLOCK(heth);
362
363 return HAL_TIMEOUT;
364 }
365 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
366
367
368 /* Enable Auto-Negotiation */
369 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
370 {
371 /* In case of write timeout */
372 err = ETH_ERROR;
373
374 /* Config MAC and DMA */
375 ETH_MACDMAConfig(heth, err);
376
377 /* Set the ETH peripheral state to READY */
378 heth->State = HAL_ETH_STATE_READY;
379
380 /* Return HAL_ERROR */
381 return HAL_ERROR;
382 }
383
384 /* Get tick */
385 tickstart = HAL_GetTick();
386
387 /* Wait until the auto-negotiation will be completed */
388 do
389 {
390 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
391
392 /* Check for the Timeout */
393 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
394 {
395 /* In case of write timeout */
396 err = ETH_ERROR;
397
398 /* Config MAC and DMA */
399 ETH_MACDMAConfig(heth, err);
400
401 heth->State= HAL_ETH_STATE_READY;
402
403 /* Process Unlocked */
404 __HAL_UNLOCK(heth);
405
406 return HAL_TIMEOUT;
407 }
408
409 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
410
411 /* Read the result of the auto-negotiation */
412 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
413 {
414 /* In case of write timeout */
415 err = ETH_ERROR;
416
417 /* Config MAC and DMA */
418 ETH_MACDMAConfig(heth, err);
419
420 /* Set the ETH peripheral state to READY */
421 heth->State = HAL_ETH_STATE_READY;
422
423 /* Return HAL_ERROR */
424 return HAL_ERROR;
425 }
426
427 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
428 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
429 {
430 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
431 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
432 }
433 else
434 {
435 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
436 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
437 }
438 /* Configure the MAC with the speed fixed by the auto-negotiation process */
439 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
440 {
441 /* Set Ethernet speed to 10M following the auto-negotiation */
442 (heth->Init).Speed = ETH_SPEED_10M;
443 }
444 else
445 {
446 /* Set Ethernet speed to 100M following the auto-negotiation */
447 (heth->Init).Speed = ETH_SPEED_100M;
448 }
449 }
450 else /* AutoNegotiation Disable */
451 {
452 /* Check parameters */
453 assert_param(IS_ETH_SPEED(heth->Init.Speed));
454 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
455
456 /* Set MAC Speed and Duplex Mode */
457 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
458 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
459 {
460 /* In case of write timeout */
461 err = ETH_ERROR;
462
463 /* Config MAC and DMA */
464 ETH_MACDMAConfig(heth, err);
465
466 /* Set the ETH peripheral state to READY */
467 heth->State = HAL_ETH_STATE_READY;
468
469 /* Return HAL_ERROR */
470 return HAL_ERROR;
471 }
472
473 /* Delay to assure PHY configuration */
474 HAL_Delay(PHY_CONFIG_DELAY);
475 }
476
477 /* Config MAC and DMA */
478 ETH_MACDMAConfig(heth, err);
479
480 /* Set ETH HAL State to Ready */
481 heth->State= HAL_ETH_STATE_READY;
482
483 /* Return function status */
484 return HAL_OK;
485 }
486
487 /**
488 * @brief De-Initializes the ETH peripheral.
489 * @param heth pointer to a ETH_HandleTypeDef structure that contains
490 * the configuration information for ETHERNET module
491 * @retval HAL status
492 */
493 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
494 {
495 /* Set the ETH peripheral state to BUSY */
496 heth->State = HAL_ETH_STATE_BUSY;
497
498 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
499 if(heth->MspDeInitCallback == NULL)
500 {
501 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
502 }
503 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
504 heth->MspDeInitCallback(heth);
505 #else
506 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
507 HAL_ETH_MspDeInit(heth);
508 #endif
509
510 /* Set ETH HAL state to Disabled */
511 heth->State= HAL_ETH_STATE_RESET;
512
513 /* Release Lock */
514 __HAL_UNLOCK(heth);
515
516 /* Return function status */
517 return HAL_OK;
518 }
519
520 /**
521 * @brief Initializes the DMA Tx descriptors in chain mode.
522 * @param heth pointer to a ETH_HandleTypeDef structure that contains
523 * the configuration information for ETHERNET module
524 * @param DMATxDescTab Pointer to the first Tx desc list
525 * @param TxBuff Pointer to the first TxBuffer list
526 * @param TxBuffCount Number of the used Tx desc in the list
527 * @retval HAL status
528 */
529 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
530 {
531 uint32_t i = 0;
532 ETH_DMADescTypeDef *dmatxdesc;
533
534 /* Process Locked */
535 __HAL_LOCK(heth);
536
537 /* Set the ETH peripheral state to BUSY */
538 heth->State = HAL_ETH_STATE_BUSY;
539
540 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
541 heth->TxDesc = DMATxDescTab;
542
543 /* Fill each DMATxDesc descriptor with the right values */
544 for(i=0; i < TxBuffCount; i++)
545 {
546 /* Get the pointer on the ith member of the Tx Desc list */
547 dmatxdesc = DMATxDescTab + i;
548
549 /* Set Second Address Chained bit */
550 dmatxdesc->Status = ETH_DMATXDESC_TCH;
551
552 /* Set Buffer1 address pointer */
553 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
554
555 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
556 {
557 /* Set the DMA Tx descriptors checksum insertion */
558 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
559 }
560
561 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
562 if(i < (TxBuffCount-1))
563 {
564 /* Set next descriptor address register with next descriptor base address */
565 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
566 }
567 else
568 {
569 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
570 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
571 }
572 }
573
574 /* Set Transmit Descriptor List Address Register */
575 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
576
577 /* Set ETH HAL State to Ready */
578 heth->State= HAL_ETH_STATE_READY;
579
580 /* Process Unlocked */
581 __HAL_UNLOCK(heth);
582
583 /* Return function status */
584 return HAL_OK;
585 }
586
587 /**
588 * @brief Initializes the DMA Rx descriptors in chain mode.
589 * @param heth pointer to a ETH_HandleTypeDef structure that contains
590 * the configuration information for ETHERNET module
591 * @param DMARxDescTab Pointer to the first Rx desc list
592 * @param RxBuff Pointer to the first RxBuffer list
593 * @param RxBuffCount Number of the used Rx desc in the list
594 * @retval HAL status
595 */
596 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
597 {
598 uint32_t i = 0;
599 ETH_DMADescTypeDef *DMARxDesc;
600
601 /* Process Locked */
602 __HAL_LOCK(heth);
603
604 /* Set the ETH peripheral state to BUSY */
605 heth->State = HAL_ETH_STATE_BUSY;
606
607 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
608 heth->RxDesc = DMARxDescTab;
609
610 /* Fill each DMARxDesc descriptor with the right values */
611 for(i=0; i < RxBuffCount; i++)
612 {
613 /* Get the pointer on the ith member of the Rx Desc list */
614 DMARxDesc = DMARxDescTab+i;
615
616 /* Set Own bit of the Rx descriptor Status */
617 DMARxDesc->Status = ETH_DMARXDESC_OWN;
618
619 /* Set Buffer1 size and Second Address Chained bit */
620 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
621
622 /* Set Buffer1 address pointer */
623 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
624
625 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
626 {
627 /* Enable Ethernet DMA Rx Descriptor interrupt */
628 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
629 }
630
631 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
632 if(i < (RxBuffCount-1))
633 {
634 /* Set next descriptor address register with next descriptor base address */
635 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
636 }
637 else
638 {
639 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
640 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
641 }
642 }
643
644 /* Set Receive Descriptor List Address Register */
645 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
646
647 /* Set ETH HAL State to Ready */
648 heth->State= HAL_ETH_STATE_READY;
649
650 /* Process Unlocked */
651 __HAL_UNLOCK(heth);
652
653 /* Return function status */
654 return HAL_OK;
655 }
656
657 /**
658 * @brief Initializes the ETH MSP.
659 * @param heth pointer to a ETH_HandleTypeDef structure that contains
660 * the configuration information for ETHERNET module
661 * @retval None
662 */
663 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
664 {
665 /* Prevent unused argument(s) compilation warning */
666 UNUSED(heth);
667
668 /* NOTE : This function Should not be modified, when the callback is needed,
669 the HAL_ETH_MspInit could be implemented in the user file
670 */
671 }
672
673 /**
674 * @brief DeInitializes ETH MSP.
675 * @param heth pointer to a ETH_HandleTypeDef structure that contains
676 * the configuration information for ETHERNET module
677 * @retval None
678 */
679 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
680 {
681 /* Prevent unused argument(s) compilation warning */
682 UNUSED(heth);
683
684 /* NOTE : This function Should not be modified, when the callback is needed,
685 the HAL_ETH_MspDeInit could be implemented in the user file
686 */
687 }
688
689 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
690 /**
691 * @brief Register a User ETH Callback
692 * To be used instead of the weak predefined callback
693 * @param heth eth handle
694 * @param CallbackID ID of the callback to be registered
695 * This parameter can be one of the following values:
696 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
697 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
698 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
699 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
700 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
701 * @param pCallback pointer to the Callback function
702 * @retval status
703 */
704 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
705 {
706 HAL_StatusTypeDef status = HAL_OK;
707
708 if(pCallback == NULL)
709 {
710 return HAL_ERROR;
711 }
712 /* Process locked */
713 __HAL_LOCK(heth);
714
715 if(heth->State == HAL_ETH_STATE_READY)
716 {
717 switch (CallbackID)
718 {
719 case HAL_ETH_TX_COMPLETE_CB_ID :
720 heth->TxCpltCallback = pCallback;
721 break;
722
723 case HAL_ETH_RX_COMPLETE_CB_ID :
724 heth->RxCpltCallback = pCallback;
725 break;
726
727 case HAL_ETH_DMA_ERROR_CB_ID :
728 heth->DMAErrorCallback = pCallback;
729 break;
730
731 case HAL_ETH_MSPINIT_CB_ID :
732 heth->MspInitCallback = pCallback;
733 break;
734
735 case HAL_ETH_MSPDEINIT_CB_ID :
736 heth->MspDeInitCallback = pCallback;
737 break;
738
739 default :
740 /* Return error status */
741 status = HAL_ERROR;
742 break;
743 }
744 }
745 else if(heth->State == HAL_ETH_STATE_RESET)
746 {
747 switch (CallbackID)
748 {
749 case HAL_ETH_MSPINIT_CB_ID :
750 heth->MspInitCallback = pCallback;
751 break;
752
753 case HAL_ETH_MSPDEINIT_CB_ID :
754 heth->MspDeInitCallback = pCallback;
755 break;
756
757 default :
758 /* Return error status */
759 status = HAL_ERROR;
760 break;
761 }
762 }
763 else
764 {
765 /* Return error status */
766 status = HAL_ERROR;
767 }
768
769 /* Release Lock */
770 __HAL_UNLOCK(heth);
771
772 return status;
773 }
774
775 /**
776 * @brief Unregister an ETH Callback
777 * ETH callabck is redirected to the weak predefined callback
778 * @param heth eth handle
779 * @param CallbackID ID of the callback to be unregistered
780 * This parameter can be one of the following values:
781 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
782 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
783 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
784 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
785 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
786 * @retval status
787 */
788 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
789 {
790 HAL_StatusTypeDef status = HAL_OK;
791
792 /* Process locked */
793 __HAL_LOCK(heth);
794
795 if(heth->State == HAL_ETH_STATE_READY)
796 {
797 switch (CallbackID)
798 {
799 case HAL_ETH_TX_COMPLETE_CB_ID :
800 heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
801 break;
802
803 case HAL_ETH_RX_COMPLETE_CB_ID :
804 heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
805 break;
806
807 case HAL_ETH_DMA_ERROR_CB_ID :
808 heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
809 break;
810
811 case HAL_ETH_MSPINIT_CB_ID :
812 heth->MspInitCallback = HAL_ETH_MspInit;
813 break;
814
815 case HAL_ETH_MSPDEINIT_CB_ID :
816 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
817 break;
818
819 default :
820 /* Return error status */
821 status = HAL_ERROR;
822 break;
823 }
824 }
825 else if(heth->State == HAL_ETH_STATE_RESET)
826 {
827 switch (CallbackID)
828 {
829 case HAL_ETH_MSPINIT_CB_ID :
830 heth->MspInitCallback = HAL_ETH_MspInit;
831 break;
832
833 case HAL_ETH_MSPDEINIT_CB_ID :
834 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
835 break;
836
837 default :
838 /* Return error status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* Return error status */
846 status = HAL_ERROR;
847 }
848
849 /* Release Lock */
850 __HAL_UNLOCK(heth);
851
852 return status;
853 }
854 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
855
856 /**
857 * @}
858 */
859
860 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
861 * @brief Data transfers functions
862 *
863 @verbatim
864 ==============================================================================
865 ##### IO operation functions #####
866 ==============================================================================
867 [..] This section provides functions allowing to:
868 (+) Transmit a frame
869 HAL_ETH_TransmitFrame();
870 (+) Receive a frame
871 HAL_ETH_GetReceivedFrame();
872 HAL_ETH_GetReceivedFrame_IT();
873 (+) Read from an External PHY register
874 HAL_ETH_ReadPHYRegister();
875 (+) Write to an External PHY register
876 HAL_ETH_WritePHYRegister();
877
878 @endverbatim
879
880 * @{
881 */
882
883 /**
884 * @brief Sends an Ethernet frame.
885 * @param heth pointer to a ETH_HandleTypeDef structure that contains
886 * the configuration information for ETHERNET module
887 * @param FrameLength Amount of data to be sent
888 * @retval HAL status
889 */
890 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
891 {
892 uint32_t bufcount = 0, size = 0, i = 0;
893
894 /* Process Locked */
895 __HAL_LOCK(heth);
896
897 /* Set the ETH peripheral state to BUSY */
898 heth->State = HAL_ETH_STATE_BUSY;
899
900 if (FrameLength == 0)
901 {
902 /* Set ETH HAL state to READY */
903 heth->State = HAL_ETH_STATE_READY;
904
905 /* Process Unlocked */
906 __HAL_UNLOCK(heth);
907
908 return HAL_ERROR;
909 }
910
911 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
912 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
913 {
914 /* OWN bit set */
915 heth->State = HAL_ETH_STATE_BUSY_TX;
916
917 /* Process Unlocked */
918 __HAL_UNLOCK(heth);
919
920 return HAL_ERROR;
921 }
922
923 /* Get the number of needed Tx buffers for the current frame */
924 if (FrameLength > ETH_TX_BUF_SIZE)
925 {
926 bufcount = FrameLength/ETH_TX_BUF_SIZE;
927 if (FrameLength % ETH_TX_BUF_SIZE)
928 {
929 bufcount++;
930 }
931 }
932 else
933 {
934 bufcount = 1;
935 }
936 if (bufcount == 1)
937 {
938 /* Set LAST and FIRST segment */
939 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
940 /* Set frame size */
941 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
942 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
943 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
944 /* Point to next descriptor */
945 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
946 }
947 else
948 {
949 for (i=0; i< bufcount; i++)
950 {
951 /* Clear FIRST and LAST segment bits */
952 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
953
954 if (i == 0)
955 {
956 /* Setting the first segment bit */
957 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
958 }
959
960 /* Program size */
961 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
962
963 if (i == (bufcount-1))
964 {
965 /* Setting the last segment bit */
966 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
967 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
968 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
969 }
970
971 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
972 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
973 /* point to next descriptor */
974 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
975 }
976 }
977
978 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
979 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
980 {
981 /* Clear TBUS ETHERNET DMA flag */
982 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
983 /* Resume DMA transmission*/
984 (heth->Instance)->DMATPDR = 0;
985 }
986
987 /* Set ETH HAL State to Ready */
988 heth->State = HAL_ETH_STATE_READY;
989
990 /* Process Unlocked */
991 __HAL_UNLOCK(heth);
992
993 /* Return function status */
994 return HAL_OK;
995 }
996
997 /**
998 * @brief Checks for received frames.
999 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1000 * the configuration information for ETHERNET module
1001 * @retval HAL status
1002 */
1003 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
1004 {
1005 uint32_t framelength = 0;
1006
1007 /* Process Locked */
1008 __HAL_LOCK(heth);
1009
1010 /* Check the ETH state to BUSY */
1011 heth->State = HAL_ETH_STATE_BUSY;
1012
1013 /* Check if segment is not owned by DMA */
1014 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
1015 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
1016 {
1017 /* Check if last segment */
1018 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
1019 {
1020 /* increment segment count */
1021 (heth->RxFrameInfos).SegCount++;
1022
1023 /* Check if last segment is first segment: one segment contains the frame */
1024 if ((heth->RxFrameInfos).SegCount == 1)
1025 {
1026 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
1027 }
1028
1029 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1030
1031 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1032 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
1033 heth->RxFrameInfos.length = framelength;
1034
1035 /* Get the address of the buffer start address */
1036 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1037 /* point to next descriptor */
1038 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
1039
1040 /* Set HAL State to Ready */
1041 heth->State = HAL_ETH_STATE_READY;
1042
1043 /* Process Unlocked */
1044 __HAL_UNLOCK(heth);
1045
1046 /* Return function status */
1047 return HAL_OK;
1048 }
1049 /* Check if first segment */
1050 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
1051 {
1052 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
1053 (heth->RxFrameInfos).LSRxDesc = NULL;
1054 (heth->RxFrameInfos).SegCount = 1;
1055 /* Point to next descriptor */
1056 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1057 }
1058 /* Check if intermediate segment */
1059 else
1060 {
1061 (heth->RxFrameInfos).SegCount++;
1062 /* Point to next descriptor */
1063 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1064 }
1065 }
1066
1067 /* Set ETH HAL State to Ready */
1068 heth->State = HAL_ETH_STATE_READY;
1069
1070 /* Process Unlocked */
1071 __HAL_UNLOCK(heth);
1072
1073 /* Return function status */
1074 return HAL_ERROR;
1075 }
1076
1077 /**
1078 * @brief Gets the Received frame in interrupt mode.
1079 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1080 * the configuration information for ETHERNET module
1081 * @retval HAL status
1082 */
1083 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
1084 {
1085 uint32_t descriptorscancounter = 0;
1086
1087 /* Process Locked */
1088 __HAL_LOCK(heth);
1089
1090 /* Set ETH HAL State to BUSY */
1091 heth->State = HAL_ETH_STATE_BUSY;
1092
1093 /* Scan descriptors owned by CPU */
1094 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
1095 {
1096 /* Just for security */
1097 descriptorscancounter++;
1098
1099 /* Check if first segment in frame */
1100 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
1101 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
1102 {
1103 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1104 heth->RxFrameInfos.SegCount = 1;
1105 /* Point to next descriptor */
1106 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1107 }
1108 /* Check if intermediate segment */
1109 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
1110 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
1111 {
1112 /* Increment segment count */
1113 (heth->RxFrameInfos.SegCount)++;
1114 /* Point to next descriptor */
1115 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
1116 }
1117 /* Should be last segment */
1118 else
1119 {
1120 /* Last segment */
1121 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1122
1123 /* Increment segment count */
1124 (heth->RxFrameInfos.SegCount)++;
1125
1126 /* Check if last segment is first segment: one segment contains the frame */
1127 if ((heth->RxFrameInfos.SegCount) == 1)
1128 {
1129 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1130 }
1131
1132 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1133 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
1134
1135 /* Get the address of the buffer start address */
1136 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1137
1138 /* Point to next descriptor */
1139 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1140
1141 /* Set HAL State to Ready */
1142 heth->State = HAL_ETH_STATE_READY;
1143
1144 /* Process Unlocked */
1145 __HAL_UNLOCK(heth);
1146
1147 /* Return function status */
1148 return HAL_OK;
1149 }
1150 }
1151
1152 /* Set HAL State to Ready */
1153 heth->State = HAL_ETH_STATE_READY;
1154
1155 /* Process Unlocked */
1156 __HAL_UNLOCK(heth);
1157
1158 /* Return function status */
1159 return HAL_ERROR;
1160 }
1161
1162 /**
1163 * @brief This function handles ETH interrupt request.
1164 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1165 * the configuration information for ETHERNET module
1166 * @retval HAL status
1167 */
1168 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
1169 {
1170 /* Frame received */
1171 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
1172 {
1173 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1174 /*Call registered Receive complete callback*/
1175 heth->RxCpltCallback(heth);
1176 #else
1177 /* Receive complete callback */
1178 HAL_ETH_RxCpltCallback(heth);
1179 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1180
1181 /* Clear the Eth DMA Rx IT pending bits */
1182 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
1183
1184 /* Set HAL State to Ready */
1185 heth->State = HAL_ETH_STATE_READY;
1186
1187 /* Process Unlocked */
1188 __HAL_UNLOCK(heth);
1189
1190 }
1191 /* Frame transmitted */
1192 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
1193 {
1194 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1195 /* Call resgistered Transfer complete callback*/
1196 heth->TxCpltCallback(heth);
1197 #else
1198 /* Transfer complete callback */
1199 HAL_ETH_TxCpltCallback(heth);
1200 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1201
1202 /* Clear the Eth DMA Tx IT pending bits */
1203 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
1204
1205 /* Set HAL State to Ready */
1206 heth->State = HAL_ETH_STATE_READY;
1207
1208 /* Process Unlocked */
1209 __HAL_UNLOCK(heth);
1210 }
1211
1212 /* Clear the interrupt flags */
1213 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
1214
1215 /* ETH DMA Error */
1216 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
1217 {
1218 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1219 heth->DMAErrorCallback(heth);
1220 #else
1221 /* Ethernet Error callback */
1222 HAL_ETH_ErrorCallback(heth);
1223 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1224
1225 /* Clear the interrupt flags */
1226 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
1227
1228 /* Set HAL State to Ready */
1229 heth->State = HAL_ETH_STATE_READY;
1230
1231 /* Process Unlocked */
1232 __HAL_UNLOCK(heth);
1233 }
1234 }
1235
1236 /**
1237 * @brief Tx Transfer completed callbacks.
1238 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1239 * the configuration information for ETHERNET module
1240 * @retval None
1241 */
1242 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1243 {
1244 /* Prevent unused argument(s) compilation warning */
1245 UNUSED(heth);
1246
1247 /* NOTE : This function Should not be modified, when the callback is needed,
1248 the HAL_ETH_TxCpltCallback could be implemented in the user file
1249 */
1250 }
1251
1252 /**
1253 * @brief Rx Transfer completed callbacks.
1254 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1255 * the configuration information for ETHERNET module
1256 * @retval None
1257 */
1258 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1259 {
1260 /* Prevent unused argument(s) compilation warning */
1261 UNUSED(heth);
1262
1263 /* NOTE : This function Should not be modified, when the callback is needed,
1264 the HAL_ETH_RxCpltCallback could be implemented in the user file
1265 */
1266 }
1267
1268 /**
1269 * @brief Ethernet transfer error callbacks
1270 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1271 * the configuration information for ETHERNET module
1272 * @retval None
1273 */
1274 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1275 {
1276 /* Prevent unused argument(s) compilation warning */
1277 UNUSED(heth);
1278
1279 /* NOTE : This function Should not be modified, when the callback is needed,
1280 the HAL_ETH_ErrorCallback could be implemented in the user file
1281 */
1282 }
1283
1284 /**
1285 * @brief Reads a PHY register
1286 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1287 * the configuration information for ETHERNET module
1288 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1289 * This parameter can be one of the following values:
1290 * PHY_BCR: Transceiver Basic Control Register,
1291 * PHY_BSR: Transceiver Basic Status Register.
1292 * More PHY register could be read depending on the used PHY
1293 * @param RegValue PHY register value
1294 * @retval HAL status
1295 */
1296 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1297 {
1298 uint32_t tmpreg = 0;
1299 uint32_t tickstart = 0;
1300
1301 /* Check parameters */
1302 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1303
1304 /* Check the ETH peripheral state */
1305 if(heth->State == HAL_ETH_STATE_BUSY_RD)
1306 {
1307 return HAL_BUSY;
1308 }
1309 /* Set ETH HAL State to BUSY_RD */
1310 heth->State = HAL_ETH_STATE_BUSY_RD;
1311
1312 /* Get the ETHERNET MACMIIAR value */
1313 tmpreg = heth->Instance->MACMIIAR;
1314
1315 /* Keep only the CSR Clock Range CR[2:0] bits value */
1316 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
1317
1318 /* Prepare the MII address register value */
1319 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1320 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1321 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1322 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1323
1324 /* Write the result value into the MII Address register */
1325 heth->Instance->MACMIIAR = tmpreg;
1326
1327 /* Get tick */
1328 tickstart = HAL_GetTick();
1329
1330 /* Check for the Busy flag */
1331 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1332 {
1333 /* Check for the Timeout */
1334 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1335 {
1336 heth->State= HAL_ETH_STATE_READY;
1337
1338 /* Process Unlocked */
1339 __HAL_UNLOCK(heth);
1340
1341 return HAL_TIMEOUT;
1342 }
1343
1344 tmpreg = heth->Instance->MACMIIAR;
1345 }
1346
1347 /* Get MACMIIDR value */
1348 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1349
1350 /* Set ETH HAL State to READY */
1351 heth->State = HAL_ETH_STATE_READY;
1352
1353 /* Return function status */
1354 return HAL_OK;
1355 }
1356
1357 /**
1358 * @brief Writes to a PHY register.
1359 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1360 * the configuration information for ETHERNET module
1361 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1362 * This parameter can be one of the following values:
1363 * PHY_BCR: Transceiver Control Register.
1364 * More PHY register could be written depending on the used PHY
1365 * @param RegValue the value to write
1366 * @retval HAL status
1367 */
1368 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1369 {
1370 uint32_t tmpreg = 0;
1371 uint32_t tickstart = 0;
1372
1373 /* Check parameters */
1374 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1375
1376 /* Check the ETH peripheral state */
1377 if(heth->State == HAL_ETH_STATE_BUSY_WR)
1378 {
1379 return HAL_BUSY;
1380 }
1381 /* Set ETH HAL State to BUSY_WR */
1382 heth->State = HAL_ETH_STATE_BUSY_WR;
1383
1384 /* Get the ETHERNET MACMIIAR value */
1385 tmpreg = heth->Instance->MACMIIAR;
1386
1387 /* Keep only the CSR Clock Range CR[2:0] bits value */
1388 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
1389
1390 /* Prepare the MII register address value */
1391 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1392 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1393 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
1394 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1395
1396 /* Give the value to the MII data register */
1397 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1398
1399 /* Write the result value into the MII Address register */
1400 heth->Instance->MACMIIAR = tmpreg;
1401
1402 /* Get tick */
1403 tickstart = HAL_GetTick();
1404
1405 /* Check for the Busy flag */
1406 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1407 {
1408 /* Check for the Timeout */
1409 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1410 {
1411 heth->State= HAL_ETH_STATE_READY;
1412
1413 /* Process Unlocked */
1414 __HAL_UNLOCK(heth);
1415
1416 return HAL_TIMEOUT;
1417 }
1418
1419 tmpreg = heth->Instance->MACMIIAR;
1420 }
1421
1422 /* Set ETH HAL State to READY */
1423 heth->State = HAL_ETH_STATE_READY;
1424
1425 /* Return function status */
1426 return HAL_OK;
1427 }
1428
1429 /**
1430 * @}
1431 */
1432
1433 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1434 * @brief Peripheral Control functions
1435 *
1436 @verbatim
1437 ===============================================================================
1438 ##### Peripheral Control functions #####
1439 ===============================================================================
1440 [..] This section provides functions allowing to:
1441 (+) Enable MAC and DMA transmission and reception.
1442 HAL_ETH_Start();
1443 (+) Disable MAC and DMA transmission and reception.
1444 HAL_ETH_Stop();
1445 (+) Set the MAC configuration in runtime mode
1446 HAL_ETH_ConfigMAC();
1447 (+) Set the DMA configuration in runtime mode
1448 HAL_ETH_ConfigDMA();
1449
1450 @endverbatim
1451 * @{
1452 */
1453
1454 /**
1455 * @brief Enables Ethernet MAC and DMA reception/transmission
1456 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1457 * the configuration information for ETHERNET module
1458 * @retval HAL status
1459 */
1460 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1461 {
1462 /* Process Locked */
1463 __HAL_LOCK(heth);
1464
1465 /* Set the ETH peripheral state to BUSY */
1466 heth->State = HAL_ETH_STATE_BUSY;
1467
1468 /* Enable transmit state machine of the MAC for transmission on the MII */
1469 ETH_MACTransmissionEnable(heth);
1470
1471 /* Enable receive state machine of the MAC for reception from the MII */
1472 ETH_MACReceptionEnable(heth);
1473
1474 /* Flush Transmit FIFO */
1475 ETH_FlushTransmitFIFO(heth);
1476
1477 /* Start DMA transmission */
1478 ETH_DMATransmissionEnable(heth);
1479
1480 /* Start DMA reception */
1481 ETH_DMAReceptionEnable(heth);
1482
1483 /* Set the ETH state to READY*/
1484 heth->State= HAL_ETH_STATE_READY;
1485
1486 /* Process Unlocked */
1487 __HAL_UNLOCK(heth);
1488
1489 /* Return function status */
1490 return HAL_OK;
1491 }
1492
1493 /**
1494 * @brief Stop Ethernet MAC and DMA reception/transmission
1495 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1496 * the configuration information for ETHERNET module
1497 * @retval HAL status
1498 */
1499 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1500 {
1501 /* Process Locked */
1502 __HAL_LOCK(heth);
1503
1504 /* Set the ETH peripheral state to BUSY */
1505 heth->State = HAL_ETH_STATE_BUSY;
1506
1507 /* Stop DMA transmission */
1508 ETH_DMATransmissionDisable(heth);
1509
1510 /* Stop DMA reception */
1511 ETH_DMAReceptionDisable(heth);
1512
1513 /* Disable receive state machine of the MAC for reception from the MII */
1514 ETH_MACReceptionDisable(heth);
1515
1516 /* Flush Transmit FIFO */
1517 ETH_FlushTransmitFIFO(heth);
1518
1519 /* Disable transmit state machine of the MAC for transmission on the MII */
1520 ETH_MACTransmissionDisable(heth);
1521
1522 /* Set the ETH state*/
1523 heth->State = HAL_ETH_STATE_READY;
1524
1525 /* Process Unlocked */
1526 __HAL_UNLOCK(heth);
1527
1528 /* Return function status */
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Set ETH MAC Configuration.
1534 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1535 * the configuration information for ETHERNET module
1536 * @param macconf MAC Configuration structure
1537 * @retval HAL status
1538 */
1539 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1540 {
1541 uint32_t tmpreg = 0;
1542
1543 /* Process Locked */
1544 __HAL_LOCK(heth);
1545
1546 /* Set the ETH peripheral state to BUSY */
1547 heth->State= HAL_ETH_STATE_BUSY;
1548
1549 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1550 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1551
1552 if (macconf != NULL)
1553 {
1554 /* Check the parameters */
1555 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1556 assert_param(IS_ETH_JABBER(macconf->Jabber));
1557 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1558 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1559 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1560 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1561 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1562 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1563 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1564 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1565 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1566 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1567 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1568 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1569 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1570 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1571 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1572 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1573 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1574 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1575 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1576 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1577 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1578 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1579 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1580 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1581 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1582
1583 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1584 /* Get the ETHERNET MACCR value */
1585 tmpreg = (heth->Instance)->MACCR;
1586 /* Clear WD, PCE, PS, TE and RE bits */
1587 tmpreg &= ETH_MACCR_CLEAR_MASK;
1588
1589 tmpreg |= (uint32_t)(macconf->Watchdog |
1590 macconf->Jabber |
1591 macconf->InterFrameGap |
1592 macconf->CarrierSense |
1593 (heth->Init).Speed |
1594 macconf->ReceiveOwn |
1595 macconf->LoopbackMode |
1596 (heth->Init).DuplexMode |
1597 macconf->ChecksumOffload |
1598 macconf->RetryTransmission |
1599 macconf->AutomaticPadCRCStrip |
1600 macconf->BackOffLimit |
1601 macconf->DeferralCheck);
1602
1603 /* Write to ETHERNET MACCR */
1604 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1605
1606 /* Wait until the write operation will be taken into account :
1607 at least four TX_CLK/RX_CLK clock cycles */
1608 tmpreg = (heth->Instance)->MACCR;
1609 HAL_Delay(ETH_REG_WRITE_DELAY);
1610 (heth->Instance)->MACCR = tmpreg;
1611
1612 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1613 /* Write to ETHERNET MACFFR */
1614 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1615 macconf->SourceAddrFilter |
1616 macconf->PassControlFrames |
1617 macconf->BroadcastFramesReception |
1618 macconf->DestinationAddrFilter |
1619 macconf->PromiscuousMode |
1620 macconf->MulticastFramesFilter |
1621 macconf->UnicastFramesFilter);
1622
1623 /* Wait until the write operation will be taken into account :
1624 at least four TX_CLK/RX_CLK clock cycles */
1625 tmpreg = (heth->Instance)->MACFFR;
1626 HAL_Delay(ETH_REG_WRITE_DELAY);
1627 (heth->Instance)->MACFFR = tmpreg;
1628
1629 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1630 /* Write to ETHERNET MACHTHR */
1631 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1632
1633 /* Write to ETHERNET MACHTLR */
1634 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1635 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1636
1637 /* Get the ETHERNET MACFCR value */
1638 tmpreg = (heth->Instance)->MACFCR;
1639 /* Clear xx bits */
1640 tmpreg &= ETH_MACFCR_CLEAR_MASK;
1641
1642 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
1643 macconf->ZeroQuantaPause |
1644 macconf->PauseLowThreshold |
1645 macconf->UnicastPauseFrameDetect |
1646 macconf->ReceiveFlowControl |
1647 macconf->TransmitFlowControl);
1648
1649 /* Write to ETHERNET MACFCR */
1650 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1651
1652 /* Wait until the write operation will be taken into account :
1653 at least four TX_CLK/RX_CLK clock cycles */
1654 tmpreg = (heth->Instance)->MACFCR;
1655 HAL_Delay(ETH_REG_WRITE_DELAY);
1656 (heth->Instance)->MACFCR = tmpreg;
1657
1658 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1659 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1660 macconf->VLANTagIdentifier);
1661
1662 /* Wait until the write operation will be taken into account :
1663 at least four TX_CLK/RX_CLK clock cycles */
1664 tmpreg = (heth->Instance)->MACVLANTR;
1665 HAL_Delay(ETH_REG_WRITE_DELAY);
1666 (heth->Instance)->MACVLANTR = tmpreg;
1667 }
1668 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1669 {
1670 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1671 /* Get the ETHERNET MACCR value */
1672 tmpreg = (heth->Instance)->MACCR;
1673
1674 /* Clear FES and DM bits */
1675 tmpreg &= ~((uint32_t)0x00004800);
1676
1677 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1678
1679 /* Write to ETHERNET MACCR */
1680 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1681
1682 /* Wait until the write operation will be taken into account:
1683 at least four TX_CLK/RX_CLK clock cycles */
1684 tmpreg = (heth->Instance)->MACCR;
1685 HAL_Delay(ETH_REG_WRITE_DELAY);
1686 (heth->Instance)->MACCR = tmpreg;
1687 }
1688
1689 /* Set the ETH state to Ready */
1690 heth->State= HAL_ETH_STATE_READY;
1691
1692 /* Process Unlocked */
1693 __HAL_UNLOCK(heth);
1694
1695 /* Return function status */
1696 return HAL_OK;
1697 }
1698
1699 /**
1700 * @brief Sets ETH DMA Configuration.
1701 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1702 * the configuration information for ETHERNET module
1703 * @param dmaconf DMA Configuration structure
1704 * @retval HAL status
1705 */
1706 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1707 {
1708 uint32_t tmpreg = 0;
1709
1710 /* Process Locked */
1711 __HAL_LOCK(heth);
1712
1713 /* Set the ETH peripheral state to BUSY */
1714 heth->State= HAL_ETH_STATE_BUSY;
1715
1716 /* Check parameters */
1717 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1718 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1719 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1720 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1721 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1722 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1723 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1724 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1725 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1726 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1727 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1728 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1729 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1730 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1731 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1732 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1733
1734 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1735 /* Get the ETHERNET DMAOMR value */
1736 tmpreg = (heth->Instance)->DMAOMR;
1737 /* Clear xx bits */
1738 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
1739
1740 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1741 dmaconf->ReceiveStoreForward |
1742 dmaconf->FlushReceivedFrame |
1743 dmaconf->TransmitStoreForward |
1744 dmaconf->TransmitThresholdControl |
1745 dmaconf->ForwardErrorFrames |
1746 dmaconf->ForwardUndersizedGoodFrames |
1747 dmaconf->ReceiveThresholdControl |
1748 dmaconf->SecondFrameOperate);
1749
1750 /* Write to ETHERNET DMAOMR */
1751 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
1752
1753 /* Wait until the write operation will be taken into account:
1754 at least four TX_CLK/RX_CLK clock cycles */
1755 tmpreg = (heth->Instance)->DMAOMR;
1756 HAL_Delay(ETH_REG_WRITE_DELAY);
1757 (heth->Instance)->DMAOMR = tmpreg;
1758
1759 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1760 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1761 dmaconf->FixedBurst |
1762 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1763 dmaconf->TxDMABurstLength |
1764 dmaconf->EnhancedDescriptorFormat |
1765 (dmaconf->DescriptorSkipLength << 2) |
1766 dmaconf->DMAArbitration |
1767 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1768
1769 /* Wait until the write operation will be taken into account:
1770 at least four TX_CLK/RX_CLK clock cycles */
1771 tmpreg = (heth->Instance)->DMABMR;
1772 HAL_Delay(ETH_REG_WRITE_DELAY);
1773 (heth->Instance)->DMABMR = tmpreg;
1774
1775 /* Set the ETH state to Ready */
1776 heth->State= HAL_ETH_STATE_READY;
1777
1778 /* Process Unlocked */
1779 __HAL_UNLOCK(heth);
1780
1781 /* Return function status */
1782 return HAL_OK;
1783 }
1784
1785 /**
1786 * @}
1787 */
1788
1789 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1790 * @brief Peripheral State functions
1791 *
1792 @verbatim
1793 ===============================================================================
1794 ##### Peripheral State functions #####
1795 ===============================================================================
1796 [..]
1797 This subsection permits to get in run-time the status of the peripheral
1798 and the data flow.
1799 (+) Get the ETH handle state:
1800 HAL_ETH_GetState();
1801
1802
1803 @endverbatim
1804 * @{
1805 */
1806
1807 /**
1808 * @brief Return the ETH HAL state
1809 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1810 * the configuration information for ETHERNET module
1811 * @retval HAL state
1812 */
1813 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1814 {
1815 /* Return ETH state */
1816 return heth->State;
1817 }
1818
1819 /**
1820 * @}
1821 */
1822
1823 /**
1824 * @}
1825 */
1826
1827 /** @addtogroup ETH_Private_Functions
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Configures Ethernet MAC and DMA with default parameters.
1833 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1834 * the configuration information for ETHERNET module
1835 * @param err Ethernet Init error
1836 * @retval HAL status
1837 */
1838 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1839 {
1840 ETH_MACInitTypeDef macinit;
1841 ETH_DMAInitTypeDef dmainit;
1842 uint32_t tmpreg = 0;
1843
1844 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1845 {
1846 /* Set Ethernet duplex mode to Full-duplex */
1847 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1848
1849 /* Set Ethernet speed to 100M */
1850 (heth->Init).Speed = ETH_SPEED_100M;
1851 }
1852
1853 /* Ethernet MAC default initialization **************************************/
1854 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1855 macinit.Jabber = ETH_JABBER_ENABLE;
1856 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1857 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1858 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1859 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1860 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1861 {
1862 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1863 }
1864 else
1865 {
1866 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1867 }
1868 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1869 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1870 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1871 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1872 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1873 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1874 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1875 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1876 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1877 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1878 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1879 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1880 macinit.HashTableHigh = 0x0;
1881 macinit.HashTableLow = 0x0;
1882 macinit.PauseTime = 0x0;
1883 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1884 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1885 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1886 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1887 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1888 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1889 macinit.VLANTagIdentifier = 0x0;
1890
1891 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1892 /* Get the ETHERNET MACCR value */
1893 tmpreg = (heth->Instance)->MACCR;
1894 /* Clear WD, PCE, PS, TE and RE bits */
1895 tmpreg &= ETH_MACCR_CLEAR_MASK;
1896 /* Set the WD bit according to ETH Watchdog value */
1897 /* Set the JD: bit according to ETH Jabber value */
1898 /* Set the IFG bit according to ETH InterFrameGap value */
1899 /* Set the DCRS bit according to ETH CarrierSense value */
1900 /* Set the FES bit according to ETH Speed value */
1901 /* Set the DO bit according to ETH ReceiveOwn value */
1902 /* Set the LM bit according to ETH LoopbackMode value */
1903 /* Set the DM bit according to ETH Mode value */
1904 /* Set the IPCO bit according to ETH ChecksumOffload value */
1905 /* Set the DR bit according to ETH RetryTransmission value */
1906 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1907 /* Set the BL bit according to ETH BackOffLimit value */
1908 /* Set the DC bit according to ETH DeferralCheck value */
1909 tmpreg |= (uint32_t)(macinit.Watchdog |
1910 macinit.Jabber |
1911 macinit.InterFrameGap |
1912 macinit.CarrierSense |
1913 (heth->Init).Speed |
1914 macinit.ReceiveOwn |
1915 macinit.LoopbackMode |
1916 (heth->Init).DuplexMode |
1917 macinit.ChecksumOffload |
1918 macinit.RetryTransmission |
1919 macinit.AutomaticPadCRCStrip |
1920 macinit.BackOffLimit |
1921 macinit.DeferralCheck);
1922
1923 /* Write to ETHERNET MACCR */
1924 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1925
1926 /* Wait until the write operation will be taken into account:
1927 at least four TX_CLK/RX_CLK clock cycles */
1928 tmpreg = (heth->Instance)->MACCR;
1929 HAL_Delay(ETH_REG_WRITE_DELAY);
1930 (heth->Instance)->MACCR = tmpreg;
1931
1932 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1933 /* Set the RA bit according to ETH ReceiveAll value */
1934 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1935 /* Set the PCF bit according to ETH PassControlFrames value */
1936 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1937 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1938 /* Set the PR bit according to ETH PromiscuousMode value */
1939 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1940 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1941 /* Write to ETHERNET MACFFR */
1942 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1943 macinit.SourceAddrFilter |
1944 macinit.PassControlFrames |
1945 macinit.BroadcastFramesReception |
1946 macinit.DestinationAddrFilter |
1947 macinit.PromiscuousMode |
1948 macinit.MulticastFramesFilter |
1949 macinit.UnicastFramesFilter);
1950
1951 /* Wait until the write operation will be taken into account:
1952 at least four TX_CLK/RX_CLK clock cycles */
1953 tmpreg = (heth->Instance)->MACFFR;
1954 HAL_Delay(ETH_REG_WRITE_DELAY);
1955 (heth->Instance)->MACFFR = tmpreg;
1956
1957 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1958 /* Write to ETHERNET MACHTHR */
1959 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1960
1961 /* Write to ETHERNET MACHTLR */
1962 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1963 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1964
1965 /* Get the ETHERNET MACFCR value */
1966 tmpreg = (heth->Instance)->MACFCR;
1967 /* Clear xx bits */
1968 tmpreg &= ETH_MACFCR_CLEAR_MASK;
1969
1970 /* Set the PT bit according to ETH PauseTime value */
1971 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1972 /* Set the PLT bit according to ETH PauseLowThreshold value */
1973 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1974 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1975 /* Set the TFE bit according to ETH TransmitFlowControl value */
1976 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
1977 macinit.ZeroQuantaPause |
1978 macinit.PauseLowThreshold |
1979 macinit.UnicastPauseFrameDetect |
1980 macinit.ReceiveFlowControl |
1981 macinit.TransmitFlowControl);
1982
1983 /* Write to ETHERNET MACFCR */
1984 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1985
1986 /* Wait until the write operation will be taken into account:
1987 at least four TX_CLK/RX_CLK clock cycles */
1988 tmpreg = (heth->Instance)->MACFCR;
1989 HAL_Delay(ETH_REG_WRITE_DELAY);
1990 (heth->Instance)->MACFCR = tmpreg;
1991
1992 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1993 /* Set the ETV bit according to ETH VLANTagComparison value */
1994 /* Set the VL bit according to ETH VLANTagIdentifier value */
1995 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1996 macinit.VLANTagIdentifier);
1997
1998 /* Wait until the write operation will be taken into account:
1999 at least four TX_CLK/RX_CLK clock cycles */
2000 tmpreg = (heth->Instance)->MACVLANTR;
2001 HAL_Delay(ETH_REG_WRITE_DELAY);
2002 (heth->Instance)->MACVLANTR = tmpreg;
2003
2004 /* Ethernet DMA default initialization ************************************/
2005 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
2006 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
2007 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
2008 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
2009 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
2010 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
2011 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
2012 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
2013 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
2014 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
2015 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
2016 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
2017 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
2018 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
2019 dmainit.DescriptorSkipLength = 0x0;
2020 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
2021
2022 /* Get the ETHERNET DMAOMR value */
2023 tmpreg = (heth->Instance)->DMAOMR;
2024 /* Clear xx bits */
2025 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
2026
2027 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
2028 /* Set the RSF bit according to ETH ReceiveStoreForward value */
2029 /* Set the DFF bit according to ETH FlushReceivedFrame value */
2030 /* Set the TSF bit according to ETH TransmitStoreForward value */
2031 /* Set the TTC bit according to ETH TransmitThresholdControl value */
2032 /* Set the FEF bit according to ETH ForwardErrorFrames value */
2033 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
2034 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
2035 /* Set the OSF bit according to ETH SecondFrameOperate value */
2036 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
2037 dmainit.ReceiveStoreForward |
2038 dmainit.FlushReceivedFrame |
2039 dmainit.TransmitStoreForward |
2040 dmainit.TransmitThresholdControl |
2041 dmainit.ForwardErrorFrames |
2042 dmainit.ForwardUndersizedGoodFrames |
2043 dmainit.ReceiveThresholdControl |
2044 dmainit.SecondFrameOperate);
2045
2046 /* Write to ETHERNET DMAOMR */
2047 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
2048
2049 /* Wait until the write operation will be taken into account:
2050 at least four TX_CLK/RX_CLK clock cycles */
2051 tmpreg = (heth->Instance)->DMAOMR;
2052 HAL_Delay(ETH_REG_WRITE_DELAY);
2053 (heth->Instance)->DMAOMR = tmpreg;
2054
2055 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
2056 /* Set the AAL bit according to ETH AddressAlignedBeats value */
2057 /* Set the FB bit according to ETH FixedBurst value */
2058 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
2059 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
2060 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
2061 /* Set the DSL bit according to ETH DesciptorSkipLength value */
2062 /* Set the PR and DA bits according to ETH DMAArbitration value */
2063 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
2064 dmainit.FixedBurst |
2065 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
2066 dmainit.TxDMABurstLength |
2067 dmainit.EnhancedDescriptorFormat |
2068 (dmainit.DescriptorSkipLength << 2) |
2069 dmainit.DMAArbitration |
2070 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
2071
2072 /* Wait until the write operation will be taken into account:
2073 at least four TX_CLK/RX_CLK clock cycles */
2074 tmpreg = (heth->Instance)->DMABMR;
2075 HAL_Delay(ETH_REG_WRITE_DELAY);
2076 (heth->Instance)->DMABMR = tmpreg;
2077
2078 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
2079 {
2080 /* Enable the Ethernet Rx Interrupt */
2081 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
2082 }
2083
2084 /* Initialize MAC address in ethernet MAC */
2085 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
2086 }
2087
2088 /**
2089 * @brief Configures the selected MAC address.
2090 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2091 * the configuration information for ETHERNET module
2092 * @param MacAddr The MAC address to configure
2093 * This parameter can be one of the following values:
2094 * @arg ETH_MAC_Address0: MAC Address0
2095 * @arg ETH_MAC_Address1: MAC Address1
2096 * @arg ETH_MAC_Address2: MAC Address2
2097 * @arg ETH_MAC_Address3: MAC Address3
2098 * @param Addr Pointer to MAC address buffer data (6 bytes)
2099 * @retval HAL status
2100 */
2101 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
2102 {
2103 uint32_t tmpreg;
2104
2105 /* Check the parameters */
2106 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
2107
2108 /* Calculate the selected MAC address high register */
2109 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
2110 /* Load the selected MAC address high register */
2111 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
2112 /* Calculate the selected MAC address low register */
2113 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
2114
2115 /* Load the selected MAC address low register */
2116 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
2117 }
2118
2119 /**
2120 * @brief Enables the MAC transmission.
2121 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2122 * the configuration information for ETHERNET module
2123 * @retval None
2124 */
2125 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
2126 {
2127 __IO uint32_t tmpreg = 0;
2128
2129 /* Enable the MAC transmission */
2130 (heth->Instance)->MACCR |= ETH_MACCR_TE;
2131
2132 /* Wait until the write operation will be taken into account:
2133 at least four TX_CLK/RX_CLK clock cycles */
2134 tmpreg = (heth->Instance)->MACCR;
2135 HAL_Delay(ETH_REG_WRITE_DELAY);
2136 (heth->Instance)->MACCR = tmpreg;
2137 }
2138
2139 /**
2140 * @brief Disables the MAC transmission.
2141 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2142 * the configuration information for ETHERNET module
2143 * @retval None
2144 */
2145 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
2146 {
2147 __IO uint32_t tmpreg = 0;
2148
2149 /* Disable the MAC transmission */
2150 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
2151
2152 /* Wait until the write operation will be taken into account:
2153 at least four TX_CLK/RX_CLK clock cycles */
2154 tmpreg = (heth->Instance)->MACCR;
2155 HAL_Delay(ETH_REG_WRITE_DELAY);
2156 (heth->Instance)->MACCR = tmpreg;
2157 }
2158
2159 /**
2160 * @brief Enables the MAC reception.
2161 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2162 * the configuration information for ETHERNET module
2163 * @retval None
2164 */
2165 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
2166 {
2167 __IO uint32_t tmpreg = 0;
2168
2169 /* Enable the MAC reception */
2170 (heth->Instance)->MACCR |= ETH_MACCR_RE;
2171
2172 /* Wait until the write operation will be taken into account:
2173 at least four TX_CLK/RX_CLK clock cycles */
2174 tmpreg = (heth->Instance)->MACCR;
2175 HAL_Delay(ETH_REG_WRITE_DELAY);
2176 (heth->Instance)->MACCR = tmpreg;
2177 }
2178
2179 /**
2180 * @brief Disables the MAC reception.
2181 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2182 * the configuration information for ETHERNET module
2183 * @retval None
2184 */
2185 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
2186 {
2187 __IO uint32_t tmpreg = 0;
2188
2189 /* Disable the MAC reception */
2190 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
2191
2192 /* Wait until the write operation will be taken into account:
2193 at least four TX_CLK/RX_CLK clock cycles */
2194 tmpreg = (heth->Instance)->MACCR;
2195 HAL_Delay(ETH_REG_WRITE_DELAY);
2196 (heth->Instance)->MACCR = tmpreg;
2197 }
2198
2199 /**
2200 * @brief Enables the DMA transmission.
2201 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2202 * the configuration information for ETHERNET module
2203 * @retval None
2204 */
2205 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
2206 {
2207 /* Enable the DMA transmission */
2208 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
2209 }
2210
2211 /**
2212 * @brief Disables the DMA transmission.
2213 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2214 * the configuration information for ETHERNET module
2215 * @retval None
2216 */
2217 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
2218 {
2219 /* Disable the DMA transmission */
2220 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
2221 }
2222
2223 /**
2224 * @brief Enables the DMA reception.
2225 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2226 * the configuration information for ETHERNET module
2227 * @retval None
2228 */
2229 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
2230 {
2231 /* Enable the DMA reception */
2232 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
2233 }
2234
2235 /**
2236 * @brief Disables the DMA reception.
2237 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2238 * the configuration information for ETHERNET module
2239 * @retval None
2240 */
2241 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2242 {
2243 /* Disable the DMA reception */
2244 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2245 }
2246
2247 /**
2248 * @brief Clears the ETHERNET transmit FIFO.
2249 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2250 * the configuration information for ETHERNET module
2251 * @retval None
2252 */
2253 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2254 {
2255 __IO uint32_t tmpreg = 0;
2256
2257 /* Set the Flush Transmit FIFO bit */
2258 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
2259
2260 /* Wait until the write operation will be taken into account:
2261 at least four TX_CLK/RX_CLK clock cycles */
2262 tmpreg = (heth->Instance)->DMAOMR;
2263 HAL_Delay(ETH_REG_WRITE_DELAY);
2264 (heth->Instance)->DMAOMR = tmpreg;
2265 }
2266
2267 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2268 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
2269 {
2270 /* Init the ETH Callback settings */
2271 heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
2272 heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
2273 heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
2274 }
2275 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2276
2277 /**
2278 * @}
2279 */
2280
2281 #endif /* ETH */
2282 #endif /* HAL_ETH_MODULE_ENABLED */
2283 /**
2284 * @}
2285 */
2286
2287 /**
2288 * @}
2289 */
2290
2291 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/