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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_i2s.c
blobaa955fc4b27060f902c5f18531bb2d1cbeb58b00
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 @verbatim
12 ===============================================================================
13 ##### How to use this driver #####
14 ===============================================================================
15 [..]
16 The I2S HAL driver can be used as follow:
17
18 (#) Declare a I2S_HandleTypeDef handle structure.
19 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
20 (##) Enable the SPIx interface clock.
21 (##) I2S pins configuration:
22 (+++) Enable the clock for the I2S GPIOs.
23 (+++) Configure these I2S pins as alternate function pull-up.
24 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
25 and HAL_I2S_Receive_IT() APIs).
26 (+++) Configure the I2Sx interrupt priority.
27 (+++) Enable the NVIC I2S IRQ handle.
28 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
29 and HAL_I2S_Receive_DMA() APIs:
30 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
31 (+++) Enable the DMAx interface clock.
32 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
33 (+++) Configure the DMA Tx/Rx Stream/Channel.
34 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
35 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
36 DMA Tx/Rx Stream/Channel.
37
38 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
39 using HAL_I2S_Init() function.
40
41 -@- The specific I2S interrupts (Transmission complete interrupt,
42 RXNE interrupt and Error Interrupts) will be managed using the macros
43 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
44 -@- Make sure that either:
45 (+@) I2S clock is configured based on SYSCLK or
46 (+@) External clock source is configured after setting correctly
47 the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.
48
49 (#) Three mode of operations are available within this driver :
50
51 *** Polling mode IO operation ***
52 =================================
53 [..]
54 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
55 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
56
57 *** Interrupt mode IO operation ***
58 ===================================
59 [..]
60 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
61 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
62 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
63 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
64 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
65 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
66 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
67 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
68 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
69 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
70 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
71 add his own code by customization of function pointer HAL_I2S_ErrorCallback
72
73 *** DMA mode IO operation ***
74 ==============================
75 [..]
76 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
77 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
78 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
79 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
80 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
81 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
82 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
83 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
84 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
85 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
86 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
87 add his own code by customization of function pointer HAL_I2S_ErrorCallback
88 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
89 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
90 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
91
92 *** I2S HAL driver macros list ***
93 ===================================
94 [..]
95 Below the list of most used macros in I2S HAL driver.
96
97 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
98 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
99 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
100 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
101 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
102
103 [..]
104 (@) You can refer to the I2S HAL driver header file for more useful macros
105
106 *** I2S HAL driver macros list ***
107 ===================================
108 [..]
109 Callback registration:
110
111 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
112 allows the user to configure dynamically the driver callbacks.
113 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
114
115 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
116 (+) TxCpltCallback : I2S Tx Completed callback
117 (+) RxCpltCallback : I2S Rx Completed callback
118 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
119 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
120 (+) ErrorCallback : I2S Error callback
121 (+) MspInitCallback : I2S Msp Init callback
122 (+) MspDeInitCallback : I2S Msp DeInit callback
123 This function takes as parameters the HAL peripheral handle, the Callback ID
124 and a pointer to the user callback function.
125
126
127 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
128 weak function.
129 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
130 and the Callback ID.
131 This function allows to reset following callbacks:
132 (+) TxCpltCallback : I2S Tx Completed callback
133 (+) RxCpltCallback : I2S Rx Completed callback
134 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
135 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
136 (+) ErrorCallback : I2S Error callback
137 (+) MspInitCallback : I2S Msp Init callback
138 (+) MspDeInitCallback : I2S Msp DeInit callback
139
140 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
141 all callbacks are set to the corresponding weak functions:
142 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
143 Exception done for MspInit and MspDeInit functions that are
144 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
145 these callbacks are null (not registered beforehand).
146 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
147 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
148
149 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
150 Exception done MspInit/MspDeInit functions that can be registered/unregistered
151 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
152 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
153 Then, the user first registers the MspInit/MspDeInit user callbacks
154 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
155 or HAL_I2S_Init() function.
156
157 When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
158 not defined, the callback registering feature is not available
159 and weak (surcharged) callbacks are used.
160
161 @endverbatim
162 ******************************************************************************
163 * @attention
164 *
165 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
166 * All rights reserved.</center></h2>
167 *
168 * This software component is licensed by ST under BSD 3-Clause license,
169 * the "License"; You may not use this file except in compliance with the
170 * License. You may obtain a copy of the License at:
171 * opensource.org/licenses/BSD-3-Clause
172 *
173 ******************************************************************************
174 */
175
176 /* Includes ------------------------------------------------------------------*/
177 #include "stm32f7xx_hal.h"
178
179 #ifdef HAL_I2S_MODULE_ENABLED
180
181 /** @addtogroup STM32F7xx_HAL_Driver
182 * @{
183 */
184
185 /** @defgroup I2S I2S
186 * @brief I2S HAL module driver
187 * @{
188 */
189
190 /* Private typedef -----------------------------------------------------------*/
191 /* Private define ------------------------------------------------------------*/
192 /* Private macro -------------------------------------------------------------*/
193 /* Private variables ---------------------------------------------------------*/
194 /* Private function prototypes -----------------------------------------------*/
195 /** @defgroup I2S_Private_Functions I2S Private Functions
196 * @{
197 */
198 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
199 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
200 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
201 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
202 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
203 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
204 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
205 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
206 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
207 uint32_t Timeout);
208 /**
209 * @}
210 */
211
212 /* Exported functions ---------------------------------------------------------*/
213
214 /** @defgroup I2S_Exported_Functions I2S Exported Functions
215 * @{
216 */
217
218 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
219 * @brief Initialization and Configuration functions
220 *
221 @verbatim
222 ===============================================================================
223 ##### Initialization and de-initialization functions #####
224 ===============================================================================
225 [..] This subsection provides a set of functions allowing to initialize and
226 de-initialize the I2Sx peripheral in simplex mode:
227
228 (+) User must Implement HAL_I2S_MspInit() function in which he configures
229 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
230
231 (+) Call the function HAL_I2S_Init() to configure the selected device with
232 the selected configuration:
233 (++) Mode
234 (++) Standard
235 (++) Data Format
236 (++) MCLK Output
237 (++) Audio frequency
238 (++) Polarity
239
240 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
241 of the selected I2Sx peripheral.
242 @endverbatim
243 * @{
244 */
245
246 /**
247 * @brief Initializes the I2S according to the specified parameters
248 * in the I2S_InitTypeDef and create the associated handle.
249 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
250 * the configuration information for I2S module
251 * @retval HAL status
252 */
253 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
254 {
255 uint32_t i2sdiv;
256 uint32_t i2sodd;
257 uint32_t packetlength;
258 uint32_t tmp;
259 uint32_t i2sclk;
260
261 /* Check the I2S handle allocation */
262 if (hi2s == NULL)
263 {
264 return HAL_ERROR;
265 }
266
267 /* Check the I2S parameters */
268 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
269 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
270 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
271 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
272 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
273 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
274 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
275 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
276
277 if (hi2s->State == HAL_I2S_STATE_RESET)
278 {
279 /* Allocate lock resource and initialize it */
280 hi2s->Lock = HAL_UNLOCKED;
281
282 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
283 /* Init the I2S Callback settings */
284 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
285 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
286 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
287 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
288 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
289
290 if (hi2s->MspInitCallback == NULL)
291 {
292 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
293 }
294
295 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
296 hi2s->MspInitCallback(hi2s);
297 #else
298 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
299 HAL_I2S_MspInit(hi2s);
300 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
301 }
302
303 hi2s->State = HAL_I2S_STATE_BUSY;
304
305 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
306 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
307 CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
308 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
309 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
310 hi2s->Instance->I2SPR = 0x0002U;
311
312 /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
313 /* If the requested audio frequency is not the default, compute the prescaler */
314 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
315 {
316 /* Check the frame length (For the Prescaler computing) ********************/
317 if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
318 {
319 /* Packet length is 16 bits */
320 packetlength = 16U;
321 }
322 else
323 {
324 /* Packet length is 32 bits */
325 packetlength = 32U;
326 }
327
328 /* I2S standard */
329 if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
330 {
331 /* In I2S standard packet lenght is multiplied by 2 */
332 packetlength = packetlength * 2U;
333 }
334
335 /* If an external I2S clock has to be used, the specific define should be set
336 in the project configuration or in the stm32f3xx_conf.h file */
337 if (hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
338 {
339 /* Set the I2S clock to the external clock value */
340 i2sclk = EXTERNAL_CLOCK_VALUE;
341 }
342 else
343 {
344 /* Get the I2S source clock value */
345 i2sclk = I2S_GetClockFreq(hi2s);
346 }
347
348 /* Compute the Real divider depending on the MCLK output state, with a floating point */
349 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
350 {
351 /* MCLK output is enabled */
352 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
353 {
354 tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
355 }
356 else
357 {
358 tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
359 }
360 }
361 else
362 {
363 /* MCLK output is disabled */
364 tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
365 }
366
367 /* Remove the flatting point */
368 tmp = tmp / 10U;
369
370 /* Check the parity of the divider */
371 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
372
373 /* Compute the i2sdiv prescaler */
374 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
375
376 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
377 i2sodd = (uint32_t)(i2sodd << 8U);
378 }
379 else
380 {
381 /* Set the default values */
382 i2sdiv = 2U;
383 i2sodd = 0U;
384 }
385
386 /* Test if the divider is 1 or 0 or greater than 0xFF */
387 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
388 {
389 /* Set the error code and execute error callback*/
390 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
391 return HAL_ERROR;
392 }
393
394 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
395
396 /* Write to SPIx I2SPR register the computed value */
397 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
398
399 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
400 /* And configure the I2S with the I2S_InitStruct values */
401 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
402 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
403 SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
404 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
405 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
406 hi2s->Init.Standard | hi2s->Init.DataFormat | \
407 hi2s->Init.CPOL));
408
409 #if defined(SPI_I2SCFGR_ASTRTEN)
410 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
411 {
412 /* Write to SPIx I2SCFGR */
413 SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
414 }
415 #endif
416
417 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
418 hi2s->State = HAL_I2S_STATE_READY;
419
420 return HAL_OK;
421 }
422
423 /**
424 * @brief DeInitializes the I2S peripheral
425 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
426 * the configuration information for I2S module
427 * @retval HAL status
428 */
429 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
430 {
431 /* Check the I2S handle allocation */
432 if (hi2s == NULL)
433 {
434 return HAL_ERROR;
435 }
436
437 /* Check the parameters */
438 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
439
440 hi2s->State = HAL_I2S_STATE_BUSY;
441
442 /* Disable the I2S Peripheral Clock */
443 __HAL_I2S_DISABLE(hi2s);
444
445 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
446 if (hi2s->MspDeInitCallback == NULL)
447 {
448 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
449 }
450
451 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
452 hi2s->MspDeInitCallback(hi2s);
453 #else
454 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
455 HAL_I2S_MspDeInit(hi2s);
456 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
457
458 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
459 hi2s->State = HAL_I2S_STATE_RESET;
460
461 /* Release Lock */
462 __HAL_UNLOCK(hi2s);
463
464 return HAL_OK;
465 }
466
467 /**
468 * @brief I2S MSP Init
469 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
470 * the configuration information for I2S module
471 * @retval None
472 */
473 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
474 {
475 /* Prevent unused argument(s) compilation warning */
476 UNUSED(hi2s);
477
478 /* NOTE : This function Should not be modified, when the callback is needed,
479 the HAL_I2S_MspInit could be implemented in the user file
480 */
481 }
482
483 /**
484 * @brief I2S MSP DeInit
485 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
486 * the configuration information for I2S module
487 * @retval None
488 */
489 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
490 {
491 /* Prevent unused argument(s) compilation warning */
492 UNUSED(hi2s);
493
494 /* NOTE : This function Should not be modified, when the callback is needed,
495 the HAL_I2S_MspDeInit could be implemented in the user file
496 */
497 }
498
499 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
500 /**
501 * @brief Register a User I2S Callback
502 * To be used instead of the weak predefined callback
503 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
504 * the configuration information for the specified I2S.
505 * @param CallbackID ID of the callback to be registered
506 * @param pCallback pointer to the Callback function
507 * @retval HAL status
508 */
509 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
510 {
511 HAL_StatusTypeDef status = HAL_OK;
512
513 if (pCallback == NULL)
514 {
515 /* Update the error code */
516 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
517
518 return HAL_ERROR;
519 }
520 /* Process locked */
521 __HAL_LOCK(hi2s);
522
523 if (HAL_I2S_STATE_READY == hi2s->State)
524 {
525 switch (CallbackID)
526 {
527 case HAL_I2S_TX_COMPLETE_CB_ID :
528 hi2s->TxCpltCallback = pCallback;
529 break;
530
531 case HAL_I2S_RX_COMPLETE_CB_ID :
532 hi2s->RxCpltCallback = pCallback;
533 break;
534
535 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
536 hi2s->TxHalfCpltCallback = pCallback;
537 break;
538
539 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
540 hi2s->RxHalfCpltCallback = pCallback;
541 break;
542
543 case HAL_I2S_ERROR_CB_ID :
544 hi2s->ErrorCallback = pCallback;
545 break;
546
547 case HAL_I2S_MSPINIT_CB_ID :
548 hi2s->MspInitCallback = pCallback;
549 break;
550
551 case HAL_I2S_MSPDEINIT_CB_ID :
552 hi2s->MspDeInitCallback = pCallback;
553 break;
554
555 default :
556 /* Update the error code */
557 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
558
559 /* Return error status */
560 status = HAL_ERROR;
561 break;
562 }
563 }
564 else if (HAL_I2S_STATE_RESET == hi2s->State)
565 {
566 switch (CallbackID)
567 {
568 case HAL_I2S_MSPINIT_CB_ID :
569 hi2s->MspInitCallback = pCallback;
570 break;
571
572 case HAL_I2S_MSPDEINIT_CB_ID :
573 hi2s->MspDeInitCallback = pCallback;
574 break;
575
576 default :
577 /* Update the error code */
578 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
579
580 /* Return error status */
581 status = HAL_ERROR;
582 break;
583 }
584 }
585 else
586 {
587 /* Update the error code */
588 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
589
590 /* Return error status */
591 status = HAL_ERROR;
592 }
593
594 /* Release Lock */
595 __HAL_UNLOCK(hi2s);
596 return status;
597 }
598
599 /**
600 * @brief Unregister an I2S Callback
601 * I2S callback is redirected to the weak predefined callback
602 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
603 * the configuration information for the specified I2S.
604 * @param CallbackID ID of the callback to be unregistered
605 * @retval HAL status
606 */
607 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
608 {
609 HAL_StatusTypeDef status = HAL_OK;
610
611 /* Process locked */
612 __HAL_LOCK(hi2s);
613
614 if (HAL_I2S_STATE_READY == hi2s->State)
615 {
616 switch (CallbackID)
617 {
618 case HAL_I2S_TX_COMPLETE_CB_ID :
619 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
620 break;
621
622 case HAL_I2S_RX_COMPLETE_CB_ID :
623 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
624 break;
625
626 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
627 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
628 break;
629
630 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
631 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
632 break;
633
634 case HAL_I2S_ERROR_CB_ID :
635 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
636 break;
637
638 case HAL_I2S_MSPINIT_CB_ID :
639 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
640 break;
641
642 case HAL_I2S_MSPDEINIT_CB_ID :
643 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
644 break;
645
646 default :
647 /* Update the error code */
648 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
649
650 /* Return error status */
651 status = HAL_ERROR;
652 break;
653 }
654 }
655 else if (HAL_I2S_STATE_RESET == hi2s->State)
656 {
657 switch (CallbackID)
658 {
659 case HAL_I2S_MSPINIT_CB_ID :
660 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
661 break;
662
663 case HAL_I2S_MSPDEINIT_CB_ID :
664 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
665 break;
666
667 default :
668 /* Update the error code */
669 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
670
671 /* Return error status */
672 status = HAL_ERROR;
673 break;
674 }
675 }
676 else
677 {
678 /* Update the error code */
679 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
680
681 /* Return error status */
682 status = HAL_ERROR;
683 }
684
685 /* Release Lock */
686 __HAL_UNLOCK(hi2s);
687 return status;
688 }
689 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
690 /**
691 * @}
692 */
693
694 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
695 * @brief Data transfers functions
696 *
697 @verbatim
698 ===============================================================================
699 ##### IO operation functions #####
700 ===============================================================================
701 [..]
702 This subsection provides a set of functions allowing to manage the I2S data
703 transfers.
704
705 (#) There are two modes of transfer:
706 (++) Blocking mode : The communication is performed in the polling mode.
707 The status of all data processing is returned by the same function
708 after finishing transfer.
709 (++) No-Blocking mode : The communication is performed using Interrupts
710 or DMA. These functions return the status of the transfer startup.
711 The end of the data processing will be indicated through the
712 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
713 using DMA mode.
714
715 (#) Blocking mode functions are :
716 (++) HAL_I2S_Transmit()
717 (++) HAL_I2S_Receive()
718
719 (#) No-Blocking mode functions with Interrupt are :
720 (++) HAL_I2S_Transmit_IT()
721 (++) HAL_I2S_Receive_IT()
722
723 (#) No-Blocking mode functions with DMA are :
724 (++) HAL_I2S_Transmit_DMA()
725 (++) HAL_I2S_Receive_DMA()
726
727 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
728 (++) HAL_I2S_TxCpltCallback()
729 (++) HAL_I2S_RxCpltCallback()
730 (++) HAL_I2S_ErrorCallback()
731
732 @endverbatim
733 * @{
734 */
735
736 /**
737 * @brief Transmit an amount of data in blocking mode
738 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
739 * the configuration information for I2S module
740 * @param pData a 16-bit pointer to data buffer.
741 * @param Size number of data sample to be sent:
742 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
743 * configuration phase, the Size parameter means the number of 16-bit data length
744 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
745 * the Size parameter means the number of 16-bit data length.
746 * @param Timeout Timeout duration
747 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
748 * between Master and Slave(example: audio streaming).
749 * @retval HAL status
750 */
751 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
752 {
753 uint32_t tmpreg_cfgr;
754
755 if ((pData == NULL) || (Size == 0U))
756 {
757 return HAL_ERROR;
758 }
759
760 /* Process Locked */
761 __HAL_LOCK(hi2s);
762
763 if (hi2s->State != HAL_I2S_STATE_READY)
764 {
765 __HAL_UNLOCK(hi2s);
766 return HAL_BUSY;
767 }
768
769 /* Set state and reset error code */
770 hi2s->State = HAL_I2S_STATE_BUSY_TX;
771 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
772 hi2s->pTxBuffPtr = pData;
773
774 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
775
776 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
777 {
778 hi2s->TxXferSize = (Size << 1U);
779 hi2s->TxXferCount = (Size << 1U);
780 }
781 else
782 {
783 hi2s->TxXferSize = Size;
784 hi2s->TxXferCount = Size;
785 }
786
787 tmpreg_cfgr = hi2s->Instance->I2SCFGR;
788
789 /* Check if the I2S is already enabled */
790 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
791 {
792 /* Enable I2S peripheral */
793 __HAL_I2S_ENABLE(hi2s);
794 }
795
796 /* Wait until TXE flag is set */
797 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
798 {
799 /* Set the error code */
800 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
801 hi2s->State = HAL_I2S_STATE_READY;
802 __HAL_UNLOCK(hi2s);
803 return HAL_ERROR;
804 }
805
806 while (hi2s->TxXferCount > 0U)
807 {
808 hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
809 hi2s->pTxBuffPtr++;
810 hi2s->TxXferCount--;
811
812 /* Wait until TXE flag is set */
813 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
814 {
815 /* Set the error code */
816 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
817 hi2s->State = HAL_I2S_STATE_READY;
818 __HAL_UNLOCK(hi2s);
819 return HAL_ERROR;
820 }
821
822 /* Check if an underrun occurs */
823 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
824 {
825 /* Clear underrun flag */
826 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
827
828 /* Set the error code */
829 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
830 }
831 }
832
833 /* Check if Slave mode is selected */
834 if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
835 {
836 /* Wait until Busy flag is reset */
837 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
838 {
839 /* Set the error code */
840 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
841 hi2s->State = HAL_I2S_STATE_READY;
842 __HAL_UNLOCK(hi2s);
843 return HAL_ERROR;
844 }
845 }
846
847 hi2s->State = HAL_I2S_STATE_READY;
848 __HAL_UNLOCK(hi2s);
849 return HAL_OK;
850 }
851
852 /**
853 * @brief Receive an amount of data in blocking mode
854 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
855 * the configuration information for I2S module
856 * @param pData a 16-bit pointer to data buffer.
857 * @param Size number of data sample to be sent:
858 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
859 * configuration phase, the Size parameter means the number of 16-bit data length
860 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
861 * the Size parameter means the number of 16-bit data length.
862 * @param Timeout Timeout duration
863 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
864 * between Master and Slave(example: audio streaming).
865 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
866 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
867 * @retval HAL status
868 */
869 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
870 {
871 uint32_t tmpreg_cfgr;
872
873 if ((pData == NULL) || (Size == 0U))
874 {
875 return HAL_ERROR;
876 }
877
878 /* Process Locked */
879 __HAL_LOCK(hi2s);
880
881 if (hi2s->State != HAL_I2S_STATE_READY)
882 {
883 __HAL_UNLOCK(hi2s);
884 return HAL_BUSY;
885 }
886
887 /* Set state and reset error code */
888 hi2s->State = HAL_I2S_STATE_BUSY_RX;
889 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
890 hi2s->pRxBuffPtr = pData;
891
892 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
893
894 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
895 {
896 hi2s->RxXferSize = (Size << 1U);
897 hi2s->RxXferCount = (Size << 1U);
898 }
899 else
900 {
901 hi2s->RxXferSize = Size;
902 hi2s->RxXferCount = Size;
903 }
904
905 /* Check if the I2S is already enabled */
906 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
907 {
908 /* Enable I2S peripheral */
909 __HAL_I2S_ENABLE(hi2s);
910 }
911
912 /* Check if Master Receiver mode is selected */
913 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
914 {
915 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
916 access to the SPI_SR register. */
917 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
918 }
919
920 /* Receive data */
921 while (hi2s->RxXferCount > 0U)
922 {
923 /* Wait until RXNE flag is set */
924 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
925 {
926 /* Set the error code */
927 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
928 hi2s->State = HAL_I2S_STATE_READY;
929 __HAL_UNLOCK(hi2s);
930 return HAL_ERROR;
931 }
932
933 (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
934 hi2s->pRxBuffPtr++;
935 hi2s->RxXferCount--;
936
937 /* Check if an overrun occurs */
938 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
939 {
940 /* Clear overrun flag */
941 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
942
943 /* Set the error code */
944 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
945 }
946 }
947
948 hi2s->State = HAL_I2S_STATE_READY;
949 __HAL_UNLOCK(hi2s);
950 return HAL_OK;
951 }
952
953 /**
954 * @brief Transmit an amount of data in non-blocking mode with Interrupt
955 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
956 * the configuration information for I2S module
957 * @param pData a 16-bit pointer to data buffer.
958 * @param Size number of data sample to be sent:
959 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
960 * configuration phase, the Size parameter means the number of 16-bit data length
961 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
962 * the Size parameter means the number of 16-bit data length.
963 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
964 * between Master and Slave(example: audio streaming).
965 * @retval HAL status
966 */
967 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
968 {
969 uint32_t tmpreg_cfgr;
970
971 if ((pData == NULL) || (Size == 0U))
972 {
973 return HAL_ERROR;
974 }
975
976 /* Process Locked */
977 __HAL_LOCK(hi2s);
978
979 if (hi2s->State != HAL_I2S_STATE_READY)
980 {
981 __HAL_UNLOCK(hi2s);
982 return HAL_BUSY;
983 }
984
985 /* Set state and reset error code */
986 hi2s->State = HAL_I2S_STATE_BUSY_TX;
987 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
988 hi2s->pTxBuffPtr = pData;
989
990 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
991
992 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
993 {
994 hi2s->TxXferSize = (Size << 1U);
995 hi2s->TxXferCount = (Size << 1U);
996 }
997 else
998 {
999 hi2s->TxXferSize = Size;
1000 hi2s->TxXferCount = Size;
1001 }
1002
1003 /* Enable TXE and ERR interrupt */
1004 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1005
1006 /* Check if the I2S is already enabled */
1007 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
1008 {
1009 /* Enable I2S peripheral */
1010 __HAL_I2S_ENABLE(hi2s);
1011 }
1012
1013 __HAL_UNLOCK(hi2s);
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Receive an amount of data in non-blocking mode with Interrupt
1019 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1020 * the configuration information for I2S module
1021 * @param pData a 16-bit pointer to the Receive data buffer.
1022 * @param Size number of data sample to be sent:
1023 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1024 * configuration phase, the Size parameter means the number of 16-bit data length
1025 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1026 * the Size parameter means the number of 16-bit data length.
1027 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1028 * between Master and Slave(example: audio streaming).
1029 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1030 * between Master and Slave otherwise the I2S interrupt should be optimized.
1031 * @retval HAL status
1032 */
1033 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1034 {
1035 uint32_t tmpreg_cfgr;
1036
1037 if ((pData == NULL) || (Size == 0U))
1038 {
1039 return HAL_ERROR;
1040 }
1041
1042 /* Process Locked */
1043 __HAL_LOCK(hi2s);
1044
1045 if (hi2s->State != HAL_I2S_STATE_READY)
1046 {
1047 __HAL_UNLOCK(hi2s);
1048 return HAL_BUSY;
1049 }
1050
1051 /* Set state and reset error code */
1052 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1053 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1054 hi2s->pRxBuffPtr = pData;
1055
1056 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1057
1058 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1059 {
1060 hi2s->RxXferSize = (Size << 1U);
1061 hi2s->RxXferCount = (Size << 1U);
1062 }
1063 else
1064 {
1065 hi2s->RxXferSize = Size;
1066 hi2s->RxXferCount = Size;
1067 }
1068
1069 /* Enable RXNE and ERR interrupt */
1070 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1071
1072 /* Check if the I2S is already enabled */
1073 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
1074 {
1075 /* Enable I2S peripheral */
1076 __HAL_I2S_ENABLE(hi2s);
1077 }
1078
1079 __HAL_UNLOCK(hi2s);
1080 return HAL_OK;
1081 }
1082
1083 /**
1084 * @brief Transmit an amount of data in non-blocking mode with DMA
1085 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1086 * the configuration information for I2S module
1087 * @param pData a 16-bit pointer to the Transmit data buffer.
1088 * @param Size number of data sample to be sent:
1089 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1090 * configuration phase, the Size parameter means the number of 16-bit data length
1091 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1092 * the Size parameter means the number of 16-bit data length.
1093 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1094 * between Master and Slave(example: audio streaming).
1095 * @retval HAL status
1096 */
1097 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1098 {
1099 uint32_t tmpreg_cfgr;
1100
1101 if ((pData == NULL) || (Size == 0U))
1102 {
1103 return HAL_ERROR;
1104 }
1105
1106 /* Process Locked */
1107 __HAL_LOCK(hi2s);
1108
1109 if (hi2s->State != HAL_I2S_STATE_READY)
1110 {
1111 __HAL_UNLOCK(hi2s);
1112 return HAL_BUSY;
1113 }
1114
1115 /* Set state and reset error code */
1116 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1117 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1118 hi2s->pTxBuffPtr = pData;
1119
1120 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1121
1122 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1123 {
1124 hi2s->TxXferSize = (Size << 1U);
1125 hi2s->TxXferCount = (Size << 1U);
1126 }
1127 else
1128 {
1129 hi2s->TxXferSize = Size;
1130 hi2s->TxXferCount = Size;
1131 }
1132
1133 /* Set the I2S Tx DMA Half transfer complete callback */
1134 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1135
1136 /* Set the I2S Tx DMA transfer complete callback */
1137 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1138
1139 /* Set the DMA error callback */
1140 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1141
1142 /* Enable the Tx DMA Stream/Channel */
1143 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
1144 {
1145 /* Update SPI error code */
1146 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1147 hi2s->State = HAL_I2S_STATE_READY;
1148
1149 __HAL_UNLOCK(hi2s);
1150 return HAL_ERROR;
1151 }
1152
1153 /* Check if the I2S is already enabled */
1154 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1155 {
1156 /* Enable I2S peripheral */
1157 __HAL_I2S_ENABLE(hi2s);
1158 }
1159
1160 /* Check if the I2S Tx request is already enabled */
1161 if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
1162 {
1163 /* Enable Tx DMA Request */
1164 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1165 }
1166
1167 __HAL_UNLOCK(hi2s);
1168 return HAL_OK;
1169 }
1170
1171 /**
1172 * @brief Receive an amount of data in non-blocking mode with DMA
1173 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1174 * the configuration information for I2S module
1175 * @param pData a 16-bit pointer to the Receive data buffer.
1176 * @param Size number of data sample to be sent:
1177 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1178 * configuration phase, the Size parameter means the number of 16-bit data length
1179 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1180 * the Size parameter means the number of 16-bit data length.
1181 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1182 * between Master and Slave(example: audio streaming).
1183 * @retval HAL status
1184 */
1185 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1186 {
1187 uint32_t tmpreg_cfgr;
1188
1189 if ((pData == NULL) || (Size == 0U))
1190 {
1191 return HAL_ERROR;
1192 }
1193
1194 /* Process Locked */
1195 __HAL_LOCK(hi2s);
1196
1197 if (hi2s->State != HAL_I2S_STATE_READY)
1198 {
1199 __HAL_UNLOCK(hi2s);
1200 return HAL_BUSY;
1201 }
1202
1203 /* Set state and reset error code */
1204 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1205 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1206 hi2s->pRxBuffPtr = pData;
1207
1208 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1209
1210 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1211 {
1212 hi2s->RxXferSize = (Size << 1U);
1213 hi2s->RxXferCount = (Size << 1U);
1214 }
1215 else
1216 {
1217 hi2s->RxXferSize = Size;
1218 hi2s->RxXferCount = Size;
1219 }
1220
1221 /* Set the I2S Rx DMA Half transfer complete callback */
1222 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1223
1224 /* Set the I2S Rx DMA transfer complete callback */
1225 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1226
1227 /* Set the DMA error callback */
1228 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1229
1230 /* Check if Master Receiver mode is selected */
1231 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
1232 {
1233 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
1234 access to the SPI_SR register. */
1235 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1236 }
1237
1238 /* Enable the Rx DMA Stream/Channel */
1239 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
1240 {
1241 /* Update SPI error code */
1242 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1243 hi2s->State = HAL_I2S_STATE_READY;
1244
1245 __HAL_UNLOCK(hi2s);
1246 return HAL_ERROR;
1247 }
1248
1249 /* Check if the I2S is already enabled */
1250 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1251 {
1252 /* Enable I2S peripheral */
1253 __HAL_I2S_ENABLE(hi2s);
1254 }
1255
1256 /* Check if the I2S Rx request is already enabled */
1257 if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
1258 {
1259 /* Enable Rx DMA Request */
1260 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1261 }
1262
1263 __HAL_UNLOCK(hi2s);
1264 return HAL_OK;
1265 }
1266
1267 /**
1268 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1269 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1270 * the configuration information for I2S module
1271 * @retval HAL status
1272 */
1273 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1274 {
1275 /* Process Locked */
1276 __HAL_LOCK(hi2s);
1277
1278 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
1279 {
1280 /* Disable the I2S DMA Tx request */
1281 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1282 }
1283 else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
1284 {
1285 /* Disable the I2S DMA Rx request */
1286 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1287 }
1288 else
1289 {
1290 /* nothing to do */
1291 }
1292
1293 /* Process Unlocked */
1294 __HAL_UNLOCK(hi2s);
1295
1296 return HAL_OK;
1297 }
1298
1299 /**
1300 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1301 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1302 * the configuration information for I2S module
1303 * @retval HAL status
1304 */
1305 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1306 {
1307 /* Process Locked */
1308 __HAL_LOCK(hi2s);
1309
1310 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
1311 {
1312 /* Enable the I2S DMA Tx request */
1313 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1314 }
1315 else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
1316 {
1317 /* Enable the I2S DMA Rx request */
1318 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1319 }
1320 else
1321 {
1322 /* nothing to do */
1323 }
1324
1325 /* If the I2S peripheral is still not enabled, enable it */
1326 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1327 {
1328 /* Enable I2S peripheral */
1329 __HAL_I2S_ENABLE(hi2s);
1330 }
1331
1332 /* Process Unlocked */
1333 __HAL_UNLOCK(hi2s);
1334
1335 return HAL_OK;
1336 }
1337
1338 /**
1339 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1340 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1341 * the configuration information for I2S module
1342 * @retval HAL status
1343 */
1344 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1345 {
1346 HAL_StatusTypeDef errorcode = HAL_OK;
1347 /* The Lock is not implemented on this API to allow the user application
1348 to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1349 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1350 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1351 */
1352
1353 /* Disable the I2S Tx/Rx DMA requests */
1354 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1355 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1356
1357 /* Abort the I2S DMA tx Stream/Channel */
1358 if (hi2s->hdmatx != NULL)
1359 {
1360 /* Disable the I2S DMA tx Stream/Channel */
1361 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1362 {
1363 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1364 errorcode = HAL_ERROR;
1365 }
1366 }
1367
1368 /* Abort the I2S DMA rx Stream/Channel */
1369 if (hi2s->hdmarx != NULL)
1370 {
1371 /* Disable the I2S DMA rx Stream/Channel */
1372 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1373 {
1374 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1375 errorcode = HAL_ERROR;
1376 }
1377 }
1378
1379 /* Disable I2S peripheral */
1380 __HAL_I2S_DISABLE(hi2s);
1381
1382 hi2s->State = HAL_I2S_STATE_READY;
1383
1384 return errorcode;
1385 }
1386
1387 /**
1388 * @brief This function handles I2S interrupt request.
1389 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1390 * the configuration information for I2S module
1391 * @retval None
1392 */
1393 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1394 {
1395 uint32_t itsource = hi2s->Instance->CR2;
1396 uint32_t itflag = hi2s->Instance->SR;
1397
1398 /* I2S in mode Receiver ------------------------------------------------*/
1399 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
1400 (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
1401 {
1402 I2S_Receive_IT(hi2s);
1403 return;
1404 }
1405
1406 /* I2S in mode Tramitter -----------------------------------------------*/
1407 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
1408 {
1409 I2S_Transmit_IT(hi2s);
1410 return;
1411 }
1412
1413 /* I2S interrupt error -------------------------------------------------*/
1414 if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
1415 {
1416 /* I2S Overrun error interrupt occurred ---------------------------------*/
1417 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
1418 {
1419 /* Disable RXNE and ERR interrupt */
1420 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1421
1422 /* Set the error code and execute error callback*/
1423 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1424 }
1425
1426 /* I2S Underrun error interrupt occurred --------------------------------*/
1427 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
1428 {
1429 /* Disable TXE and ERR interrupt */
1430 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1431
1432 /* Set the error code and execute error callback*/
1433 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1434 }
1435
1436 /* Set the I2S State ready */
1437 hi2s->State = HAL_I2S_STATE_READY;
1438
1439 /* Call user error callback */
1440 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1441 hi2s->ErrorCallback(hi2s);
1442 #else
1443 HAL_I2S_ErrorCallback(hi2s);
1444 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1445 }
1446 }
1447
1448 /**
1449 * @brief Tx Transfer Half completed callbacks
1450 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1451 * the configuration information for I2S module
1452 * @retval None
1453 */
1454 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1455 {
1456 /* Prevent unused argument(s) compilation warning */
1457 UNUSED(hi2s);
1458
1459 /* NOTE : This function Should not be modified, when the callback is needed,
1460 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1461 */
1462 }
1463
1464 /**
1465 * @brief Tx Transfer completed callbacks
1466 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1467 * the configuration information for I2S module
1468 * @retval None
1469 */
1470 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1471 {
1472 /* Prevent unused argument(s) compilation warning */
1473 UNUSED(hi2s);
1474
1475 /* NOTE : This function Should not be modified, when the callback is needed,
1476 the HAL_I2S_TxCpltCallback could be implemented in the user file
1477 */
1478 }
1479
1480 /**
1481 * @brief Rx Transfer half completed callbacks
1482 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1483 * the configuration information for I2S module
1484 * @retval None
1485 */
1486 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1487 {
1488 /* Prevent unused argument(s) compilation warning */
1489 UNUSED(hi2s);
1490
1491 /* NOTE : This function Should not be modified, when the callback is needed,
1492 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
1493 */
1494 }
1495
1496 /**
1497 * @brief Rx Transfer completed callbacks
1498 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1499 * the configuration information for I2S module
1500 * @retval None
1501 */
1502 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1503 {
1504 /* Prevent unused argument(s) compilation warning */
1505 UNUSED(hi2s);
1506
1507 /* NOTE : This function Should not be modified, when the callback is needed,
1508 the HAL_I2S_RxCpltCallback could be implemented in the user file
1509 */
1510 }
1511
1512 /**
1513 * @brief I2S error callbacks
1514 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1515 * the configuration information for I2S module
1516 * @retval None
1517 */
1518 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1519 {
1520 /* Prevent unused argument(s) compilation warning */
1521 UNUSED(hi2s);
1522
1523 /* NOTE : This function Should not be modified, when the callback is needed,
1524 the HAL_I2S_ErrorCallback could be implemented in the user file
1525 */
1526 }
1527
1528 /**
1529 * @}
1530 */
1531
1532 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
1533 * @brief Peripheral State functions
1534 *
1535 @verbatim
1536 ===============================================================================
1537 ##### Peripheral State and Errors functions #####
1538 ===============================================================================
1539 [..]
1540 This subsection permits to get in run-time the status of the peripheral
1541 and the data flow.
1542
1543 @endverbatim
1544 * @{
1545 */
1546
1547 /**
1548 * @brief Return the I2S state
1549 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1550 * the configuration information for I2S module
1551 * @retval HAL state
1552 */
1553 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1554 {
1555 return hi2s->State;
1556 }
1557
1558 /**
1559 * @brief Return the I2S error code
1560 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1561 * the configuration information for I2S module
1562 * @retval I2S Error Code
1563 */
1564 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1565 {
1566 return hi2s->ErrorCode;
1567 }
1568 /**
1569 * @}
1570 */
1571
1572 /**
1573 * @}
1574 */
1575
1576 /** @addtogroup I2S_Private_Functions I2S Private Functions
1577 * @{
1578 */
1579 /**
1580 * @brief Get I2S Input Clock based on I2S source clock selection
1581 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
1582 * the configuration information for I2S module.
1583 * @retval I2S Clock Input
1584 */
1585 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
1586 {
1587 uint32_t tmpreg;
1588 /* This variable used to store the VCO Input (value in Hz) */
1589 uint32_t vcoinput;
1590 /* This variable used to store the I2S_CK_x (value in Hz) */
1591 uint32_t i2sclocksource;
1592
1593 /* Configure I2S Clock based on I2S source clock selection */
1594
1595 /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
1596 switch (hi2s->Init.ClockSource)
1597 {
1598 case I2S_CLOCK_PLL :
1599 {
1600 /* Configure the PLLI2S division factor */
1601 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
1602 if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1603 {
1604 /* In Case the PLL Source is HSI (Internal Clock) */
1605 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
1606 }
1607 else
1608 {
1609 /* In Case the PLL Source is HSE (External Clock) */
1610 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
1611 }
1612
1613 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
1614 /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
1615 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
1616 i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
1617
1618 break;
1619 }
1620 case I2S_CLOCK_EXTERNAL :
1621 {
1622 i2sclocksource = EXTERNAL_CLOCK_VALUE;
1623 break;
1624 }
1625 default :
1626 {
1627 i2sclocksource = 0U;
1628 break;
1629 }
1630 }
1631
1632 /* the return result is the value of I2S clock */
1633 return i2sclocksource;
1634 }
1635
1636 /**
1637 * @brief DMA I2S transmit process complete callback
1638 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1639 * the configuration information for the specified DMA module.
1640 * @retval None
1641 */
1642 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1643 {
1644 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1645
1646 /* if DMA is configured in DMA_NORMAL Mode */
1647 if (hdma->Init.Mode == DMA_NORMAL)
1648 {
1649 /* Disable Tx DMA Request */
1650 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1651
1652 hi2s->TxXferCount = 0U;
1653 hi2s->State = HAL_I2S_STATE_READY;
1654 }
1655 /* Call user Tx complete callback */
1656 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1657 hi2s->TxCpltCallback(hi2s);
1658 #else
1659 HAL_I2S_TxCpltCallback(hi2s);
1660 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1661 }
1662
1663 /**
1664 * @brief DMA I2S transmit process half complete callback
1665 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1666 * the configuration information for the specified DMA module.
1667 * @retval None
1668 */
1669 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1670 {
1671 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1672
1673 /* Call user Tx half complete callback */
1674 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1675 hi2s->TxHalfCpltCallback(hi2s);
1676 #else
1677 HAL_I2S_TxHalfCpltCallback(hi2s);
1678 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1679 }
1680
1681 /**
1682 * @brief DMA I2S receive process complete callback
1683 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1684 * the configuration information for the specified DMA module.
1685 * @retval None
1686 */
1687 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1688 {
1689 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1690
1691 /* if DMA is configured in DMA_NORMAL Mode */
1692 if (hdma->Init.Mode == DMA_NORMAL)
1693 {
1694 /* Disable Rx DMA Request */
1695 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1696 hi2s->RxXferCount = 0U;
1697 hi2s->State = HAL_I2S_STATE_READY;
1698 }
1699 /* Call user Rx complete callback */
1700 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1701 hi2s->RxCpltCallback(hi2s);
1702 #else
1703 HAL_I2S_RxCpltCallback(hi2s);
1704 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1705 }
1706
1707 /**
1708 * @brief DMA I2S receive process half complete callback
1709 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1710 * the configuration information for the specified DMA module.
1711 * @retval None
1712 */
1713 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1714 {
1715 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1716
1717 /* Call user Rx half complete callback */
1718 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1719 hi2s->RxHalfCpltCallback(hi2s);
1720 #else
1721 HAL_I2S_RxHalfCpltCallback(hi2s);
1722 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1723 }
1724
1725 /**
1726 * @brief DMA I2S communication error callback
1727 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1728 * the configuration information for the specified DMA module.
1729 * @retval None
1730 */
1731 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
1732 {
1733 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1734
1735 /* Disable Rx and Tx DMA Request */
1736 CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
1737 hi2s->TxXferCount = 0U;
1738 hi2s->RxXferCount = 0U;
1739
1740 hi2s->State = HAL_I2S_STATE_READY;
1741
1742 /* Set the error code and execute error callback*/
1743 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1744 /* Call user error callback */
1745 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1746 hi2s->ErrorCallback(hi2s);
1747 #else
1748 HAL_I2S_ErrorCallback(hi2s);
1749 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1750 }
1751
1752 /**
1753 * @brief Transmit an amount of data in non-blocking mode with Interrupt
1754 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1755 * the configuration information for I2S module
1756 * @retval None
1757 */
1758 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
1759 {
1760 /* Transmit data */
1761 hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
1762 hi2s->pTxBuffPtr++;
1763 hi2s->TxXferCount--;
1764
1765 if (hi2s->TxXferCount == 0U)
1766 {
1767 /* Disable TXE and ERR interrupt */
1768 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1769
1770 hi2s->State = HAL_I2S_STATE_READY;
1771 /* Call user Tx complete callback */
1772 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1773 hi2s->TxCpltCallback(hi2s);
1774 #else
1775 HAL_I2S_TxCpltCallback(hi2s);
1776 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1777 }
1778 }
1779
1780 /**
1781 * @brief Receive an amount of data in non-blocking mode with Interrupt
1782 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1783 * the configuration information for I2S module
1784 * @retval None
1785 */
1786 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
1787 {
1788 /* Receive data */
1789 (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
1790 hi2s->pRxBuffPtr++;
1791 hi2s->RxXferCount--;
1792
1793 if (hi2s->RxXferCount == 0U)
1794 {
1795 /* Disable RXNE and ERR interrupt */
1796 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1797
1798 hi2s->State = HAL_I2S_STATE_READY;
1799 /* Call user Rx complete callback */
1800 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1801 hi2s->RxCpltCallback(hi2s);
1802 #else
1803 HAL_I2S_RxCpltCallback(hi2s);
1804 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1805 }
1806 }
1807
1808 /**
1809 * @brief This function handles I2S Communication Timeout.
1810 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1811 * the configuration information for I2S module
1812 * @param Flag Flag checked
1813 * @param State Value of the flag expected
1814 * @param Timeout Duration of the timeout
1815 * @retval HAL status
1816 */
1817 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
1818 {
1819 uint32_t tickstart;
1820
1821 /* Get tick */
1822 tickstart = HAL_GetTick();
1823
1824 /* Wait until flag is set to status*/
1825 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
1826 {
1827 if (Timeout != HAL_MAX_DELAY)
1828 {
1829 if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
1830 {
1831 /* Set the I2S State ready */
1832 hi2s->State = HAL_I2S_STATE_READY;
1833
1834 /* Process Unlocked */
1835 __HAL_UNLOCK(hi2s);
1836
1837 return HAL_TIMEOUT;
1838 }
1839 }
1840 }
1841 return HAL_OK;
1842 }
1843
1844 /**
1845 * @}
1846 */
1847
1848 /**
1849 * @}
1850 */
1851
1852 /**
1853 * @}
1854 */
1855
1856 #endif /* HAL_I2S_MODULE_ENABLED */
1857
1858 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/