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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_adc.c
blobbec94293ace0703959f1712db1f30779ab0123cb
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f7xx_ll_adc.h"
23 #include "stm32f7xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /** @addtogroup ADC_LL_Private_Macros
47 * @{
48 */
49
50 /* Check of parameters for configuration of ADC hierarchical scope: */
51 /* common to several ADC instances. */
52 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
53 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
54 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
55 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
56 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
57 )
58
59 /* Check of parameters for configuration of ADC hierarchical scope: */
60 /* ADC instance. */
61 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
62 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
63 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
64 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
65 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
66 )
67
68 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
69 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
70 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
71 )
72
73 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
74 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
75 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
76 )
77
78 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
79 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
80 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
81 )
82
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* ADC group regular */
85 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
86 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
87 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
88 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
89 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
90 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
91 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \
92 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
101 )
102
103 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
104 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
105 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
106 )
107
108 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
109 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
110 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
111 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
112 )
113
114 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
115 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
116 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
117 )
118
119 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
120 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
121 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
135 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
136 )
137
138 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
139 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
140 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
147 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
148 )
149
150 /* Check of parameters for configuration of ADC hierarchical scope: */
151 /* ADC group injected */
152 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
153 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
154 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
167 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
168 )
169 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
170 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
171 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
172 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
173 )
174
175 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
176 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
177 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
178 )
179
180 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
181 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
182 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
183 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
184 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
185 )
186
187 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
188 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
189 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
190 )
191
192 /* Check of parameters for configuration of ADC hierarchical scope: */
193 /* multimode. */
194 #if defined(ADC3)
195 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
196 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
197 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
198 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
199 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
200 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
201 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
203 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
204 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
205 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
206 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
207 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
208 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
209 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
210 )
211 #else
212 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
213 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
214 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
215 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
216 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
217 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
221 )
222 #endif
223
224 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
225 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
226 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
227 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
228 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
229 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
230 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
231 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
232 )
233
234 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
235 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
236 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
237 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
238 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
239 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
240 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
250 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
251 )
252
253 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
254 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
255 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
256 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
257 )
258
259 /**
260 * @}
261 */
262
263
264 /* Private function prototypes -----------------------------------------------*/
265
266 /* Exported functions --------------------------------------------------------*/
267 /** @addtogroup ADC_LL_Exported_Functions
268 * @{
269 */
270
271 /** @addtogroup ADC_LL_EF_Init
272 * @{
273 */
274
275 /**
276 * @brief De-initialize registers of all ADC instances belonging to
277 * the same ADC common instance to their default reset values.
278 * @param ADCxy_COMMON ADC common instance
279 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
280 * @retval An ErrorStatus enumeration value:
281 * - SUCCESS: ADC common registers are de-initialized
282 * - ERROR: not applicable
283 */
284 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
285 {
286 /* Check the parameters */
287 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
288
289
290 /* Force reset of ADC clock (core clock) */
291 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
292
293 /* Release reset of ADC clock (core clock) */
294 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
295
296 return SUCCESS;
297 }
298
299 /**
300 * @brief Initialize some features of ADC common parameters
301 * (all ADC instances belonging to the same ADC common instance)
302 * and multimode (for devices with several ADC instances available).
303 * @note The setting of ADC common parameters is conditioned to
304 * ADC instances state:
305 * All ADC instances belonging to the same ADC common instance
306 * must be disabled.
307 * @param ADCxy_COMMON ADC common instance
308 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
309 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
310 * @retval An ErrorStatus enumeration value:
311 * - SUCCESS: ADC common registers are initialized
312 * - ERROR: ADC common registers are not initialized
313 */
314 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
315 {
316 ErrorStatus status = SUCCESS;
317
318 /* Check the parameters */
319 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
320 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
321
322 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
323 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
324 {
325 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
326 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
327 }
328
329 /* Note: Hardware constraint (refer to description of functions */
330 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
331 /* On this STM32 serie, setting of these features is conditioned to */
332 /* ADC state: */
333 /* All ADC instances of the ADC common group must be disabled. */
334 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
335 {
336 /* Configuration of ADC hierarchical scope: */
337 /* - common to several ADC */
338 /* (all ADC instances belonging to the same ADC common instance) */
339 /* - Set ADC clock (conversion clock) */
340 /* - multimode (if several ADC instances available on the */
341 /* selected device) */
342 /* - Set ADC multimode configuration */
343 /* - Set ADC multimode DMA transfer */
344 /* - Set ADC multimode: delay between 2 sampling phases */
345 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
346 {
347 MODIFY_REG(ADCxy_COMMON->CCR,
348 ADC_CCR_ADCPRE
349 | ADC_CCR_MULTI
350 | ADC_CCR_DMA
351 | ADC_CCR_DDS
352 | ADC_CCR_DELAY
353 ,
354 ADC_CommonInitStruct->CommonClock
355 | ADC_CommonInitStruct->Multimode
356 | ADC_CommonInitStruct->MultiDMATransfer
357 | ADC_CommonInitStruct->MultiTwoSamplingDelay
358 );
359 }
360 else
361 {
362 MODIFY_REG(ADCxy_COMMON->CCR,
363 ADC_CCR_ADCPRE
364 | ADC_CCR_MULTI
365 | ADC_CCR_DMA
366 | ADC_CCR_DDS
367 | ADC_CCR_DELAY
368 ,
369 ADC_CommonInitStruct->CommonClock
370 | LL_ADC_MULTI_INDEPENDENT
371 );
372 }
373 }
374 else
375 {
376 /* Initialization error: One or several ADC instances belonging to */
377 /* the same ADC common instance are not disabled. */
378 status = ERROR;
379 }
380
381 return status;
382 }
383
384 /**
385 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
386 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
387 * whose fields will be set to default values.
388 * @retval None
389 */
390 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
391 {
392 /* Set ADC_CommonInitStruct fields to default values */
393 /* Set fields of ADC common */
394 /* (all ADC instances belonging to the same ADC common instance) */
395 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
396
397 /* Set fields of ADC multimode */
398 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
399 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
400 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
401 }
402
403 /**
404 * @brief De-initialize registers of the selected ADC instance
405 * to their default reset values.
406 * @note To reset all ADC instances quickly (perform a hard reset),
407 * use function @ref LL_ADC_CommonDeInit().
408 * @param ADCx ADC instance
409 * @retval An ErrorStatus enumeration value:
410 * - SUCCESS: ADC registers are de-initialized
411 * - ERROR: ADC registers are not de-initialized
412 */
413 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
414 {
415 ErrorStatus status = SUCCESS;
416
417 /* Check the parameters */
418 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
419
420 /* Disable ADC instance if not already disabled. */
421 if(LL_ADC_IsEnabled(ADCx) == 1U)
422 {
423 /* Set ADC group regular trigger source to SW start to ensure to not */
424 /* have an external trigger event occurring during the conversion stop */
425 /* ADC disable process. */
426 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
427
428 /* Set ADC group injected trigger source to SW start to ensure to not */
429 /* have an external trigger event occurring during the conversion stop */
430 /* ADC disable process. */
431 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
432
433 /* Disable the ADC instance */
434 LL_ADC_Disable(ADCx);
435 }
436
437 /* Check whether ADC state is compliant with expected state */
438 /* (hardware requirements of bits state to reset registers below) */
439 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
440 {
441 /* ========== Reset ADC registers ========== */
442 /* Reset register SR */
443 CLEAR_BIT(ADCx->SR,
444 ( LL_ADC_FLAG_STRT
445 | LL_ADC_FLAG_JSTRT
446 | LL_ADC_FLAG_EOCS
447 | LL_ADC_FLAG_OVR
448 | LL_ADC_FLAG_JEOS
449 | LL_ADC_FLAG_AWD1 )
450 );
451
452 /* Reset register CR1 */
453 CLEAR_BIT(ADCx->CR1,
454 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
455 | ADC_CR1_JAWDEN
456 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
457 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
458 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
459 | ADC_CR1_AWDCH )
460 );
461
462 /* Reset register CR2 */
463 CLEAR_BIT(ADCx->CR2,
464 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
465 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
466 | ADC_CR2_ALIGN | ADC_CR2_EOCS
467 | ADC_CR2_DDS | ADC_CR2_DMA
468 | ADC_CR2_CONT | ADC_CR2_ADON )
469 );
470
471 /* Reset register SMPR1 */
472 CLEAR_BIT(ADCx->SMPR1,
473 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
474 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
475 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
476 );
477
478 /* Reset register SMPR2 */
479 CLEAR_BIT(ADCx->SMPR2,
480 ( ADC_SMPR2_SMP9
481 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
482 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
483 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
484 );
485
486 /* Reset register JOFR1 */
487 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
488 /* Reset register JOFR2 */
489 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
490 /* Reset register JOFR3 */
491 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
492 /* Reset register JOFR4 */
493 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
494
495 /* Reset register HTR */
496 SET_BIT(ADCx->HTR, ADC_HTR_HT);
497 /* Reset register LTR */
498 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
499
500 /* Reset register SQR1 */
501 CLEAR_BIT(ADCx->SQR1,
502 ( ADC_SQR1_L
503 | ADC_SQR1_SQ16
504 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
505 );
506
507 /* Reset register SQR2 */
508 CLEAR_BIT(ADCx->SQR2,
509 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
510 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
511 );
512
513
514 /* Reset register JSQR */
515 CLEAR_BIT(ADCx->JSQR,
516 ( ADC_JSQR_JL
517 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
518 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
519 );
520
521 /* Reset register DR */
522 /* bits in access mode read only, no direct reset applicable */
523
524 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
525 /* bits in access mode read only, no direct reset applicable */
526
527 /* Reset register CCR */
528 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
529 }
530
531 return status;
532 }
533
534 /**
535 * @brief Initialize some features of ADC instance.
536 * @note These parameters have an impact on ADC scope: ADC instance.
537 * Affects both group regular and group injected (availability
538 * of ADC group injected depends on STM32 families).
539 * Refer to corresponding unitary functions into
540 * @ref ADC_LL_EF_Configuration_ADC_Instance .
541 * @note The setting of these parameters by function @ref LL_ADC_Init()
542 * is conditioned to ADC state:
543 * ADC instance must be disabled.
544 * This condition is applied to all ADC features, for efficiency
545 * and compatibility over all STM32 families. However, the different
546 * features can be set under different ADC state conditions
547 * (setting possible with ADC enabled without conversion on going,
548 * ADC enabled with conversion on going, ...)
549 * Each feature can be updated afterwards with a unitary function
550 * and potentially with ADC in a different state than disabled,
551 * refer to description of each function for setting
552 * conditioned to ADC state.
553 * @note After using this function, some other features must be configured
554 * using LL unitary functions.
555 * The minimum configuration remaining to be done is:
556 * - Set ADC group regular or group injected sequencer:
557 * map channel on the selected sequencer rank.
558 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
559 * - Set ADC channel sampling time
560 * Refer to function LL_ADC_SetChannelSamplingTime();
561 * @param ADCx ADC instance
562 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
563 * @retval An ErrorStatus enumeration value:
564 * - SUCCESS: ADC registers are initialized
565 * - ERROR: ADC registers are not initialized
566 */
567 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
568 {
569 ErrorStatus status = SUCCESS;
570
571 /* Check the parameters */
572 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
573
574 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
575 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
576 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
577
578 /* Note: Hardware constraint (refer to description of this function): */
579 /* ADC instance must be disabled. */
580 if(LL_ADC_IsEnabled(ADCx) == 0U)
581 {
582 /* Configuration of ADC hierarchical scope: */
583 /* - ADC instance */
584 /* - Set ADC data resolution */
585 /* - Set ADC conversion data alignment */
586 MODIFY_REG(ADCx->CR1,
587 ADC_CR1_RES
588 | ADC_CR1_SCAN
589 ,
590 ADC_InitStruct->Resolution
591 | ADC_InitStruct->SequencersScanMode
592 );
593
594 MODIFY_REG(ADCx->CR2,
595 ADC_CR2_ALIGN
596 ,
597 ADC_InitStruct->DataAlignment
598 );
599
600 }
601 else
602 {
603 /* Initialization error: ADC instance is not disabled. */
604 status = ERROR;
605 }
606 return status;
607 }
608
609 /**
610 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
611 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
612 * whose fields will be set to default values.
613 * @retval None
614 */
615 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
616 {
617 /* Set ADC_InitStruct fields to default values */
618 /* Set fields of ADC instance */
619 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
620 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
621
622 /* Enable scan mode to have a generic behavior with ADC of other */
623 /* STM32 families, without this setting available: */
624 /* ADC group regular sequencer and ADC group injected sequencer depend */
625 /* only of their own configuration. */
626 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
627
628 }
629
630 /**
631 * @brief Initialize some features of ADC group regular.
632 * @note These parameters have an impact on ADC scope: ADC group regular.
633 * Refer to corresponding unitary functions into
634 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
635 * (functions with prefix "REG").
636 * @note The setting of these parameters by function @ref LL_ADC_Init()
637 * is conditioned to ADC state:
638 * ADC instance must be disabled.
639 * This condition is applied to all ADC features, for efficiency
640 * and compatibility over all STM32 families. However, the different
641 * features can be set under different ADC state conditions
642 * (setting possible with ADC enabled without conversion on going,
643 * ADC enabled with conversion on going, ...)
644 * Each feature can be updated afterwards with a unitary function
645 * and potentially with ADC in a different state than disabled,
646 * refer to description of each function for setting
647 * conditioned to ADC state.
648 * @note After using this function, other features must be configured
649 * using LL unitary functions.
650 * The minimum configuration remaining to be done is:
651 * - Set ADC group regular or group injected sequencer:
652 * map channel on the selected sequencer rank.
653 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
654 * - Set ADC channel sampling time
655 * Refer to function LL_ADC_SetChannelSamplingTime();
656 * @param ADCx ADC instance
657 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
658 * @retval An ErrorStatus enumeration value:
659 * - SUCCESS: ADC registers are initialized
660 * - ERROR: ADC registers are not initialized
661 */
662 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
663 {
664 ErrorStatus status = SUCCESS;
665
666 /* Check the parameters */
667 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
668 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
669 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
670 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
671 {
672 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
673 }
674 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
675 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
676
677 /* Note: Hardware constraint (refer to description of this function): */
678 /* ADC instance must be disabled. */
679 if(LL_ADC_IsEnabled(ADCx) == 0U)
680 {
681 /* Configuration of ADC hierarchical scope: */
682 /* - ADC group regular */
683 /* - Set ADC group regular trigger source */
684 /* - Set ADC group regular sequencer length */
685 /* - Set ADC group regular sequencer discontinuous mode */
686 /* - Set ADC group regular continuous mode */
687 /* - Set ADC group regular conversion data transfer: no transfer or */
688 /* transfer by DMA, and DMA requests mode */
689 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
690 /* ADC conversion. */
691 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
692 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
693 {
694 MODIFY_REG(ADCx->CR1,
695 ADC_CR1_DISCEN
696 | ADC_CR1_DISCNUM
697 ,
698 ADC_REG_InitStruct->SequencerLength
699 | ADC_REG_InitStruct->SequencerDiscont
700 );
701 }
702 else
703 {
704 MODIFY_REG(ADCx->CR1,
705 ADC_CR1_DISCEN
706 | ADC_CR1_DISCNUM
707 ,
708 ADC_REG_InitStruct->SequencerLength
709 | LL_ADC_REG_SEQ_DISCONT_DISABLE
710 );
711 }
712
713 MODIFY_REG(ADCx->CR2,
714 ADC_CR2_EXTSEL
715 | ADC_CR2_EXTEN
716 | ADC_CR2_CONT
717 | ADC_CR2_DMA
718 | ADC_CR2_DDS
719 ,
720 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
721 | ADC_REG_InitStruct->ContinuousMode
722 | ADC_REG_InitStruct->DMATransfer
723 );
724
725 /* Set ADC group regular sequencer length and scan direction */
726 /* Note: Hardware constraint (refer to description of this function): */
727 /* Note: If ADC instance feature scan mode is disabled */
728 /* (refer to ADC instance initialization structure */
729 /* parameter @ref SequencersScanMode */
730 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
731 /* this parameter is discarded. */
732 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
733 }
734 else
735 {
736 /* Initialization error: ADC instance is not disabled. */
737 status = ERROR;
738 }
739 return status;
740 }
741
742 /**
743 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
744 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
745 * whose fields will be set to default values.
746 * @retval None
747 */
748 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
749 {
750 /* Set ADC_REG_InitStruct fields to default values */
751 /* Set fields of ADC group regular */
752 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
753 /* ADC conversion. */
754 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
755 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
756 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
757 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
758 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
759 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
760 }
761
762 /**
763 * @brief Initialize some features of ADC group injected.
764 * @note These parameters have an impact on ADC scope: ADC group injected.
765 * Refer to corresponding unitary functions into
766 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
767 * (functions with prefix "INJ").
768 * @note The setting of these parameters by function @ref LL_ADC_Init()
769 * is conditioned to ADC state:
770 * ADC instance must be disabled.
771 * This condition is applied to all ADC features, for efficiency
772 * and compatibility over all STM32 families. However, the different
773 * features can be set under different ADC state conditions
774 * (setting possible with ADC enabled without conversion on going,
775 * ADC enabled with conversion on going, ...)
776 * Each feature can be updated afterwards with a unitary function
777 * and potentially with ADC in a different state than disabled,
778 * refer to description of each function for setting
779 * conditioned to ADC state.
780 * @note After using this function, other features must be configured
781 * using LL unitary functions.
782 * The minimum configuration remaining to be done is:
783 * - Set ADC group injected sequencer:
784 * map channel on the selected sequencer rank.
785 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
786 * - Set ADC channel sampling time
787 * Refer to function LL_ADC_SetChannelSamplingTime();
788 * @param ADCx ADC instance
789 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
790 * @retval An ErrorStatus enumeration value:
791 * - SUCCESS: ADC registers are initialized
792 * - ERROR: ADC registers are not initialized
793 */
794 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
795 {
796 ErrorStatus status = SUCCESS;
797
798 /* Check the parameters */
799 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
800 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
801 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
802 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
803 {
804 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
805 }
806 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
807
808 /* Note: Hardware constraint (refer to description of this function): */
809 /* ADC instance must be disabled. */
810 if(LL_ADC_IsEnabled(ADCx) == 0U)
811 {
812 /* Configuration of ADC hierarchical scope: */
813 /* - ADC group injected */
814 /* - Set ADC group injected trigger source */
815 /* - Set ADC group injected sequencer length */
816 /* - Set ADC group injected sequencer discontinuous mode */
817 /* - Set ADC group injected conversion trigger: independent or */
818 /* from ADC group regular */
819 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
820 /* ADC conversion. */
821 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
822 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
823 {
824 MODIFY_REG(ADCx->CR1,
825 ADC_CR1_JDISCEN
826 | ADC_CR1_JAUTO
827 ,
828 ADC_INJ_InitStruct->SequencerDiscont
829 | ADC_INJ_InitStruct->TrigAuto
830 );
831 }
832 else
833 {
834 MODIFY_REG(ADCx->CR1,
835 ADC_CR1_JDISCEN
836 | ADC_CR1_JAUTO
837 ,
838 LL_ADC_REG_SEQ_DISCONT_DISABLE
839 | ADC_INJ_InitStruct->TrigAuto
840 );
841 }
842
843 MODIFY_REG(ADCx->CR2,
844 ADC_CR2_JEXTSEL
845 | ADC_CR2_JEXTEN
846 ,
847 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
848 );
849
850 /* Note: Hardware constraint (refer to description of this function): */
851 /* Note: If ADC instance feature scan mode is disabled */
852 /* (refer to ADC instance initialization structure */
853 /* parameter @ref SequencersScanMode */
854 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
855 /* this parameter is discarded. */
856 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
857 }
858 else
859 {
860 /* Initialization error: ADC instance is not disabled. */
861 status = ERROR;
862 }
863 return status;
864 }
865
866 /**
867 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
868 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
869 * whose fields will be set to default values.
870 * @retval None
871 */
872 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
873 {
874 /* Set ADC_INJ_InitStruct fields to default values */
875 /* Set fields of ADC group injected */
876 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
877 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
878 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
879 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
880 }
881
882 /**
883 * @}
884 */
885
886 /**
887 * @}
888 */
889
890 /**
891 * @}
892 */
893
894 #endif /* ADC1 || ADC2 || ADC3 */
895
896 /**
897 * @}
898 */
899
900 #endif /* USE_FULL_LL_DRIVER */
901
902 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/