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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_dma.c
blob5e8c069049d7be3f025faff885c0f0648658c7f1
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f7xx_ll_dma.h"
23 #include "stm32f7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup DMA_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
49 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
50
51 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
52 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
53 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
54
55 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
56 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
57
58 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
59 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
60
61 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
62 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
63 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
64
65 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
66 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
67 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
68
69 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
70
71 #if defined(DMA_CHANNEL_SELECTION_8_15)
72 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
73 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
74 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
75 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
76 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
77 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
78 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
79 ((__VALUE__) == LL_DMA_CHANNEL_7) || \
80 ((__VALUE__) == LL_DMA_CHANNEL_8) || \
81 ((__VALUE__) == LL_DMA_CHANNEL_9) || \
82 ((__VALUE__) == LL_DMA_CHANNEL_10) || \
83 ((__VALUE__) == LL_DMA_CHANNEL_11) || \
84 ((__VALUE__) == LL_DMA_CHANNEL_12) || \
85 ((__VALUE__) == LL_DMA_CHANNEL_13) || \
86 ((__VALUE__) == LL_DMA_CHANNEL_14) || \
87 ((__VALUE__) == LL_DMA_CHANNEL_15))
88
89 #else
90 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
91 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
92 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
93 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
94 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
95 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
96 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
97 ((__VALUE__) == LL_DMA_CHANNEL_7))
98
99 #endif /* DMA_CHANNEL_SELECTION_8_15 */
100
101 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
102 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
103 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
104 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
105
106 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
107 (((STREAM) == LL_DMA_STREAM_0) || \
108 ((STREAM) == LL_DMA_STREAM_1) || \
109 ((STREAM) == LL_DMA_STREAM_2) || \
110 ((STREAM) == LL_DMA_STREAM_3) || \
111 ((STREAM) == LL_DMA_STREAM_4) || \
112 ((STREAM) == LL_DMA_STREAM_5) || \
113 ((STREAM) == LL_DMA_STREAM_6) || \
114 ((STREAM) == LL_DMA_STREAM_7) || \
115 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
116 (((INSTANCE) == DMA2) && \
117 (((STREAM) == LL_DMA_STREAM_0) || \
118 ((STREAM) == LL_DMA_STREAM_1) || \
119 ((STREAM) == LL_DMA_STREAM_2) || \
120 ((STREAM) == LL_DMA_STREAM_3) || \
121 ((STREAM) == LL_DMA_STREAM_4) || \
122 ((STREAM) == LL_DMA_STREAM_5) || \
123 ((STREAM) == LL_DMA_STREAM_6) || \
124 ((STREAM) == LL_DMA_STREAM_7) || \
125 ((STREAM) == LL_DMA_STREAM_ALL))))
126
127 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
128 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
129
130 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
131 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
132 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
133 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
134
135 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
136 ((BURST) == LL_DMA_MBURST_INC4) || \
137 ((BURST) == LL_DMA_MBURST_INC8) || \
138 ((BURST) == LL_DMA_MBURST_INC16))
139
140 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
141 ((BURST) == LL_DMA_PBURST_INC4) || \
142 ((BURST) == LL_DMA_PBURST_INC8) || \
143 ((BURST) == LL_DMA_PBURST_INC16))
144
145 /**
146 * @}
147 */
148
149 /* Private function prototypes -----------------------------------------------*/
150
151 /* Exported functions --------------------------------------------------------*/
152 /** @addtogroup DMA_LL_Exported_Functions
153 * @{
154 */
155
156 /** @addtogroup DMA_LL_EF_Init
157 * @{
158 */
159
160 /**
161 * @brief De-initialize the DMA registers to their default reset values.
162 * @param DMAx DMAx Instance
163 * @param Stream This parameter can be one of the following values:
164 * @arg @ref LL_DMA_STREAM_0
165 * @arg @ref LL_DMA_STREAM_1
166 * @arg @ref LL_DMA_STREAM_2
167 * @arg @ref LL_DMA_STREAM_3
168 * @arg @ref LL_DMA_STREAM_4
169 * @arg @ref LL_DMA_STREAM_5
170 * @arg @ref LL_DMA_STREAM_6
171 * @arg @ref LL_DMA_STREAM_7
172 * @arg @ref LL_DMA_STREAM_ALL
173 * @retval An ErrorStatus enumeration value:
174 * - SUCCESS: DMA registers are de-initialized
175 * - ERROR: DMA registers are not de-initialized
176 */
177 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
178 {
179 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
180 ErrorStatus status = SUCCESS;
181
182 /* Check the DMA Instance DMAx and Stream parameters*/
183 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
184
185 if (Stream == LL_DMA_STREAM_ALL)
186 {
187 if (DMAx == DMA1)
188 {
189 /* Force reset of DMA clock */
190 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
191
192 /* Release reset of DMA clock */
193 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
194 }
195 else if (DMAx == DMA2)
196 {
197 /* Force reset of DMA clock */
198 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
199
200 /* Release reset of DMA clock */
201 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
202 }
203 else
204 {
205 status = ERROR;
206 }
207 }
208 else
209 {
210 /* Disable the selected Stream */
211 LL_DMA_DisableStream(DMAx,Stream);
212
213 /* Get the DMA Stream Instance */
214 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
215
216 /* Reset DMAx_Streamy configuration register */
217 LL_DMA_WriteReg(tmp, CR, 0U);
218
219 /* Reset DMAx_Streamy remaining bytes register */
220 LL_DMA_WriteReg(tmp, NDTR, 0U);
221
222 /* Reset DMAx_Streamy peripheral address register */
223 LL_DMA_WriteReg(tmp, PAR, 0U);
224
225 /* Reset DMAx_Streamy memory address register */
226 LL_DMA_WriteReg(tmp, M0AR, 0U);
227
228 /* Reset DMAx_Streamy memory address register */
229 LL_DMA_WriteReg(tmp, M1AR, 0U);
230
231 /* Reset DMAx_Streamy FIFO control register */
232 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
233
234 /* Reset Channel register field for DMAx Stream*/
235 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
236
237 if(Stream == LL_DMA_STREAM_0)
238 {
239 /* Reset the Stream0 pending flags */
240 DMAx->LIFCR = 0x0000003FU;
241 }
242 else if(Stream == LL_DMA_STREAM_1)
243 {
244 /* Reset the Stream1 pending flags */
245 DMAx->LIFCR = 0x00000F40U;
246 }
247 else if(Stream == LL_DMA_STREAM_2)
248 {
249 /* Reset the Stream2 pending flags */
250 DMAx->LIFCR = 0x003F0000U;
251 }
252 else if(Stream == LL_DMA_STREAM_3)
253 {
254 /* Reset the Stream3 pending flags */
255 DMAx->LIFCR = 0x0F400000U;
256 }
257 else if(Stream == LL_DMA_STREAM_4)
258 {
259 /* Reset the Stream4 pending flags */
260 DMAx->HIFCR = 0x0000003FU;
261 }
262 else if(Stream == LL_DMA_STREAM_5)
263 {
264 /* Reset the Stream5 pending flags */
265 DMAx->HIFCR = 0x00000F40U;
266 }
267 else if(Stream == LL_DMA_STREAM_6)
268 {
269 /* Reset the Stream6 pending flags */
270 DMAx->HIFCR = 0x003F0000U;
271 }
272 else if(Stream == LL_DMA_STREAM_7)
273 {
274 /* Reset the Stream7 pending flags */
275 DMAx->HIFCR = 0x0F400000U;
276 }
277 else
278 {
279 status = ERROR;
280 }
281 }
282
283 return status;
284 }
285
286 /**
287 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
288 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
289 * @arg @ref __LL_DMA_GET_INSTANCE
290 * @arg @ref __LL_DMA_GET_STREAM
291 * @param DMAx DMAx Instance
292 * @param Stream This parameter can be one of the following values:
293 * @arg @ref LL_DMA_STREAM_0
294 * @arg @ref LL_DMA_STREAM_1
295 * @arg @ref LL_DMA_STREAM_2
296 * @arg @ref LL_DMA_STREAM_3
297 * @arg @ref LL_DMA_STREAM_4
298 * @arg @ref LL_DMA_STREAM_5
299 * @arg @ref LL_DMA_STREAM_6
300 * @arg @ref LL_DMA_STREAM_7
301 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
302 * @retval An ErrorStatus enumeration value:
303 * - SUCCESS: DMA registers are initialized
304 * - ERROR: Not applicable
305 */
306 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
307 {
308 /* Check the DMA Instance DMAx and Stream parameters*/
309 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
310
311 /* Check the DMA parameters from DMA_InitStruct */
312 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
313 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
314 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
315 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
316 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
317 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
318 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
319 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
320 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
321 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
322 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
323 when FIFO mode is enabled */
324 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
325 {
326 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
327 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
328 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
329 }
330
331 /*---------------------------- DMAx SxCR Configuration ------------------------
332 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
333 * peripheral and memory increment mode,
334 * data size alignment and priority level with parameters :
335 * - Direction: DMA_SxCR_DIR[1:0] bits
336 * - Mode: DMA_SxCR_CIRC bit
337 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
338 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
339 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
340 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
341 * - Priority: DMA_SxCR_PL[1:0] bits
342 */
343 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
344 DMA_InitStruct->Mode | \
345 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
346 DMA_InitStruct->MemoryOrM2MDstIncMode | \
347 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
348 DMA_InitStruct->MemoryOrM2MDstDataSize | \
349 DMA_InitStruct->Priority
350 );
351
352 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
353 {
354 /*---------------------------- DMAx SxFCR Configuration ------------------------
355 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
356 * - FIFOMode: DMA_SxFCR_DMDIS bit
357 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
358 */
359 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
360
361 /*---------------------------- DMAx SxCR Configuration --------------------------
362 * Configure DMAx_Streamy: memory burst transfer with parameters :
363 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
364 */
365 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
366
367 /*---------------------------- DMAx SxCR Configuration --------------------------
368 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
369 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
370 */
371 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
372 }
373
374 /*-------------------------- DMAx SxM0AR Configuration --------------------------
375 * Configure the memory or destination base address with parameter :
376 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
377 */
378 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
379
380 /*-------------------------- DMAx SxPAR Configuration ---------------------------
381 * Configure the peripheral or source base address with parameter :
382 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
383 */
384 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
385
386 /*--------------------------- DMAx SxNDTR Configuration -------------------------
387 * Configure the peripheral base address with parameter :
388 * - NbData: DMA_SxNDT[15:0] bits
389 */
390 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
391
392 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
393 * Configure the peripheral base address with parameter :
394 * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits
395 */
396 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
397
398 return SUCCESS;
399 }
400
401 /**
402 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
403 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
404 * @retval None
405 */
406 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
407 {
408 /* Set DMA_InitStruct fields to default values */
409 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
410 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
411 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
412 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
413 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
414 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
415 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
416 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
417 DMA_InitStruct->NbData = 0x00000000U;
418 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
419 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
420 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
421 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
422 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
423 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
424 }
425
426 /**
427 * @}
428 */
429
430 /**
431 * @}
432 */
433
434 /**
435 * @}
436 */
437
438 #endif /* DMA1 || DMA2 */
439
440 /**
441 * @}
442 */
443
444 #endif /* USE_FULL_LL_DRIVER */
445
446 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/