lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_ll_fmc.c
   4   * @author  MCD Application Team
   5   * @brief   FMC Low Layer HAL module driver.
   6   *
   7   *          This file provides firmware functions to manage the following
   8   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
   9   *           + Initialization/de-initialization functions
  10   *           + Peripheral Control functions
  11   *           + Peripheral State functions
  12   *
  13   @verbatim
  14   ==============================================================================
  15                         ##### FMC peripheral features #####
  16   ==============================================================================
  17   [..] The Flexible memory controller (FMC) includes three memory controllers:
  18        (+) The NOR/PSRAM memory controller
  19        (+) The NAND memory controller
  20        (+) The Synchronous DRAM (SDRAM) controller
  21
  22   [..] The FMC functional block makes the interface with synchronous and asynchronous static
  23        memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
  24        (+) to translate AHB transactions into the appropriate external device protocol
  25        (+) to meet the access time requirements of the external memory devices
  26
  27   [..] All external memories share the addresses, data and control signals with the controller.
  28        Each external device is accessed by means of a unique Chip Select. The FMC performs
  29        only one access at a time to an external device.
  30        The main features of the FMC controller are the following:
  31         (+) Interface with static-memory mapped devices including:
  32            (++) Static random access memory (SRAM)
  33            (++) Read-only memory (ROM)
  34            (++) NOR Flash memory/OneNAND Flash memory
  35            (++) PSRAM (4 memory banks)
  36            (++) 16-bit PC Card compatible devices
  37            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  38                 data
  39         (+) Interface with synchronous DRAM (SDRAM) memories
  40         (+) Independent Chip Select control for each memory bank
  41         (+) Independent configuration for each memory bank
  42
  43   @endverbatim
  44   ******************************************************************************
  45   * @attention
  46   *
  47   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  48   * All rights reserved.</center></h2>
  49   *
  50   * This software component is licensed by ST under BSD 3-Clause license,
  51   * the "License"; You may not use this file except in compliance with the
  52   * License. You may obtain a copy of the License at:
  53   *                        opensource.org/licenses/BSD-3-Clause
  54   *
  55   ******************************************************************************
  56   */
  57
  58 /* Includes ------------------------------------------------------------------*/
  59 #include "stm32f7xx_hal.h"
  60
  61 /** @addtogroup STM32F7xx_HAL_Driver
  62   * @{
  63   */
  64
  65 /** @defgroup FMC_LL  FMC Low Layer
  66   * @brief FMC driver modules
  67   * @{
  68   */
  69
  70 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
  71
  72 /* Private typedef -----------------------------------------------------------*/
  73 /* Private define ------------------------------------------------------------*/
  74 /* Private macro -------------------------------------------------------------*/
  75 /* Private variables ---------------------------------------------------------*/
  76 /* Private function prototypes -----------------------------------------------*/
  77 /* Exported functions --------------------------------------------------------*/
  78
  79 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
  80   * @{
  81   */
  82
  83 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
  84   * @brief  NORSRAM Controller functions
  85   *
  86   @verbatim
  87   ==============================================================================
  88                    ##### How to use NORSRAM device driver #####
  89   ==============================================================================
  90
  91   [..]
  92     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
  93     to run the NORSRAM external devices.
  94
  95     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
  96     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
  97     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
  98     (+) FMC NORSRAM bank extended timing configuration using the function
  99         FMC_NORSRAM_Extended_Timing_Init()
 100     (+) FMC NORSRAM bank enable/disable write operation using the functions
 101         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
 102
 103
 104 @endverbatim
 105   * @{
 106   */
 107
 108 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 109   * @brief    Initialization and Configuration functions
 110   *
 111   @verbatim
 112   ==============================================================================
 113               ##### Initialization and de_initialization functions #####
 114   ==============================================================================
 115   [..]
 116     This section provides functions allowing to:
 117     (+) Initialize and configure the FMC NORSRAM interface
 118     (+) De-initialize the FMC NORSRAM interface
 119     (+) Configure the FMC clock and associated GPIOs
 120
 121 @endverbatim
 122   * @{
 123   */
 124
 125 /**
 126   * @brief  Initialize the FMC_NORSRAM device according to the specified
 127   *         control parameters in the FMC_NORSRAM_InitTypeDef
 128   * @param  Device Pointer to NORSRAM device instance
 129   * @param  Init Pointer to NORSRAM Initialization structure
 130   * @retval HAL status
 131   */
 132 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
 133 {
 134   uint32_t tmpr = 0;
 135
 136   /* Check the parameters */
 137   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 138   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
 139   assert_param(IS_FMC_MUX(Init->DataAddressMux));
 140   assert_param(IS_FMC_MEMORY(Init->MemoryType));
 141   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 142   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
 143   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 144   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 145   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
 146   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
 147   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
 148   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
 149   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
 150   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
 151   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
 152   assert_param(IS_FMC_PAGESIZE(Init->PageSize));
 153
 154   /* Get the BTCR register value */
 155   tmpr = Device->BTCR[Init->NSBank];
 156
 157   /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
 158            WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
 159   tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN     | FMC_BCR1_MUXEN    | FMC_BCR1_MTYP     | \
 160                        FMC_BCR1_MWID      | FMC_BCR1_FACCEN   | FMC_BCR1_BURSTEN  | \
 161                        FMC_BCR1_WAITPOL   | FMC_BCR1_CPSIZE    | FMC_BCR1_WAITCFG  | \
 162                        FMC_BCR1_WREN      | FMC_BCR1_WAITEN   | FMC_BCR1_EXTMOD   | \
 163                        FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
 164
 165   /* Set NORSRAM device control parameters */
 166   tmpr |= (uint32_t)(Init->DataAddressMux       |\
 167                     Init->MemoryType           |\
 168                     Init->MemoryDataWidth      |\
 169                     Init->BurstAccessMode      |\
 170                     Init->WaitSignalPolarity   |\
 171                     Init->WaitSignalActive     |\
 172                     Init->WriteOperation       |\
 173                     Init->WaitSignal           |\
 174                     Init->ExtendedMode         |\
 175                     Init->AsynchronousWait     |\
 176                     Init->WriteBurst           |\
 177                     Init->ContinuousClock      |\
 178                     Init->PageSize             |\
 179                     Init->WriteFifo);
 180
 181   if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
 182   {
 183     tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
 184   }
 185
 186   Device->BTCR[Init->NSBank] = tmpr;
 187
 188   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
 189   if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
 190   {
 191     Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
 192   }
 193   if(Init->NSBank != FMC_NORSRAM_BANK1)
 194   {
 195     Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
 196   }
 197
 198   return HAL_OK;
 199 }
 200
 201
 202 /**
 203   * @brief  DeInitialize the FMC_NORSRAM peripheral
 204   * @param  Device Pointer to NORSRAM device instance
 205   * @param  ExDevice Pointer to NORSRAM extended mode device instance
 206   * @param  Bank NORSRAM bank number
 207   * @retval HAL status
 208   */
 209 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 210 {
 211   /* Check the parameters */
 212   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 213   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 214   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 215
 216   /* Disable the FMC_NORSRAM device */
 217   __FMC_NORSRAM_DISABLE(Device, Bank);
 218
 219   /* De-initialize the FMC_NORSRAM device */
 220   /* FMC_NORSRAM_BANK1 */
 221   if(Bank == FMC_NORSRAM_BANK1)
 222   {
 223     Device->BTCR[Bank] = 0x000030DB;
 224   }
 225   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
 226   else
 227   {
 228     Device->BTCR[Bank] = 0x000030D2;
 229   }
 230
 231   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
 232   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
 233
 234   return HAL_OK;
 235 }
 236
 237
 238 /**
 239   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
 240   *         parameters in the FMC_NORSRAM_TimingTypeDef
 241   * @param  Device Pointer to NORSRAM device instance
 242   * @param  Timing Pointer to NORSRAM Timing structure
 243   * @param  Bank NORSRAM bank number
 244   * @retval HAL status
 245   */
 246 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 247 {
 248   uint32_t tmpr = 0;
 249
 250   /* Check the parameters */
 251   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 252   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 253   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 254   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 255   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 256   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 257   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 258   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 259   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 260
 261   /* Get the BTCR register value */
 262   tmpr = Device->BTCR[Bank + 1];
 263
 264   /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
 265   tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET  | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
 266                        FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
 267                        FMC_BTR1_ACCMOD));
 268
 269   /* Set FMC_NORSRAM device timing parameters */
 270   tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\
 271                    ((Timing->AddressHoldTime) << 4)          |\
 272                    ((Timing->DataSetupTime) << 8)            |\
 273                    ((Timing->BusTurnAroundDuration) << 16)   |\
 274                    (((Timing->CLKDivision)-1) << 20)         |\
 275                    (((Timing->DataLatency)-2) << 24)         |\
 276                     (Timing->AccessMode)
 277                     );
 278
 279   Device->BTCR[Bank + 1] = tmpr;
 280
 281   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
 282   if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
 283   {
 284     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
 285     tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
 286     Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
 287   }
 288
 289   return HAL_OK;
 290 }
 291
 292 /**
 293   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
 294   *         parameters in the FMC_NORSRAM_TimingTypeDef
 295   * @param  Device Pointer to NORSRAM device instance
 296   * @param  Timing Pointer to NORSRAM Timing structure
 297   * @param  Bank NORSRAM bank number
 298   * @retval HAL status
 299   */
 300 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 301 {
 302   uint32_t tmpr = 0;
 303
 304   /* Check the parameters */
 305   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
 306
 307   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 308   if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
 309   {
 310     /* Check the parameters */
 311     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
 312     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 313     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 314     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 315     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 316     assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 317     assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 318     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 319     assert_param(IS_FMC_NORSRAM_BANK(Bank));
 320
 321     /* Get the BWTR register value */
 322     tmpr = Device->BWTR[Bank];
 323
 324     /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
 325     tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET  | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
 326                          FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
 327
 328     tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\
 329                       ((Timing->AddressHoldTime) << 4)          |\
 330                       ((Timing->DataSetupTime) << 8)            |\
 331                       ((Timing->BusTurnAroundDuration) << 16)   |\
 332                       (Timing->AccessMode));
 333
 334     Device->BWTR[Bank] = tmpr;
 335   }
 336   else
 337   {
 338     Device->BWTR[Bank] = 0x0FFFFFFF;
 339   }
 340
 341   return HAL_OK;
 342 }
 343 /**
 344   * @}
 345   */
 346
 347 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
 348  *  @brief   management functions
 349  *
 350 @verbatim
 351   ==============================================================================
 352                       ##### FMC_NORSRAM Control functions #####
 353   ==============================================================================
 354   [..]
 355     This subsection provides a set of functions allowing to control dynamically
 356     the FMC NORSRAM interface.
 357
 358 @endverbatim
 359   * @{
 360   */
 361
 362 /**
 363   * @brief  Enables dynamically FMC_NORSRAM write operation.
 364   * @param  Device Pointer to NORSRAM device instance
 365   * @param  Bank NORSRAM bank number
 366   * @retval HAL status
 367   */
 368 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 369 {
 370   /* Check the parameters */
 371   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 372   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 373
 374   /* Enable write operation */
 375   Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
 376
 377   return HAL_OK;
 378 }
 379
 380 /**
 381   * @brief  Disables dynamically FMC_NORSRAM write operation.
 382   * @param  Device Pointer to NORSRAM device instance
 383   * @param  Bank NORSRAM bank number
 384   * @retval HAL status
 385   */
 386 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 387 {
 388   /* Check the parameters */
 389   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 390   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 391
 392   /* Disable write operation */
 393   Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
 394
 395   return HAL_OK;
 396 }
 397
 398 /**
 399   * @}
 400   */
 401
 402 /**
 403   * @}
 404   */
 405
 406 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
 407   * @brief    NAND Controller functions
 408   *
 409   @verbatim
 410   ==============================================================================
 411                     ##### How to use NAND device driver #####
 412   ==============================================================================
 413   [..]
 414     This driver contains a set of APIs to interface with the FMC NAND banks in order
 415     to run the NAND external devices.
 416
 417     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
 418     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
 419     (+) FMC NAND bank common space timing configuration using the function
 420         FMC_NAND_CommonSpace_Timing_Init()
 421     (+) FMC NAND bank attribute space timing configuration using the function
 422         FMC_NAND_AttributeSpace_Timing_Init()
 423     (+) FMC NAND bank enable/disable ECC correction feature using the functions
 424         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
 425     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
 426
 427 @endverbatim
 428   * @{
 429   */
 430
 431 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 432  *  @brief    Initialization and Configuration functions
 433  *
 434 @verbatim
 435   ==============================================================================
 436               ##### Initialization and de_initialization functions #####
 437   ==============================================================================
 438   [..]
 439     This section provides functions allowing to:
 440     (+) Initialize and configure the FMC NAND interface
 441     (+) De-initialize the FMC NAND interface
 442     (+) Configure the FMC clock and associated GPIOs
 443
 444 @endverbatim
 445   * @{
 446   */
 447
 448 /**
 449   * @brief  Initializes the FMC_NAND device according to the specified
 450   *         control parameters in the FMC_NAND_HandleTypeDef
 451   * @param  Device Pointer to NAND device instance
 452   * @param  Init Pointer to NAND Initialization structure
 453   * @retval HAL status
 454   */
 455 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
 456 {
 457   uint32_t tmpr  = 0;
 458
 459   /* Check the parameters */
 460   assert_param(IS_FMC_NAND_DEVICE(Device));
 461   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
 462   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 463   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 464   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
 465   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
 466   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 467   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 468
 469   /* Get the NAND bank 3 register value */
 470   tmpr = Device->PCR;
 471
 472   /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
 473   tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN  | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
 474                        FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
 475                        FMC_PCR_TAR | FMC_PCR_ECCPS));
 476   /* Set NAND device control parameters */
 477   tmpr |= (uint32_t)(Init->Waitfeature                |\
 478                       FMC_PCR_MEMORY_TYPE_NAND         |\
 479                       Init->MemoryDataWidth            |\
 480                       Init->EccComputation             |\
 481                       Init->ECCPageSize                |\
 482                       ((Init->TCLRSetupTime) << 9)     |\
 483                       ((Init->TARSetupTime) << 13));
 484
 485     /* NAND bank 3 registers configuration */
 486     Device->PCR  = tmpr;
 487
 488   return HAL_OK;
 489
 490 }
 491
 492 /**
 493   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
 494   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 495   * @param  Device Pointer to NAND device instance
 496   * @param  Timing Pointer to NAND timing structure
 497   * @param  Bank NAND bank number
 498   * @retval HAL status
 499   */
 500 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 501 {
 502   uint32_t tmpr = 0;
 503
 504   /* Check the parameters */
 505   assert_param(IS_FMC_NAND_DEVICE(Device));
 506   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 507   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 508   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 509   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 510   assert_param(IS_FMC_NAND_BANK(Bank));
 511
 512   /* Get the NAND bank 3 register value */
 513   tmpr = Device->PMEM;
 514
 515   /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
 516   tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3  | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
 517                        FMC_PMEM_MEMHIZ3));
 518   /* Set FMC_NAND device timing parameters */
 519   tmpr |= (uint32_t)(Timing->SetupTime                  |\
 520                        ((Timing->WaitSetupTime) << 8)     |\
 521                        ((Timing->HoldSetupTime) << 16)    |\
 522                        ((Timing->HiZSetupTime) << 24)
 523                        );
 524
 525     /* NAND bank 3 registers configuration */
 526     Device->PMEM = tmpr;
 527
 528   return HAL_OK;
 529 }
 530
 531 /**
 532   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
 533   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 534   * @param  Device Pointer to NAND device instance
 535   * @param  Timing Pointer to NAND timing structure
 536   * @param  Bank NAND bank number
 537   * @retval HAL status
 538   */
 539 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 540 {
 541   uint32_t tmpr = 0;
 542
 543   /* Check the parameters */
 544   assert_param(IS_FMC_NAND_DEVICE(Device));
 545   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 546   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 547   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 548   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 549   assert_param(IS_FMC_NAND_BANK(Bank));
 550
 551   /* Get the NAND bank 3 register value */
 552   tmpr = Device->PATT;
 553
 554   /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
 555   tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3  | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
 556                        FMC_PATT_ATTHIZ3));
 557   /* Set FMC_NAND device timing parameters */
 558   tmpr |= (uint32_t)(Timing->SetupTime                  |\
 559                    ((Timing->WaitSetupTime) << 8)     |\
 560                    ((Timing->HoldSetupTime) << 16)    |\
 561                    ((Timing->HiZSetupTime) << 24));
 562
 563     /* NAND bank 3 registers configuration */
 564     Device->PATT = tmpr;
 565
 566   return HAL_OK;
 567 }
 568
 569 /**
 570   * @brief  DeInitializes the FMC_NAND device
 571   * @param  Device Pointer to NAND device instance
 572   * @param  Bank NAND bank number
 573   * @retval HAL status
 574   */
 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
 576 {
 577   /* Check the parameters */
 578   assert_param(IS_FMC_NAND_DEVICE(Device));
 579   assert_param(IS_FMC_NAND_BANK(Bank));
 580
 581   /* Disable the NAND Bank */
 582   __FMC_NAND_DISABLE(Device);
 583
 584     /* Set the FMC_NAND_BANK3 registers to their reset values */
 585     Device->PCR  = 0x00000018U;
 586     Device->SR   = 0x00000040U;
 587     Device->PMEM = 0xFCFCFCFCU;
 588     Device->PATT = 0xFCFCFCFCU;
 589
 590   return HAL_OK;
 591 }
 592
 593 /**
 594   * @}
 595   */
 596
 597 /** @defgroup HAL_FMC_NAND_Group3 Control functions
 598   *  @brief   management functions
 599   *
 600 @verbatim
 601   ==============================================================================
 602                        ##### FMC_NAND Control functions #####
 603   ==============================================================================
 604   [..]
 605     This subsection provides a set of functions allowing to control dynamically
 606     the FMC NAND interface.
 607
 608 @endverbatim
 609   * @{
 610   */
 611
 612
 613 /**
 614   * @brief  Enables dynamically FMC_NAND ECC feature.
 615   * @param  Device Pointer to NAND device instance
 616   * @param  Bank NAND bank number
 617   * @retval HAL status
 618   */
 619 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 620 {
 621   /* Check the parameters */
 622   assert_param(IS_FMC_NAND_DEVICE(Device));
 623   assert_param(IS_FMC_NAND_BANK(Bank));
 624
 625   /* Enable ECC feature */
 626     Device->PCR |= FMC_PCR_ECCEN;
 627
 628   return HAL_OK;
 629 }
 630
 631
 632 /**
 633   * @brief  Disables dynamically FMC_NAND ECC feature.
 634   * @param  Device Pointer to NAND device instance
 635   * @param  Bank NAND bank number
 636   * @retval HAL status
 637   */
 638 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 639 {
 640   /* Check the parameters */
 641   assert_param(IS_FMC_NAND_DEVICE(Device));
 642   assert_param(IS_FMC_NAND_BANK(Bank));
 643
 644   /* Disable ECC feature */
 645     Device->PCR &= ~FMC_PCR_ECCEN;
 646
 647   return HAL_OK;
 648 }
 649
 650 /**
 651   * @brief  Disables dynamically FMC_NAND ECC feature.
 652   * @param  Device Pointer to NAND device instance
 653   * @param  ECCval Pointer to ECC value
 654   * @param  Bank NAND bank number
 655   * @param  Timeout Timeout wait value
 656   * @retval HAL status
 657   */
 658 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 659 {
 660   uint32_t tickstart = 0;
 661
 662   /* Check the parameters */
 663   assert_param(IS_FMC_NAND_DEVICE(Device));
 664   assert_param(IS_FMC_NAND_BANK(Bank));
 665
 666   /* Get tick */
 667   tickstart = HAL_GetTick();
 668
 669   /* Wait until FIFO is empty */
 670   while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
 671   {
 672     /* Check for the Timeout */
 673     if(Timeout != HAL_MAX_DELAY)
 674     {
 675       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
 676       {
 677         return HAL_TIMEOUT;
 678       }
 679     }
 680   }
 681
 682   /* Get the ECCR register value */
 683   *ECCval = (uint32_t)Device->ECCR;
 684
 685   return HAL_OK;
 686 }
 687
 688 /**
 689   * @}
 690   */
 691
 692 /**
 693   * @}
 694   */
 695
 696 /** @defgroup FMC_LL_SDRAM
 697   * @brief    SDRAM Controller functions
 698   *
 699   @verbatim
 700   ==============================================================================
 701                      ##### How to use SDRAM device driver #####
 702   ==============================================================================
 703   [..]
 704     This driver contains a set of APIs to interface with the FMC SDRAM banks in order
 705     to run the SDRAM external devices.
 706
 707     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
 708     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
 709     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
 710     (+) FMC SDRAM bank enable/disable write operation using the functions
 711         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
 712     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
 713
 714 @endverbatim
 715   * @{
 716   */
 717
 718 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
 719   *  @brief    Initialization and Configuration functions
 720   *
 721 @verbatim
 722   ==============================================================================
 723               ##### Initialization and de_initialization functions #####
 724   ==============================================================================
 725   [..]
 726     This section provides functions allowing to:
 727     (+) Initialize and configure the FMC SDRAM interface
 728     (+) De-initialize the FMC SDRAM interface
 729     (+) Configure the FMC clock and associated GPIOs
 730
 731 @endverbatim
 732   * @{
 733   */
 734
 735 /**
 736   * @brief  Initializes the FMC_SDRAM device according to the specified
 737   *         control parameters in the FMC_SDRAM_InitTypeDef
 738   * @param  Device Pointer to SDRAM device instance
 739   * @param  Init Pointer to SDRAM Initialization structure
 740   * @retval HAL status
 741   */
 742 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
 743 {
 744   uint32_t tmpr1 = 0;
 745   uint32_t tmpr2 = 0;
 746
 747   /* Check the parameters */
 748   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 749   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
 750   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
 751   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
 752   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
 753   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
 754   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
 755   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
 756   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
 757   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
 758   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
 759
 760   /* Set SDRAM bank configuration parameters */
 761   if (Init->SDBank != FMC_SDRAM_BANK2)
 762   {
 763     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
 764
 765     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
 766     tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
 767                           FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP   | \
 768                           FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
 769
 770     tmpr1 |= (uint32_t)(Init->ColumnBitsNumber   |\
 771                         Init->RowBitsNumber      |\
 772                         Init->MemoryDataWidth    |\
 773                         Init->InternalBankNumber |\
 774                         Init->CASLatency         |\
 775                         Init->WriteProtection    |\
 776                         Init->SDClockPeriod      |\
 777                         Init->ReadBurst          |\
 778                         Init->ReadPipeDelay
 779                         );
 780     Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
 781   }
 782   else /* FMC_Bank2_SDRAM */
 783   {
 784     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
 785
 786     /* Clear SDCLK, RBURST, and RPIPE bits */
 787     tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
 788
 789     tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
 790                         Init->ReadBurst          |\
 791                         Init->ReadPipeDelay);
 792
 793     tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
 794
 795     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
 796     tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
 797                           FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP   | \
 798                           FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
 799
 800     tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\
 801                        Init->RowBitsNumber       |\
 802                        Init->MemoryDataWidth     |\
 803                        Init->InternalBankNumber  |\
 804                        Init->CASLatency          |\
 805                        Init->WriteProtection);
 806
 807     Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
 808     Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
 809   }
 810
 811   return HAL_OK;
 812 }
 813
 814
 815 /**
 816   * @brief  Initializes the FMC_SDRAM device timing according to the specified
 817   *         parameters in the FMC_SDRAM_TimingTypeDef
 818   * @param  Device Pointer to SDRAM device instance
 819   * @param  Timing Pointer to SDRAM Timing structure
 820   * @param  Bank SDRAM bank number
 821   * @retval HAL status
 822   */
 823 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
 824 {
 825   uint32_t tmpr1 = 0;
 826   uint32_t tmpr2 = 0;
 827
 828   /* Check the parameters */
 829   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 830   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
 831   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
 832   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
 833   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
 834   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
 835   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
 836   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
 837   assert_param(IS_FMC_SDRAM_BANK(Bank));
 838
 839   /* Set SDRAM device timing parameters */
 840   if (Bank != FMC_SDRAM_BANK2)
 841   {
 842     tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
 843
 844     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
 845     tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
 846                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
 847                           FMC_SDTR1_TRCD));
 848
 849     tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
 850                        (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
 851                        (((Timing->SelfRefreshTime)-1) << 8)      |\
 852                        (((Timing->RowCycleDelay)-1) << 12)       |\
 853                        (((Timing->WriteRecoveryTime)-1) <<16)    |\
 854                        (((Timing->RPDelay)-1) << 20)             |\
 855                        (((Timing->RCDDelay)-1) << 24));
 856     Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
 857   }
 858   else /* FMC_Bank2_SDRAM */
 859   {
 860     tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
 861
 862     /* Clear TRC and TRP bits */
 863     tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
 864
 865     tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
 866                         (((Timing->RPDelay)-1) << 20));
 867
 868     tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
 869
 870     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
 871     tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
 872                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
 873                           FMC_SDTR1_TRCD));
 874
 875     tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
 876                        (((Timing->ExitSelfRefreshDelay)-1) << 4)  |\
 877                        (((Timing->SelfRefreshTime)-1) << 8)       |\
 878                        (((Timing->WriteRecoveryTime)-1) <<16)     |\
 879                        (((Timing->RCDDelay)-1) << 24));
 880
 881     Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
 882     Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
 883   }
 884
 885   return HAL_OK;
 886 }
 887
 888 /**
 889   * @brief  DeInitializes the FMC_SDRAM peripheral
 890   * @param  Device Pointer to SDRAM device instance
 891   * @retval HAL status
 892   */
 893 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 894 {
 895   /* Check the parameters */
 896   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 897   assert_param(IS_FMC_SDRAM_BANK(Bank));
 898
 899   /* De-initialize the SDRAM device */
 900   Device->SDCR[Bank] = 0x000002D0;
 901   Device->SDTR[Bank] = 0x0FFFFFFF;
 902   Device->SDCMR      = 0x00000000;
 903   Device->SDRTR      = 0x00000000;
 904   Device->SDSR       = 0x00000000;
 905
 906   return HAL_OK;
 907 }
 908
 909 /**
 910   * @}
 911   */
 912
 913 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
 914   *  @brief   management functions
 915   *
 916 @verbatim
 917   ==============================================================================
 918                       ##### FMC_SDRAM Control functions #####
 919   ==============================================================================
 920   [..]
 921     This subsection provides a set of functions allowing to control dynamically
 922     the FMC SDRAM interface.
 923
 924 @endverbatim
 925   * @{
 926   */
 927
 928 /**
 929   * @brief  Enables dynamically FMC_SDRAM write protection.
 930   * @param  Device Pointer to SDRAM device instance
 931   * @param  Bank SDRAM bank number
 932   * @retval HAL status
 933   */
 934 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 935 {
 936   /* Check the parameters */
 937   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 938   assert_param(IS_FMC_SDRAM_BANK(Bank));
 939
 940   /* Enable write protection */
 941   Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
 942
 943   return HAL_OK;
 944 }
 945
 946 /**
 947   * @brief  Disables dynamically FMC_SDRAM write protection.
 948   * @param  hsdram FMC_SDRAM handle
 949   * @retval HAL status
 950   */
 951 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 952 {
 953   /* Check the parameters */
 954   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 955   assert_param(IS_FMC_SDRAM_BANK(Bank));
 956
 957   /* Disable write protection */
 958   Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
 959
 960   return HAL_OK;
 961 }
 962
 963 /**
 964   * @brief  Send Command to the FMC SDRAM bank
 965   * @param  Device Pointer to SDRAM device instance
 966   * @param  Command Pointer to SDRAM command structure
 967   * @param  Timing Pointer to SDRAM Timing structure
 968   * @param  Timeout Timeout wait value
 969   * @retval HAL state
 970   */
 971 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
 972 {
 973   __IO uint32_t tmpr = 0;
 974
 975   /* Check the parameters */
 976   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 977   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
 978   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
 979   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
 980   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
 981
 982   /* Set command register */
 983   tmpr = (uint32_t)((Command->CommandMode)                  |\
 984                     (Command->CommandTarget)                |\
 985                     (((Command->AutoRefreshNumber)-1) << 5) |\
 986                     ((Command->ModeRegisterDefinition) << 9)
 987                     );
 988
 989   Device->SDCMR = tmpr;
 990
 991   return HAL_OK;
 992 }
 993
 994 /**
 995   * @brief  Program the SDRAM Memory Refresh rate.
 996   * @param  Device Pointer to SDRAM device instance
 997   * @param  RefreshRate The SDRAM refresh rate value.
 998   * @retval HAL state
 999   */
1000 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1001 {
1002   /* Check the parameters */
1003   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1004   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1005
1006   /* Set the refresh rate in command register */
1007   Device->SDRTR |= (RefreshRate<<1);
1008
1009   return HAL_OK;
1010 }
1011
1012 /**
1013   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
1014   * @param  Device Pointer to SDRAM device instance
1015   * @param  AutoRefreshNumber Specifies the auto Refresh number.
1016   * @retval None
1017   */
1018 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1019 {
1020   /* Check the parameters */
1021   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1022   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1023
1024   /* Set the Auto-refresh number in command register */
1025   Device->SDCMR |= (AutoRefreshNumber << 5);
1026
1027   return HAL_OK;
1028 }
1029
1030 /**
1031   * @brief  Returns the indicated FMC SDRAM bank mode status.
1032   * @param  Device Pointer to SDRAM device instance
1033   * @param  Bank Defines the FMC SDRAM bank. This parameter can be
1034   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1035   * @retval The FMC SDRAM bank mode status, could be on of the following values:
1036   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1037   *         FMC_SDRAM_POWER_DOWN_MODE.
1038   */
1039 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1040 {
1041   uint32_t tmpreg = 0;
1042
1043   /* Check the parameters */
1044   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1045   assert_param(IS_FMC_SDRAM_BANK(Bank));
1046
1047   /* Get the corresponding bank mode */
1048   if(Bank == FMC_SDRAM_BANK1)
1049   {
1050     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1051   }
1052   else
1053   {
1054     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
1055   }
1056
1057   /* Return the mode status */
1058   return tmpreg;
1059 }
1060
1061 /**
1062   * @}
1063   */
1064
1065 /**
1066   * @}
1067   */
1068
1069 /**
1070   * @}
1071   */
1072 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
1073
1074 /**
1075   * @}
1076   */
1077
1078 /**
1079   * @}
1080   */
1081
1082 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/