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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_rcc.c
blob1172876860e83e8fc6dda303936c77dccb76894f
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f7xx_ll_rcc.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28
29 /** @addtogroup STM32F7xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @addtogroup RCC_LL
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup RCC_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
50
51 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
55
56 #if defined(I2C4)
57 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
60 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
61 #else
62 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
64 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
65 #endif /* I2C4 */
66
67 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
68
69 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
70 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
71
72 #if defined(SDMMC2)
73 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
74 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
75 #else
76 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
77 #endif /* SDMMC2 */
78
79 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
80
81 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
82
83 #if defined(DFSDM1_Channel0)
84 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
85
86 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
87 #endif /* DFSDM1_Channel0 */
88
89 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
90
91 #if defined(CEC)
92 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
93 #endif /* CEC */
94
95 #if defined(DSI)
96 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
97 #endif /* DSI */
98
99 #if defined(LTDC)
100 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
101 #endif /* LTDC */
102
103 #if defined(SPDIFRX)
104 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
105 #endif /* SPDIFRX */
106
107 /**
108 * @}
109 */
110
111 /* Private function prototypes -----------------------------------------------*/
112 /** @defgroup RCC_LL_Private_Functions RCC Private functions
113 * @{
114 */
115 uint32_t RCC_GetSystemClockFreq(void);
116 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
117 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
118 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
119 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
120 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
121 uint32_t RCC_PLL_GetFreqDomain_48M(void);
122 #if defined(DSI)
123 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
124 #endif /* DSI */
125 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
126 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
127 #if defined(LTDC)
128 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
129 #endif /* LTDC */
130 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
131 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
132 #if defined(SPDIFRX)
133 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
134 #endif /* SPDIFRX */
135 /**
136 * @}
137 */
138
139
140 /* Exported functions --------------------------------------------------------*/
141 /** @addtogroup RCC_LL_Exported_Functions
142 * @{
143 */
144
145 /** @addtogroup RCC_LL_EF_Init
146 * @{
147 */
148
149 /**
150 * @brief Reset the RCC clock configuration to the default reset state.
151 * @note The default reset state of the clock configuration is given below:
152 * - HSI ON and used as system clock source
153 * - HSE, PLL, PLLI2S, PLLSAI OFF
154 * - AHB, APB1 and APB2 prescaler set to 1.
155 * - CSS, MCO OFF
156 * - All interrupts disabled
157 * @note This function doesn't modify the configuration of the
158 * - Peripheral clocks
159 * - LSI, LSE and RTC clocks
160 * @retval An ErrorStatus enumeration value:
161 * - SUCCESS: RCC registers are de-initialized
162 * - ERROR: not applicable
163 */
164 ErrorStatus LL_RCC_DeInit(void)
165 {
166 uint32_t vl_mask = 0xFFFFFFFFU;
167
168 /* Set HSION bit */
169 LL_RCC_HSI_Enable();
170
171 /* Wait for HSI READY bit */
172 while(LL_RCC_HSI_IsReady() != 1U)
173 {}
174
175 /* Reset CFGR register */
176 LL_RCC_WriteReg(CFGR, 0x00000000U);
177
178 /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
179 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
180
181 /* Write new mask in CR register */
182 LL_RCC_WriteReg(CR, vl_mask);
183
184 /* Set HSITRIM bits to the reset value*/
185 LL_RCC_HSI_SetCalibTrimming(0x10U);
186
187 /* Wait for PLL READY bit to be reset */
188 while(LL_RCC_PLL_IsReady() != 0U)
189 {}
190
191 /* Wait for PLLI2S READY bit to be reset */
192 while(LL_RCC_PLLI2S_IsReady() != 0U)
193 {}
194
195 /* Wait for PLLSAI READY bit to be reset */
196 while(LL_RCC_PLLSAI_IsReady() != 0U)
197 {}
198
199 /* Reset PLLCFGR register */
200 LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
201
202 /* Reset PLLI2SCFGR register */
203 LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
204
205 /* Reset PLLSAICFGR register */
206 LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
207
208 /* Disable all interrupts */
209 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
210
211 /* Clear all interrupt flags */
212 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
213
214 /* Clear LSION bit */
215 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
216
217 /* Reset all CSR flags */
218 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
219
220 return SUCCESS;
221 }
222
223 /**
224 * @}
225 */
226
227 /** @addtogroup RCC_LL_EF_Get_Freq
228 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
229 * and different peripheral clocks available on the device.
230 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
231 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
232 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
233 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
234 * @note (**) HSI_VALUE is a constant defined in this file (default value
235 * 16 MHz) but the real value may vary depending on the variations
236 * in voltage and temperature.
237 * @note (***) HSE_VALUE is a constant defined in this file (default value
238 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
239 * frequency of the crystal used. Otherwise, this function may
240 * have wrong result.
241 * @note The result of this function could be incorrect when using fractional
242 * value for HSE crystal.
243 * @note This function can be used by the user application to compute the
244 * baud-rate for the communication peripherals or configure other parameters.
245 * @{
246 */
247
248 /**
249 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
250 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
251 * must be called to update structure fields. Otherwise, any
252 * configuration based on this function will be incorrect.
253 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
254 * @retval None
255 */
256 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
257 {
258 /* Get SYSCLK frequency */
259 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
260
261 /* HCLK clock frequency */
262 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
263
264 /* PCLK1 clock frequency */
265 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
266
267 /* PCLK2 clock frequency */
268 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
269 }
270
271 /**
272 * @brief Return USARTx clock frequency
273 * @param USARTxSource This parameter can be one of the following values:
274 * @arg @ref LL_RCC_USART1_CLKSOURCE
275 * @arg @ref LL_RCC_USART2_CLKSOURCE
276 * @arg @ref LL_RCC_USART3_CLKSOURCE
277 * @arg @ref LL_RCC_USART6_CLKSOURCE
278 * @retval USART clock frequency (in Hz)
279 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
280 */
281 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
282 {
283 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
284
285 /* Check parameter */
286 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
287
288 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
289 {
290 /* USART1CLK clock frequency */
291 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
292 {
293 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
294 usart_frequency = RCC_GetSystemClockFreq();
295 break;
296
297 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
298 if (LL_RCC_HSI_IsReady())
299 {
300 usart_frequency = HSI_VALUE;
301 }
302 break;
303
304 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
305 if (LL_RCC_LSE_IsReady())
306 {
307 usart_frequency = LSE_VALUE;
308 }
309 break;
310
311 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
312 default:
313 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
314 break;
315 }
316 }
317 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
318 {
319 /* USART2CLK clock frequency */
320 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
321 {
322 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
323 usart_frequency = RCC_GetSystemClockFreq();
324 break;
325
326 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
327 if (LL_RCC_HSI_IsReady())
328 {
329 usart_frequency = HSI_VALUE;
330 }
331 break;
332
333 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
334 if (LL_RCC_LSE_IsReady())
335 {
336 usart_frequency = LSE_VALUE;
337 }
338 break;
339
340 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
341 default:
342 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
343 break;
344 }
345 }
346 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
347 {
348 /* USART6CLK clock frequency */
349 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
350 {
351 case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
352 usart_frequency = RCC_GetSystemClockFreq();
353 break;
354
355 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
356 if (LL_RCC_HSI_IsReady())
357 {
358 usart_frequency = HSI_VALUE;
359 }
360 break;
361
362 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
363 if (LL_RCC_LSE_IsReady())
364 {
365 usart_frequency = LSE_VALUE;
366 }
367 break;
368
369 case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */
370 default:
371 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
372 break;
373 }
374 }
375 else
376 {
377 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
378 {
379 /* USART3CLK clock frequency */
380 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
381 {
382 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
383 usart_frequency = RCC_GetSystemClockFreq();
384 break;
385
386 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
387 if (LL_RCC_HSI_IsReady())
388 {
389 usart_frequency = HSI_VALUE;
390 }
391 break;
392
393 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
394 if (LL_RCC_LSE_IsReady())
395 {
396 usart_frequency = LSE_VALUE;
397 }
398 break;
399
400 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
401 default:
402 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
403 break;
404 }
405 }
406 }
407 return usart_frequency;
408 }
409
410 /**
411 * @brief Return UARTx clock frequency
412 * @param UARTxSource This parameter can be one of the following values:
413 * @arg @ref LL_RCC_UART4_CLKSOURCE
414 * @arg @ref LL_RCC_UART5_CLKSOURCE
415 * @arg @ref LL_RCC_UART7_CLKSOURCE
416 * @arg @ref LL_RCC_UART8_CLKSOURCE
417 * @retval UART clock frequency (in Hz)
418 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
419 */
420 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
421 {
422 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
423
424 /* Check parameter */
425 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
426
427 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
428 {
429 /* UART4CLK clock frequency */
430 switch (LL_RCC_GetUARTClockSource(UARTxSource))
431 {
432 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
433 uart_frequency = RCC_GetSystemClockFreq();
434 break;
435
436 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
437 if (LL_RCC_HSI_IsReady())
438 {
439 uart_frequency = HSI_VALUE;
440 }
441 break;
442
443 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
444 if (LL_RCC_LSE_IsReady())
445 {
446 uart_frequency = LSE_VALUE;
447 }
448 break;
449
450 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
451 default:
452 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
453 break;
454 }
455 }
456 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
457 {
458 /* UART5CLK clock frequency */
459 switch (LL_RCC_GetUARTClockSource(UARTxSource))
460 {
461 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
462 uart_frequency = RCC_GetSystemClockFreq();
463 break;
464
465 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
466 if (LL_RCC_HSI_IsReady())
467 {
468 uart_frequency = HSI_VALUE;
469 }
470 break;
471
472 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
473 if (LL_RCC_LSE_IsReady())
474 {
475 uart_frequency = LSE_VALUE;
476 }
477 break;
478
479 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
480 default:
481 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
482 break;
483 }
484 }
485 else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
486 {
487 /* UART7CLK clock frequency */
488 switch (LL_RCC_GetUARTClockSource(UARTxSource))
489 {
490 case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
491 uart_frequency = RCC_GetSystemClockFreq();
492 break;
493
494 case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
495 if (LL_RCC_HSI_IsReady())
496 {
497 uart_frequency = HSI_VALUE;
498 }
499 break;
500
501 case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
502 if (LL_RCC_LSE_IsReady())
503 {
504 uart_frequency = LSE_VALUE;
505 }
506 break;
507
508 case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
509 default:
510 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
511 break;
512 }
513 }
514 else
515 {
516 if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
517 {
518 /* UART8CLK clock frequency */
519 switch (LL_RCC_GetUARTClockSource(UARTxSource))
520 {
521 case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
522 uart_frequency = RCC_GetSystemClockFreq();
523 break;
524
525 case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
526 if (LL_RCC_HSI_IsReady())
527 {
528 uart_frequency = HSI_VALUE;
529 }
530 break;
531
532 case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
533 if (LL_RCC_LSE_IsReady())
534 {
535 uart_frequency = LSE_VALUE;
536 }
537 break;
538
539 case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
540 default:
541 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
542 break;
543 }
544 }
545 }
546 return uart_frequency;
547 }
548
549 /**
550 * @brief Return I2Cx clock frequency
551 * @param I2CxSource This parameter can be one of the following values:
552 * @arg @ref LL_RCC_I2C1_CLKSOURCE
553 * @arg @ref LL_RCC_I2C2_CLKSOURCE
554 * @arg @ref LL_RCC_I2C3_CLKSOURCE
555 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
556 *
557 * (*) value not defined in all devices.
558 * @retval I2C clock frequency (in Hz)
559 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
560 */
561 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
562 {
563 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
564
565 /* Check parameter */
566 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
567
568 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
569 {
570 /* I2C1 CLK clock frequency */
571 switch (LL_RCC_GetI2CClockSource(I2CxSource))
572 {
573 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
574 i2c_frequency = RCC_GetSystemClockFreq();
575 break;
576
577 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
578 if (LL_RCC_HSI_IsReady())
579 {
580 i2c_frequency = HSI_VALUE;
581 }
582 break;
583
584 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
585 default:
586 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
587 break;
588 }
589 }
590 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
591 {
592 /* I2C2 CLK clock frequency */
593 switch (LL_RCC_GetI2CClockSource(I2CxSource))
594 {
595 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
596 i2c_frequency = RCC_GetSystemClockFreq();
597 break;
598
599 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
600 if (LL_RCC_HSI_IsReady())
601 {
602 i2c_frequency = HSI_VALUE;
603 }
604 break;
605
606 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
607 default:
608 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
609 break;
610 }
611 }
612 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
613 {
614 /* I2C3 CLK clock frequency */
615 switch (LL_RCC_GetI2CClockSource(I2CxSource))
616 {
617 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
618 i2c_frequency = RCC_GetSystemClockFreq();
619 break;
620
621 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
622 if (LL_RCC_HSI_IsReady())
623 {
624 i2c_frequency = HSI_VALUE;
625 }
626 break;
627
628 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
629 default:
630 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
631 break;
632 }
633 }
634 #if defined(I2C4)
635 else
636 {
637 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
638 {
639 /* I2C4 CLK clock frequency */
640 switch (LL_RCC_GetI2CClockSource(I2CxSource))
641 {
642 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
643 i2c_frequency = RCC_GetSystemClockFreq();
644 break;
645
646 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
647 if (LL_RCC_HSI_IsReady())
648 {
649 i2c_frequency = HSI_VALUE;
650 }
651 break;
652
653 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
654 default:
655 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
656 break;
657 }
658 }
659 }
660 #endif /* I2C4 */
661
662 return i2c_frequency;
663 }
664
665 /**
666 * @brief Return I2Sx clock frequency
667 * @param I2SxSource This parameter can be one of the following values:
668 * @arg @ref LL_RCC_I2S1_CLKSOURCE
669 * @retval I2S clock frequency (in Hz)
670 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
671 */
672 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
673 {
674 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
675
676 /* Check parameter */
677 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
678
679 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
680 {
681 /* I2S1 CLK clock frequency */
682 switch (LL_RCC_GetI2SClockSource(I2SxSource))
683 {
684 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
685 if (LL_RCC_PLLI2S_IsReady())
686 {
687 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
688 }
689 break;
690
691 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
692 default:
693 i2s_frequency = EXTERNAL_CLOCK_VALUE;
694 break;
695 }
696 }
697
698 return i2s_frequency;
699 }
700
701 /**
702 * @brief Return LPTIMx clock frequency
703 * @param LPTIMxSource This parameter can be one of the following values:
704 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
705 * @retval LPTIM clock frequency (in Hz)
706 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
707 */
708 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
709 {
710 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
711
712 /* Check parameter */
713 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
714
715 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
716 {
717 /* LPTIM1CLK clock frequency */
718 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
719 {
720 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
721 if (LL_RCC_LSI_IsReady())
722 {
723 lptim_frequency = LSI_VALUE;
724 }
725 break;
726
727 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
728 if (LL_RCC_HSI_IsReady())
729 {
730 lptim_frequency = HSI_VALUE;
731 }
732 break;
733
734 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
735 if (LL_RCC_LSE_IsReady())
736 {
737 lptim_frequency = LSE_VALUE;
738 }
739 break;
740
741 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
742 default:
743 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
744 break;
745 }
746 }
747
748 return lptim_frequency;
749 }
750
751 /**
752 * @brief Return SAIx clock frequency
753 * @param SAIxSource This parameter can be one of the following values:
754 * @arg @ref LL_RCC_SAI1_CLKSOURCE
755 * @arg @ref LL_RCC_SAI2_CLKSOURCE
756 * @retval SAI clock frequency (in Hz)
757 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
758 */
759 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
760 {
761 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
762
763 /* Check parameter */
764 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
765
766 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
767 {
768 /* SAI1CLK clock frequency */
769 switch (LL_RCC_GetSAIClockSource(SAIxSource))
770 {
771 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
772 if (LL_RCC_PLLSAI_IsReady())
773 {
774 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
775 }
776 break;
777
778 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
779 if (LL_RCC_PLLI2S_IsReady())
780 {
781 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
782 }
783 break;
784
785 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
786 case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
787 switch (LL_RCC_PLL_GetMainSource())
788 {
789 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
790 if (LL_RCC_HSE_IsReady())
791 {
792 sai_frequency = HSE_VALUE;
793 }
794 break;
795
796 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
797 default:
798 if (LL_RCC_HSI_IsReady())
799 {
800 sai_frequency = HSI_VALUE;
801 }
802 break;
803 }
804 break;
805 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
806 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
807 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
808 break;
809
810 default:
811 break;
812 }
813 }
814 else
815 {
816 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
817 {
818 /* SAI2CLK clock frequency */
819 switch (LL_RCC_GetSAIClockSource(SAIxSource))
820 {
821 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
822 if (LL_RCC_PLLSAI_IsReady())
823 {
824 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
825 }
826 break;
827
828 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
829 if (LL_RCC_PLLI2S_IsReady())
830 {
831 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
832 }
833 break;
834
835 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
836 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
837 switch (LL_RCC_PLL_GetMainSource())
838 {
839 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
840 if (LL_RCC_HSE_IsReady())
841 {
842 sai_frequency = HSE_VALUE;
843 }
844 break;
845
846 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
847 default:
848 if (LL_RCC_HSI_IsReady())
849 {
850 sai_frequency = HSI_VALUE;
851 }
852 break;
853 }
854 break;
855 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
856 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
857 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
858 break;
859
860 default:
861 break;
862 }
863 }
864 }
865
866 return sai_frequency;
867 }
868
869 /**
870 * @brief Return SDMMCx clock frequency
871 * @param SDMMCxSource This parameter can be one of the following values:
872 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
873 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
874 *
875 * (*) value not defined in all devices.
876 * @retval SDMMC clock frequency (in Hz)
877 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
878 */
879 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
880 {
881 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
882
883 /* Check parameter */
884 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
885
886 if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
887 {
888 /* SDMMC1CLK clock frequency */
889 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
890 {
891 case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
892 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
893 {
894 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
895 if (LL_RCC_PLL_IsReady())
896 {
897 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
898 }
899 break;
900
901 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
902 default:
903 if (LL_RCC_PLLSAI_IsReady())
904 {
905 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
906 }
907 break;
908 }
909 break;
910
911 case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
912 default:
913 sdmmc_frequency = RCC_GetSystemClockFreq();
914 break;
915 }
916 }
917 #if defined(SDMMC2)
918 else
919 {
920 /* SDMMC2CLK clock frequency */
921 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
922 {
923 case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
924 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
925 {
926 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
927 if (LL_RCC_PLL_IsReady())
928 {
929 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
930 }
931 break;
932
933 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
934 default:
935 if (LL_RCC_PLLSAI_IsReady())
936 {
937 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
938 }
939 break;
940 }
941 break;
942
943 case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
944 default:
945 sdmmc_frequency = RCC_GetSystemClockFreq();
946 break;
947 }
948 }
949 #endif /* SDMMC2 */
950
951 return sdmmc_frequency;
952 }
953
954 /**
955 * @brief Return RNGx clock frequency
956 * @param RNGxSource This parameter can be one of the following values:
957 * @arg @ref LL_RCC_RNG_CLKSOURCE
958 * @retval RNG clock frequency (in Hz)
959 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
960 */
961 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
962 {
963 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
964
965 /* Check parameter */
966 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
967
968 /* RNGCLK clock frequency */
969 switch (LL_RCC_GetRNGClockSource(RNGxSource))
970 {
971 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
972 if (LL_RCC_PLL_IsReady())
973 {
974 rng_frequency = RCC_PLL_GetFreqDomain_48M();
975 }
976 break;
977
978 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
979 default:
980 if (LL_RCC_PLLSAI_IsReady())
981 {
982 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
983 }
984 break;
985 }
986
987 return rng_frequency;
988 }
989
990 #if defined(CEC)
991 /**
992 * @brief Return CEC clock frequency
993 * @param CECxSource This parameter can be one of the following values:
994 * @arg @ref LL_RCC_CEC_CLKSOURCE
995 * @retval CEC clock frequency (in Hz)
996 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
997 */
998 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
999 {
1000 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1001
1002 /* Check parameter */
1003 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
1004
1005 /* CECCLK clock frequency */
1006 switch (LL_RCC_GetCECClockSource(CECxSource))
1007 {
1008 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
1009 if (LL_RCC_LSE_IsReady())
1010 {
1011 cec_frequency = LSE_VALUE;
1012 }
1013 break;
1014
1015 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
1016 default:
1017 if (LL_RCC_HSI_IsReady())
1018 {
1019 cec_frequency = HSI_VALUE/488U;
1020 }
1021 break;
1022 }
1023
1024 return cec_frequency;
1025 }
1026 #endif /* CEC */
1027
1028 /**
1029 * @brief Return USBx clock frequency
1030 * @param USBxSource This parameter can be one of the following values:
1031 * @arg @ref LL_RCC_USB_CLKSOURCE
1032 * @retval USB clock frequency (in Hz)
1033 */
1034 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1035 {
1036 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1037
1038 /* Check parameter */
1039 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1040
1041 /* USBCLK clock frequency */
1042 switch (LL_RCC_GetUSBClockSource(USBxSource))
1043 {
1044 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1045 if (LL_RCC_PLL_IsReady())
1046 {
1047 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1048 }
1049 break;
1050
1051 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
1052 default:
1053 if (LL_RCC_PLLSAI_IsReady())
1054 {
1055 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
1056 }
1057 break;
1058 }
1059
1060 return usb_frequency;
1061 }
1062
1063 #if defined(DFSDM1_Channel0)
1064 /**
1065 * @brief Return DFSDMx clock frequency
1066 * @param DFSDMxSource This parameter can be one of the following values:
1067 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1068 * @retval DFSDM clock frequency (in Hz)
1069 */
1070 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1071 {
1072 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1073
1074 /* Check parameter */
1075 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1076
1077 /* DFSDM1CLK clock frequency */
1078 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1079 {
1080 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1081 dfsdm_frequency = RCC_GetSystemClockFreq();
1082 break;
1083
1084 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1085 default:
1086 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1087 break;
1088 }
1089
1090 return dfsdm_frequency;
1091 }
1092
1093 /**
1094 * @brief Return DFSDMx Audio clock frequency
1095 * @param DFSDMxSource This parameter can be one of the following values:
1096 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1097 * @retval DFSDM clock frequency (in Hz)
1098 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1099 */
1100 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1101 {
1102 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1103
1104 /* Check parameter */
1105 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1106
1107 /* DFSDM1CLK clock frequency */
1108 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1109 {
1110 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1111 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1112 break;
1113
1114 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */
1115 default:
1116 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
1117 break;
1118 }
1119
1120 return dfsdm_frequency;
1121 }
1122 #endif /* DFSDM1_Channel0 */
1123
1124 #if defined(DSI)
1125 /**
1126 * @brief Return DSI clock frequency
1127 * @param DSIxSource This parameter can be one of the following values:
1128 * @arg @ref LL_RCC_DSI_CLKSOURCE
1129 * @retval DSI clock frequency (in Hz)
1130 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1131 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1132 */
1133 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1134 {
1135 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1136
1137 /* Check parameter */
1138 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1139
1140 /* DSICLK clock frequency */
1141 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1142 {
1143 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1144 if (LL_RCC_PLL_IsReady())
1145 {
1146 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1147 }
1148 break;
1149
1150 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1151 default:
1152 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1153 break;
1154 }
1155
1156 return dsi_frequency;
1157 }
1158 #endif /* DSI */
1159
1160 #if defined(LTDC)
1161 /**
1162 * @brief Return LTDC clock frequency
1163 * @param LTDCxSource This parameter can be one of the following values:
1164 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1165 * @retval LTDC clock frequency (in Hz)
1166 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1167 */
1168 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1169 {
1170 UNUSED(LTDCxSource);
1171
1172 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1173
1174 /* Check parameter */
1175 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1176
1177 if (LL_RCC_PLLSAI_IsReady())
1178 {
1179 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1180 }
1181
1182 return ltdc_frequency;
1183 }
1184 #endif /* LTDC */
1185
1186 #if defined(SPDIFRX)
1187 /**
1188 * @brief Return SPDIFRX clock frequency
1189 * @param SPDIFRXxSource This parameter can be one of the following values:
1190 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1191 * @retval SPDIFRX clock frequency (in Hz)
1192 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1193 */
1194 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1195 {
1196 UNUSED(SPDIFRXxSource);
1197
1198 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1199
1200 /* Check parameter */
1201 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1202
1203 if (LL_RCC_PLLI2S_IsReady())
1204 {
1205 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1206 }
1207
1208 return spdifrx_frequency;
1209 }
1210 #endif /* SPDIFRX */
1211
1212 /**
1213 * @}
1214 */
1215
1216 /**
1217 * @}
1218 */
1219
1220 /** @addtogroup RCC_LL_Private_Functions
1221 * @{
1222 */
1223
1224 /**
1225 * @brief Return SYSTEM clock frequency
1226 * @retval SYSTEM clock frequency (in Hz)
1227 */
1228 uint32_t RCC_GetSystemClockFreq(void)
1229 {
1230 uint32_t frequency = 0U;
1231
1232 /* Get SYSCLK source -------------------------------------------------------*/
1233 switch (LL_RCC_GetSysClkSource())
1234 {
1235 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1236 frequency = HSI_VALUE;
1237 break;
1238
1239 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1240 frequency = HSE_VALUE;
1241 break;
1242
1243 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1244 frequency = RCC_PLL_GetFreqDomain_SYS();
1245 break;
1246
1247 default:
1248 frequency = HSI_VALUE;
1249 break;
1250 }
1251
1252 return frequency;
1253 }
1254
1255 /**
1256 * @brief Return HCLK clock frequency
1257 * @param SYSCLK_Frequency SYSCLK clock frequency
1258 * @retval HCLK clock frequency (in Hz)
1259 */
1260 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1261 {
1262 /* HCLK clock frequency */
1263 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1264 }
1265
1266 /**
1267 * @brief Return PCLK1 clock frequency
1268 * @param HCLK_Frequency HCLK clock frequency
1269 * @retval PCLK1 clock frequency (in Hz)
1270 */
1271 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1272 {
1273 /* PCLK1 clock frequency */
1274 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1275 }
1276
1277 /**
1278 * @brief Return PCLK2 clock frequency
1279 * @param HCLK_Frequency HCLK clock frequency
1280 * @retval PCLK2 clock frequency (in Hz)
1281 */
1282 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1283 {
1284 /* PCLK2 clock frequency */
1285 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1286 }
1287
1288 /**
1289 * @brief Return PLL clock frequency used for system domain
1290 * @retval PLL clock frequency (in Hz)
1291 */
1292 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1293 {
1294 uint32_t pllinputfreq = 0U, pllsource = 0U;
1295
1296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1297 SYSCLK = PLL_VCO / PLLP
1298 */
1299 pllsource = LL_RCC_PLL_GetMainSource();
1300
1301 switch (pllsource)
1302 {
1303 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1304 pllinputfreq = HSI_VALUE;
1305 break;
1306
1307 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1308 pllinputfreq = HSE_VALUE;
1309 break;
1310
1311 default:
1312 pllinputfreq = HSI_VALUE;
1313 break;
1314 }
1315 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1316 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1317 }
1318
1319 /**
1320 * @brief Return PLL clock frequency used for 48 MHz domain
1321 * @retval PLL clock frequency (in Hz)
1322 */
1323 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1324 {
1325 uint32_t pllinputfreq = 0U, pllsource = 0U;
1326
1327 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1328 48M Domain clock = PLL_VCO / PLLQ
1329 */
1330 pllsource = LL_RCC_PLL_GetMainSource();
1331
1332 switch (pllsource)
1333 {
1334 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1335 pllinputfreq = HSI_VALUE;
1336 break;
1337
1338 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1339 pllinputfreq = HSE_VALUE;
1340 break;
1341
1342 default:
1343 pllinputfreq = HSI_VALUE;
1344 break;
1345 }
1346 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1347 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1348 }
1349
1350 #if defined(DSI)
1351 /**
1352 * @brief Return PLL clock frequency used for DSI clock
1353 * @retval PLL clock frequency (in Hz)
1354 */
1355 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1356 {
1357 uint32_t pllinputfreq = 0U, pllsource = 0U;
1358
1359 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1360 DSICLK = PLL_VCO / PLLR
1361 */
1362 pllsource = LL_RCC_PLL_GetMainSource();
1363
1364 switch (pllsource)
1365 {
1366 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1367 pllinputfreq = HSE_VALUE;
1368 break;
1369
1370 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1371 default:
1372 pllinputfreq = HSI_VALUE;
1373 break;
1374 }
1375 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1376 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1377 }
1378 #endif /* DSI */
1379
1380 /**
1381 * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains
1382 * @retval PLLSAI clock frequency (in Hz)
1383 */
1384 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1385 {
1386 uint32_t pllinputfreq = 0U, pllsource = 0U;
1387
1388 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1389 SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1390 */
1391 pllsource = LL_RCC_PLL_GetMainSource();
1392
1393 switch (pllsource)
1394 {
1395 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1396 pllinputfreq = HSI_VALUE;
1397 break;
1398
1399 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1400 pllinputfreq = HSE_VALUE;
1401 break;
1402
1403 default:
1404 pllinputfreq = HSI_VALUE;
1405 break;
1406 }
1407 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1408 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1409 }
1410
1411 /**
1412 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1413 * @retval PLLSAI clock frequency (in Hz)
1414 */
1415 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1416 {
1417 uint32_t pllinputfreq = 0U, pllsource = 0U;
1418
1419 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1420 48M Domain clock = PLLSAI_VCO / PLLSAIP
1421 */
1422 pllsource = LL_RCC_PLL_GetMainSource();
1423
1424 switch (pllsource)
1425 {
1426 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1427 pllinputfreq = HSI_VALUE;
1428 break;
1429
1430 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1431 pllinputfreq = HSE_VALUE;
1432 break;
1433
1434 default:
1435 pllinputfreq = HSI_VALUE;
1436 break;
1437 }
1438 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1439 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1440 }
1441
1442 #if defined(LTDC)
1443 /**
1444 * @brief Return PLLSAI clock frequency used for LTDC domain
1445 * @retval PLLSAI clock frequency (in Hz)
1446 */
1447 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1448 {
1449 uint32_t pllinputfreq = 0U, pllsource = 0U;
1450
1451 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1452 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1453 */
1454 pllsource = LL_RCC_PLL_GetMainSource();
1455
1456 switch (pllsource)
1457 {
1458 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1459 pllinputfreq = HSI_VALUE;
1460 break;
1461
1462 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1463 pllinputfreq = HSE_VALUE;
1464 break;
1465
1466 default:
1467 pllinputfreq = HSI_VALUE;
1468 break;
1469 }
1470 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1471 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1472 }
1473 #endif /* LTDC */
1474
1475 /**
1476 * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
1477 * @retval PLLI2S clock frequency (in Hz)
1478 */
1479 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1480 {
1481 uint32_t pllinputfreq = 0U, pllsource = 0U;
1482
1483 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1484 SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1485 */
1486 pllsource = LL_RCC_PLL_GetMainSource();
1487
1488 switch (pllsource)
1489 {
1490 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1491 pllinputfreq = HSI_VALUE;
1492 break;
1493
1494 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1495 pllinputfreq = HSE_VALUE;
1496 break;
1497
1498 default:
1499 pllinputfreq = HSI_VALUE;
1500 break;
1501 }
1502 return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1503 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1504 }
1505
1506 #if defined(SPDIFRX)
1507 /**
1508 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1509 * @retval PLLI2S clock frequency (in Hz)
1510 */
1511 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1512 {
1513 uint32_t pllinputfreq = 0U, pllsource = 0U;
1514
1515 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1516 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1517 */
1518 pllsource = LL_RCC_PLL_GetMainSource();
1519
1520 switch (pllsource)
1521 {
1522 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1523 pllinputfreq = HSI_VALUE;
1524 break;
1525
1526 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1527 pllinputfreq = HSE_VALUE;
1528 break;
1529
1530 default:
1531 pllinputfreq = HSI_VALUE;
1532 break;
1533 }
1534
1535 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1536 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1537 }
1538 #endif /* SPDIFRX */
1539
1540 /**
1541 * @brief Return PLLI2S clock frequency used for I2S domain
1542 * @retval PLLI2S clock frequency (in Hz)
1543 */
1544 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1545 {
1546 uint32_t pllinputfreq = 0U, pllsource = 0U;
1547
1548 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1549 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1550 */
1551 pllsource = LL_RCC_PLL_GetMainSource();
1552
1553 switch (pllsource)
1554 {
1555 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1556 pllinputfreq = HSE_VALUE;
1557 break;
1558
1559 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1560 default:
1561 pllinputfreq = HSI_VALUE;
1562 break;
1563 }
1564 return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1565 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1566 }
1567
1568 /**
1569 * @}
1570 */
1571
1572 /**
1573 * @}
1574 */
1575
1576 #endif /* defined(RCC) */
1577
1578 /**
1579 * @}
1580 */
1581
1582 #endif /* USE_FULL_LL_DRIVER */
1583
1584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/