lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @brief   TIM LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32f7xx_ll_tim.h"
  23 #include "stm32f7xx_ll_bus.h"
  24
  25 #ifdef  USE_FULL_ASSERT
  26 #include "stm32_assert.h"
  27 #else
  28 #define assert_param(expr) ((void)0U)
  29 #endif
  30
  31 /** @addtogroup STM32F7xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
  36
  37 /** @addtogroup TIM_LL
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45 /** @addtogroup TIM_LL_Private_Macros
  46   * @{
  47   */
  48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  49                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  50                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  51                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  52                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  53
  54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  55                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  56                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  57
  58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  59                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  60                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  61                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  62                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  63                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  64                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  65                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  66                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  67                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  68                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  69                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  70                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  71                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
  72
  73 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  74                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  75
  76 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  77                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  78
  79 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  80                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  81
  82 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  83                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  84                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  85
  86 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  87                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  88                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  89                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  90
  91 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  92                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  93                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  94                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  95                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  96                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  97                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  98                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  99                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 100                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 101                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 102                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 103                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 104                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 105                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 106                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 107
 108 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 109                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 110                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 111
 112 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 113                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 114                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 115
 116 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 117                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 118
 119 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 120                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 121
 122 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 123                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 124
 125 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 126                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 127                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 128                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 129
 130 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 131                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 132
 133 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 134                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 135
 136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
 137                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
 138                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
 139                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
 140                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
 141                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
 142                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
 143                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
 144                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
 145                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
 146                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
 147                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
 148                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
 149                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
 150                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
 151                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
 152
 153 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
 154                                         || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
 155
 156 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
 157                                            || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
 158
 159 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
 160                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
 161                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
 162                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
 163                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
 164                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
 165                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
 166                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
 167                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
 168                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
 169                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
 170                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
 171                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
 172                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
 173                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
 174                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
 175
 176 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 177                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 178 /**
 179   * @}
 180   */
 181
 182
 183 /* Private function prototypes -----------------------------------------------*/
 184 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 185   * @{
 186   */
 187 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 188 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 189 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 190 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 192 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 193 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 194 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 195 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 196 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 197 /**
 198   * @}
 199   */
 200
 201 /* Exported functions --------------------------------------------------------*/
 202 /** @addtogroup TIM_LL_Exported_Functions
 203   * @{
 204   */
 205
 206 /** @addtogroup TIM_LL_EF_Init
 207   * @{
 208   */
 209
 210 /**
 211   * @brief  Set TIMx registers to their reset values.
 212   * @param  TIMx Timer instance
 213   * @retval An ErrorStatus enumeration value:
 214   *          - SUCCESS: TIMx registers are de-initialized
 215   *          - ERROR: invalid TIMx instance
 216   */
 217 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 218 {
 219   ErrorStatus result = SUCCESS;
 220
 221   /* Check the parameters */
 222   assert_param(IS_TIM_INSTANCE(TIMx));
 223
 224   if (TIMx == TIM1)
 225   {
 226     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 227     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 228   }
 229   else if (TIMx == TIM2)
 230   {
 231     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 232     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 233   }
 234 #if defined(TIM3)
 235   else if (TIMx == TIM3)
 236   {
 237     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 238     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 239   }
 240 #endif
 241 #if defined(TIM4)
 242   else if (TIMx == TIM4)
 243   {
 244     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 245     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 246   }
 247 #endif
 248 #if defined(TIM5)
 249   else if (TIMx == TIM5)
 250   {
 251     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 252     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 253   }
 254 #endif
 255 #if defined(TIM6)
 256   else if (TIMx == TIM6)
 257   {
 258     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 259     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 260   }
 261 #endif
 262 #if defined (TIM7)
 263   else if (TIMx == TIM7)
 264   {
 265     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 266     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 267   }
 268 #endif
 269 #if defined(TIM8)
 270   else if (TIMx == TIM8)
 271   {
 272     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 273     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 274   }
 275 #endif
 276 #if defined(TIM9)
 277   else if (TIMx == TIM9)
 278   {
 279     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
 280     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
 281   }
 282 #endif
 283 #if defined(TIM10)
 284   else if (TIMx == TIM10)
 285   {
 286     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
 287     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
 288   }
 289 #endif
 290 #if defined(TIM11)
 291   else if (TIMx == TIM11)
 292   {
 293     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
 294     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
 295   }
 296 #endif
 297 #if defined(TIM12)
 298   else if (TIMx == TIM12)
 299   {
 300     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 301     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 302   }
 303 #endif
 304 #if defined(TIM13)
 305   else if (TIMx == TIM13)
 306   {
 307     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 308     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 309   }
 310 #endif
 311 #if defined(TIM14)
 312   else if (TIMx == TIM14)
 313   {
 314     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 315     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 316   }
 317 #endif
 318   else
 319   {
 320     result = ERROR;
 321   }
 322
 323   return result;
 324 }
 325
 326 /**
 327   * @brief  Set the fields of the time base unit configuration data structure
 328   *         to their default values.
 329   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 330   * @retval None
 331   */
 332 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 333 {
 334   /* Set the default configuration */
 335   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
 336   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 337   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 338   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 339   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
 340 }
 341
 342 /**
 343   * @brief  Configure the TIMx time base unit.
 344   * @param  TIMx Timer Instance
 345   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 346   * @retval An ErrorStatus enumeration value:
 347   *          - SUCCESS: TIMx registers are de-initialized
 348   *          - ERROR: not applicable
 349   */
 350 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 351 {
 352   uint32_t tmpcr1;
 353
 354   /* Check the parameters */
 355   assert_param(IS_TIM_INSTANCE(TIMx));
 356   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 357   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 358
 359   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 360
 361   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 362   {
 363     /* Select the Counter Mode */
 364     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 365   }
 366
 367   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 368   {
 369     /* Set the clock division */
 370     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 371   }
 372
 373   /* Write to TIMx CR1 */
 374   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 375
 376   /* Set the Autoreload value */
 377   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 378
 379   /* Set the Prescaler value */
 380   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 381
 382   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 383   {
 384     /* Set the Repetition Counter value */
 385     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 386   }
 387
 388   /* Generate an update event to reload the Prescaler
 389      and the repetition counter value (if applicable) immediately */
 390   LL_TIM_GenerateEvent_UPDATE(TIMx);
 391
 392   return SUCCESS;
 393 }
 394
 395 /**
 396   * @brief  Set the fields of the TIMx output channel configuration data
 397   *         structure to their default values.
 398   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 399   * @retval None
 400   */
 401 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 402 {
 403   /* Set the default configuration */
 404   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 405   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 406   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 407   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 408   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 409   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 410   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 411   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 412 }
 413
 414 /**
 415   * @brief  Configure the TIMx output channel.
 416   * @param  TIMx Timer Instance
 417   * @param  Channel This parameter can be one of the following values:
 418   *         @arg @ref LL_TIM_CHANNEL_CH1
 419   *         @arg @ref LL_TIM_CHANNEL_CH2
 420   *         @arg @ref LL_TIM_CHANNEL_CH3
 421   *         @arg @ref LL_TIM_CHANNEL_CH4
 422   *         @arg @ref LL_TIM_CHANNEL_CH5
 423   *         @arg @ref LL_TIM_CHANNEL_CH6
 424   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 425   * @retval An ErrorStatus enumeration value:
 426   *          - SUCCESS: TIMx output channel is initialized
 427   *          - ERROR: TIMx output channel is not initialized
 428   */
 429 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 430 {
 431   ErrorStatus result = ERROR;
 432
 433   switch (Channel)
 434   {
 435     case LL_TIM_CHANNEL_CH1:
 436       result = OC1Config(TIMx, TIM_OC_InitStruct);
 437       break;
 438     case LL_TIM_CHANNEL_CH2:
 439       result = OC2Config(TIMx, TIM_OC_InitStruct);
 440       break;
 441     case LL_TIM_CHANNEL_CH3:
 442       result = OC3Config(TIMx, TIM_OC_InitStruct);
 443       break;
 444     case LL_TIM_CHANNEL_CH4:
 445       result = OC4Config(TIMx, TIM_OC_InitStruct);
 446       break;
 447     case LL_TIM_CHANNEL_CH5:
 448       result = OC5Config(TIMx, TIM_OC_InitStruct);
 449       break;
 450     case LL_TIM_CHANNEL_CH6:
 451       result = OC6Config(TIMx, TIM_OC_InitStruct);
 452       break;
 453     default:
 454       break;
 455   }
 456
 457   return result;
 458 }
 459
 460 /**
 461   * @brief  Set the fields of the TIMx input channel configuration data
 462   *         structure to their default values.
 463   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 464   * @retval None
 465   */
 466 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 467 {
 468   /* Set the default configuration */
 469   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 470   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 471   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 472   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 473 }
 474
 475 /**
 476   * @brief  Configure the TIMx input channel.
 477   * @param  TIMx Timer Instance
 478   * @param  Channel This parameter can be one of the following values:
 479   *         @arg @ref LL_TIM_CHANNEL_CH1
 480   *         @arg @ref LL_TIM_CHANNEL_CH2
 481   *         @arg @ref LL_TIM_CHANNEL_CH3
 482   *         @arg @ref LL_TIM_CHANNEL_CH4
 483   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 484   * @retval An ErrorStatus enumeration value:
 485   *          - SUCCESS: TIMx output channel is initialized
 486   *          - ERROR: TIMx output channel is not initialized
 487   */
 488 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 489 {
 490   ErrorStatus result = ERROR;
 491
 492   switch (Channel)
 493   {
 494     case LL_TIM_CHANNEL_CH1:
 495       result = IC1Config(TIMx, TIM_IC_InitStruct);
 496       break;
 497     case LL_TIM_CHANNEL_CH2:
 498       result = IC2Config(TIMx, TIM_IC_InitStruct);
 499       break;
 500     case LL_TIM_CHANNEL_CH3:
 501       result = IC3Config(TIMx, TIM_IC_InitStruct);
 502       break;
 503     case LL_TIM_CHANNEL_CH4:
 504       result = IC4Config(TIMx, TIM_IC_InitStruct);
 505       break;
 506     default:
 507       break;
 508   }
 509
 510   return result;
 511 }
 512
 513 /**
 514   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 515   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 516   * @retval None
 517   */
 518 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 519 {
 520   /* Set the default configuration */
 521   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 522   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 523   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 524   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 525   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 526   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 527   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 528   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 529   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 530 }
 531
 532 /**
 533   * @brief  Configure the encoder interface of the timer instance.
 534   * @param  TIMx Timer Instance
 535   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 536   * @retval An ErrorStatus enumeration value:
 537   *          - SUCCESS: TIMx registers are de-initialized
 538   *          - ERROR: not applicable
 539   */
 540 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 541 {
 542   uint32_t tmpccmr1;
 543   uint32_t tmpccer;
 544
 545   /* Check the parameters */
 546   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 547   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 548   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 549   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 550   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 551   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 552   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 553   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 554   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 555   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 556
 557   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 558   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 559
 560   /* Get the TIMx CCMR1 register value */
 561   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 562
 563   /* Get the TIMx CCER register value */
 564   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 565
 566   /* Configure TI1 */
 567   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 568   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 569   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 570   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 571
 572   /* Configure TI2 */
 573   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 574   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 575   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 576   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 577
 578   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 579   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 580   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 581   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 582   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 583
 584   /* Set encoder mode */
 585   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 586
 587   /* Write to TIMx CCMR1 */
 588   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 589
 590   /* Write to TIMx CCER */
 591   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 592
 593   return SUCCESS;
 594 }
 595
 596 /**
 597   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 598   *         structure to their default values.
 599   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 600   * @retval None
 601   */
 602 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 603 {
 604   /* Set the default configuration */
 605   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 606   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 607   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 608   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 609 }
 610
 611 /**
 612   * @brief  Configure the Hall sensor interface of the timer instance.
 613   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 614   *       to the TI1 input channel
 615   * @note TIMx slave mode controller is configured in reset mode.
 616           Selected internal trigger is TI1F_ED.
 617   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 618   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 619   *       between 2 changes on the inputs. It gives information about motor speed.
 620   * @note Channel 2 is configured in output PWM 2 mode.
 621   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 622   * @note OC2REF is selected as trigger output on TRGO.
 623   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 624   *       when TIMx operates in Hall sensor interface mode.
 625   * @param  TIMx Timer Instance
 626   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 627   * @retval An ErrorStatus enumeration value:
 628   *          - SUCCESS: TIMx registers are de-initialized
 629   *          - ERROR: not applicable
 630   */
 631 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 632 {
 633   uint32_t tmpcr2;
 634   uint32_t tmpccmr1;
 635   uint32_t tmpccer;
 636   uint32_t tmpsmcr;
 637
 638   /* Check the parameters */
 639   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 640   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 641   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 642   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 643
 644   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 645   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 646
 647   /* Get the TIMx CR2 register value */
 648   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 649
 650   /* Get the TIMx CCMR1 register value */
 651   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 652
 653   /* Get the TIMx CCER register value */
 654   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 655
 656   /* Get the TIMx SMCR register value */
 657   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 658
 659   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 660   tmpcr2 |= TIM_CR2_TI1S;
 661
 662   /* OC2REF signal is used as trigger output (TRGO) */
 663   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 664
 665   /* Configure the slave mode controller */
 666   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 667   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 668   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 669
 670   /* Configure input channel 1 */
 671   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 672   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 673   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 674   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 675
 676   /* Configure input channel 2 */
 677   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 678   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 679
 680   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 681   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 682   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 683   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 684
 685   /* Write to TIMx CR2 */
 686   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 687
 688   /* Write to TIMx SMCR */
 689   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 690
 691   /* Write to TIMx CCMR1 */
 692   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 693
 694   /* Write to TIMx CCER */
 695   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 696
 697   /* Write to TIMx CCR2 */
 698   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 699
 700   return SUCCESS;
 701 }
 702
 703 /**
 704   * @brief  Set the fields of the Break and Dead Time configuration data structure
 705   *         to their default values.
 706   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 707   * @retval None
 708   */
 709 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 710 {
 711   /* Set the default configuration */
 712   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 713   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 714   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 715   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
 716   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 717   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 718   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
 719   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
 720   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
 721   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
 722   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 723 }
 724
 725 /**
 726   * @brief  Configure the Break and Dead Time feature of the timer instance.
 727   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
 728   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
 729   *  can be necessary to configure all of them during the first write access to
 730   *  the TIMx_BDTR register.
 731   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 732   *       a timer instance provides a break input.
 733   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
 734   *       a timer instance provides a second break input.
 735   * @param  TIMx Timer Instance
 736   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 737   * @retval An ErrorStatus enumeration value:
 738   *          - SUCCESS: Break and Dead Time is initialized
 739   *          - ERROR: not applicable
 740   */
 741 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 742 {
 743   uint32_t tmpbdtr = 0;
 744
 745   /* Check the parameters */
 746   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 747   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 748   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 749   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 750   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 751   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 752   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 753
 754   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 755   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 756
 757   /* Set the BDTR bits */
 758   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 759   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 760   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 761   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 762   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 763   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 764   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 765   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 766   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
 767   {
 768     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
 769     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
 770   }
 771
 772   if (IS_TIM_BKIN2_INSTANCE(TIMx))
 773   {
 774     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
 775     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
 776     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
 777
 778     /* Set the BREAK2 input related BDTR bit-fields */
 779     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
 780     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
 781     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
 782   }
 783
 784   /* Set TIMx_BDTR */
 785   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 786
 787   return SUCCESS;
 788 }
 789 /**
 790   * @}
 791   */
 792
 793 /**
 794   * @}
 795   */
 796
 797 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 798  *  @brief   Private functions
 799   * @{
 800   */
 801 /**
 802   * @brief  Configure the TIMx output channel 1.
 803   * @param  TIMx Timer Instance
 804   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 805   * @retval An ErrorStatus enumeration value:
 806   *          - SUCCESS: TIMx registers are de-initialized
 807   *          - ERROR: not applicable
 808   */
 809 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 810 {
 811   uint32_t tmpccmr1;
 812   uint32_t tmpccer;
 813   uint32_t tmpcr2;
 814
 815   /* Check the parameters */
 816   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 817   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 818   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 819   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 820   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 821   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 822
 823   /* Disable the Channel 1: Reset the CC1E Bit */
 824   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 825
 826   /* Get the TIMx CCER register value */
 827   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 828
 829   /* Get the TIMx CR2 register value */
 830   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 831
 832   /* Get the TIMx CCMR1 register value */
 833   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 834
 835   /* Reset Capture/Compare selection Bits */
 836   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 837
 838   /* Set the Output Compare Mode */
 839   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 840
 841   /* Set the Output Compare Polarity */
 842   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 843
 844   /* Set the Output State */
 845   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 846
 847   if (IS_TIM_BREAK_INSTANCE(TIMx))
 848   {
 849     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 850     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 851
 852     /* Set the complementary output Polarity */
 853     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 854
 855     /* Set the complementary output State */
 856     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 857
 858     /* Set the Output Idle state */
 859     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 860
 861     /* Set the complementary output Idle state */
 862     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 863   }
 864
 865   /* Write to TIMx CR2 */
 866   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 867
 868   /* Write to TIMx CCMR1 */
 869   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 870
 871   /* Set the Capture Compare Register value */
 872   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 873
 874   /* Write to TIMx CCER */
 875   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 876
 877   return SUCCESS;
 878 }
 879
 880 /**
 881   * @brief  Configure the TIMx output channel 2.
 882   * @param  TIMx Timer Instance
 883   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 884   * @retval An ErrorStatus enumeration value:
 885   *          - SUCCESS: TIMx registers are de-initialized
 886   *          - ERROR: not applicable
 887   */
 888 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 889 {
 890   uint32_t tmpccmr1;
 891   uint32_t tmpccer;
 892   uint32_t tmpcr2;
 893
 894   /* Check the parameters */
 895   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 896   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 897   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 898   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 899   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 900   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 901
 902   /* Disable the Channel 2: Reset the CC2E Bit */
 903   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 904
 905   /* Get the TIMx CCER register value */
 906   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 907
 908   /* Get the TIMx CR2 register value */
 909   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 910
 911   /* Get the TIMx CCMR1 register value */
 912   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 913
 914   /* Reset Capture/Compare selection Bits */
 915   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 916
 917   /* Select the Output Compare Mode */
 918   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 919
 920   /* Set the Output Compare Polarity */
 921   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 922
 923   /* Set the Output State */
 924   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 925
 926   if (IS_TIM_BREAK_INSTANCE(TIMx))
 927   {
 928     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 929     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 930
 931     /* Set the complementary output Polarity */
 932     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 933
 934     /* Set the complementary output State */
 935     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 936
 937     /* Set the Output Idle state */
 938     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 939
 940     /* Set the complementary output Idle state */
 941     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 942   }
 943
 944   /* Write to TIMx CR2 */
 945   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 946
 947   /* Write to TIMx CCMR1 */
 948   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 949
 950   /* Set the Capture Compare Register value */
 951   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 952
 953   /* Write to TIMx CCER */
 954   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 955
 956   return SUCCESS;
 957 }
 958
 959 /**
 960   * @brief  Configure the TIMx output channel 3.
 961   * @param  TIMx Timer Instance
 962   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 963   * @retval An ErrorStatus enumeration value:
 964   *          - SUCCESS: TIMx registers are de-initialized
 965   *          - ERROR: not applicable
 966   */
 967 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 968 {
 969   uint32_t tmpccmr2;
 970   uint32_t tmpccer;
 971   uint32_t tmpcr2;
 972
 973   /* Check the parameters */
 974   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 975   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 976   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 977   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 978   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 979   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 980
 981   /* Disable the Channel 3: Reset the CC3E Bit */
 982   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
 983
 984   /* Get the TIMx CCER register value */
 985   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 986
 987   /* Get the TIMx CR2 register value */
 988   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 989
 990   /* Get the TIMx CCMR2 register value */
 991   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
 992
 993   /* Reset Capture/Compare selection Bits */
 994   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
 995
 996   /* Select the Output Compare Mode */
 997   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
 998
 999   /* Set the Output Compare Polarity */
1000   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1001
1002   /* Set the Output State */
1003   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1004
1005   if (IS_TIM_BREAK_INSTANCE(TIMx))
1006   {
1007     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1008     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1009
1010     /* Set the complementary output Polarity */
1011     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1012
1013     /* Set the complementary output State */
1014     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1015
1016     /* Set the Output Idle state */
1017     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1018
1019     /* Set the complementary output Idle state */
1020     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1021   }
1022
1023   /* Write to TIMx CR2 */
1024   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1025
1026   /* Write to TIMx CCMR2 */
1027   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1028
1029   /* Set the Capture Compare Register value */
1030   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1031
1032   /* Write to TIMx CCER */
1033   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1034
1035   return SUCCESS;
1036 }
1037
1038 /**
1039   * @brief  Configure the TIMx output channel 4.
1040   * @param  TIMx Timer Instance
1041   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1042   * @retval An ErrorStatus enumeration value:
1043   *          - SUCCESS: TIMx registers are de-initialized
1044   *          - ERROR: not applicable
1045   */
1046 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1047 {
1048   uint32_t tmpccmr2;
1049   uint32_t tmpccer;
1050   uint32_t tmpcr2;
1051
1052   /* Check the parameters */
1053   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1054   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1055   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1056   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1057   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1058   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1059
1060   /* Disable the Channel 4: Reset the CC4E Bit */
1061   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1062
1063   /* Get the TIMx CCER register value */
1064   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1065
1066   /* Get the TIMx CR2 register value */
1067   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1068
1069   /* Get the TIMx CCMR2 register value */
1070   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1071
1072   /* Reset Capture/Compare selection Bits */
1073   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1074
1075   /* Select the Output Compare Mode */
1076   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1077
1078   /* Set the Output Compare Polarity */
1079   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1080
1081   /* Set the Output State */
1082   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1083
1084   if (IS_TIM_BREAK_INSTANCE(TIMx))
1085   {
1086     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1087     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1088
1089     /* Set the Output Idle state */
1090     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1091   }
1092
1093   /* Write to TIMx CR2 */
1094   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1095
1096   /* Write to TIMx CCMR2 */
1097   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1098
1099   /* Set the Capture Compare Register value */
1100   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1101
1102   /* Write to TIMx CCER */
1103   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1104
1105   return SUCCESS;
1106 }
1107
1108 /**
1109   * @brief  Configure the TIMx output channel 5.
1110   * @param  TIMx Timer Instance
1111   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1112   * @retval An ErrorStatus enumeration value:
1113   *          - SUCCESS: TIMx registers are de-initialized
1114   *          - ERROR: not applicable
1115   */
1116 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1117 {
1118   uint32_t tmpccmr3;
1119   uint32_t tmpccer;
1120
1121   /* Check the parameters */
1122   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1123   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1124   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1125   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1126   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1127   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1128
1129   /* Disable the Channel 5: Reset the CC5E Bit */
1130   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1131
1132   /* Get the TIMx CCER register value */
1133   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1134
1135   /* Get the TIMx CCMR3 register value */
1136   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1137
1138   /* Select the Output Compare Mode */
1139   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1140
1141   /* Set the Output Compare Polarity */
1142   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1143
1144   /* Set the Output State */
1145   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1146
1147   if (IS_TIM_BREAK_INSTANCE(TIMx))
1148   {
1149     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1150     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1151
1152     /* Set the Output Idle state */
1153     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1154
1155   }
1156
1157   /* Write to TIMx CCMR3 */
1158   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1159
1160   /* Set the Capture Compare Register value */
1161   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1162
1163   /* Write to TIMx CCER */
1164   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1165
1166   return SUCCESS;
1167 }
1168
1169 /**
1170   * @brief  Configure the TIMx output channel 6.
1171   * @param  TIMx Timer Instance
1172   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1173   * @retval An ErrorStatus enumeration value:
1174   *          - SUCCESS: TIMx registers are de-initialized
1175   *          - ERROR: not applicable
1176   */
1177 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1178 {
1179   uint32_t tmpccmr3;
1180   uint32_t tmpccer;
1181
1182   /* Check the parameters */
1183   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1184   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1185   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1186   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1187   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1188   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1189
1190   /* Disable the Channel 5: Reset the CC6E Bit */
1191   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1192
1193   /* Get the TIMx CCER register value */
1194   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1195
1196   /* Get the TIMx CCMR3 register value */
1197   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1198
1199   /* Select the Output Compare Mode */
1200   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1201
1202   /* Set the Output Compare Polarity */
1203   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1204
1205   /* Set the Output State */
1206   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1207
1208   if (IS_TIM_BREAK_INSTANCE(TIMx))
1209   {
1210     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1211     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1212
1213     /* Set the Output Idle state */
1214     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1215   }
1216
1217   /* Write to TIMx CCMR3 */
1218   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1219
1220   /* Set the Capture Compare Register value */
1221   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1222
1223   /* Write to TIMx CCER */
1224   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1225
1226   return SUCCESS;
1227 }
1228
1229 /**
1230   * @brief  Configure the TIMx input channel 1.
1231   * @param  TIMx Timer Instance
1232   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1233   * @retval An ErrorStatus enumeration value:
1234   *          - SUCCESS: TIMx registers are de-initialized
1235   *          - ERROR: not applicable
1236   */
1237 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1238 {
1239   /* Check the parameters */
1240   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1241   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1242   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1243   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1244   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1245
1246   /* Disable the Channel 1: Reset the CC1E Bit */
1247   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1248
1249   /* Select the Input and set the filter and the prescaler value */
1250   MODIFY_REG(TIMx->CCMR1,
1251              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1252              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1253
1254   /* Select the Polarity and set the CC1E Bit */
1255   MODIFY_REG(TIMx->CCER,
1256              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1257              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1258
1259   return SUCCESS;
1260 }
1261
1262 /**
1263   * @brief  Configure the TIMx input channel 2.
1264   * @param  TIMx Timer Instance
1265   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1266   * @retval An ErrorStatus enumeration value:
1267   *          - SUCCESS: TIMx registers are de-initialized
1268   *          - ERROR: not applicable
1269   */
1270 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1271 {
1272   /* Check the parameters */
1273   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1274   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1275   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1276   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1277   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1278
1279   /* Disable the Channel 2: Reset the CC2E Bit */
1280   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1281
1282   /* Select the Input and set the filter and the prescaler value */
1283   MODIFY_REG(TIMx->CCMR1,
1284              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1285              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1286
1287   /* Select the Polarity and set the CC2E Bit */
1288   MODIFY_REG(TIMx->CCER,
1289              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1290              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1291
1292   return SUCCESS;
1293 }
1294
1295 /**
1296   * @brief  Configure the TIMx input channel 3.
1297   * @param  TIMx Timer Instance
1298   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1299   * @retval An ErrorStatus enumeration value:
1300   *          - SUCCESS: TIMx registers are de-initialized
1301   *          - ERROR: not applicable
1302   */
1303 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1304 {
1305   /* Check the parameters */
1306   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1307   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1308   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1309   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1310   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1311
1312   /* Disable the Channel 3: Reset the CC3E Bit */
1313   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1314
1315   /* Select the Input and set the filter and the prescaler value */
1316   MODIFY_REG(TIMx->CCMR2,
1317              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1318              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1319
1320   /* Select the Polarity and set the CC3E Bit */
1321   MODIFY_REG(TIMx->CCER,
1322              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1323              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1324
1325   return SUCCESS;
1326 }
1327
1328 /**
1329   * @brief  Configure the TIMx input channel 4.
1330   * @param  TIMx Timer Instance
1331   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1332   * @retval An ErrorStatus enumeration value:
1333   *          - SUCCESS: TIMx registers are de-initialized
1334   *          - ERROR: not applicable
1335   */
1336 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1337 {
1338   /* Check the parameters */
1339   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1340   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1341   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1342   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1343   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1344
1345   /* Disable the Channel 4: Reset the CC4E Bit */
1346   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1347
1348   /* Select the Input and set the filter and the prescaler value */
1349   MODIFY_REG(TIMx->CCMR2,
1350              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1351              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1352
1353   /* Select the Polarity and set the CC2E Bit */
1354   MODIFY_REG(TIMx->CCER,
1355              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1356              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1357
1358   return SUCCESS;
1359 }
1360
1361
1362 /**
1363   * @}
1364   */
1365
1366 /**
1367   * @}
1368   */
1369
1370 #endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
1371
1372 /**
1373   * @}
1374   */
1375
1376 #endif /* USE_FULL_LL_DRIVER */
1377
1378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/