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Updated and Validated
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_utils.c
blob0717d8970abf32dd0a07208d6a10dc02d2515dc9
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f7xx_ll_utils.h"
21 #include "stm32f7xx_ll_rcc.h"
22 #include "stm32f7xx_ll_system.h"
23 #include "stm32f7xx_ll_pwr.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 /** @addtogroup UTILS_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44 #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
46 #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
47
48 /* Defines used for PLL range */
49 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
50 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
51 #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
52 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
53
54 /* Defines used for HSE range */
55 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
56 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
57
58 /* Defines used for FLASH latency according to HCLK Frequency */
59 #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
60 #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
61 #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
62 #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
63 #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
64 #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
65 #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
66 #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
67 #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
68 #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
69 #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
70 #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
71 #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
72 #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
73 #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
74 #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
75 /**
76 * @}
77 */
78
79 /* Private macros ------------------------------------------------------------*/
80 /** @addtogroup UTILS_LL_Private_Macros
81 * @{
82 */
83 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
84 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
85 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
86 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
87 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
88 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
89 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
90 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
91 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
92
93 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
94 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
95 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
96 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
97 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
98
99 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
100 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
101 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
102 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
103 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
104
105 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
106 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
107 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
108 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
109 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
110 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
111 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
112 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
113 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
114 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
115 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
116 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
117 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
118 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
119 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
120 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
121 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
122 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
123 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
124 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
125 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
126 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
127 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
128 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
129 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
130 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
131 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
132 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
133 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
134 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
167
168 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
169
170 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
171 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
172 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
173 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
174
175 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
176
177 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
178
179 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
180 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
181 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
182
183 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
184 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
185
186 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
187 /**
188 * @}
189 */
190 /* Private function prototypes -----------------------------------------------*/
191 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
192 * @{
193 */
194 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
195 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
196 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
197 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
198 static ErrorStatus UTILS_PLL_IsBusy(void);
199 /**
200 * @}
201 */
202
203 /* Exported functions --------------------------------------------------------*/
204 /** @addtogroup UTILS_LL_Exported_Functions
205 * @{
206 */
207
208 /** @addtogroup UTILS_LL_EF_DELAY
209 * @{
210 */
211
212 /**
213 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
214 * @note When a RTOS is used, it is recommended to avoid changing the Systick
215 * configuration by calling this function, for a delay use rather osDelay RTOS service.
216 * @param HCLKFrequency HCLK frequency in Hz
217 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
218 * @retval None
219 */
220 void LL_Init1msTick(uint32_t HCLKFrequency)
221 {
222 /* Use frequency provided in argument */
223 LL_InitTick(HCLKFrequency, 1000U);
224 }
225
226 /**
227 * @brief This function provides accurate delay (in milliseconds) based
228 * on SysTick counter flag
229 * @note When a RTOS is used, it is recommended to avoid using blocking delay
230 * and use rather osDelay service.
231 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
232 * will configure Systick to 1ms
233 * @param Delay specifies the delay time length, in milliseconds.
234 * @retval None
235 */
236 void LL_mDelay(uint32_t Delay)
237 {
238 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
239 /* Add this code to indicate that local variable is not used */
240 ((void)tmp);
241
242 /* Add a period to guaranty minimum wait */
243 if(Delay < LL_MAX_DELAY)
244 {
245 Delay++;
246 }
247
248 while (Delay)
249 {
250 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
251 {
252 Delay--;
253 }
254 }
255 }
256
257 /**
258 * @}
259 */
260
261 /** @addtogroup UTILS_EF_SYSTEM
262 * @brief System Configuration functions
263 *
264 @verbatim
265 ===============================================================================
266 ##### System Configuration functions #####
267 ===============================================================================
268 [..]
269 System, AHB and APB buses clocks configuration
270
271 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
272 @endverbatim
273 @internal
274 Depending on the device voltage range, the maximum frequency should be
275 adapted accordingly:
276 (++) +------------------------------------------------------------------------------------------------+
277 (++) | Wait states | HCLK clock frequency (MHz) |
278 (++) | |-------------------------------------------------------------------------------|
279 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
280 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
281 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
282 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
283 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
284 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
285 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
286 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
287 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
288 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
289 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
290 (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
291 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
292 (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
293 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
294 (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
295 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
296 (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
297 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
298 (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
299 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
300 (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
301 (++) +------------------------------------------------------------------------------------------------+
302
303 @endinternal
304 * @{
305 */
306
307 /**
308 * @brief This function sets directly SystemCoreClock CMSIS variable.
309 * @note Variable can be calculated also through SystemCoreClockUpdate function.
310 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
311 * @retval None
312 */
313 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
314 {
315 /* HCLK clock frequency */
316 SystemCoreClock = HCLKFrequency;
317 }
318
319 /**
320 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
321 * @note The application need to ensure that PLL is disabled.
322 * @note Function is based on the following formula:
323 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
324 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
325 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
326 * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
327 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
328 * the configuration information for the PLL.
329 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
330 * the configuration information for the BUS prescalers.
331 * @retval An ErrorStatus enumeration value:
332 * - SUCCESS: Max frequency configuration done
333 * - ERROR: Max frequency configuration not done
334 */
335 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
336 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
337 {
338 ErrorStatus status = SUCCESS;
339 uint32_t pllfreq = 0U;
340
341 /* Check if one of the PLL is enabled */
342 if(UTILS_PLL_IsBusy() == SUCCESS)
343 {
344 /* Calculate the new PLL output frequency */
345 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
346
347 /* Enable HSI if not enabled */
348 if(LL_RCC_HSI_IsReady() != 1U)
349 {
350 LL_RCC_HSI_Enable();
351 while (LL_RCC_HSI_IsReady() != 1U)
352 {
353 /* Wait for HSI ready */
354 }
355 }
356
357 /* Configure PLL */
358 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
359 UTILS_PLLInitStruct->PLLP);
360
361 /* Enable PLL and switch system clock to PLL */
362 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
363 }
364 else
365 {
366 /* Current PLL configuration cannot be modified */
367 status = ERROR;
368 }
369
370 return status;
371 }
372
373 /**
374 * @brief This function configures system clock with HSE as clock source of the PLL
375 * @note The application need to ensure that PLL is disabled.
376 * @note Function is based on the following formula:
377 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
378 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
379 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
380 * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
381 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
382 * @param HSEBypass This parameter can be one of the following values:
383 * @arg @ref LL_UTILS_HSEBYPASS_ON
384 * @arg @ref LL_UTILS_HSEBYPASS_OFF
385 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
386 * the configuration information for the PLL.
387 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
388 * the configuration information for the BUS prescalers.
389 * @retval An ErrorStatus enumeration value:
390 * - SUCCESS: Max frequency configuration done
391 * - ERROR: Max frequency configuration not done
392 */
393 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
394 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
395 {
396 ErrorStatus status = SUCCESS;
397 uint32_t pllfreq = 0U;
398
399 /* Check the parameters */
400 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
401 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
402
403 /* Check if one of the PLL is enabled */
404 if(UTILS_PLL_IsBusy() == SUCCESS)
405 {
406 /* Calculate the new PLL output frequency */
407 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
408
409 /* Enable HSE if not enabled */
410 if(LL_RCC_HSE_IsReady() != 1U)
411 {
412 /* Check if need to enable HSE bypass feature or not */
413 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
414 {
415 LL_RCC_HSE_EnableBypass();
416 }
417 else
418 {
419 LL_RCC_HSE_DisableBypass();
420 }
421
422 /* Enable HSE */
423 LL_RCC_HSE_Enable();
424 while (LL_RCC_HSE_IsReady() != 1U)
425 {
426 /* Wait for HSE ready */
427 }
428 }
429
430 /* Configure PLL */
431 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
432 UTILS_PLLInitStruct->PLLP);
433
434 /* Enable PLL and switch system clock to PLL */
435 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
436 }
437 else
438 {
439 /* Current PLL configuration cannot be modified */
440 status = ERROR;
441 }
442
443 return status;
444 }
445
446 /**
447 * @}
448 */
449
450 /**
451 * @}
452 */
453
454 /** @addtogroup UTILS_LL_Private_Functions
455 * @{
456 */
457 /**
458 * @brief Update number of Flash wait states in line with new frequency and current
459 voltage range.
460 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
461 * @param HCLK_Frequency HCLK frequency
462 * @retval An ErrorStatus enumeration value:
463 * - SUCCESS: Latency has been modified
464 * - ERROR: Latency cannot be modified
465 */
466 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
467 {
468 ErrorStatus status = SUCCESS;
469
470 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
471
472 /* Frequency cannot be equal to 0 */
473 if(HCLK_Frequency == 0U)
474 {
475 status = ERROR;
476 }
477 else
478 {
479 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
480 {
481 if(LL_PWR_IsEnabledOverDriveMode() != 0U)
482 {
483 if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
484 {
485 /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
486 latency = LL_FLASH_LATENCY_7;
487 }
488 else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
489 {
490 /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
491 latency = LL_FLASH_LATENCY_6;
492 }
493 }
494 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
495 {
496 /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
497 latency = LL_FLASH_LATENCY_5;
498 }
499 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
500 {
501 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
502 latency = LL_FLASH_LATENCY_4;
503 }
504 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
505 {
506 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
507 latency = LL_FLASH_LATENCY_3;
508 }
509 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
510 {
511 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
512 latency = LL_FLASH_LATENCY_2;
513 }
514 else
515 {
516 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
517 {
518 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
519 latency = LL_FLASH_LATENCY_1;
520 }
521 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
522 }
523 }
524 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
525 {
526 if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
527 {
528 /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
529 latency = LL_FLASH_LATENCY_5;
530 }
531 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
532 {
533 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
534 latency = LL_FLASH_LATENCY_4;
535 }
536 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
537 {
538 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
539 latency = LL_FLASH_LATENCY_3;
540 }
541 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
542 {
543 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
544 latency = LL_FLASH_LATENCY_2;
545 }
546 else
547 {
548 if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
549 {
550 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
551 latency = LL_FLASH_LATENCY_1;
552 }
553 /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
554 }
555 }
556 else /* Scale 3 */
557 {
558 if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
559 {
560 /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
561 latency = LL_FLASH_LATENCY_4;
562 }
563 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
564 {
565 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
566 latency = LL_FLASH_LATENCY_3;
567 }
568 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
569 {
570 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
571 latency = LL_FLASH_LATENCY_2;
572 }
573 else
574 {
575 if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
576 {
577 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
578 latency = LL_FLASH_LATENCY_1;
579 }
580 /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
581 }
582 }
583
584 LL_FLASH_SetLatency(latency);
585
586 /* Check that the new number of wait states is taken into account to access the Flash
587 memory by reading the FLASH_ACR register */
588 if(LL_FLASH_GetLatency() != latency)
589 {
590 status = ERROR;
591 }
592 }
593 return status;
594 }
595
596 /**
597 * @brief Function to check that PLL can be modified
598 * @param PLL_InputFrequency PLL input frequency (in Hz)
599 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
600 * the configuration information for the PLL.
601 * @retval PLL output frequency (in Hz)
602 */
603 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
604 {
605 uint32_t pllfreq = 0U;
606
607 /* Check the parameters */
608 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
609 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
610 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
611
612 /* Check different PLL parameters according to RM */
613 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
614 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
615 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
616
617 /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
618 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
619 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
620
621 /* - PLLP: ensure that max frequency at 216000000 Hz is reached */
622 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
623 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
624
625 return pllfreq;
626 }
627
628 /**
629 * @brief Function to check that PLL can be modified
630 * @retval An ErrorStatus enumeration value:
631 * - SUCCESS: PLL modification can be done
632 * - ERROR: PLL is busy
633 */
634 static ErrorStatus UTILS_PLL_IsBusy(void)
635 {
636 ErrorStatus status = SUCCESS;
637
638 /* Check if PLL is busy*/
639 if(LL_RCC_PLL_IsReady() != 0U)
640 {
641 /* PLL configuration cannot be modified */
642 status = ERROR;
643 }
644
645 /* Check if PLLSAI is busy*/
646 if(LL_RCC_PLLSAI_IsReady() != 0U)
647 {
648 /* PLLSAI1 configuration cannot be modified */
649 status = ERROR;
650 }
651 /* Check if PLLI2S is busy*/
652 if(LL_RCC_PLLI2S_IsReady() != 0U)
653 {
654 /* PLLI2S configuration cannot be modified */
655 status = ERROR;
656 }
657 return status;
658 }
659
660 /**
661 * @brief Function to enable PLL and switch system clock to PLL
662 * @param SYSCLK_Frequency SYSCLK frequency
663 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
664 * the configuration information for the BUS prescalers.
665 * @retval An ErrorStatus enumeration value:
666 * - SUCCESS: No problem to switch system to PLL
667 * - ERROR: Problem to switch system to PLL
668 */
669 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
670 {
671 ErrorStatus status = SUCCESS;
672 uint32_t hclk_frequency = 0U;
673
674 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
675 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
676 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
677
678 /* Calculate HCLK frequency */
679 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
680
681 /* Increasing the number of wait states because of higher CPU frequency */
682 if(SystemCoreClock < hclk_frequency)
683 {
684 /* Set FLASH latency to highest latency */
685 status = UTILS_SetFlashLatency(hclk_frequency);
686 }
687
688 /* Update system clock configuration */
689 if(status == SUCCESS)
690 {
691 /* Enable PLL */
692 LL_RCC_PLL_Enable();
693 while (LL_RCC_PLL_IsReady() != 1U)
694 {
695 /* Wait for PLL ready */
696 }
697
698 /* Sysclk activation on the main PLL */
699 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
700 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
701 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
702 {
703 /* Wait for system clock switch to PLL */
704 }
705
706 /* Set APB1 & APB2 prescaler*/
707 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
708 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
709 }
710
711 /* Decreasing the number of wait states because of lower CPU frequency */
712 if(SystemCoreClock > hclk_frequency)
713 {
714 /* Set FLASH latency to lowest latency */
715 status = UTILS_SetFlashLatency(hclk_frequency);
716 }
717
718 /* Update SystemCoreClock variable */
719 if(status == SUCCESS)
720 {
721 LL_SetSystemCoreClock(hclk_frequency);
722 }
723
724 return status;
725 }
726
727 /**
728 * @}
729 */
730
731 /**
732 * @}
733 */
734
735 /**
736 * @}
737 */
738
739 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/