lib/main/STM32F1/Drivers/CMSIS/Device/ST/STM32F10x/system_stm32f10x.c

   1 #include <stdbool.h>
   2 #include "stm32f10x.h"
   3
   4 #define SYSCLK_FREQ_72MHz  72000000
   5
   6 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz;   /*!< System Clock Frequency (Core Clock) */
   7
   8 static const uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
   9
  10 uint32_t hse_value = 8000000;
  11
  12 void SystemInit(void)
  13 {
  14     /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  15     /* Set HSION bit */
  16     RCC->CR |= (uint32_t) 0x00000001;
  17
  18     /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
  19     RCC->CFGR &= (uint32_t) 0xF8FF0000;
  20
  21     /* Reset HSEON, CSSON and PLLON bits */
  22     RCC->CR &= (uint32_t) 0xFEF6FFFF;
  23
  24     /* Reset HSEBYP bit */
  25     RCC->CR &= (uint32_t) 0xFFFBFFFF;
  26
  27     /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  28     RCC->CFGR &= (uint32_t) 0xFF80FFFF;
  29
  30     /* Disable all interrupts and clear pending bits  */
  31     RCC->CIR = 0x009F0000;
  32
  33     SCB->VTOR = FLASH_BASE;     /* Vector Table Relocation in Internal FLASH. */
  34 }
  35
  36 void SystemCoreClockUpdate(void)
  37 {
  38     uint32_t tmp = 0, pllmull = 0, pllsource = 0;
  39
  40     /* Get SYSCLK source ------------------------------------------------------- */
  41     tmp = RCC->CFGR & RCC_CFGR_SWS;
  42
  43     switch (tmp) {
  44         case 0x00:                 /* HSI used as system clock */
  45             SystemCoreClock = HSI_VALUE;
  46             break;
  47         case 0x04:                 /* HSE used as system clock */
  48             SystemCoreClock = hse_value;
  49             break;
  50         case 0x08:                 /* PLL used as system clock */
  51
  52             /* Get PLL clock source and multiplication factor ---------------------- */
  53             pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
  54             pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
  55
  56             pllmull = (pllmull >> 18) + 2;
  57
  58             if (pllsource == 0x00) {
  59                 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  60                 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
  61             } else {
  62                 /* HSE selected as PLL clock entry */
  63                 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t) RESET) {  /* HSE oscillator clock divided by 2 */
  64                     SystemCoreClock = (hse_value >> 1) * pllmull;
  65                 } else {
  66                     SystemCoreClock = hse_value * pllmull;
  67                 }
  68             }
  69             break;
  70
  71         default:
  72             SystemCoreClock = HSI_VALUE;
  73             break;
  74     }
  75
  76     /* Compute HCLK clock frequency ---------------- */
  77     /* Get HCLK prescaler */
  78     tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  79     /* HCLK clock frequency */
  80     SystemCoreClock >>= tmp;
  81 }
  82
  83 enum {
  84     SRC_NONE = 0,
  85     SRC_HSI,
  86     SRC_HSE
  87 };
  88
  89 // Set system clock to 72 (HSE) or 64 (HSI) MHz
  90 void SetSysClock(bool overclock)
  91 {
  92     __IO uint32_t StartUpCounter = 0, status = 0, clocksrc = SRC_NONE;
  93     __IO uint32_t *RCC_CRH = &GPIOC->CRH;
  94     __IO uint32_t RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
  95
  96     // First, try running off HSE
  97     RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  98     RCC->APB2ENR |= RCC_CFGR_HPRE_0;
  99
 100     // Wait till HSE is ready
 101     do {
 102         status = RCC->CR & RCC_CR_HSERDY;
 103         StartUpCounter++;
 104     } while ((status == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 105
 106     if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
 107         // external xtal started up, we're good to go
 108         clocksrc = SRC_HSE;
 109     } else {
 110         // If HSE fails to start-up, try to enable HSI and configure for 64MHz operation
 111         RCC->CR |= ((uint32_t)RCC_CR_HSION);
 112         StartUpCounter = 0;
 113         do {
 114             status = RCC->CR & RCC_CR_HSIRDY;
 115             StartUpCounter++;
 116         } while ((status == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 117         if ((RCC->CR & RCC_CR_HSIRDY) != RESET) {
 118             // we're on internal RC
 119             clocksrc = SRC_HSI;
 120         } else {
 121             while(1); // Unable to continue.
 122         }
 123     }
 124
 125     // Enable Prefetch Buffer
 126     FLASH->ACR |= FLASH_ACR_PRFTBE;
 127     // Flash 2 wait state
 128     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
 129     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 130     // HCLK = SYSCLK
 131     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 132     // PCLK2 = HCLK
 133     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 134     // PCLK1 = HCLK
 135     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
 136     *RCC_CRH &= (uint32_t)~((uint32_t)0xF << (RCC_CFGR_PLLMULL9 >> 16));
 137
 138     // Configure PLL
 139     hse_value = 8000000;
 140     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 141     *RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
 142     GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
 143
 144 #if defined(CJMCU)
 145     // On CJMCU new revision boards (Late 2014) bit 15 of GPIOC->IDR is '1'.
 146     RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
 147 #else
 148     RCC_CFGR_PLLMUL = GPIOC->IDR & GPIO_IDR_IDR15 ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
 149 #endif
 150     switch (clocksrc) {
 151         case SRC_HSE:
 152             if (overclock) {
 153                 if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL6)
 154                     RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL7;
 155                 else if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL9)
 156                     RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL10;
 157             }
 158             // overclock=false : PLL configuration: PLLCLK = HSE * 9 = 72 MHz || HSE * 6 = 72 MHz
 159             // overclock=true  : PLL configuration: PLLCLK = HSE * 10 = 80 MHz || HSE * 7 = 84 MHz
 160             RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL);
 161             break;
 162         case SRC_HSI:
 163             // PLL configuration: PLLCLK = HSI / 2 * 16 = 64 MHz
 164             RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16);
 165             break;
 166     }
 167
 168     // Enable PLL
 169     RCC->CR |= RCC_CR_PLLON;
 170     // Wait till PLL is ready
 171     while ((RCC->CR & RCC_CR_PLLRDY) == 0);
 172     // Select PLL as system clock source
 173     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 174     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 175     // Wait till PLL is used as system clock source
 176     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08);
 177
 178     SystemCoreClockUpdate();
 179 }