lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_adc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    04-April-2014
   7   * @brief   This file contains all the functions prototypes for the ADC firmware
   8   *          library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  13   *
  14   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  15   * You may not use this file except in compliance with the License.
  16   * You may obtain a copy of the License at:
  17   *
  18   *        http://www.st.com/software_license_agreement_liberty_v2
  19   *
  20   * Unless required by applicable law or agreed to in writing, software
  21   * distributed under the License is distributed on an "AS IS" BASIS,
  22   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23   * See the License for the specific language governing permissions and
  24   * limitations under the License.
  25   *
  26   ******************************************************************************
  27   */
  28
  29 /* Define to prevent recursive inclusion -------------------------------------*/
  30 #ifndef __STM32F30x_ADC_H
  31 #define __STM32F30x_ADC_H
  32
  33 #ifdef __cplusplus
  34  extern "C" {
  35 #endif
  36
  37 /* Includes ------------------------------------------------------------------*/
  38 #include "stm32f30x.h"
  39
  40 /** @addtogroup STM32F30x_StdPeriph_Driver
  41   * @{
  42   */
  43
  44 /** @addtogroup ADC
  45   * @{
  46   */
  47
  48 /* Exported types ------------------------------------------------------------*/
  49
  50 /**
  51   * @brief  ADC Init structure definition
  52   */
  53 typedef struct
  54 {
  55
  56   uint32_t ADC_ContinuousConvMode;        /*!< Specifies whether the conversion is performed in
  57                                                Continuous or Single mode.
  58                                                This parameter can be set to ENABLE or DISABLE. */
  59   uint32_t ADC_Resolution;                /*!< Configures the ADC resolution.
  60                                                This parameter can be a value of @ref ADC_resolution */
  61   uint32_t ADC_ExternalTrigConvEvent;      /*!< Defines the external trigger used to start the analog
  62                                                to digital conversion of regular channels. This parameter
  63                                                can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
  64   uint32_t ADC_ExternalTrigEventEdge;      /*!< Select the external trigger edge and enable the trigger of a regular group.
  65                                                This parameter can be a value of
  66                                                @ref ADC_external_trigger_edge_for_regular_channels_conversion */
  67   uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
  68                                                This parameter can be a value of @ref ADC_data_align */
  69   uint32_t ADC_OverrunMode;               /*!< Specifies the way data overrun are managed.
  70                                                This parameter can be set to ENABLE or DISABLE. */
  71   uint32_t ADC_AutoInjMode;               /*!< Enable/disable automatic injected group conversion after
  72                                                regular group conversion.
  73                                                This parameter can be set to ENABLE or DISABLE. */
  74   uint8_t ADC_NbrOfRegChannel;            /*!< Specifies the number of ADC channels that will be converted
  75                                                using the sequencer for regular channel group.
  76                                                This parameter must range from 1 to 16. */
  77 }ADC_InitTypeDef;
  78
  79 /**
  80   * @}
  81   */
  82 /**
  83   * @brief  ADC Init structure definition
  84   */
  85 typedef struct
  86 {
  87
  88    uint32_t ADC_ExternalTrigInjecConvEvent;     /*!< Defines the external trigger used to start the analog
  89                                                      to digital conversion of injected channels. This parameter
  90                                                      can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
  91   uint32_t ADC_ExternalTrigInjecEventEdge;     /*!< Select the external trigger edge and enable the trigger of an injected group.
  92                                                     This parameter can be a value of
  93                                                     @ref ADC_external_trigger_edge_for_Injected_channels_conversion */
  94   uint8_t ADC_NbrOfInjecChannel;               /*!< Specifies the number of ADC channels that will be converted
  95                                                     using the sequencer for injected channel group.
  96                                                     This parameter must range from 1 to 4. */
  97   uint32_t ADC_InjecSequence1;
  98   uint32_t ADC_InjecSequence2;
  99   uint32_t ADC_InjecSequence3;
 100   uint32_t ADC_InjecSequence4;
 101 }ADC_InjectedInitTypeDef;
 102
 103 /**
 104   * @}
 105   */
 106 typedef struct
 107 {
 108   uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in
 109                                                independent or multi mode.
 110                                                This parameter can be a value of @ref ADC_mode */
 111   uint32_t ADC_Clock;                    /*!< Select the clock of the ADC. The clock is common for both master
 112                                               and slave ADCs.
 113                                               This parameter can be a value of @ref ADC_Clock */
 114   uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access mode for multi ADC mode.
 115                                                This parameter can be a value of
 116                                                @ref ADC_Direct_memory_access_mode_for_multi_mode */
 117   uint32_t ADC_DMAMode;                  /*!< Configures the DMA mode for ADC.
 118                                               This parameter can be a value of @ref ADC_DMA_Mode_definition */
 119   uint8_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
 120                                                This parameter can be a value between  0x0 and 0xF  */
 121
 122 }ADC_CommonInitTypeDef;
 123
 124 /* Exported constants --------------------------------------------------------*/
 125
 126 /** @defgroup ADC_Exported_Constants
 127   * @{
 128   */
 129
 130 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
 131                                    ((PERIPH) == ADC2) || \
 132                                    ((PERIPH) == ADC3) || \
 133                                    ((PERIPH) == ADC4))
 134
 135 #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
 136                                    ((PERIPH) == ADC2) || \
 137                                    ((PERIPH) == ADC3) || \
 138                                    ((PERIPH) == ADC4))
 139
 140 /** @defgroup ADC_ContinuousConvMode
 141   * @{
 142   */
 143 #define ADC_ContinuousConvMode_Enable    ((uint32_t)0x00002000)  /*!<  ADC continuous conversion mode enable */
 144 #define ADC_ContinuousConvMode_Disable   ((uint32_t)0x00000000)  /*!<  ADC continuous conversion mode disable */
 145 #define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
 146                                ((MODE) == ADC_ContinuousConvMode_Disable))
 147 /**
 148   * @}
 149   */
 150 /** @defgroup ADC_OverunMode
 151   * @{
 152   */
 153 #define ADC_OverrunMode_Enable   ((uint32_t)0x00001000)  /*!<  ADC Overrun Mode enable */
 154 #define ADC_OverrunMode_Disable  ((uint32_t)0x00000000)  /*!<  ADC Overrun Mode disable */
 155 #define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
 156                                 ((MODE) == ADC_OverrunMode_Disable))
 157 /**
 158   * @}
 159   */
 160 /** @defgroup ADC_AutoInjecMode
 161   * @{
 162   */
 163 #define ADC_AutoInjec_Enable     ((uint32_t)0x02000000)  /*!<  ADC Auto injected Mode enable */
 164 #define ADC_AutoInjec_Disable    ((uint32_t)0x00000000)  /*!<  ADC Auto injected Mode disable */
 165 #define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
 166                                     ((MODE) == ADC_AutoInjec_Disable))
 167 /**
 168   * @}
 169   */
 170 /** @defgroup ADC_resolution
 171   * @{
 172   */
 173 #define ADC_Resolution_12b                         ((uint32_t)0x00000000)  /*!<  ADC 12-bit resolution */
 174 #define ADC_Resolution_10b                         ((uint32_t)0x00000008)  /*!<  ADC 10-bit resolution */
 175 #define ADC_Resolution_8b                          ((uint32_t)0x00000010)  /*!<  ADC 8-bit resolution */
 176 #define ADC_Resolution_6b                          ((uint32_t)0x00000018)  /*!<  ADC 6-bit resolution */
 177 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
 178                                        ((RESOLUTION) == ADC_Resolution_10b) || \
 179                                        ((RESOLUTION) == ADC_Resolution_8b) || \
 180                                        ((RESOLUTION) == ADC_Resolution_6b))
 181
 182 /**
 183   * @}
 184   */
 185
 186
 187 /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
 188   * @{
 189   */
 190 #define ADC_ExternalTrigEventEdge_None            ((uint16_t)0x0000)     /*!<  ADC No external trigger for regular conversion */
 191 #define ADC_ExternalTrigEventEdge_RisingEdge      ((uint16_t)0x0400)     /*!<  ADC external trigger rising edge for regular conversion */
 192 #define ADC_ExternalTrigEventEdge_FallingEdge     ((uint16_t)0x0800)     /*!<  ADC ADC external trigger falling edge for regular conversion */
 193 #define ADC_ExternalTrigEventEdge_BothEdge        ((uint16_t)0x0C00)     /*!<  ADC ADC external trigger both edges for regular conversion */
 194
 195 #define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
 196                                     ((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
 197                                     ((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
 198                                     ((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
 199
 200 /**
 201   * @}
 202   */
 203
 204 /** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
 205   * @{
 206   */
 207 #define ADC_ExternalTrigInjecEventEdge_None                  ((uint16_t)0x0000)    /*!<  ADC No external trigger for regular conversion */
 208 #define ADC_ExternalTrigInjecEventEdge_RisingEdge        ((uint16_t)0x0040)    /*!<  ADC external trigger rising edge for injected conversion */
 209 #define ADC_ExternalTrigInjecEventEdge_FallingEdge       ((uint16_t)0x0080)  /*!<  ADC external trigger falling edge for injected conversion */
 210 #define ADC_ExternalTrigInjecEventEdge_BothEdge      ((uint16_t)0x00C0)  /*!<  ADC external trigger both edges for injected conversion */
 211
 212 #define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
 213                                        ((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
 214                                        ((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
 215                                        ((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
 216
 217 /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
 218   * @{
 219   */
 220 #define ADC_ExternalTrigConvEvent_0              ((uint16_t)0x0000)   /*!<  ADC external trigger event 0 */
 221 #define ADC_ExternalTrigConvEvent_1              ((uint16_t)0x0040)   /*!<  ADC external trigger event 1 */
 222 #define ADC_ExternalTrigConvEvent_2              ((uint16_t)0x0080)   /*!<  ADC external trigger event 2 */
 223 #define ADC_ExternalTrigConvEvent_3              ((uint16_t)0x00C0)   /*!<  ADC external trigger event 3 */
 224 #define ADC_ExternalTrigConvEvent_4              ((uint16_t)0x0100)   /*!<  ADC external trigger event 4 */
 225 #define ADC_ExternalTrigConvEvent_5              ((uint16_t)0x0140)   /*!<  ADC external trigger event 5 */
 226 #define ADC_ExternalTrigConvEvent_6              ((uint16_t)0x0180)   /*!<  ADC external trigger event 6 */
 227 #define ADC_ExternalTrigConvEvent_7              ((uint16_t)0x01C0)   /*!<  ADC external trigger event 7 */
 228 #define ADC_ExternalTrigConvEvent_8              ((uint16_t)0x0200)   /*!<  ADC external trigger event 8 */
 229 #define ADC_ExternalTrigConvEvent_9              ((uint16_t)0x0240)   /*!<  ADC external trigger event 9 */
 230 #define ADC_ExternalTrigConvEvent_10             ((uint16_t)0x0280)   /*!<  ADC external trigger event 10 */
 231 #define ADC_ExternalTrigConvEvent_11             ((uint16_t)0x02C0)   /*!<  ADC external trigger event 11 */
 232 #define ADC_ExternalTrigConvEvent_12             ((uint16_t)0x0300)   /*!<  ADC external trigger event 12 */
 233 #define ADC_ExternalTrigConvEvent_13             ((uint16_t)0x0340)   /*!<  ADC external trigger event 13 */
 234 #define ADC_ExternalTrigConvEvent_14             ((uint16_t)0x0380)   /*!<  ADC external trigger event 14 */
 235 #define ADC_ExternalTrigConvEvent_15             ((uint16_t)0x03C0)   /*!<  ADC external trigger event 15 */
 236
 237 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
 238                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
 239                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
 240                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
 241                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
 242                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
 243                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
 244                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
 245                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
 246                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
 247                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
 248                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
 249                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
 250                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
 251                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
 252                                   ((REGTRIG) == ADC_ExternalTrigConvEvent_15))
 253
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
 259   * @{
 260   */
 261
 262 #define ADC_ExternalTrigInjecConvEvent_0              ((uint16_t)0x0000)  /*!<  ADC external trigger for injected conversion event 0 */
 263 #define ADC_ExternalTrigInjecConvEvent_1              ((uint16_t)0x0004)  /*!<  ADC external trigger for injected conversion event 1 */
 264 #define ADC_ExternalTrigInjecConvEvent_2              ((uint16_t)0x0008)  /*!<  ADC external trigger for injected conversion event 2 */
 265 #define ADC_ExternalTrigInjecConvEvent_3              ((uint16_t)0x000C)  /*!<  ADC external trigger for injected conversion event 3 */
 266 #define ADC_ExternalTrigInjecConvEvent_4              ((uint16_t)0x0010)  /*!<  ADC external trigger for injected conversion event 4 */
 267 #define ADC_ExternalTrigInjecConvEvent_5              ((uint16_t)0x0014)  /*!<  ADC external trigger for injected conversion event 5 */
 268 #define ADC_ExternalTrigInjecConvEvent_6              ((uint16_t)0x0018)  /*!<  ADC external trigger for injected conversion event 6 */
 269 #define ADC_ExternalTrigInjecConvEvent_7              ((uint16_t)0x001C)  /*!<  ADC external trigger for injected conversion event 7 */
 270 #define ADC_ExternalTrigInjecConvEvent_8              ((uint16_t)0x0020)  /*!<  ADC external trigger for injected conversion event 8 */
 271 #define ADC_ExternalTrigInjecConvEvent_9              ((uint16_t)0x0024)  /*!<  ADC external trigger for injected conversion event 9 */
 272 #define ADC_ExternalTrigInjecConvEvent_10             ((uint16_t)0x0028)  /*!<  ADC external trigger for injected conversion event 10 */
 273 #define ADC_ExternalTrigInjecConvEvent_11             ((uint16_t)0x002C)  /*!<  ADC external trigger for injected conversion event 11 */
 274 #define ADC_ExternalTrigInjecConvEvent_12             ((uint16_t)0x0030)  /*!<  ADC external trigger for injected conversion event 12 */
 275 #define ADC_ExternalTrigInjecConvEvent_13             ((uint16_t)0x0034)  /*!<  ADC external trigger for injected conversion event 13 */
 276 #define ADC_ExternalTrigInjecConvEvent_14             ((uint16_t)0x0038)  /*!<  ADC external trigger for injected conversion event 14 */
 277 #define ADC_ExternalTrigInjecConvEvent_15             ((uint16_t)0x003C)  /*!<  ADC external trigger for injected conversion event 15 */
 278
 279 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
 280                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
 281                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
 282                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
 283                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
 284                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
 285                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
 286                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
 287                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
 288                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
 289                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
 290                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
 291                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
 292                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
 293                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
 294                                         ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
 295 /**
 296   * @}
 297   */
 298 /** @defgroup ADC_data_align
 299   * @{
 300   */
 301
 302 #define ADC_DataAlign_Right                        ((uint32_t)0x00000000)  /*!<  ADC Data alignment right */
 303 #define ADC_DataAlign_Left                         ((uint32_t)0x00000020)  /*!<  ADC Data alignment left */
 304 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
 305                                   ((ALIGN) == ADC_DataAlign_Left))
 306 /**
 307   * @}
 308   */
 309
 310 /** @defgroup ADC_channels
 311   * @{
 312   */
 313
 314 #define ADC_Channel_1                               ((uint8_t)0x01)    /*!<  ADC Channel 1 */
 315 #define ADC_Channel_2                               ((uint8_t)0x02)    /*!<  ADC Channel 2 */
 316 #define ADC_Channel_3                               ((uint8_t)0x03)    /*!<  ADC Channel 3 */
 317 #define ADC_Channel_4                               ((uint8_t)0x04)    /*!<  ADC Channel 4 */
 318 #define ADC_Channel_5                               ((uint8_t)0x05)    /*!<  ADC Channel 5 */
 319 #define ADC_Channel_6                               ((uint8_t)0x06)    /*!<  ADC Channel 6 */
 320 #define ADC_Channel_7                               ((uint8_t)0x07)    /*!<  ADC Channel 7 */
 321 #define ADC_Channel_8                               ((uint8_t)0x08)    /*!<  ADC Channel 8 */
 322 #define ADC_Channel_9                               ((uint8_t)0x09)    /*!<  ADC Channel 9 */
 323 #define ADC_Channel_10                              ((uint8_t)0x0A)    /*!<  ADC Channel 10 */
 324 #define ADC_Channel_11                              ((uint8_t)0x0B)    /*!<  ADC Channel 11 */
 325 #define ADC_Channel_12                              ((uint8_t)0x0C)    /*!<  ADC Channel 12 */
 326 #define ADC_Channel_13                              ((uint8_t)0x0D)    /*!<  ADC Channel 13 */
 327 #define ADC_Channel_14                              ((uint8_t)0x0E)    /*!<  ADC Channel 14 */
 328 #define ADC_Channel_15                              ((uint8_t)0x0F)    /*!<  ADC Channel 15 */
 329 #define ADC_Channel_16                              ((uint8_t)0x10)    /*!<  ADC Channel 16 */
 330 #define ADC_Channel_17                              ((uint8_t)0x11)    /*!<  ADC Channel 17 */
 331 #define ADC_Channel_18                              ((uint8_t)0x12)    /*!<  ADC Channel 18 */
 332
 333 #define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
 334 #define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_18)
 335 #define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_17)
 336
 337 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1)  || \
 338                                  ((CHANNEL) == ADC_Channel_2)  || \
 339                                  ((CHANNEL) == ADC_Channel_3)  || \
 340                                  ((CHANNEL) == ADC_Channel_4)  || \
 341                                  ((CHANNEL) == ADC_Channel_5)  || \
 342                                  ((CHANNEL) == ADC_Channel_6)  || \
 343                                  ((CHANNEL) == ADC_Channel_7)  || \
 344                                  ((CHANNEL) == ADC_Channel_8)  || \
 345                                  ((CHANNEL) == ADC_Channel_9)  || \
 346                                  ((CHANNEL) == ADC_Channel_10) || \
 347                                  ((CHANNEL) == ADC_Channel_11) || \
 348                                  ((CHANNEL) == ADC_Channel_12) || \
 349                                  ((CHANNEL) == ADC_Channel_13) || \
 350                                  ((CHANNEL) == ADC_Channel_14) || \
 351                                  ((CHANNEL) == ADC_Channel_15) || \
 352                                  ((CHANNEL) == ADC_Channel_16) || \
 353                                  ((CHANNEL) == ADC_Channel_17) || \
 354                                  ((CHANNEL) == ADC_Channel_18))
 355 #define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1)  || \
 356                                      ((CHANNEL) == ADC_Channel_2)  || \
 357                                      ((CHANNEL) == ADC_Channel_3)  || \
 358                                      ((CHANNEL) == ADC_Channel_4)  || \
 359                                      ((CHANNEL) == ADC_Channel_5)  || \
 360                                      ((CHANNEL) == ADC_Channel_6)  || \
 361                                      ((CHANNEL) == ADC_Channel_7)  || \
 362                                      ((CHANNEL) == ADC_Channel_8)  || \
 363                                      ((CHANNEL) == ADC_Channel_9)  || \
 364                                      ((CHANNEL) == ADC_Channel_10) || \
 365                                      ((CHANNEL) == ADC_Channel_11) || \
 366                                      ((CHANNEL) == ADC_Channel_12) || \
 367                                      ((CHANNEL) == ADC_Channel_13) || \
 368                                      ((CHANNEL) == ADC_Channel_14))
 369 /**
 370   * @}
 371   */
 372
 373 /** @defgroup ADC_mode
 374   * @{
 375   */
 376 #define ADC_Mode_Independent                  ((uint32_t)0x00000000) /*!<  ADC independent mode */
 377 #define ADC_Mode_CombRegSimulInjSimul         ((uint32_t)0x00000001) /*!<  ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
 378 #define ADC_Mode_CombRegSimulAltTrig          ((uint32_t)0x00000002) /*!<  ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
 379 #define ADC_Mode_InjSimul                     ((uint32_t)0x00000005) /*!<  ADC multi ADC mode: Injected simultaneous mode */
 380 #define ADC_Mode_RegSimul                     ((uint32_t)0x00000006) /*!<  ADC multi ADC mode: Regular simultaneous mode */
 381 #define ADC_Mode_Interleave                   ((uint32_t)0x00000007) /*!<  ADC multi ADC mode: Interleave mode */
 382 #define ADC_Mode_AltTrig                      ((uint32_t)0x00000009) /*!<  ADC multi ADC mode: Alternate Trigger mode */
 383
 384 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
 385                            ((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
 386                            ((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
 387                            ((MODE) == ADC_Mode_InjSimul) || \
 388                            ((MODE) == ADC_Mode_RegSimul) || \
 389                            ((MODE) == ADC_Mode_Interleave) || \
 390                            ((MODE) == ADC_Mode_AltTrig))
 391
 392 /**
 393   * @}
 394   */
 395
 396 /** @defgroup ADC_Clock
 397   * @{
 398   */
 399 #define ADC_Clock_AsynClkMode                  ((uint32_t)0x00000000)   /*!< ADC Asynchronous clock mode */
 400 #define ADC_Clock_SynClkModeDiv1               ((uint32_t)0x00010000)   /*!< Synchronous clock mode divided by 1 */
 401 #define ADC_Clock_SynClkModeDiv2               ((uint32_t)0x00020000)   /*!<  Synchronous clock mode divided by 2 */
 402 #define ADC_Clock_SynClkModeDiv4               ((uint32_t)0x00030000)   /*!<  Synchronous clock mode divided by 4 */
 403 #define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
 404                                 ((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
 405                                 ((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
 406                                 ((CLOCK) == ADC_Clock_SynClkModeDiv4))
 407 /**
 408   * @}
 409   */
 410 /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
 411   * @{
 412   */
 413 #define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /*!<  DMA mode disabled */
 414 #define ADC_DMAAccessMode_1             ((uint32_t)0x00008000)     /*!<  DMA mode enabled for 12 and 10-bit resolution (6 bit) */
 415 #define ADC_DMAAccessMode_2             ((uint32_t)0x0000C000)     /*!<  DMA mode enabled for 8 and 6-bit resolution (8bit) */
 416 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
 417                                       ((MODE) == ADC_DMAAccessMode_1) || \
 418                                       ((MODE) == ADC_DMAAccessMode_2))
 419
 420 /**
 421   * @}
 422   */
 423 /** @defgroup ADC_sampling_time
 424   * @{
 425   */
 426
 427 #define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)   /*!<  ADC sampling time 1.5 cycle */
 428 #define ADC_SampleTime_2Cycles5                    ((uint8_t)0x01)   /*!<  ADC sampling time 2.5 cycles */
 429 #define ADC_SampleTime_4Cycles5                    ((uint8_t)0x02)   /*!<  ADC sampling time 4.5 cycles */
 430 #define ADC_SampleTime_7Cycles5                    ((uint8_t)0x03)   /*!<  ADC sampling time 7.5 cycles */
 431 #define ADC_SampleTime_19Cycles5                   ((uint8_t)0x04)   /*!<  ADC sampling time 19.5 cycles */
 432 #define ADC_SampleTime_61Cycles5                   ((uint8_t)0x05)   /*!<  ADC sampling time 61.5 cycles */
 433 #define ADC_SampleTime_181Cycles5                  ((uint8_t)0x06)   /*!<  ADC sampling time 181.5 cycles */
 434 #define ADC_SampleTime_601Cycles5                  ((uint8_t)0x07)   /*!<  ADC sampling time 601.5 cycles */
 435 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
 436                                   ((TIME) == ADC_SampleTime_2Cycles5) || \
 437                                   ((TIME) == ADC_SampleTime_4Cycles5) || \
 438                                   ((TIME) == ADC_SampleTime_7Cycles5) || \
 439                                   ((TIME) == ADC_SampleTime_19Cycles5) || \
 440                                   ((TIME) == ADC_SampleTime_61Cycles5) || \
 441                                   ((TIME) == ADC_SampleTime_181Cycles5) || \
 442                                   ((TIME) == ADC_SampleTime_601Cycles5))
 443 /**
 444   * @}
 445   */
 446
 447 /** @defgroup ADC_injected_Channel_selection
 448   * @{
 449   */
 450
 451 #define ADC_InjectedChannel_1                       ADC_Channel_1        /*!<  ADC Injected channel 1 */
 452 #define ADC_InjectedChannel_2                       ADC_Channel_2        /*!<  ADC Injected channel 2 */
 453 #define ADC_InjectedChannel_3                       ADC_Channel_3        /*!<  ADC Injected channel 3 */
 454 #define ADC_InjectedChannel_4                       ADC_Channel_4        /*!<  ADC Injected channel 4 */
 455 #define ADC_InjectedChannel_5                       ADC_Channel_5        /*!<  ADC Injected channel 5 */
 456 #define ADC_InjectedChannel_6                       ADC_Channel_6        /*!<  ADC Injected channel 6 */
 457 #define ADC_InjectedChannel_7                       ADC_Channel_7        /*!<  ADC Injected channel 7 */
 458 #define ADC_InjectedChannel_8                       ADC_Channel_8        /*!<  ADC Injected channel 8 */
 459 #define ADC_InjectedChannel_9                       ADC_Channel_9        /*!<  ADC Injected channel 9 */
 460 #define ADC_InjectedChannel_10                      ADC_Channel_10       /*!<  ADC Injected channel 10 */
 461 #define ADC_InjectedChannel_11                      ADC_Channel_11       /*!<  ADC Injected channel 11 */
 462 #define ADC_InjectedChannel_12                      ADC_Channel_12       /*!<  ADC Injected channel 12 */
 463 #define ADC_InjectedChannel_13                      ADC_Channel_13       /*!<  ADC Injected channel 13 */
 464 #define ADC_InjectedChannel_14                      ADC_Channel_14       /*!<  ADC Injected channel 14 */
 465 #define ADC_InjectedChannel_15                      ADC_Channel_15       /*!<  ADC Injected channel 15 */
 466 #define ADC_InjectedChannel_16                      ADC_Channel_16       /*!<  ADC Injected channel 16 */
 467 #define ADC_InjectedChannel_17                      ADC_Channel_17       /*!<  ADC Injected channel 17 */
 468 #define ADC_InjectedChannel_18                      ADC_Channel_18       /*!<  ADC Injected channel 18 */
 469
 470 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
 471                                           ((CHANNEL) == ADC_InjectedChannel_2) || \
 472                                           ((CHANNEL) == ADC_InjectedChannel_3) || \
 473                                           ((CHANNEL) == ADC_InjectedChannel_4) ||\
 474                                           ((CHANNEL) == ADC_InjectedChannel_5) ||\
 475                                           ((CHANNEL) == ADC_InjectedChannel_6) ||\
 476                                           ((CHANNEL) == ADC_InjectedChannel_7) ||\
 477                                           ((CHANNEL) == ADC_InjectedChannel_8) ||\
 478                                           ((CHANNEL) == ADC_InjectedChannel_9) ||\
 479                                           ((CHANNEL) == ADC_InjectedChannel_10) ||\
 480                                           ((CHANNEL) == ADC_InjectedChannel_11) ||\
 481                                           ((CHANNEL) == ADC_InjectedChannel_12) ||\
 482                                           ((CHANNEL) == ADC_InjectedChannel_13) ||\
 483                                           ((CHANNEL) == ADC_InjectedChannel_14) ||\
 484                                           ((CHANNEL) == ADC_InjectedChannel_15) ||\
 485                                           ((CHANNEL) == ADC_InjectedChannel_16) ||\
 486                                           ((CHANNEL) == ADC_InjectedChannel_17) ||\
 487                                           ((CHANNEL) == ADC_InjectedChannel_18))
 488 /**
 489   * @}
 490   */
 491
 492 /** @defgroup ADC_injected_Sequence_selection
 493   * @{
 494   */
 495
 496 #define ADC_InjectedSequence_1                       ADC_Channel_1        /*!<  ADC Injected sequence 1 */
 497 #define ADC_InjectedSequence_2                       ADC_Channel_2        /*!<  ADC Injected sequence 2 */
 498 #define ADC_InjectedSequence_3                       ADC_Channel_3        /*!<  ADC Injected sequence 3 */
 499 #define ADC_InjectedSequence_4                       ADC_Channel_4        /*!<  ADC Injected sequence 4 */
 500 #define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
 501                                             ((SEQUENCE) == ADC_InjectedSequence_2) || \
 502                                             ((SEQUENCE) == ADC_InjectedSequence_3) || \
 503                                             ((SEQUENCE) == ADC_InjectedSequence_4))
 504 /**
 505   * @}
 506   */
 507
 508 /** @defgroup ADC_analog_watchdog_selection
 509   * @{
 510   */
 511
 512 #define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00C00000)    /*!<  ADC Analog watchdog single regular mode */
 513 #define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x01400000)    /*!<  ADC Analog watchdog single injected mode */
 514 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x01C00000)    /*!<  ADC Analog watchdog single regular or injected mode */
 515 #define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)    /*!<  ADC Analog watchdog all regular mode */
 516 #define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x01000000)    /*!<  ADC Analog watchdog all injected mode */
 517 #define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x01800000)    /*!<  ADC Analog watchdog all regular and all injected mode */
 518 #define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)    /*!<  ADC Analog watchdog off */
 519
 520 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
 521                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
 522                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
 523                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
 524                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
 525                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
 526                                           ((WATCHDOG) == ADC_AnalogWatchdog_None))
 527 /**
 528   * @}
 529   */
 530
 531 /** @defgroup ADC_Calibration_Mode_definition
 532   * @{
 533   */
 534 #define ADC_CalibrationMode_Single         ((uint32_t)0x00000000)   /*!<  ADC Calibration for single ended channel */
 535 #define ADC_CalibrationMode_Differential   ((uint32_t)0x40000000)   /*!<  ADC Calibration for differential channel */
 536
 537 #define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
 538
 539 /**
 540   * @}
 541   */
 542
 543 /** @defgroup ADC_DMA_Mode_definition
 544   * @{
 545   */
 546 #define ADC_DMAMode_OneShot        ((uint32_t)0x00000000)   /*!<  ADC DMA Oneshot mode */
 547 #define ADC_DMAMode_Circular   ((uint32_t)0x00000002)   /*!<  ADC DMA circular mode */
 548
 549 #define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
 550 /**
 551   * @}
 552   */
 553
 554 /** @defgroup ADC_interrupts_definition
 555   * @{
 556   */
 557
 558 #define ADC_IT_RDY           ((uint16_t)0x0001)  /*!< ADC Ready (ADRDY) interrupt source */
 559 #define ADC_IT_EOSMP         ((uint16_t)0x0002)  /*!< ADC End of Sampling interrupt source */
 560 #define ADC_IT_EOC           ((uint16_t)0x0004)  /*!< ADC End of Regular Conversion interrupt source */
 561 #define ADC_IT_EOS           ((uint16_t)0x0008)  /*!< ADC End of Regular sequence of Conversions interrupt source */
 562 #define ADC_IT_OVR           ((uint16_t)0x0010)  /*!< ADC overrun interrupt source */
 563 #define ADC_IT_JEOC          ((uint16_t)0x0020)  /*!< ADC End of Injected Conversion interrupt source */
 564 #define ADC_IT_JEOS          ((uint16_t)0x0040)  /*!< ADC End of Injected sequence of Conversions interrupt source */
 565 #define ADC_IT_AWD1          ((uint16_t)0x0080)  /*!< ADC Analog watchdog 1 interrupt source */
 566 #define ADC_IT_AWD2          ((uint16_t)0x0100)  /*!< ADC Analog watchdog 2 interrupt source */
 567 #define ADC_IT_AWD3          ((uint16_t)0x0200)  /*!< ADC Analog watchdog 3 interrupt source */
 568 #define ADC_IT_JQOVF         ((uint16_t)0x0400)  /*!< ADC Injected Context Queue Overflow interrupt source */
 569
 570
 571 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
 572
 573 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
 574                            ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
 575                            ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
 576                            ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
 577                            ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
 578                            ((IT) == ADC_IT_JQOVF))
 579 /**
 580   * @}
 581   */
 582
 583 /** @defgroup ADC_flags_definition
 584   * @{
 585   */
 586
 587 #define ADC_FLAG_RDY           ((uint16_t)0x0001)  /*!< ADC Ready (ADRDY) flag */
 588 #define ADC_FLAG_EOSMP         ((uint16_t)0x0002)  /*!< ADC End of Sampling flag */
 589 #define ADC_FLAG_EOC           ((uint16_t)0x0004)  /*!< ADC End of Regular Conversion flag */
 590 #define ADC_FLAG_EOS           ((uint16_t)0x0008)  /*!< ADC End of Regular sequence of Conversions flag */
 591 #define ADC_FLAG_OVR           ((uint16_t)0x0010)  /*!< ADC overrun flag */
 592 #define ADC_FLAG_JEOC          ((uint16_t)0x0020)  /*!< ADC End of Injected Conversion flag */
 593 #define ADC_FLAG_JEOS          ((uint16_t)0x0040)  /*!< ADC End of Injected sequence of Conversions flag */
 594 #define ADC_FLAG_AWD1          ((uint16_t)0x0080)  /*!< ADC Analog watchdog 1 flag */
 595 #define ADC_FLAG_AWD2          ((uint16_t)0x0100)  /*!< ADC Analog watchdog 2 flag */
 596 #define ADC_FLAG_AWD3          ((uint16_t)0x0200)  /*!< ADC Analog watchdog 3 flag */
 597 #define ADC_FLAG_JQOVF         ((uint16_t)0x0400)  /*!< ADC Injected Context Queue Overflow flag */
 598
 599 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
 600 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
 601                                ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
 602                                ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
 603                                ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
 604                                ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
 605                                ((FLAG) == ADC_FLAG_JQOVF))
 606 /**
 607   * @}
 608   */
 609
 610 /** @defgroup ADC_Common_flags_definition
 611   * @{
 612   */
 613
 614 #define ADC_FLAG_MSTRDY           ((uint32_t)0x00000001)  /*!< ADC Master Ready (ADRDY) flag */
 615 #define ADC_FLAG_MSTEOSMP         ((uint32_t)0x00000002)  /*!< ADC Master End of Sampling flag */
 616 #define ADC_FLAG_MSTEOC           ((uint32_t)0x00000004)  /*!< ADC Master End of Regular Conversion flag */
 617 #define ADC_FLAG_MSTEOS           ((uint32_t)0x00000008)  /*!< ADC Master End of Regular sequence of Conversions flag */
 618 #define ADC_FLAG_MSTOVR           ((uint32_t)0x00000010)  /*!< ADC Master overrun flag */
 619 #define ADC_FLAG_MSTJEOC          ((uint32_t)0x00000020)  /*!< ADC Master End of Injected Conversion flag */
 620 #define ADC_FLAG_MSTJEOS          ((uint32_t)0x00000040)  /*!< ADC Master End of Injected sequence of Conversions flag */
 621 #define ADC_FLAG_MSTAWD1          ((uint32_t)0x00000080)  /*!< ADC Master Analog watchdog 1 flag */
 622 #define ADC_FLAG_MSTAWD2          ((uint32_t)0x00000100)  /*!< ADC Master Analog watchdog 2 flag */
 623 #define ADC_FLAG_MSTAWD3          ((uint32_t)0x00000200)  /*!< ADC Master Analog watchdog 3 flag */
 624 #define ADC_FLAG_MSTJQOVF         ((uint32_t)0x00000400)  /*!< ADC Master Injected Context Queue Overflow flag */
 625
 626 #define ADC_FLAG_SLVRDY           ((uint32_t)0x00010000)  /*!< ADC Slave Ready (ADRDY) flag */
 627 #define ADC_FLAG_SLVEOSMP         ((uint32_t)0x00020000)  /*!< ADC Slave End of Sampling flag */
 628 #define ADC_FLAG_SLVEOC           ((uint32_t)0x00040000)  /*!< ADC Slave End of Regular Conversion flag */
 629 #define ADC_FLAG_SLVEOS           ((uint32_t)0x00080000)  /*!< ADC Slave End of Regular sequence of Conversions flag */
 630 #define ADC_FLAG_SLVOVR           ((uint32_t)0x00100000)  /*!< ADC Slave overrun flag */
 631 #define ADC_FLAG_SLVJEOC          ((uint32_t)0x00200000)  /*!< ADC Slave End of Injected Conversion flag */
 632 #define ADC_FLAG_SLVJEOS          ((uint32_t)0x00400000)  /*!< ADC Slave End of Injected sequence of Conversions flag */
 633 #define ADC_FLAG_SLVAWD1          ((uint32_t)0x00800000)  /*!< ADC Slave Analog watchdog 1 flag */
 634 #define ADC_FLAG_SLVAWD2          ((uint32_t)0x01000000)  /*!< ADC Slave Analog watchdog 2 flag */
 635 #define ADC_FLAG_SLVAWD3          ((uint32_t)0x02000000)  /*!< ADC Slave Analog watchdog 3 flag */
 636 #define ADC_FLAG_SLVJQOVF         ((uint32_t)0x04000000)  /*!< ADC Slave Injected Context Queue Overflow flag */
 637
 638 #define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
 639 #define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
 640                                      ((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
 641                                      ((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
 642                                      ((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
 643                                      ((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
 644                                      ((FLAG) == ADC_FLAG_MSTJQOVF) || \
 645                                      ((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
 646                                      ((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
 647                                      ((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
 648                                      ((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
 649                                      ((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
 650                                      ((FLAG) == ADC_FLAG_SLVJQOVF))
 651 /**
 652   * @}
 653   */
 654
 655 /** @defgroup ADC_thresholds
 656   * @{
 657   */
 658
 659 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
 660
 661 /**
 662   * @}
 663   */
 664
 665 /** @defgroup ADC_injected_offset
 666   * @{
 667   */
 668
 669 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
 670
 671 /**
 672   * @}
 673   */
 674
 675 /** @defgroup ADC_injected_length
 676   * @{
 677   */
 678
 679 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
 680
 681 /**
 682   * @}
 683   */
 684
 685
 686 /** @defgroup ADC_regular_length
 687   * @{
 688   */
 689
 690 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
 691 /**
 692   * @}
 693   */
 694
 695 /** @defgroup ADC_regular_discontinuous_mode_number
 696   * @{
 697   */
 698
 699 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
 700
 701 /**
 702   * @}
 703   */
 704
 705 /** @defgroup ADC_two_sampling_delay_number
 706   * @{
 707   */
 708 #define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
 709
 710 /**
 711   * @}
 712   */
 713 /**
 714   * @}
 715   */
 716
 717
 718 /* Exported macro ------------------------------------------------------------*/
 719 /* Exported functions ------------------------------------------------------- */
 720
 721 /*  Function used to set the ADC configuration to the default reset state *****/
 722 void ADC_DeInit(ADC_TypeDef* ADCx);
 723
 724 /* Initialization and Configuration functions *********************************/
 725 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
 726 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
 727 void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
 728 void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
 729 void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
 730 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
 731
 732 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 733 void ADC_StartCalibration(ADC_TypeDef* ADCx);
 734 uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
 735 void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
 736 void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
 737 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
 738 void ADC_DisableCmd(ADC_TypeDef* ADCx);
 739 FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
 740 void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 741 void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
 742 void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
 743 void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 744
 745 /* Analog Watchdog configuration functions ************************************/
 746 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
 747 void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
 748 void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
 749 void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
 750 void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
 751 void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
 752 void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
 753
 754 /* Temperature Sensor, Vrefint and Vbat management function */
 755 void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 756 void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 757 void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 758
 759 /* Channels Configuration functions ***********************************/
 760 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
 761 void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
 762 void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
 763
 764 void ADC_StartConversion(ADC_TypeDef* ADCx);
 765 FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
 766 void ADC_StopConversion(ADC_TypeDef* ADCx);
 767 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
 768 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 769 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
 770 uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
 771
 772 void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
 773 void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
 774 void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
 775 void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
 776
 777 void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 778 void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 779 void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 780 void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 781
 782 /* Regular Channels DMA Configuration functions *******************************/
 783 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 784 void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
 785
 786 /* Injected channels Configuration functions **********************************/
 787 void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
 788 void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
 789 FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
 790 void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
 791 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 792 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 793 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
 794
 795 /* ADC Dual Modes Configuration functions *************************************/
 796 FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
 797 void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
 798
 799 /* Interrupts and flags management functions **********************************/
 800 void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
 801 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
 802 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
 803 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
 804 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
 805
 806 #ifdef __cplusplus
 807 }
 808 #endif
 809
 810 #endif /*__STM32F30x_ADC_H */
 811
 812 /**
 813   * @}
 814   */
 815
 816 /**
 817   * @}
 818   */
 819
 820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/