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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F30x_StdPeriph_Driver / inc / stm32f30x_hrtim.h
blob39dea380b70875caa3055315d8469bd29feb635d
1 /**
2 ******************************************************************************
3 * @file stm32f30x_hrtim.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 04-April-2014
7 * @brief This file contains all the functions prototypes for the HRTIM firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
13 *
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
17 *
18 * http://www.st.com/software_license_agreement_liberty_v2
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************
27 */
28
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_HRTIM_H
31 #define __STM32F30x_HRTIM_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39
40 /** @addtogroup STM32F30x_StdPeriph_Driver
41 * @{
42 */
43
44 /** @addtogroup ADC
45 * @{
46 */
47
48 /* Exported types ------------------------------------------------------------*/
49
50 /**
51 * @brief HRTIM Configuration Structure definition - Time base related parameters
52 */
53 typedef struct
54 {
55 uint32_t Period; /*!< Specifies the timer period
56 The period value must be above 3 periods of the fHRTIM clock.
57 Maximum value is = 0xFFDF */
58 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
60 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
61 This parameter can be any value of @ref HRTIM_PrescalerRatio */
62 uint32_t Mode; /*!< Specifies the counter operating mode
63 This parameter can be any value of @ref HRTIM_Mode */
64 } HRTIM_BaseInitTypeDef;
65 /**
66 * @brief Waveform mode initialization parameters definition
67 */
68 typedef struct {
69 uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
70 This parameter can be a combination of @ref HRTIM_HalfModeEnable */
71 uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
72 This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
73 uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
74 This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
75 uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
76 This parameter can be any value of @ref HRTIM_DACSynchronization */
77 uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
78 This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
79 uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
80 update enable inputs (Slave timers only)
81 This parameter can be any value of @ref HRTIM_UpdateGating */
82 uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
83 This parameter can be a combination of @ref HRTIM_TimerBurstMode */
84 uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
85 This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
86 } HRTIM_TimerInitTypeDef;
87
88 /**
89 * @brief Basic output compare mode configuration definition
90 */
91 typedef struct {
92 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
93 This parameter can be a combination of @ref HRTIM_BasicOCMode */
94 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
95 The compare value must be above or equal to 3 periods of the fHRTIM clock */
96 uint32_t Polarity; /*!< Specifies the output polarity
97 This parameter can be any value of @ref HRTIM_Output_Polarity */
98 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
99 This parameter can be any value of @ref HRTIM_OutputIDLEState */
100 } HRTIM_BasicOCChannelCfgTypeDef;
101
102 /**
103 * @brief Basic PWM output mode configuration definition
104 */
105 typedef struct {
106 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
107 The compare value must be above or equal to 3 periods of the fHRTIM clock */
108 uint32_t Polarity; /*!< Specifies the output polarity
109 This parameter can be any value of @ref HRTIM_OutputPolarity */
110 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
111 This parameter can be any value of @ref HRTIM_OutputIDLEState */
112 } HRTIM_BasicPWMChannelCfgTypeDef;
113
114 /**
115 * @brief Basic capture mode configuration definition
116 */
117 typedef struct {
118 uint32_t CaptureUnit; /*!< Specifies the external event Channel
119 This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
120 uint32_t Event; /*!< Specifies the external event triggering the capture
121 This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
122 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
123 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
124 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
125 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
126 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
127 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
128 } HRTIM_BasicCaptureChannelCfgTypeDef;
129
130 /**
131 * @brief Basic One Pulse mode configuration definition
132 */
133 typedef struct {
134 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
135 The compare value must be above or equal to 3 periods of the fHRTIM clock */
136 uint32_t OutputPolarity; /*!< Specifies the output polarity
137 This parameter can be any value of @ref HRTIM_Output_Polarity */
138 uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
139 This parameter can be any value of @ref HRTIM_Output_IDLE_State */
140 uint32_t Event; /*!< Specifies the external event triggering the pulse generation
141 This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
142 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
143 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
144 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
145 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
146 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
147 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
148 } HRTIM_BasicOnePulseChannelCfgTypeDef;
149
150 /**
151 * @brief Timer configuration definition
152 */
153 typedef struct {
154 uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
155 This parameter can be a value of @ref HRTIM_TimerPushPullMode */
156 uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
157 This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
158 uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
159 This parameter can be a value of @ref HRTIM_TimerFaultLock */
160 uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
161 This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
162 uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
163 This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
164 uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
165 This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
166 uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
167 This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
168 uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
169 This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
170 } HRTIM_TimerCfgTypeDef;
171
172 /**
173 * @brief Compare unit configuration definition
174 */
175 typedef struct {
176 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
177 the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
178 the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
179 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
180 This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
181 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
182 CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
183 } HRTIM_CompareCfgTypeDef;
184
185 /**
186 * @brief Capture unit configuration definition
187 */
188 typedef struct {
189 uint32_t Trigger; /*!< Specifies source(s) triggering the capture
190 This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
191 } HRTIM_CaptureCfgTypeDef;
192
193 /**
194 * @brief Output configuration definition
195 */
196 typedef struct {
197 uint32_t Polarity; /*!< Specifies the output polarity
198 This parameter can be any value of @ref HRTIM_Output_Polarity */
199 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
200 This parameter can be any value of @ref HRTIM_OutputSetSource */
201 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
202 This parameter can be any value of @ref HRTIM_OutputResetSource */
203 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
204 This parameter can be any value of @ref HRTIM_OutputIdleMode */
205 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
206 This parameter can be any value of @ref HRTIM_OutputIDLEState */
207 uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
208 This parameter can be any value of @ref HRTIM_OutputFAULTState */
209 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
210 This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
211 uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
212 during a burst mode operation
213 This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */
214 } HRTIM_OutputCfgTypeDef;
215
216 /**
217 * @brief External event filtering in timing units configuration definition
218 */
219 typedef struct {
220 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
221 This parameter can be a value of @ref HRTIM_TimerExternalEventFilter */
222 uint32_t Latch; /*!< Specifies whether or not the signal is latched
223 This parameter can be a value of @ref HRTIM_TimerExternalEventLatch */
224 } HRTIM_TimerEventFilteringCfgTypeDef;
225
226 /**
227 * @brief Dead time feature configuration definition
228 */
229 typedef struct {
230 uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
231 This parameter can be a number between 0x0 and = 0x7 */
232 uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
233 This parameter can be a number between 0x0 and 0xFF */
234 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
235 This parameter can be a value of @ref HRTIM_DeadtimeRisingSign */
236 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
237 This parameter can be a value of @ref HRTIM_DeadtimeRisingLock */
238 uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
239 This parameter can be a value of @ref HRTIM_DeadtimeRisingSignLock */
240 uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
241 This parameter can be a number between 0x0 and 0xFF */
242 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
243 This parameter can be a value of @ref HRTIM_DeadtimeFallingSign */
244 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
245 This parameter can be a value of @ref HRTIM_DeadtimeFallingLock */
246 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
247 This parameter can be a value of @ref HRTIM_DeadtimeFallingSignLock */
248 } HRTIM_DeadTimeCfgTypeDef;
249
250 /**
251 * @brief Chopper mode configuration definition
252 */
253 typedef struct {
254 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
255 This parameter can be a value between 0 and 0xF */
256 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
257 This parameter can be a value between 0 and 0x7 */
258 uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
259 This parameter can be a value between 0 and 0xF */
260 } HRTIM_ChopperModeCfgTypeDef;
261
262 /**
263 * @brief Master synchronization configuration definition
264 */
265 typedef struct {
266 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
267 This parameter can be a value of @ref HRTIM_SynchronizationInputSource */
268 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
269 This parameter can be a value of @ref HRTIM_SynchronizationOutputSource */
270 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization outputs
271 This parameter can be a value of @ref HRTIM_SynchronizationOutputPolarity */
272 } HRTIM_SynchroCfgTypeDef;
273
274 /**
275 * @brief External event channel configuration definition
276 */
277 typedef struct {
278 uint32_t Source; /*!< Identifies the source of the external event
279 This parameter can be a value of @ref HRTIM_ExternalEventSources */
280 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
281 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
282 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
283 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
284 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
285 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
286 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
287 This parameter can be a value of @ref HRTIM_ExternalEventFastMode */
288 } HRTIM_EventCfgTypeDef;
289
290 /**
291 * @brief Fault channel configuration definition
292 */
293 typedef struct {
294 uint32_t Source; /*!< Identifies the source of the fault
295 This parameter can be a value of @ref HRTIM_FaultSources */
296 uint32_t Polarity; /*!< Specifies the polarity of the fault event
297 This parameter can be a value of @ref HRTIM_FaultPolarity */
298 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
299 This parameter can be a value of @ref HRTIM_FaultFilter */
300 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
301 This parameter can be a value of @ref HRTIM_FaultLock */
302 } HRTIM_FaultCfgTypeDef;
303
304 /**
305 * @brief Burst mode configuration definition
306 */
307 typedef struct {
308 uint32_t Mode; /*!< Specifies the burst mode operating mode
309 This parameter can be a value of @ref HRTIM_BurstModeOperatingMode */
310 uint32_t ClockSource; /*!< Specifies the burst mode clock source
311 This parameter can be a value of @ref HRTIM_BurstModeClockSource */
312 uint32_t Prescaler; /*!< Specifies the burst mode prescaler
313 This parameter can be a value of @ref HRTIM_BurstModePrescaler */
314 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
315 This parameter can be a combination of @ref HRTIM_BurstModeRegisterPreloadEnable */
316 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation
317 This parameter can be a combination of @ref HRTIM_BurstModeTrigger */
318 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
319 This parameter can be a number between 0x0 and 0xFFFF */
320 uint32_t Period; /*!< Specifies burst mode repetition period
321 This parameter can be a number between 0x1 and 0xFFFF */
322 } HRTIM_BurstModeCfgTypeDef;
323
324 /**
325 * @brief ADC trigger configuration definition
326 */
327 typedef struct {
328 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
329 This parameter can be a combination of @ref HRTIM_ADCTriggerUpdateSource */
330 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
331 This parameter can be a combination of @ref HRTIM_ADCTriggerEvent */
332 } HRTIM_ADCTriggerCfgTypeDef;
333
334
335 /* Exported constants --------------------------------------------------------*/
336 /** @defgroup HRTIM_Exported_Constants
337 * @{
338 */
339
340 /** @defgroup HRTIM_TimerIndex
341 * @{
342 * @brief Constants defining the timer indexes
343 */
344 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index associated to timer A */
345 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index associated to timer B */
346 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index associated to timer C */
347 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index associated to timer D */
348 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index associated to timer E */
349 #define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index associated to master timer */
350 #define HRTIM_COMMONINDEX (uint32_t)0x6 /*!< Index associated to Common space */
351
352 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
353 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
354 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
355 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
356 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
357 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
358 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
359
360 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
361 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
362 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
363 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
364 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
365 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
366 /**
367 * @}
368 */
369
370 /** @defgroup HRTIM_TimerIdentifier
371 * @{
372 * @brief Constants defining timer identifiers
373 */
374 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
375 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
376 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
377 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
378 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
379 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
380
381 #define IS_HRTIM_TIMERID(TIMERID)\
382 (((TIMERID) == HRTIM_TIMERID_MASTER) || \
383 ((TIMERID) == HRTIM_TIMERID_TIMER_A) || \
384 ((TIMERID) == HRTIM_TIMERID_TIMER_B) || \
385 ((TIMERID) == HRTIM_TIMERID_TIMER_C) || \
386 ((TIMERID) == HRTIM_TIMERID_TIMER_D) || \
387 ((TIMERID) == HRTIM_TIMERID_TIMER_E))
388 /**
389 * @}
390 */
391
392 /** @defgroup HRTIM_CompareUnit
393 * @{
394 * @brief Constants defining compare unit identifiers
395 */
396 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
397 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
398 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
399 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
400
401 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
402 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
403 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
404 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
405 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
406 /**
407 * @}
408 */
409
410 /** @defgroup HRTIM_CaptureUnit
411 * @{
412 * @brief Constants defining capture unit identifiers
413 */
414 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
415 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
416
417 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
418 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
419 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
420 /**
421 * @}
422 */
423
424 /** @defgroup HRTIM_TimerOutput
425 * @{
426 * @brief Constants defining timer output identifiers
427 */
428 #define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */
429 #define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */
430 #define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */
431 #define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */
432 #define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */
433 #define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */
434 #define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */
435 #define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */
436 #define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */
437 #define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */
438
439 #define IS_HRTIM_OUTPUT(OUTPUT)\
440 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
441 ((OUTPUT) == HRTIM_OUTPUT_TA2) || \
442 ((OUTPUT) == HRTIM_OUTPUT_TB1) || \
443 ((OUTPUT) == HRTIM_OUTPUT_TB2) || \
444 ((OUTPUT) == HRTIM_OUTPUT_TC1) || \
445 ((OUTPUT) == HRTIM_OUTPUT_TC2) || \
446 ((OUTPUT) == HRTIM_OUTPUT_TD1) || \
447 ((OUTPUT) == HRTIM_OUTPUT_TD2) || \
448 ((OUTPUT) == HRTIM_OUTPUT_TE1) || \
449 ((OUTPUT) == HRTIM_OUTPUT_TE2))
450
451 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
452 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
453 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
454 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
455 || \
456 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
457 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
458 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
459 || \
460 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
461 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
462 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
463 || \
464 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
465 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
466 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
467 || \
468 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
469 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
470 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
471 /**
472 * @}
473 */
474
475 /** @defgroup HRTIM_ADCTrigger
476 * @{
477 * @brief Constants defining ADC triggers identifiers
478 */
479 #define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
480 #define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 1 identifier */
481 #define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 1 identifier */
482 #define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 1 identifier */
483
484 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
485 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
486 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
487 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
488 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
489 /**
490 * @}
491 */
492
493 /** @defgroup HRTIM_ExternalEventChannels
494 * @{
495 * @brief Constants defining external event channel identifiers
496 */
497 #define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
498 #define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
499 #define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
500 #define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
501 #define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
502 #define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
503 #define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
504 #define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
505 #define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
506 #define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
507 #define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
508
509 #define IS_HRTIM_EVENT(EVENT)\
510 (((EVENT) == HRTIM_EVENT_1) || \
511 ((EVENT) == HRTIM_EVENT_2) || \
512 ((EVENT) == HRTIM_EVENT_3) || \
513 ((EVENT) == HRTIM_EVENT_4) || \
514 ((EVENT) == HRTIM_EVENT_5) || \
515 ((EVENT) == HRTIM_EVENT_6) || \
516 ((EVENT) == HRTIM_EVENT_7) || \
517 ((EVENT) == HRTIM_EVENT_8) || \
518 ((EVENT) == HRTIM_EVENT_9) || \
519 ((EVENT) == HRTIM_EVENT_10))
520 /**
521 * @}
522 */
523
524 /** @defgroup HRTIM_FaultChannel
525 * @{
526 * @brief Constants defining fault channel identifiers
527 */
528 #define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
529 #define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
530 #define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
531 #define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
532 #define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
533
534 #define IS_HRTIM_FAULT(FAULT)\
535 (((FAULT) == HRTIM_FAULT_1) || \
536 ((FAULT) == HRTIM_FAULT_2) || \
537 ((FAULT) == HRTIM_FAULT_3) || \
538 ((FAULT) == HRTIM_FAULT_4) || \
539 ((FAULT) == HRTIM_FAULT_5))
540 /**
541 * @}
542 */
543
544
545 /** @defgroup HRTIM_PrescalerRatio
546 * @{
547 * @brief Constants defining timer high-resolution clock prescaler ratio.
548 */
549 #define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
550 #define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
551 #define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
552 #define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
553 #define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
554 #define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
555 #define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
556 #define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
557
558 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
559 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
560 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
561 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
562 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
563 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
564 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
565 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
566 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
567 /**
568 * @}
569 */
570
571 /** @defgroup HRTIM_Mode
572 * @{
573 * @brief Constants defining timer counter operating mode.
574 */
575 #define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
576 #define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
577 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
578
579 #define IS_HRTIM_MODE(MODE)\
580 (((MODE) == HRTIM_MODE_CONTINOUS) || \
581 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
582 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
583
584 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
585 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
586 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
587
588 /**
589 * @}
590 */
591
592 /** @defgroup HRTIM_HalfModeEnable
593 * @{
594 * @brief Constants defining half mode enabling status.
595 */
596 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
597 #define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
598
599 #define IS_HRTIM_HALFMODE(HALFMODE)\
600 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
601 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
602 /**
603 * @}
604 */
605
606 /** @defgroup HRTIM_StartOnSyncInputEvent
607 * @{
608 * @brief Constants defining the timer behavior following the synchronization event
609 */
610 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
611 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
612
613 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
614 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
615 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
616 /**
617 * @}
618 */
619
620 /** @defgroup HRTIM_ResetOnSyncInputEvent
621 * @{
622 * @brief Constants defining the timer behavior following the synchronization event
623 */
624 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
625 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
626
627 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
628 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
629 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
630 /**
631 * @}
632 */
633
634 /** @defgroup HRTIM_DACSynchronization
635 * @{
636 * @brief Constants defining on which output the DAC synchronization event is sent
637 */
638 #define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
639 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
640 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
641 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
642
643 #define IS_HRTIM_DACSYNC(DACSYNC)\
644 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
645 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
646 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
647 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
648 /**
649 * @}
650 */
651
652 /** @defgroup HRTIM_RegisterPreloadEnable
653 * @{
654 * @brief Constants defining whether a write access into a preloadable
655 * register is done into the active or the preload register.
656 */
657 #define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
658 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
659
660 #define IS_HRTIM_PRELOAD(PRELOAD)\
661 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
662 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
663 /**
664 * @}
665 */
666
667 /** @defgroup HRTIM_UpdateGating
668 * @{
669 * @brief Constants defining how the update occurs relatively to the burst DMA
670 * transaction and the external update request on update enable inputs 1 to 3.
671 */
672 #define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
673 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
674 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
675 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
676 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
677 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
678 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
679 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
680 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
681
682 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
683 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
684 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
685 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
686
687 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
688 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
689 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
690 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
691 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
692 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
693 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
694 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
695 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
696 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
697 /**
698 * @}
699 */
700
701 /** @defgroup HRTIM_TimerBurstMode
702 * @{
703 * @brief Constants defining how the timer behaves during a burst
704 mode operation.
705 */
706 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
707 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
708
709 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
710 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
711 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
712 /**
713 * @}
714 */
715
716 /** @defgroup HRTIM_TimerRepetitionUpdate
717 * @{
718 * @brief Constants defining whether registers are updated when the timer
719 * repetition period is completed (either due to roll-over or
720 * reset events)
721 */
722 #define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
723 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
724
725 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
726 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
727 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
728 /**
729 * @}
730 */
731
732
733 /** @defgroup HRTIM_TimerPushPullMode
734 * @{
735 * @brief Constants defining whether or not the push-pull mode is enabled for
736 * a timer.
737 */
738 #define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
739 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
740
741 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
742 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
743 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
744 /**
745 * @}
746 */
747
748 /** @defgroup HRTIM_TimerFaultEnabling
749 * @{
750 * @brief Constants defining whether a faut channel is enabled for a timer
751 */
752 #define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
753 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
754 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
755 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
756 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
757 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
758
759 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
760
761 /**
762 * @}
763 */
764
765 /** @defgroup HRTIM_TimerFaultLock
766 * @{
767 * @brief Constants defining whether or not fault enabling bits are write
768 * protected for a timer
769 */
770 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
771 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) /*!< Timer fault enabling bits are read only */
772
773 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
774 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
775 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
776 /**
777 * @}
778 */
779
780 /** @defgroup HRTIM_TimerDeadtimeInsertion
781 * @{
782 * @brief Constants defining whether or not fault the dead time insertion
783 * feature is enabled for a timer
784 */
785 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
786 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
787
788 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\
789 (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
790 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
791 /**
792 * @}
793 */
794
795 /** @defgroup HRTIM_TimerDelayedProtectionMode
796 * @{
797 * @brief Constants defining all possible delayed protection modes
798 * for a timer. Also define the source and outputs on which the delayed
799 * protection schemes are applied
800 */
801 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
802 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */
803 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */
804 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */
805 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */
806 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */
807 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */
808 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */
809 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */
810
811 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\
812 (((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
813 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
814 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
815 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
816 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
817 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
818 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
819 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) || \
820 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
821 /**
822 * @}
823 */
824
825 /** @defgroup HRTIM_TimerUpdateTrigger
826 * @{
827 * @brief Constants defining whether the registers update is done synchronously
828 * with any other timer or master update
829 */
830 #define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
831 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
832 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
833 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
834 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
835 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
836 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
837
838 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
839 /**
840 * @}
841 */
842
843 /** @defgroup HRTIM_TimerResetTrigger
844 * @{
845 * @brief Constants defining the events that can be selected to trigger the reset
846 * of the timer counter
847 */
848 #define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
849 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
850 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
851 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
852 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
853 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
854 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
855 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
856 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
857 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
858 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
859 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
860 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
861 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
862 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
863 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
864 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
865 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
866 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
867 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
868 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
869 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
870 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
871 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
872 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
873 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
874 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
875 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
876 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
877 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
878 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
879
880 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
881
882 /**
883 * @}
884 */
885
886 /** @defgroup HRTIM_TimerResetUpdate
887 * @{
888 * @brief Constants defining whether the register are updated upon Timerx
889 * counter reset or rollover to 0 after reaching the period value
890 * in continuous mode
891 */
892 #define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / rollover disabled */
893 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / rollover enabled */
894
895 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
896 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
897 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
898 /**
899 * @}
900 */
901
902 /** @defgroup HRTIM_CompareUnitAutoDelayedMode
903 * @{
904 * @brief Constants defining whether the compare register is behaving in
905 * regular mode (compare match issued as soon as counter equal compare),
906 * or in auto-delayed mode
907 */
908 #define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
909 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */
910 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
911 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
912
913 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
914 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
915 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
916 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
917 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
918
919 /* Auto delayed mode is only available for compare units 2 and 4 */
920 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
921 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \
922 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
923 || \
924 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
925 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
926 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
927 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
928 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
929 || \
930 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \
931 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
932 || \
933 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
934 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
935 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
936 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
937 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
938 /**
939 * @}
940 */
941
942 /** @defgroup HRTIM_BasicOCMode
943 * @{
944 * @brief Constants defining the behavior of the output signal when the timer
945 operates in basic output compare mode
946 */
947 #define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Output toggles when the timer counter reaches the compare value */
948 #define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Output forced to active level when the timer counter reaches the compare value */
949 #define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Output forced to inactive level when the timer counter reaches the compare value */
950
951 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
952 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
953 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
954 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
955 /**
956 * @}
957 */
958
959 /** @defgroup HRTIM_OutputPolarity
960 * @{
961 * @brief Constants defining the polarity of a timer output
962 */
963 #define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is active HIGH */
964 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
965
966 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
967 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
968 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
969 /**
970 * @}
971 */
972
973 /** @defgroup HRTIM_OutputSetSource
974 * @{
975 * @brief Constants defining the events that can be selected to configure the
976 * set crossbar of a timer output
977 */
978 #define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
979 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
980 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
981 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
982 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
983 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
984 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
985 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
986 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
987 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
988 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
989 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
990 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
991 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
992 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
993 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
994 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
995 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
996 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
997 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
998 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
999 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
1000 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
1001 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
1002 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
1003 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
1004 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
1005 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
1006 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
1007 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
1008 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
1009 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
1010
1011 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
1012 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
1013 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
1014 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
1015 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
1016 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
1017 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
1018 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
1019 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
1020 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
1021 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
1022 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
1023 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
1024 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
1025 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
1026 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
1027 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
1028 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
1029 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
1030 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
1031 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
1032 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
1033 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
1034 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
1035 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
1036 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
1037 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
1038 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
1039 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
1040 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
1041 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
1042 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
1043 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup HRTIM_OutputResetSource
1049 * @{
1050 * @brief Constants defining the events that can be selected to configure the
1051 * set crossbar of a timer output
1052 */
1053 #define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
1054 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1055 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1056 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1057 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1058 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1059 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1060 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1061 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1062 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1063 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1064 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1065 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1066 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1067 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1068 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1069 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1070 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1071 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1072 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1073 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1074 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1075 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1076 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1077 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1078 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1079 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1080 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1081 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1082 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1083 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1084 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1085
1086 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
1087 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
1088 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
1089 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
1090 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
1091 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
1092 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
1093 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
1094 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
1095 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
1096 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
1097 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
1098 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
1099 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
1100 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
1101 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
1102 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
1103 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
1104 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
1105 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
1106 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
1107 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
1108 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
1109 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
1110 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
1111 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
1112 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
1113 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
1114 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
1115 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
1116 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
1117 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
1118 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
1119 /**
1120 * @}
1121 */
1122
1123 /** @defgroup HRTIM_OutputIdleMode
1124 * @{
1125 * @brief Constants defining whether or not the timer output transition to its
1126 IDLE state when burst mode is entered
1127 */
1128 #define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
1129 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1130
1131 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
1132 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
1133 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup HRTIM_OutputIDLEState
1139 * @{
1140 * @brief Constants defining the IDLE state of a timer output
1141 */
1142 #define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
1143 #define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1144
1145 #define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\
1146 (((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) || \
1147 ((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE))
1148 /**
1149 * @}
1150 */
1151
1152 /** @defgroup HRTIM_OutputFAULTState
1153 * @{
1154 * @brief Constants defining the FAULT state of a timer output
1155 */
1156 #define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
1157 #define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1158 #define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1159 #define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1160
1161 #define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\
1162 (((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) || \
1163 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) || \
1164 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) || \
1165 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ))
1166 /**
1167 * @}
1168 */
1169
1170 /** @defgroup HRTIM_OutputChopperModeEnable
1171 * @{
1172 * @brief Constants defining whether or not chopper mode is enabled for a timer
1173 output
1174 */
1175 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
1176 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output at active level when in FAULT state */
1177
1178 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
1179 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
1180 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
1181 /**
1182 * @}
1183 */
1184
1185 /** @defgroup HRTIM_OutputBurstModeEntryDelayed
1186 * @{
1187 * @brief Constants defining the idle mode entry is delayed by forcing a
1188 deadtime insertion before switching the outputs to their idle state
1189 */
1190 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
1191 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1192
1193 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
1194 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
1195 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup HRTIM_CaptureUnitTrigger
1201 * @{
1202 * @brief Constants defining the events that can be selected to trigger the
1203 * capture of the timing unit counter
1204 */
1205 #define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
1206 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
1207 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
1208 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
1209 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
1210 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
1211 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
1212 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
1213 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
1214 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
1215 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
1216 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
1217 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
1218 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
1219 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) /*!< Timer A Compare 1 triggers Capture */
1220 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) /*!< Timer A Compare 2 triggers Capture */
1221 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
1222 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
1223 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) /*!< Timer B Compare 1 triggers Capture */
1224 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) /*!< Timer B Compare 2 triggers Capture */
1225 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
1226 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
1227 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) /*!< Timer C Compare 1 triggers Capture */
1228 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) /*!< Timer C Compare 2 triggers Capture */
1229 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
1230 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
1231 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) /*!< Timer D Compare 1 triggers Capture */
1232 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) /*!< Timer D Compare 2 triggers Capture */
1233 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
1234 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
1235 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) /*!< Timer E Compare 1 triggers Capture */
1236 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) /*!< Timer E Compare 2 triggers Capture */
1237
1238 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
1239 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
1240 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
1241 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
1242 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
1243 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
1244 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
1245 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
1246 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
1247 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
1248 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
1249 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
1250 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
1251 || \
1252 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
1253 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1254 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1255 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1256 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \
1257 || \
1258 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
1259 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1260 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1261 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1262 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \
1263 || \
1264 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
1265 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1266 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1267 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1268 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \
1269 || \
1270 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
1271 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1272 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1273 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1274 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
1275 || \
1276 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
1277 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1278 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1279 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1280 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup HRTIM_TimerExternalEventFilter
1286 * @{
1287 * @brief Constants defining the event filtering applied to external events
1288 * by a timer
1289 */
1290 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
1291 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
1292 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
1293 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
1294 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
1295 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1296 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1297 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1298 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1299 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1300 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1301 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1302 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1303 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
1304 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
1305 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1306
1307 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
1308 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
1309 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
1310 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
1311 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
1312 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
1313 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
1314 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
1315 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
1316 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
1317 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
1318 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
1319 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
1320 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
1321 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
1322 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
1323 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup HRTIM_TimerExternalEventLatch
1329 * @{
1330 * @brief Constants defining whether or not the external event is
1331 * memorized (latched) and generated as soon as the blanking period
1332 * is completed or the window ends
1333 */
1334 #define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
1335 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event 1 is latched and delayed till the end of the blanking or windowing period */ /*!< Blanking from counter reset/roll-over to Compare 1 */
1336
1337 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
1338 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
1339 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
1340 /**
1341 * @}
1342 */
1343
1344 /** @defgroup HRTIM_DeadtimeRisingSign
1345 * @{
1346 * @brief Constants defining whether the deadtime is positive or negative
1347 * (overlapping signal) on rising edge
1348 */
1349 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
1350 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1351
1352 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
1353 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
1354 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
1355 /**
1356 * @}
1357 */
1358
1359 /** @defgroup HRTIM_DeadtimeRisingLock
1360 * @{
1361 * @brief Constants defining whether or not the deadtime (rising sign and
1362 * value) is write protected
1363 */
1364 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */
1365 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
1366
1367 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
1368 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
1369 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
1370 /**
1371 * @}
1372 */
1373
1374 /** @defgroup HRTIM_DeadtimeRisingSignLock
1375 * @{
1376 * @brief Constants defining whether or not the deadtime rising sign is write
1377 * protected
1378 */
1379 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */
1380 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
1381
1382 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
1383 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
1384 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup HRTIM_DeadtimeFallingSign
1390 * @{
1391 * @brief Constants defining whether the deadtime is positive or negative
1392 * (overlapping signal) on falling edge
1393 */
1394 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
1395 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1396
1397 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
1398 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
1399 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
1400 /**
1401 * @}
1402 */
1403
1404 /** @defgroup HRTIM_DeadtimeFallingLock
1405 * @{
1406 * @brief Constants defining whether or not the deadtime (falling sign and
1407 * value) is write protected
1408 */
1409 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */
1410 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
1411
1412 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
1413 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
1414 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
1415 /**
1416 * @}
1417 */
1418
1419 /** @defgroup HRTIM_DeadtimeFallingSignLock
1420 * @{
1421 * @brief Constants defining whether or not the deadtime falling sign is write
1422 * protected
1423 */
1424 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */
1425 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
1426
1427 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
1428 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
1429 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
1430 /**
1431 * @}
1432 */
1433
1434 /** @defgroup HRTIM_SynchronizationInputSource
1435 * @{
1436 * @brief Constants defining defining the synchronization input source
1437 */
1438 #define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
1439 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
1440 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
1441
1442 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
1443 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
1444 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
1445 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
1446 /**
1447 * @}
1448 */
1449
1450 /** @defgroup HRTIM_SynchronizationOutputSource
1451 * @{
1452 * @brief Constants defining the source and event to be sent on the
1453 * synchronization outputs
1454 */
1455 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */
1456 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/
1457 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */
1458 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */
1459
1460 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
1461 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
1462 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
1463 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
1464 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
1465 /**
1466 * @}
1467 */
1468
1469 /** @defgroup HRTIM_SynchronizationOutputPolarity
1470 * @{
1471 * @brief Constants defining the routing and conditioning of the synchronization output event
1472 */
1473 #define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
1474 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1475 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1476
1477 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
1478 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
1479 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
1480 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
1481 /**
1482 * @}
1483 */
1484
1485 /** @defgroup HRTIM_ExternalEventSources
1486 * @{
1487 * @brief Constants defining available sources associated to external events
1488 */
1489 #define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
1490 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
1491 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
1492 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
1493
1494 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
1495 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
1496 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
1497 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
1498 ((EVENTSRC) == HRTIM_EVENTSRC_4))
1499 /**
1500 * @}
1501 */
1502
1503 /** @defgroup HRTIM_ExternalEventPolarity
1504 * @{
1505 * @brief Constants defining the polarity of an external event
1506 */
1507 #define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
1508 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1509
1510 #define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\
1511 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
1512 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))
1513 /**
1514 * @}
1515 */
1516
1517 /** @defgroup HRTIM_ExternalEventSensitivity
1518 * @{
1519 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
1520 * of an external event
1521 */
1522 #define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
1523 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1524 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1525 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1526
1527 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
1528 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
1529 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
1530 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
1531 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
1532 /**
1533 * @}
1534 */
1535
1536 /** @defgroup HRTIM_ExternalEventFastMode
1537 * @{
1538 * @brief Constants defining whether or not an external event is programmed in
1539 fast mode
1540 */
1541 #define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1542 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1543
1544 #define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\
1545 (((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
1546 ((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))
1547
1548 #define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\
1549 (((EVENT) == HRTIM_EVENT_1) || \
1550 ((EVENT) == HRTIM_EVENT_2) || \
1551 ((EVENT) == HRTIM_EVENT_3) || \
1552 ((EVENT) == HRTIM_EVENT_4) || \
1553 ((EVENT) == HRTIM_EVENT_5))
1554 /**
1555 * @}
1556 */
1557
1558 /** @defgroup HRTIM_ExternalEventFilter
1559 * @{
1560 * @brief Constants defining the frequency used to sample an external event 6
1561 * input and the length (N) of the digital filter applied
1562 */
1563 #define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1564 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1565 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1566 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1567 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
1568 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
1569 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
1570 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
1571 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
1572 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
1573 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
1574 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
1575 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
1576 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
1577 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
1578 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
1579
1580 #define IS_HRTIM_EVENTFILTER(EVENTFILTER)\
1581 (((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) || \
1582 ((EVENTFILTER) == HRTIM_EVENTFILTER_1) || \
1583 ((EVENTFILTER) == HRTIM_EVENTFILTER_2) || \
1584 ((EVENTFILTER) == HRTIM_EVENTFILTER_3) || \
1585 ((EVENTFILTER) == HRTIM_EVENTFILTER_4) || \
1586 ((EVENTFILTER) == HRTIM_EVENTFILTER_5) || \
1587 ((EVENTFILTER) == HRTIM_EVENTFILTER_6) || \
1588 ((EVENTFILTER) == HRTIM_EVENTFILTER_7) || \
1589 ((EVENTFILTER) == HRTIM_EVENTFILTER_8) || \
1590 ((EVENTFILTER) == HRTIM_EVENTFILTER_9) || \
1591 ((EVENTFILTER) == HRTIM_EVENTFILTER_10) || \
1592 ((EVENTFILTER) == HRTIM_EVENTFILTER_11) || \
1593 ((EVENTFILTER) == HRTIM_EVENTFILTER_12) || \
1594 ((EVENTFILTER) == HRTIM_EVENTFILTER_13) || \
1595 ((EVENTFILTER) == HRTIM_EVENTFILTER_14) || \
1596 ((EVENTFILTER) == HRTIM_EVENTFILTER_15))
1597 /**
1598 * @}
1599 */
1600
1601 /** @defgroup HRTIM_ ExternalEventPrescaler
1602 * @{
1603 * @brief Constants defining division ratio between the timer clock frequency
1604 * fHRTIM) and the external event signal sampling clock (fEEVS)
1605 * used by the digital filters
1606 */
1607 #define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
1608 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
1609 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
1610 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
1611
1612 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
1613 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
1614 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
1615 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
1616 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
1617 /**
1618 * @}
1619 */
1620
1621 /** @defgroup HRTIM_FaultSources
1622 * @{
1623 * @brief Constants defining whether a faults is be triggered by any external
1624 * or internal fault source
1625 */
1626 #define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
1627 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1628
1629
1630 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
1631 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
1632 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
1633 /**
1634 * @}
1635 */
1636
1637 /** @defgroup HRTIM_FaultPolarity
1638 * @{
1639 * @brief Constants defining the polarity of a fault event
1640 */
1641 #define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
1642 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1643
1644 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
1645 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
1646 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
1647 /**
1648 * @}
1649 */
1650
1651 /** @defgroup HRTIM_FaultFilter
1652 * @{
1653 * @ brief Constants defining the frequency used to sample the fault input and
1654 * the length (N) of the digital filter applied
1655 */
1656 #define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1657 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1658 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1659 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1660 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1661 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1662 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1663 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1664 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1665 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1666 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1667 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1668 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1669 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1670 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1671 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1672
1673 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
1674 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
1675 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
1676 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
1677 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
1678 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
1679 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
1680 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
1681 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
1682 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
1683 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
1684 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
1685 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
1686 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
1687 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
1688 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
1689 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
1690 /**
1691 * @}
1692 */
1693
1694 /** @defgroup HRTIM_FaultLock
1695 * @{
1696 * @brief Constants defining whether or not the fault programming bits are
1697 write protected
1698 */
1699 #define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
1700 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
1701
1702 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
1703 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
1704 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
1705 /**
1706 * @}
1707 */
1708
1709 /** @defgroup HRTIM_ExternalFaultPrescaler
1710 * @{
1711 * @brief Constants defining the division ratio between the timer clock
1712 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
1713 * by the digital filters.
1714 */
1715 #define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
1716 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
1717 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
1718 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
1719
1720 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
1721 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
1722 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
1723 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
1724 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
1725 /**
1726 * @}
1727 */
1728
1729 /** @defgroup HRTIM_BurstModeOperatingmode
1730 * @{
1731 * @brief Constants defining if the burst mode is entered once or if it is
1732 * continuously operating
1733 */
1734 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
1735 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1736
1737 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
1738 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
1739 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup HRTIM_BurstModeClockSource
1745 * @{
1746 * @brief Constants defining the clock source for the burst mode counter
1747 */
1748 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1749 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1750 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1751 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1752 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1753 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1754 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1755 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1756 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1757 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock */
1758 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1759
1760 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
1761 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
1762 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
1763 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
1764 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
1765 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
1766 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
1767 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) || \
1768 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) || \
1769 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) || \
1770 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) || \
1771 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
1772 /**
1773 * @}
1774 */
1775
1776 /** @defgroup HRTIM_BurstModePrescaler
1777 * @{
1778 * @brief Constants defining the prescaling ratio of the fHRTIM clock
1779 * for the burst mode controller
1780 */
1781 #define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
1782 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2 */
1783 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/4 */
1784 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8 */
1785 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/16 */
1786 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32 */
1787 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/64 */
1788 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/128 */
1789 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) /*!< fBRST = fHRTIM/256 */
1790 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/512 */
1791 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/1024 */
1792 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2048*/
1793 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/4096 */
1794 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8192 */
1795 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/16384 */
1796 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32768 */
1797
1798 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
1799 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
1800 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
1801 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
1802 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
1803 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
1804 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
1805 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
1806 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
1807 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
1808 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
1809 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
1810 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
1811 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
1812 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
1813 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
1814 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
1815 /**
1816 * @}
1817 */
1818
1819 /** @defgroup HRTIM_BurstModeRegisterPreloadEnable
1820 * @{
1821 * @brief Constants defining whether or not burst mode registers preload
1822 mechanism is enabled, i.e. a write access into a preloadable register
1823 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
1824 */
1825 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
1826 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
1827
1828 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
1829 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
1830 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
1831 /**
1832 * @}
1833 */
1834
1835 /** @defgroup HRTIM_BurstModeTrigger
1836 * @{
1837 * @brief Constants defining the events that can be used tor trig the burst
1838 * mode operation
1839 */
1840 #define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000
1841 #define HRTIM_BURSTMODETRIGGER_SOFTWARE (HRTIM_BMTRGR_SW) /*!< Software trigger */
1842 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
1843 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
1844 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
1845 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
1846 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
1847 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
1848 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
1849 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
1850 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
1851 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
1852 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
1853 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
1854 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
1855 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
1856 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
1857 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
1858 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
1859 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
1860 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
1861 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
1862 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
1863 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
1864 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
1865 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
1866 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
1867 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
1868 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
1869 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
1870 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 */
1871 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 */
1872 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
1873
1874 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
1875 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
1876 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
1877 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
1878 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
1879 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
1880 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
1881 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
1882 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
1883 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
1884 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
1885 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
1886 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
1887 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
1888 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
1889 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
1890 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
1891 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
1892 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
1893 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
1894 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
1895 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
1896 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
1897 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
1898 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
1899 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
1900 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
1901 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
1902 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
1903 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
1904 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
1905 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
1906 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
1907 /**
1908 * @}
1909 */
1910
1911 /** @defgroup HRTIM_ADCTriggerUpdateSource
1912 * @{
1913 * @brief constants defining the source triggering the update of the
1914 HRTIM_ADCxR register (transfer from preload to active register).
1915 */
1916 #define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
1917 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
1918 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
1919 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
1920 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
1921 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
1922
1923 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
1924 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
1925 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
1926 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
1927 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
1928 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
1929 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
1930 /**
1931 * @}
1932 */
1933
1934 /** @defgroup HRTIM_ADCTriggerEvent
1935 * @{
1936 * @brief constants defining the events triggering ADC conversion.
1937 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
1938 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
1939 */
1940 #define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
1941 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
1942 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
1943 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
1944 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
1945 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
1946 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
1947 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
1948 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
1949 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
1950 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
1951 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
1952 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
1953 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
1954 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
1955 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
1956 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
1957 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
1958 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
1959 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
1960 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
1961 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
1962 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
1963 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
1964 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
1965 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
1966 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
1967 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
1968 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
1969 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
1970 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
1971 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
1972 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
1973
1974 #define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
1975 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
1976 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
1977 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
1978 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
1979 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
1980 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
1981 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
1982 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
1983 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
1984 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
1985 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
1986 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
1987 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
1988 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
1989 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
1990 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
1991 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
1992 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
1993 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
1994 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
1995 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
1996 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
1997 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
1998 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
1999 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
2000 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
2001 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
2002 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
2003 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
2004 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
2005 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
2006 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
2007
2008 /**
2009 * @}
2010 */
2011
2012 /** @defgroup HRTIM_DLLCalibrationRate
2013 * @{
2014 * @brief Constants defining the DLL calibration periods (in micro seconds)
2015 */
2016
2017 #define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF /*!< Non periodic DLL calibration */
2018 #define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< 1048576 * tHRTIM (7.3 ms) */
2019 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
2020 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< 131072 * tHRTIM (910 µs) */
2021 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
2022
2023 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2024 (((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2025 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
2026 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
2027 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2028 /**
2029 * @}
2030 */
2031
2032 /** @defgroup HRTIM_BurstDMARegistersUpdate
2033 * @{
2034 * @brief Constants defining the registers that can be written during a burst
2035 * DMA operation
2036 */
2037 #define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
2038 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
2039 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
2040 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
2041 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
2042 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
2043 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
2044 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
2045 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
2046 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
2047 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
2048 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
2049 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
2050 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
2051 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
2052 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
2053 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
2054 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
2055 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
2056 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
2057 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
2058 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
2059
2060 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
2061 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
2062 || \
2063 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2064 || \
2065 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2066 || \
2067 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2068 || \
2069 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2070 || \
2071 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
2072 /**
2073 * @}
2074 */
2075
2076 /** @defgroup HRTIM_BursttModeControl
2077 * @{
2078 * @brief Constants used to enable or disable the burst mode controller
2079 */
2080 #define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
2081 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
2082
2083 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2084 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
2085 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2086 /**
2087 * @}
2088 */
2089
2090 /** @defgroup HRTIM_FaultModeControl
2091 * @{
2092 * @brief Constants used to enable or disable the Fault mode
2093 */
2094 #define HRTIM_FAULT_DISABLED (uint32_t)0x00000000 /*!< Fault mode disabled */
2095 #define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) /*!< Fault mode enabled */
2096
2097 #define IS_HRTIM_FAULTCTL(FAULTCTL)\
2098 (((FAULTCTL) == HRTIM_FAULT_DISABLED) || \
2099 ((FAULTCTL) == HRTIM_FAULT_ENABLED))
2100 /**
2101 * @}
2102 */
2103
2104 /** @defgroup HRTIM_SoftwareTimerUpdate
2105 * @{
2106 * @brief Constants used to force timer registers update
2107 */
2108 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
2109 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
2110 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
2111 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
2112 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
2113 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
2114
2115 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
2116 /**
2117 * @}
2118 */
2119
2120 /** @defgroup HRTIM_SoftwareTimerReset
2121 * @{
2122 * @brief Constants used to force timer counter reset
2123 */
2124 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
2125 #define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
2126 #define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
2127 #define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
2128 #define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
2129 #define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
2130
2131 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
2132 /**
2133 * @}
2134 */
2135
2136 /** @defgroup HRTIM_OutputLevel
2137 * @{
2138 * @brief Constants defining the level of a timer output
2139 */
2140 #define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
2141 #define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
2142
2143 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
2144 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
2145 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
2146 /**
2147 * @}
2148 */
2149
2150 /** @defgroup HRTIM_OutputState
2151 * @{
2152 * @brief Constants defining the state of a timer output
2153 */
2154 #define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
2155 inactive level as programmed in the crossbar unit */
2156 #define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
2157 outputs are disabled by software or during a burst mode operation */
2158 #define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
2159 FAULTx inputs */
2160 /**
2161 * @}
2162 */
2163
2164 /** @defgroup HRTIM_BurstModeStatus
2165 * @{
2166 * @brief Constants defining the operating state of the burst mode controller
2167 */
2168 #define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
2169 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
2170 /**
2171 * @}
2172 */
2173
2174 /** @defgroup HRTIM_CurrentPushPullStatus
2175 * @{
2176 * @brief Constants defining on which output the signal is currently applied
2177 * in push-pull mode
2178 */
2179 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
2180 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
2181 /**
2182 * @}
2183 */
2184
2185 /** @defgroup HRTIM_IdlePushPullStatus
2186 * @{
2187 * @brief Constants defining on which output the signal was applied, in
2188 * push-pull mode balanced fault mode or delayed idle mode, when the
2189 * protection was triggered
2190 */
2191 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
2192 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
2193 /**
2194 * @}
2195 */
2196
2197 /** @defgroup HRTIM_CommonInterrupt
2198 * @{
2199 */
2200 #define HRTIM_IT_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
2201 #define HRTIM_IT_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
2202 #define HRTIM_IT_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
2203 #define HRTIM_IT_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
2204 #define HRTIM_IT_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
2205 #define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
2206 #define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
2207 #define HRTIM_IT_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
2208
2209 #define IS_HRTIM_IT(IT)\
2210 (((IT) == HRTIM_ISR_FLT1) || \
2211 ((IT) == HRTIM_ISR_FLT2) || \
2212 ((IT) == HRTIM_ISR_FLT3) || \
2213 ((IT) == HRTIM_ISR_FLT4) || \
2214 ((IT) == HRTIM_ISR_FLT5) || \
2215 ((IT) == HRTIM_ISR_SYSFLT) || \
2216 ((IT) == HRTIM_ISR_DLLRDY) || \
2217 ((IT) == HRTIM_ISR_BMPER))
2218
2219 /**
2220 * @}
2221 */
2222 /** @defgroup HRTIM_CommonFlag
2223 * @{
2224 */
2225 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
2226 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
2227 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
2228 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
2229 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
2230 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
2231 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
2232 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
2233
2234 #define IS_HRTIM_FLAG(FLAG)\
2235 (((FLAG) == HRTIM_ISR_FLT1) || \
2236 ((FLAG) == HRTIM_ISR_FLT2) || \
2237 ((FLAG) == HRTIM_ISR_FLT3) || \
2238 ((FLAG) == HRTIM_ISR_FLT4) || \
2239 ((FLAG) == HRTIM_ISR_FLT5) || \
2240 ((FLAG) == HRTIM_ISR_SYSFLT) || \
2241 ((FLAG) == HRTIM_ISR_DLLRDY) || \
2242 ((FLAG) == HRTIM_ISR_BMPER))
2243 /**
2244 * @}
2245 */
2246
2247 /** @defgroup HRTIM_MasterInterrupt
2248 * @{
2249 */
2250 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt flag */
2251 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt flag */
2252 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt flag */
2253 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt flag */
2254 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt flag */
2255 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt flag */
2256 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt flag */
2257
2258 #define IS_HRTIM_MASTER_IT(IT)\
2259 (((IT) == HRTIM_MDIER_MCMP1IE) || \
2260 ((IT) == HRTIM_MDIER_MCMP2IE) || \
2261 ((IT) == HRTIM_MDIER_MCMP3IE) || \
2262 ((IT) == HRTIM_MDIER_MCMP4IE) || \
2263 ((IT) == HRTIM_MDIER_MREPIE) || \
2264 ((IT) == HRTIM_MDIER_SYNCIE) || \
2265 ((IT) == HRTIM_MDIER_MUPDIE))
2266
2267 /** @defgroup HRTIM_MasterFlag
2268 * @{
2269 */
2270 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
2271 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
2272 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
2273 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
2274 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
2275 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
2276 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
2277
2278 #define IS_HRTIM_MASTER_FLAG(FLAG)\
2279 (((FLAG) == HRTIM_MISR_MCMP1) || \
2280 ((FLAG) == HRTIM_MISR_MCMP2) || \
2281 ((FLAG) == HRTIM_MISR_MCMP3) || \
2282 ((FLAG) == HRTIM_MISR_MCMP4) || \
2283 ((FLAG) == HRTIM_MISR_MREP) || \
2284 ((FLAG) == HRTIM_MISR_SYNC) || \
2285 ((FLAG) == HRTIM_MISR_MUPD))
2286 /**
2287 * @}
2288 */
2289
2290 /** @defgroup HRTIM_TimingUnitInterrupt
2291 * @{
2292 */
2293 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt flag */
2294 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt flag */
2295 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt flag */
2296 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt flag */
2297 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt flag */
2298 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt flag */
2299 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt flag */
2300 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt flag */
2301 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt flag */
2302 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt flag */
2303 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt flag */
2304 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt flag */
2305 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
2306 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt flag */
2307
2308 #define IS_HRTIM_TIM_IT(IT)\
2309 (((IT) == HRTIM_TIMDIER_CMP1IE) || \
2310 ((IT) == HRTIM_TIMDIER_CMP2IE) || \
2311 ((IT) == HRTIM_TIMDIER_CMP3IE) || \
2312 ((IT) == HRTIM_TIMDIER_CMP4IE) || \
2313 ((IT) == HRTIM_TIMDIER_REPIE) || \
2314 ((IT) == HRTIM_TIMDIER_UPDIE) || \
2315 ((IT) == HRTIM_TIMDIER_CPT1IE) || \
2316 ((IT) == HRTIM_TIMDIER_CPT2IE) || \
2317 ((IT) == HRTIM_TIMDIER_SET1IE) || \
2318 ((IT) == HRTIM_TIMDIER_RST1IE) || \
2319 ((IT) == HRTIM_TIMDIER_SET2IE) || \
2320 ((IT) == HRTIM_TIMDIER_RST2IE) || \
2321 ((IT) == HRTIM_TIMDIER_RSTIE) || \
2322 ((IT) == HRTIM_TIMDIER_DLYPRTIE))
2323
2324 /**
2325 * @}
2326 */
2327
2328 /** @defgroup HRTIM_TimingUnitFlag
2329 * @{
2330 */
2331 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
2332 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
2333 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
2334 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
2335 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
2336 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
2337 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
2338 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
2339 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
2340 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
2341 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
2342 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
2343 #define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
2344 #define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
2345
2346 #define IS_HRTIM_TIM_FLAG(FLAG)\
2347 (((FLAG) == HRTIM_TIM_FLAG_CMP1) || \
2348 ((FLAG) == HRTIM_TIM_FLAG_CMP2) || \
2349 ((FLAG) == HRTIM_TIM_FLAG_CMP3) || \
2350 ((FLAG) == HRTIM_TIM_FLAG_CMP4) || \
2351 ((FLAG) == HRTIM_TIM_FLAG_REP) || \
2352 ((FLAG) == HRTIM_TIM_FLAG_UPD) || \
2353 ((FLAG) == HRTIM_TIM_FLAG_CPT1) || \
2354 ((FLAG) == HRTIM_TIM_FLAG_CPT2) || \
2355 ((FLAG) == HRTIM_TIM_FLAG_SET1) || \
2356 ((FLAG) == HRTIM_TIM_FLAG_RST1) || \
2357 ((FLAG) == HRTIM_TIM_FLAG_SET2) || \
2358 ((FLAG) == HRTIM_TIM_FLAG_RST2) || \
2359 ((FLAG) == HRTIM_TIM_FLAG_RST) || \
2360 ((FLAG) == HRTIM_TIM_FLAG_DLYPRT1))
2361
2362 /**
2363 * @}
2364 */
2365
2366 /** @defgroup HRTIM_MasterDMARequest
2367 * @{
2368 */
2369 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request flag */
2370 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request flag */
2371 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request flag */
2372 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request flag */
2373 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request flag */
2374 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request flag */
2375 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request flag */
2376
2377 #define IS_HRTIM_MASTER_DMA(DMA)\
2378 (((DMA) == HRTIM_MDIER_MCMP1DE) || \
2379 ((DMA) == HRTIM_MDIER_MCMP2DE) || \
2380 ((DMA) == HRTIM_MDIER_MCMP3DE) || \
2381 ((DMA) == HRTIM_MDIER_MCMP4DE) || \
2382 ((DMA) == HRTIM_MDIER_MREPDE) || \
2383 ((DMA) == HRTIM_MDIER_SYNCDE) || \
2384 ((DMA) == HRTIM_MDIER_MUPDDE))
2385 /**
2386 * @}
2387 */
2388
2389 /** @defgroup HRTIM_TimingUnitDMARequest
2390 * @{
2391 */
2392 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 interrupt flag */
2393 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 interrupt flag */
2394 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 interrupt flag */
2395 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 interrupt flag */
2396 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition interrupt flag */
2397 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update interrupt flag */
2398 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 interrupt flag */
2399 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 interrupt flag */
2400 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set interrupt flag */
2401 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset interrupt flag */
2402 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set interrupt flag */
2403 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset interrupt flag */
2404 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset interrupt flag */
2405 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection interrupt flag */
2406
2407 #define IS_HRTIM_TIM_DMA(DMA)\
2408 (((DMA) == HRTIM_TIMDIER_CMP1DE) || \
2409 ((DMA) == HRTIM_TIMDIER_CMP2DE) || \
2410 ((DMA) == HRTIM_TIMDIER_CMP3DE) || \
2411 ((DMA) == HRTIM_TIMDIER_CMP4DE) || \
2412 ((DMA) == HRTIM_TIMDIER_REPDE) || \
2413 ((DMA) == HRTIM_TIMDIER_UPDDE) || \
2414 ((DMA) == HRTIM_TIMDIER_CPT1DE) || \
2415 ((DMA) == HRTIM_TIMDIER_CPT2DE) || \
2416 ((DMA) == HRTIM_TIMDIER_SET1DE) || \
2417 ((DMA) == HRTIM_TIMDIER_RST1DE) || \
2418 ((DMA) == HRTIM_TIMDIER_SET2DE) || \
2419 ((DMA) == HRTIM_TIMDIER_RST2DE) || \
2420 ((DMA) == HRTIM_TIMDIER_RSTDE) || \
2421 ((DMA) == HRTIM_TIMDIER_DLYPRTDE))
2422
2423 /**
2424 * @}
2425 */
2426
2427 /**
2428 * @}
2429 */
2430
2431 /** @defgroup HRTIM_Instancedefinition
2432 * @{
2433 */
2434 #define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
2435 /**
2436 * @}
2437 */
2438
2439 /**
2440 * @}
2441 */
2442
2443 /* Exported macro ------------------------------------------------------------*/
2444
2445
2446 /** @brief Enables or disables the timer counter(s)
2447 * @param __HANDLE__: specifies the HRTIM Handle.
2448 * @param __TIMERS__: timersto enable/disable
2449 * This parameter can be any combinations of the following values:
2450 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
2451 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
2452 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
2453 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
2454 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
2455 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
2456 * @retval None
2457 */
2458 #define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__))
2459
2460 /* The counter of a timing unit is disabled only if all the timer outputs */
2461 /* are disabled and no capture is configured */
2462 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2463 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2464 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2465 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2466 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2467 #define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2468 do {\
2469 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2470 {\
2471 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
2472 }\
2473 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2474 {\
2475 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
2476 {\
2477 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2478 }\
2479 }\
2480 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2481 {\
2482 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
2483 {\
2484 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2485 }\
2486 }\
2487 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2488 {\
2489 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
2490 {\
2491 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2492 }\
2493 }\
2494 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2495 {\
2496 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
2497 {\
2498 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2499 }\
2500 }\
2501 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2502 {\
2503 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
2504 {\
2505 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2506 }\
2507 }\
2508 } while(0)
2509
2510 /* Exported functions --------------------------------------------------------*/
2511
2512 /* Simple time base related functions *****************************************/
2513 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2514
2515 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
2516
2517 void HRTIM_SimpleBaseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx);
2518 void HRTIM_SimpleBaseStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx);
2519
2520 /* Simple output compare related functions ************************************/
2521 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2522
2523 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *HRTIMx,
2524 uint32_t TimerIdx,
2525 uint32_t OCChannel,
2526 HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
2527
2528 void HRTIM_SimpleOCStart(HRTIM_TypeDef *HRTIMx,
2529 uint32_t TimerIdx,
2530 uint32_t OCChannel);
2531 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
2532 uint32_t TimerIdx,
2533 uint32_t OCChannel);
2534 /* Simple PWM output related functions ****************************************/
2535 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2536
2537 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *HRTIMx,
2538 uint32_t TimerIdx,
2539 uint32_t PWMChannel,
2540 HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
2541
2542 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
2543 uint32_t TimerIdx,
2544 uint32_t PWMChannel);
2545 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
2546 uint32_t TimerIdx,
2547 uint32_t PWMChannel);
2548 /* Simple capture related functions *******************************************/
2549 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2550
2551 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *HRTIMx,
2552 uint32_t TimerIdx,
2553 uint32_t CaptureChannel,
2554 HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
2555
2556 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
2557 uint32_t TimerIdx,
2558 uint32_t CaptureChannel);
2559 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
2560 uint32_t TimerIdx,
2561 uint32_t CaptureChannel);
2562 /* SImple one pulse related functions *****************************************/
2563 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2564
2565 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *HRTIMx,
2566 uint32_t TimerIdx,
2567 uint32_t OnePulseChannel,
2568 HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
2569
2570 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
2571 uint32_t TimerIdx,
2572 uint32_t OnePulseChannel);
2573 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
2574 uint32_t TimerIdx,
2575 uint32_t OnePulseChannel);
2576 /* Waveform related functions *************************************************/
2577 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
2578 uint32_t TimerIdx,
2579 HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
2580 HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
2581
2582 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *HRTIMx,
2583 uint32_t TimerIdx,
2584 HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
2585
2586 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *HRTIMx,
2587 uint32_t TimerIdx,
2588 uint32_t CompareUnit,
2589 HRTIM_CompareCfgTypeDef* pCompareCfg);
2590
2591 void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx,
2592 uint32_t TimerIdx,
2593 uint32_t CompareUnit,
2594 uint32_t Compare);
2595
2596 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
2597 uint32_t CompareUnit,
2598 uint32_t Compare);
2599
2600 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *HRTIMx,
2601 uint32_t TimerIdx,
2602 uint32_t CaptureUnit,
2603 HRTIM_CaptureCfgTypeDef* pCaptureCfg);
2604
2605 void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *HRTIMx,
2606 uint32_t TimerIdx,
2607 uint32_t Output,
2608 HRTIM_OutputCfgTypeDef * pOutputCfg);
2609
2610 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *HRTIMx,
2611 uint32_t TimerIdx,
2612 uint32_t Event,
2613 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
2614
2615 void HRTIM_DeadTimeConfig(HRTIM_TypeDef *HRTIMx,
2616 uint32_t TimerIdx,
2617 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
2618
2619 void HRTIM_ChopperModeConfig(HRTIM_TypeDef *HRTIMx,
2620 uint32_t TimerIdx,
2621 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
2622
2623 void HRTIM_BurstDMAConfig(HRTIM_TypeDef *HRTIMx,
2624 uint32_t TimerIdx,
2625 uint32_t RegistersToUpdate);
2626
2627 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
2628 HRTIM_SynchroCfgTypeDef * pSynchroCfg);
2629
2630 void HRTIM_BurstModeConfig(HRTIM_TypeDef *HRTIMx,
2631 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
2632
2633 void HRTIM_EventConfig(HRTIM_TypeDef *HRTIMx,
2634 uint32_t Event,
2635 HRTIM_EventCfgTypeDef* pEventCfg);
2636
2637 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *HRTIMx,
2638 uint32_t Prescaler);
2639
2640 void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
2641 HRTIM_FaultCfgTypeDef* pFaultCfg,
2642 uint32_t Fault);
2643
2644 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *HRTIMx,
2645 uint32_t Prescaler);
2646 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
2647
2648 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *HRTIMx,
2649 uint32_t ADCTrigger,
2650 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
2651
2652 void HRTIM_WaveformCounterStart(HRTIM_TypeDef *HRTIMx,
2653 uint32_t TimersToStart);
2654
2655 void HRTIM_WaveformCounterStop(HRTIM_TypeDef *HRTIMx,
2656 uint32_t TimersToStop);
2657
2658 void HRTIM_WaveformOutputStart(HRTIM_TypeDef *HRTIMx,
2659 uint32_t OuputsToStart);
2660 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
2661 uint32_t OuputsToStop);
2662
2663 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *HRTIMx,
2664 uint32_t CalibrationRate);
2665
2666 /* Interrupt/flags and DMA management */
2667 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
2668 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
2669
2670 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2671 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2672
2673 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2674 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2675
2676 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2677 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2678
2679 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2680 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2681
2682
2683 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
2684
2685 void HRTIM_BurstModeCtl(HRTIM_TypeDef *HRTIMx,
2686 uint32_t Enable);
2687
2688 void HRTIM_SoftwareCapture(HRTIM_TypeDef *HRTIMx,
2689 uint32_t TimerIdx,
2690 uint32_t CaptureUnit);
2691
2692 void HRTIM_SoftwareUpdate(HRTIM_TypeDef *HRTIMx,
2693 uint32_t TimersToUpdate);
2694
2695 void HRTIM_SoftwareReset(HRTIM_TypeDef *HRTIMx,
2696 uint32_t TimersToReset);
2697
2698
2699 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *HRTIMx,
2700 uint32_t TimerIdx,
2701 uint32_t CaptureUnit);
2702
2703 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx,
2704 uint32_t TimerIdx,
2705 uint32_t Output,
2706 HRTIM_OutputCfgTypeDef * pOutputCfg);
2707
2708 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *HRTIMx,
2709 uint32_t TimerIdx,
2710 uint32_t Output,
2711 uint32_t OutputLevel);
2712
2713 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *HRTIMx,
2714 uint32_t TimerIdx,
2715 uint32_t Output);
2716
2717 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
2718 uint32_t TimerIdx,
2719 uint32_t Output);
2720
2721 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *HRTIMx,
2722 uint32_t TimerIdx,
2723 uint32_t Output);
2724
2725 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *HRTIMx);
2726
2727 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx,
2728 uint32_t TimerIdx);
2729
2730 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx,
2731 uint32_t TimerIdx);
2732 /**
2733 * @}
2734 */
2735
2736 /**
2737 * @}
2738 */
2739
2740 #ifdef __cplusplus
2741 }
2742 #endif
2743
2744 #endif /* __STM32F30x_HRTIM_H */
2745
2746 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/