2 ******************************************************************************
3 * @file stm32f30x_rcc.h
4 * @author MCD Application Team
7 * @brief This file contains all the functions prototypes for the RCC
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
18 * http://www.st.com/software_license_agreement_liberty_v2
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
26 ******************************************************************************
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_RCC_H
31 #define __STM32F30x_RCC_H
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
40 /** @addtogroup STM32F30x_StdPeriph_Driver
48 /* Exported types ------------------------------------------------------------*/
52 uint32_t SYSCLK_Frequency
;
53 uint32_t HCLK_Frequency
;
54 uint32_t PCLK1_Frequency
;
55 uint32_t PCLK2_Frequency
;
56 uint32_t ADC12CLK_Frequency
;
57 uint32_t ADC34CLK_Frequency
;
58 uint32_t I2C1CLK_Frequency
;
59 uint32_t I2C2CLK_Frequency
;
60 uint32_t I2C3CLK_Frequency
;
61 uint32_t TIM1CLK_Frequency
;
62 uint32_t HRTIM1CLK_Frequency
;
63 uint32_t TIM8CLK_Frequency
;
64 uint32_t USART1CLK_Frequency
;
65 uint32_t USART2CLK_Frequency
;
66 uint32_t USART3CLK_Frequency
;
67 uint32_t UART4CLK_Frequency
;
68 uint32_t UART5CLK_Frequency
;
69 uint32_t TIM15CLK_Frequency
;
70 uint32_t TIM16CLK_Frequency
;
71 uint32_t TIM17CLK_Frequency
;
74 /* Exported constants --------------------------------------------------------*/
76 /** @defgroup RCC_Exported_Constants
80 /** @defgroup RCC_HSE_configuration
84 #define RCC_HSE_OFF ((uint8_t)0x00)
85 #define RCC_HSE_ON ((uint8_t)0x01)
86 #define RCC_HSE_Bypass ((uint8_t)0x05)
87 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
88 ((HSE) == RCC_HSE_Bypass))
94 /** @defgroup RCC_PLL_Clock_Source
98 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
99 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
101 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
102 ((SOURCE) == RCC_PLLSource_PREDIV1))
107 /** @defgroup RCC_PLL_Multiplication_Factor
111 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
112 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
113 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
114 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
115 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
116 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
117 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
118 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
119 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
120 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
121 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
122 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
123 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
124 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
125 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
126 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
127 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
128 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
129 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
130 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
131 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
132 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
133 ((MUL) == RCC_PLLMul_16))
138 /** @defgroup RCC_PREDIV1_division_factor
141 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
142 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
143 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
144 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
145 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
146 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
147 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
148 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
149 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
150 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
151 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
152 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
153 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
154 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
155 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
156 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
158 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
159 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
160 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
161 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
162 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
163 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
164 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
165 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
170 /** @defgroup RCC_System_Clock_Source
174 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
175 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
176 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
177 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
178 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
179 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
184 /** @defgroup RCC_AHB_Clock_Source
188 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
189 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
190 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
191 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
192 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
193 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
194 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
195 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
196 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
197 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
198 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
199 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
200 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
201 ((HCLK) == RCC_SYSCLK_Div512))
206 /** @defgroup RCC_APB1_APB2_clock_source
210 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
211 #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
212 #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
213 #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
214 #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
215 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
216 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
217 ((PCLK) == RCC_HCLK_Div16))
222 /** @defgroup RCC_ADC_clock_source
227 #define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
228 #define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
229 #define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
230 #define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
231 #define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
232 #define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
233 #define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
234 #define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
235 #define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
236 #define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
237 #define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
238 #define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
239 #define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
242 #define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
243 #define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
244 #define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
245 #define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
246 #define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
247 #define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
248 #define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
249 #define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
250 #define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
251 #define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
252 #define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
253 #define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
254 #define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
256 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
257 ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
258 ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
259 ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
260 ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
261 ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
262 ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
263 ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
264 ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
265 ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
266 ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
267 ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
268 ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
274 /** @defgroup RCC_TIM_clock_source
278 #define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
279 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
281 #define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
282 #define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
284 #define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
285 #define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
287 #define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
288 #define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
290 #define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
291 #define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
293 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
294 ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
295 ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
296 ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
297 ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
303 /** @defgroup RCC_HRTIM_clock_source
307 #define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
308 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
310 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
316 /** @defgroup RCC_I2C_clock_source
320 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
321 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
323 #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
324 #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
326 #define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
327 #define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
329 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
330 ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
331 ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
337 /** @defgroup RCC_USART_clock_source
341 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
342 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
343 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
344 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
346 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
347 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
348 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
349 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
351 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
352 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
353 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
354 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
356 #define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
357 #define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
358 #define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
359 #define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
361 #define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
362 #define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
363 #define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
364 #define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
366 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
367 ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
368 ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
369 ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
370 ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
371 ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
372 ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
373 ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
374 ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
375 ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
381 /** @defgroup RCC_Interrupt_Source
385 #define RCC_IT_LSIRDY ((uint8_t)0x01)
386 #define RCC_IT_LSERDY ((uint8_t)0x02)
387 #define RCC_IT_HSIRDY ((uint8_t)0x04)
388 #define RCC_IT_HSERDY ((uint8_t)0x08)
389 #define RCC_IT_PLLRDY ((uint8_t)0x10)
390 #define RCC_IT_CSS ((uint8_t)0x80)
392 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
394 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
395 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
396 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
399 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
405 /** @defgroup RCC_LSE_configuration
409 #define RCC_LSE_OFF ((uint32_t)0x00000000)
410 #define RCC_LSE_ON RCC_BDCR_LSEON
411 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
412 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
413 ((LSE) == RCC_LSE_Bypass))
418 /** @defgroup RCC_RTC_Clock_Source
422 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
423 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
424 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
426 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
427 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
428 ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
433 /** @defgroup RCC_I2S_Clock_Source
436 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
437 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
439 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
441 /** @defgroup RCC_LSE_Drive_Configuration
445 #define RCC_LSEDrive_Low ((uint32_t)0x00000000)
446 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
447 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
448 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV
449 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
450 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
455 /** @defgroup RCC_AHB_Peripherals
459 #define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
460 #define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
461 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
462 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
463 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
464 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
465 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
466 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
467 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
468 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
469 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
470 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
471 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
472 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
474 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
475 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
481 /** @defgroup RCC_APB2_Peripherals
485 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
486 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
487 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
488 #define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
489 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
490 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
491 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
492 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
493 #define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
495 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
501 /** @defgroup RCC_APB1_Peripherals
504 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
505 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
506 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
507 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
508 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
509 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
510 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
511 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
512 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
513 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
514 #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
515 #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
516 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
517 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
518 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
519 #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
520 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
521 #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
522 #define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
523 #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
524 #define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
527 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
532 /** @defgroup RCC_MCO_Clock_Source
536 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
537 #define RCC_MCOSource_LSI ((uint8_t)0x02)
538 #define RCC_MCOSource_LSE ((uint8_t)0x03)
539 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
540 #define RCC_MCOSource_HSI ((uint8_t)0x05)
541 #define RCC_MCOSource_HSE ((uint8_t)0x06)
542 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
544 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
545 ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
546 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
547 ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
552 /** @defgroup RCC_MCOPrescaler
556 #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
557 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
558 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
559 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
560 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
561 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
562 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
563 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
565 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
566 ((PRESCALER) == RCC_MCOPrescaler_2) || \
567 ((PRESCALER) == RCC_MCOPrescaler_4) || \
568 ((PRESCALER) == RCC_MCOPrescaler_8) || \
569 ((PRESCALER) == RCC_MCOPrescaler_16) || \
570 ((PRESCALER) == RCC_MCOPrescaler_32) || \
571 ((PRESCALER) == RCC_MCOPrescaler_64) || \
572 ((PRESCALER) == RCC_MCOPrescaler_128))
577 /** @defgroup RCC_USB_Device_clock_source
581 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
582 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
584 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
585 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
590 /** @defgroup RCC_Flag
593 #define RCC_FLAG_HSIRDY ((uint8_t)0x01)
594 #define RCC_FLAG_HSERDY ((uint8_t)0x11)
595 #define RCC_FLAG_PLLRDY ((uint8_t)0x19)
596 #define RCC_FLAG_MCOF ((uint8_t)0x9C)
597 #define RCC_FLAG_LSERDY ((uint8_t)0x21)
598 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
599 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
600 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
601 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
602 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
603 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
604 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
605 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
607 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
608 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
609 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
610 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
611 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
612 ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
613 ((FLAG) == RCC_FLAG_MCOF))
615 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
625 /* Exported macro ------------------------------------------------------------*/
626 /* Exported functions ------------------------------------------------------- */
628 /* Function used to set the RCC clock configuration to the default reset state */
629 void RCC_DeInit(void);
631 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
632 void RCC_HSEConfig(uint8_t RCC_HSE
);
633 ErrorStatus
RCC_WaitForHSEStartUp(void);
634 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue
);
635 void RCC_HSICmd(FunctionalState NewState
);
636 void RCC_LSEConfig(uint32_t RCC_LSE
);
637 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive
);
638 void RCC_LSICmd(FunctionalState NewState
);
639 void RCC_PLLConfig(uint32_t RCC_PLLSource
, uint32_t RCC_PLLMul
);
640 void RCC_PLLCmd(FunctionalState NewState
);
641 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div
);
642 void RCC_ClockSecuritySystemCmd(FunctionalState NewState
);
644 void RCC_MCOConfig(uint8_t RCC_MCOSource
);
646 void RCC_MCOConfig(uint8_t RCC_MCOSource
,uint32_t RCC_MCOPrescaler
);
647 #endif /* STM32F303xC */
649 /* System, AHB and APB busses clocks configuration functions ******************/
650 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource
);
651 uint8_t RCC_GetSYSCLKSource(void);
652 void RCC_HCLKConfig(uint32_t RCC_SYSCLK
);
653 void RCC_PCLK1Config(uint32_t RCC_HCLK
);
654 void RCC_PCLK2Config(uint32_t RCC_HCLK
);
655 void RCC_GetClocksFreq(RCC_ClocksTypeDef
* RCC_Clocks
);
657 /* Peripheral clocks configuration functions **********************************/
658 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK
);
659 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK
);
660 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK
);
661 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK
);
662 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource
);
663 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK
);
664 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource
);
666 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource
);
667 void RCC_RTCCLKCmd(FunctionalState NewState
);
668 void RCC_BackupResetCmd(FunctionalState NewState
);
670 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph
, FunctionalState NewState
);
671 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph
, FunctionalState NewState
);
672 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph
, FunctionalState NewState
);
674 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph
, FunctionalState NewState
);
675 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph
, FunctionalState NewState
);
676 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph
, FunctionalState NewState
);
678 /* Interrupts and flags management functions **********************************/
679 void RCC_ITConfig(uint8_t RCC_IT
, FunctionalState NewState
);
680 FlagStatus
RCC_GetFlagStatus(uint8_t RCC_FLAG
);
681 void RCC_ClearFlag(void);
682 ITStatus
RCC_GetITStatus(uint8_t RCC_IT
);
683 void RCC_ClearITPendingBit(uint8_t RCC_IT
);
689 #endif /* __STM32F30x_RCC_H */
699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/