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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F30x_StdPeriph_Driver / inc / stm32f30x_spi.h
blob4cd0c3e679ca7e4327c7773f955ed075bc685d82
1 /**
2 ******************************************************************************
3 * @file stm32f30x_spi.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 04-April-2014
7 * @brief This file contains all the functions prototypes for the SPI
8 * firmware library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
13 *
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
17 *
18 * http://www.st.com/software_license_agreement_liberty_v2
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************
27 */
28
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_SPI_H
31 #define __STM32F30x_SPI_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39
40 /** @addtogroup STM32F30x_StdPeriph_Driver
41 * @{
42 */
43
44 /** @addtogroup SPI
45 * @{
46 */
47
48 /* Exported types ------------------------------------------------------------*/
49
50 /**
51 * @brief SPI Init structure definition
52 */
53
54 typedef struct
55 {
56 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
57 This parameter can be a value of @ref SPI_data_direction */
58
59 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
60 This parameter can be a value of @ref SPI_mode */
61
62 uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
63 This parameter can be a value of @ref SPI_data_size */
64
65 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
66 This parameter can be a value of @ref SPI_Clock_Polarity */
67
68 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
69 This parameter can be a value of @ref SPI_Clock_Phase */
70
71 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
72 hardware (NSS pin) or by software using the SSI bit.
73 This parameter can be a value of @ref SPI_Slave_Select_management */
74
75 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
76 used to configure the transmit and receive SCK clock.
77 This parameter can be a value of @ref SPI_BaudRate_Prescaler.
78 @note The communication clock is derived from the master
79 clock. The slave clock does not need to be set. */
80
81 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
82 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
83
84 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
85 }SPI_InitTypeDef;
86
87
88 /**
89 * @brief I2S Init structure definition
90 */
91
92 typedef struct
93 {
94 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
95 This parameter can be a value of @ref I2S_Mode */
96
97 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
98 This parameter can be a value of @ref I2S_Standard */
99
100 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
101 This parameter can be a value of @ref I2S_Data_Format */
102
103 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
104 This parameter can be a value of @ref I2S_MCLK_Output */
105
106 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
107 This parameter can be a value of @ref I2S_Audio_Frequency */
108
109 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
110 This parameter can be a value of @ref I2S_Clock_Polarity */
111 }I2S_InitTypeDef;
112
113 /* Exported constants --------------------------------------------------------*/
114
115 /** @defgroup SPI_Exported_Constants
116 * @{
117 */
118
119 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
120 ((PERIPH) == SPI2) || \
121 ((PERIPH) == SPI3))
122
123 #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
124 ((PERIPH) == SPI2) || \
125 ((PERIPH) == SPI3) || \
126 ((PERIPH) == I2S2ext) || \
127 ((PERIPH) == I2S3ext))
128
129 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
130 ((PERIPH) == SPI3))
131
132 #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
133 ((PERIPH) == SPI3) || \
134 ((PERIPH) == I2S2ext) || \
135 ((PERIPH) == I2S3ext))
136
137 #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
138 ((PERIPH) == I2S3ext))
139
140 /** @defgroup SPI_data_direction
141 * @{
142 */
143
144 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
145 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
146 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
147 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
148 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
149 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
150 ((MODE) == SPI_Direction_1Line_Rx) || \
151 ((MODE) == SPI_Direction_1Line_Tx))
152 /**
153 * @}
154 */
155
156 /** @defgroup SPI_mode
157 * @{
158 */
159
160 #define SPI_Mode_Master ((uint16_t)0x0104)
161 #define SPI_Mode_Slave ((uint16_t)0x0000)
162 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
163 ((MODE) == SPI_Mode_Slave))
164 /**
165 * @}
166 */
167
168 /** @defgroup SPI_data_size
169 * @{
170 */
171
172 #define SPI_DataSize_4b ((uint16_t)0x0300)
173 #define SPI_DataSize_5b ((uint16_t)0x0400)
174 #define SPI_DataSize_6b ((uint16_t)0x0500)
175 #define SPI_DataSize_7b ((uint16_t)0x0600)
176 #define SPI_DataSize_8b ((uint16_t)0x0700)
177 #define SPI_DataSize_9b ((uint16_t)0x0800)
178 #define SPI_DataSize_10b ((uint16_t)0x0900)
179 #define SPI_DataSize_11b ((uint16_t)0x0A00)
180 #define SPI_DataSize_12b ((uint16_t)0x0B00)
181 #define SPI_DataSize_13b ((uint16_t)0x0C00)
182 #define SPI_DataSize_14b ((uint16_t)0x0D00)
183 #define SPI_DataSize_15b ((uint16_t)0x0E00)
184 #define SPI_DataSize_16b ((uint16_t)0x0F00)
185 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
186 ((SIZE) == SPI_DataSize_5b) || \
187 ((SIZE) == SPI_DataSize_6b) || \
188 ((SIZE) == SPI_DataSize_7b) || \
189 ((SIZE) == SPI_DataSize_8b) || \
190 ((SIZE) == SPI_DataSize_9b) || \
191 ((SIZE) == SPI_DataSize_10b) || \
192 ((SIZE) == SPI_DataSize_11b) || \
193 ((SIZE) == SPI_DataSize_12b) || \
194 ((SIZE) == SPI_DataSize_13b) || \
195 ((SIZE) == SPI_DataSize_14b) || \
196 ((SIZE) == SPI_DataSize_15b) || \
197 ((SIZE) == SPI_DataSize_16b))
198 /**
199 * @}
200 */
201
202 /** @defgroup SPI_CRC_length
203 * @{
204 */
205
206 #define SPI_CRCLength_8b ((uint16_t)0x0000)
207 #define SPI_CRCLength_16b ((uint16_t)0x0800)
208 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
209 ((LENGTH) == SPI_CRCLength_16b))
210 /**
211 * @}
212 */
213
214 /** @defgroup SPI_Clock_Polarity
215 * @{
216 */
217
218 #define SPI_CPOL_Low ((uint16_t)0x0000)
219 #define SPI_CPOL_High ((uint16_t)0x0002)
220 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
221 ((CPOL) == SPI_CPOL_High))
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_Clock_Phase
227 * @{
228 */
229
230 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
231 #define SPI_CPHA_2Edge ((uint16_t)0x0001)
232 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
233 ((CPHA) == SPI_CPHA_2Edge))
234 /**
235 * @}
236 */
237
238 /** @defgroup SPI_Slave_Select_management
239 * @{
240 */
241
242 #define SPI_NSS_Soft ((uint16_t)0x0200)
243 #define SPI_NSS_Hard ((uint16_t)0x0000)
244 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
245 ((NSS) == SPI_NSS_Hard))
246 /**
247 * @}
248 */
249
250 /** @defgroup SPI_BaudRate_Prescaler
251 * @{
252 */
253
254 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
255 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
256 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
257 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
258 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
259 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
260 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
261 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
262 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
263 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
264 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
265 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
266 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
267 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
268 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
269 ((PRESCALER) == SPI_BaudRatePrescaler_256))
270 /**
271 * @}
272 */
273
274 /** @defgroup SPI_MSB_LSB_transmission
275 * @{
276 */
277
278 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
279 #define SPI_FirstBit_LSB ((uint16_t)0x0080)
280 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
281 ((BIT) == SPI_FirstBit_LSB))
282 /**
283 * @}
284 */
285
286 /** @defgroup I2S_Mode
287 * @{
288 */
289
290 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
291 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
292 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
293 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
294 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
295 ((MODE) == I2S_Mode_SlaveRx) || \
296 ((MODE) == I2S_Mode_MasterTx)|| \
297 ((MODE) == I2S_Mode_MasterRx))
298 /**
299 * @}
300 */
301
302 /** @defgroup I2S_Standard
303 * @{
304 */
305
306 #define I2S_Standard_Phillips ((uint16_t)0x0000)
307 #define I2S_Standard_MSB ((uint16_t)0x0010)
308 #define I2S_Standard_LSB ((uint16_t)0x0020)
309 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
310 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
311 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
312 ((STANDARD) == I2S_Standard_MSB) || \
313 ((STANDARD) == I2S_Standard_LSB) || \
314 ((STANDARD) == I2S_Standard_PCMShort) || \
315 ((STANDARD) == I2S_Standard_PCMLong))
316 /**
317 * @}
318 */
319
320 /** @defgroup I2S_Data_Format
321 * @{
322 */
323
324 #define I2S_DataFormat_16b ((uint16_t)0x0000)
325 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
326 #define I2S_DataFormat_24b ((uint16_t)0x0003)
327 #define I2S_DataFormat_32b ((uint16_t)0x0005)
328 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
329 ((FORMAT) == I2S_DataFormat_16bextended) || \
330 ((FORMAT) == I2S_DataFormat_24b) || \
331 ((FORMAT) == I2S_DataFormat_32b))
332 /**
333 * @}
334 */
335
336 /** @defgroup I2S_MCLK_Output
337 * @{
338 */
339
340 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
341 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
342 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
343 ((OUTPUT) == I2S_MCLKOutput_Disable))
344 /**
345 * @}
346 */
347
348 /** @defgroup I2S_Audio_Frequency
349 * @{
350 */
351
352 #define I2S_AudioFreq_192k ((uint32_t)192000)
353 #define I2S_AudioFreq_96k ((uint32_t)96000)
354 #define I2S_AudioFreq_48k ((uint32_t)48000)
355 #define I2S_AudioFreq_44k ((uint32_t)44100)
356 #define I2S_AudioFreq_32k ((uint32_t)32000)
357 #define I2S_AudioFreq_22k ((uint32_t)22050)
358 #define I2S_AudioFreq_16k ((uint32_t)16000)
359 #define I2S_AudioFreq_11k ((uint32_t)11025)
360 #define I2S_AudioFreq_8k ((uint32_t)8000)
361 #define I2S_AudioFreq_Default ((uint32_t)2)
362
363 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
364 ((FREQ) <= I2S_AudioFreq_192k)) || \
365 ((FREQ) == I2S_AudioFreq_Default))
366 /**
367 * @}
368 */
369
370 /** @defgroup I2S_Clock_Polarity
371 * @{
372 */
373
374 #define I2S_CPOL_Low ((uint16_t)0x0000)
375 #define I2S_CPOL_High ((uint16_t)0x0008)
376 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
377 ((CPOL) == I2S_CPOL_High))
378 /**
379 * @}
380 */
381
382 /** @defgroup SPI_FIFO_reception_threshold
383 * @{
384 */
385
386 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
387 #define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
388 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
389 ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
390 /**
391 * @}
392 */
393
394 /** @defgroup SPI_I2S_DMA_transfer_requests
395 * @{
396 */
397
398 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
399 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
400 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
401 /**
402 * @}
403 */
404
405 /** @defgroup SPI_last_DMA_transfers
406 * @{
407 */
408
409 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
410 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
411 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
412 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
413 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
414 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
415 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
416 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
417 /**
418 * @}
419 */
420 /** @defgroup SPI_NSS_internal_software_management
421 * @{
422 */
423
424 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
425 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
426 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
427 ((INTERNAL) == SPI_NSSInternalSoft_Reset))
428 /**
429 * @}
430 */
431
432 /** @defgroup SPI_CRC_Transmit_Receive
433 * @{
434 */
435
436 #define SPI_CRC_Tx ((uint8_t)0x00)
437 #define SPI_CRC_Rx ((uint8_t)0x01)
438 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
439 /**
440 * @}
441 */
442
443 /** @defgroup SPI_direction_transmit_receive
444 * @{
445 */
446
447 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
448 #define SPI_Direction_Tx ((uint16_t)0x4000)
449 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
450 ((DIRECTION) == SPI_Direction_Tx))
451 /**
452 * @}
453 */
454
455 /** @defgroup SPI_I2S_interrupts_definition
456 * @{
457 */
458
459 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
460 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
461 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
462
463 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
464 ((IT) == SPI_I2S_IT_RXNE) || \
465 ((IT) == SPI_I2S_IT_ERR))
466
467 #define I2S_IT_UDR ((uint8_t)0x53)
468 #define SPI_IT_MODF ((uint8_t)0x55)
469 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
470 #define SPI_I2S_IT_FRE ((uint8_t)0x58)
471
472 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
473 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
474 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
475 /**
476 * @}
477 */
478
479
480 /** @defgroup SPI_transmission_fifo_status_level
481 * @{
482 */
483
484 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
485 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
486 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
487 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
488
489 /**
490 * @}
491 */
492
493 /** @defgroup SPI_reception_fifo_status_level
494 * @{
495 */
496 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
497 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
498 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
499 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
500
501 /**
502 * @}
503 */
504
505
506 /** @defgroup SPI_I2S_flags_definition
507 * @{
508 */
509
510 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
511 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
512 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
513 #define I2S_FLAG_UDR ((uint16_t)0x0008)
514 #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
515 #define SPI_FLAG_MODF ((uint16_t)0x0020)
516 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
517 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
518 #define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
519
520
521
522 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
523 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
524 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
525 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
526 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
527 ((FLAG) == I2S_FLAG_UDR))
528 /**
529 * @}
530 */
531
532 /** @defgroup SPI_CRC_polynomial
533 * @{
534 */
535
536 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
537 /**
538 * @}
539 */
540
541 /**
542 * @}
543 */
544
545 /* Exported macro ------------------------------------------------------------*/
546 /* Exported functions ------------------------------------------------------- */
547
548 /* Function used to set the SPI configuration to the default reset state*******/
549 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
550
551 /* Initialization and Configuration functions *********************************/
552 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
553 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
554 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
555 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
556 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
557 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
558 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
559 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
560 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
561 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
562 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
563 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
564 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
565 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
566
567 /* Data transfers functions ***************************************************/
568 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
569 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
570 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
571 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
572
573 /* Hardware CRC Calculation functions *****************************************/
574 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
575 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
576 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
577 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
578 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
579
580 /* DMA transfers management functions *****************************************/
581 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
582 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
583
584 /* Interrupts and flags management functions **********************************/
585 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
586 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
587 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
588 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
589 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
590 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
591
592 #ifdef __cplusplus
593 }
594 #endif
595
596 #endif /*__STM32F30x_SPI_H */
597
598 /**
599 * @}
600 */
601
602 /**
603 * @}
604 */
605
606 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/