lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_syscfg.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    04-April-2014
   7   * @brief   This file contains all the functions prototypes for the SYSCFG firmware
   8   *          library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  13   *
  14   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  15   * You may not use this file except in compliance with the License.
  16   * You may obtain a copy of the License at:
  17   *
  18   *        http://www.st.com/software_license_agreement_liberty_v2
  19   *
  20   * Unless required by applicable law or agreed to in writing, software
  21   * distributed under the License is distributed on an "AS IS" BASIS,
  22   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23   * See the License for the specific language governing permissions and
  24   * limitations under the License.
  25   *
  26   ******************************************************************************
  27   */
  28
  29 /*!< Define to prevent recursive inclusion -----------------------------------*/
  30 #ifndef __STM32F30x_SYSCFG_H
  31 #define __STM32F30x_SYSCFG_H
  32
  33 #ifdef __cplusplus
  34  extern "C" {
  35 #endif
  36
  37 /*!< Includes ----------------------------------------------------------------*/
  38 #include "stm32f30x.h"
  39
  40 /** @addtogroup STM32F30x_StdPeriph_Driver
  41   * @{
  42   */
  43
  44 /** @addtogroup SYSCFG
  45   * @{
  46   */
  47
  48 /* Exported types ------------------------------------------------------------*/
  49 /* Exported constants --------------------------------------------------------*/
  50
  51 /** @defgroup SYSCFG_Exported_Constants
  52   * @{
  53   */
  54
  55 /** @defgroup SYSCFG_EXTI_Port_Sources
  56   * @{
  57   */
  58 #define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
  59 #define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
  60 #define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
  61 #define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
  62 #define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
  63 #define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
  64
  65 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
  66                                          ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
  67                                          ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
  68                                          ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
  69                                          ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
  70                                          ((PORTSOURCE) == EXTI_PortSourceGPIOF))
  71 /**
  72   * @}
  73   */
  74
  75 /** @defgroup SYSCFG_EXTI_Pin_sources
  76   * @{
  77   */
  78 #define EXTI_PinSource0            ((uint8_t)0x00)
  79 #define EXTI_PinSource1            ((uint8_t)0x01)
  80 #define EXTI_PinSource2            ((uint8_t)0x02)
  81 #define EXTI_PinSource3            ((uint8_t)0x03)
  82 #define EXTI_PinSource4            ((uint8_t)0x04)
  83 #define EXTI_PinSource5            ((uint8_t)0x05)
  84 #define EXTI_PinSource6            ((uint8_t)0x06)
  85 #define EXTI_PinSource7            ((uint8_t)0x07)
  86 #define EXTI_PinSource8            ((uint8_t)0x08)
  87 #define EXTI_PinSource9            ((uint8_t)0x09)
  88 #define EXTI_PinSource10           ((uint8_t)0x0A)
  89 #define EXTI_PinSource11           ((uint8_t)0x0B)
  90 #define EXTI_PinSource12           ((uint8_t)0x0C)
  91 #define EXTI_PinSource13           ((uint8_t)0x0D)
  92 #define EXTI_PinSource14           ((uint8_t)0x0E)
  93 #define EXTI_PinSource15           ((uint8_t)0x0F)
  94
  95 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
  96                                        ((PINSOURCE) == EXTI_PinSource1) || \
  97                                        ((PINSOURCE) == EXTI_PinSource2) || \
  98                                        ((PINSOURCE) == EXTI_PinSource3) || \
  99                                        ((PINSOURCE) == EXTI_PinSource4) || \
 100                                        ((PINSOURCE) == EXTI_PinSource5) || \
 101                                        ((PINSOURCE) == EXTI_PinSource6) || \
 102                                        ((PINSOURCE) == EXTI_PinSource7) || \
 103                                        ((PINSOURCE) == EXTI_PinSource8) || \
 104                                        ((PINSOURCE) == EXTI_PinSource9) || \
 105                                        ((PINSOURCE) == EXTI_PinSource10) || \
 106                                        ((PINSOURCE) == EXTI_PinSource11) || \
 107                                        ((PINSOURCE) == EXTI_PinSource12) || \
 108                                        ((PINSOURCE) == EXTI_PinSource13) || \
 109                                        ((PINSOURCE) == EXTI_PinSource14) || \
 110                                        ((PINSOURCE) == EXTI_PinSource15))
 111 /**
 112   * @}
 113   */
 114
 115 /** @defgroup SYSCFG_Memory_Remap_Config
 116   * @{
 117   */
 118 #define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
 119 #define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
 120 #define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
 121
 122
 123 #define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)        || \
 124                                        ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
 125                                        ((REMAP) == SYSCFG_MemoryRemap_SRAM))
 126
 127 /**
 128   * @}
 129   */
 130
 131 /** @defgroup SYSCFG_DMA_Remap_Config
 132   * @{
 133   */
 134 #define SYSCFG_DMARemap_TIM17              SYSCFG_CFGR1_TIM17_DMA_RMP        /*!< Remap TIM17 DMA requests from channel1 to channel2 */
 135 #define SYSCFG_DMARemap_TIM16              SYSCFG_CFGR1_TIM16_DMA_RMP        /*!< Remap TIM16 DMA requests from channel3 to channel4 */
 136 #define SYSCFG_DMARemap_ADC2ADC4           SYSCFG_CFGR1_ADC24_DMA_RMP        /*!< Remap ADC2 and ADC4 DMA requests */
 137
 138 #define SYSCFG_DMARemap_TIM6DAC1Ch1        SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP  /* Remap TIM6/DAC1 Ch1 DMA requests */
 139 #define SYSCFG_DMARemap_TIM7DAC1Ch2        SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP  /* Remap TIM7/DAC1 Ch2 DMA requests */
 140 #define SYSCFG_DMARemap_DAC2Ch1            SYSCFG_CFGR1_DAC2Ch1_DMA_RMP      /* Remap DAC2 Ch1 DMA requests */
 141
 142 #define SYSCFG_DMARemapCh2_SPI1_RX         ((uint32_t)0x80000003)            /* Remap SPI1 RX DMA CH2 requests */
 143 #define SYSCFG_DMARemapCh4_SPI1_RX         ((uint32_t)0x80000001)            /* Remap SPI1 RX DMA CH4 requests */
 144 #define SYSCFG_DMARemapCh6_SPI1_RX         ((uint32_t)0x80000002)            /* Remap SPI1 RX DMA CH6 requests */
 145
 146 #define SYSCFG_DMARemapCh3_SPI1_TX         ((uint32_t)0x8000000C)            /* Remap SPI1 TX DMA CH2 requests */
 147 #define SYSCFG_DMARemapCh5_SPI1_TX         ((uint32_t)0x80000004)            /* Remap SPI1 TX DMA CH5 requests */
 148 #define SYSCFG_DMARemapCh7_SPI1_TX         ((uint32_t)0x80000008)            /* Remap SPI1 TX DMA CH7 requests */
 149
 150 #define SYSCFG_DMARemapCh7_I2C1_RX         ((uint32_t)0x80000030)            /* Remap I2C1 RX DMA CH7 requests */
 151 #define SYSCFG_DMARemapCh3_I2C1_RX         ((uint32_t)0x80000010)            /* Remap I2C1 RX DMA CH3 requests */
 152 #define SYSCFG_DMARemapCh5_I2C1_RX         ((uint32_t)0x80000020)            /* Remap I2C1 RX DMA CH5 requests */
 153
 154 #define SYSCFG_DMARemapCh6_I2C1_TX         ((uint32_t)0x800000C0)            /* Remap I2C1 TX DMA CH6 requests */
 155 #define SYSCFG_DMARemapCh2_I2C1_TX         ((uint32_t)0x80000040)            /* Remap I2C1 TX DMA CH2 requests */
 156 #define SYSCFG_DMARemapCh4_I2C1_TX         ((uint32_t)0x80000080)            /* Remap I2C1 TX DMA CH4 requests */
 157
 158 #define SYSCFG_DMARemapCh4_ADC2            ((uint32_t)0x80000300)            /* Remap ADC2 DMA1 Ch4 requests */
 159 #define SYSCFG_DMARemapCh2_ADC2            ((uint32_t)0x80000200)            /* Remap ADC2 DMA1 Ch2 requests */
 160
 161 /* SYSCFG_DMA_Remap_Legacy */
 162 #define SYSCFG_DMARemap_TIM6DAC1           SYSCFG_DMARemap_TIM6DAC1Ch1       /*!< Remap TIM6/DAC1 DMA requests */
 163 #define SYSCFG_DMARemap_TIM7DAC2           SYSCFG_DMARemap_TIM7DAC1Ch2       /*!< Remap TIM7/DAC2 DMA requests */
 164
 165 #define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17)    || \
 166                                     ((REMAP) == SYSCFG_DMARemap_TIM16)    || \
 167                                     ((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
 168                                     ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
 169                                     ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
 170                                     ((REMAP) == SYSCFG_DMARemap_DAC2Ch1)    || \
 171                                     ((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
 172                                     ((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
 173                                     ((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
 174                                     ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
 175                                     ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
 176                                     ((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
 177                                     ((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
 178                                     ((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
 179                                     ((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
 180                                     ((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
 181                                     ((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
 182                                     ((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
 183                                     ((REMAP) == SYSCFG_DMARemapCh4_ADC2)    || \
 184                                     ((REMAP) == SYSCFG_DMARemapCh2_ADC2))
 185
 186 /**
 187   * @}
 188   */
 189
 190 /** @defgroup SYSCFG_Trigger_Remap_Config
 191   * @{
 192   */
 193 #define SYSCFG_TriggerRemap_DACTIM3              SYSCFG_CFGR1_DAC1_TRIG1_RMP     /*!< Remap DAC trigger to TIM3 */
 194 #define SYSCFG_TriggerRemap_TIM1TIM17            SYSCFG_CFGR1_TIM1_ITR3_RMP      /*!< Remap TIM1 ITR3 to TIM17 OC */
 195 #define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1      ((uint32_t)0x80010000)          /*!< Remap DAC trigger to HRTIM1 TRIG1 */
 196 #define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2      ((uint32_t)0x80020000)          /*!< Remap DAC trigger to HRTIM1 TRIG2 */
 197
 198 #define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3)         || \
 199                                         ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
 200                                         ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
 201                                         ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
 202
 203 /**
 204   * @}
 205   */
 206
 207 /** @defgroup SYSCFG_EncoderRemap_Config
 208   * @{
 209   */
 210 #define SYSCFG_EncoderRemap_No              ((uint32_t)0x00000000)      /*!< No redirection */
 211 #define SYSCFG_EncoderRemap_TIM2            SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
 212 #define SYSCFG_EncoderRemap_TIM3            SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
 213 #define SYSCFG_EncoderRemap_TIM4            SYSCFG_CFGR1_ENCODER_MODE   /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
 214
 215 #define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No)    || \
 216                                         ((REMAP) == SYSCFG_EncoderRemap_TIM2)  || \
 217                                         ((REMAP) == SYSCFG_EncoderRemap_TIM3)  || \
 218                                         ((REMAP) == SYSCFG_EncoderRemap_TIM4))
 219
 220 /**
 221   * @}
 222   */
 223
 224 /** @defgroup SYSCFG_I2C_FastModePlus_Config
 225   * @{
 226   */
 227 #define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6 */
 228 #define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7 */
 229 #define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8 */
 230 #define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9 */
 231 #define SYSCFG_I2CFastModePlus_I2C1      SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
 232 #define SYSCFG_I2CFastModePlus_I2C2      SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
 233
 234 #define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6)  || \
 235                                 ((PIN) == SYSCFG_I2CFastModePlus_PB7)  || \
 236                                 ((PIN) == SYSCFG_I2CFastModePlus_PB8)  || \
 237                                 ((PIN) == SYSCFG_I2CFastModePlus_PB9)  || \
 238                                 ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
 239                                 ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
 240
 241 /**
 242   * @}
 243   */
 244
 245 /** @defgroup SYSCFG_FPU_Interrupt_Config
 246   * @{
 247   */
 248 #define SYSCFG_IT_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Inexact Interrupt enable (interrupt disabled by default) */
 249 #define SYSCFG_IT_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Input denormal Interrupt enable */
 250 #define SYSCFG_IT_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Overflow Interrupt enable */
 251 #define SYSCFG_IT_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Underflow Interrupt enable */
 252 #define SYSCFG_IT_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Divide-by-zero Interrupt enable */
 253 #define SYSCFG_IT_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Invalid operation Interrupt enable */
 254
 255 #define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
 256
 257 /**
 258   * @}
 259   */
 260
 261 /** @defgroup SYSCFG_Lock_Config
 262   * @{
 263   */
 264 #define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK          /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
 265 #define SYSCFG_Break_SRAMParity              SYSCFG_CFGR2_SRAM_PARITY_LOCK  /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
 266 #define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
 267
 268 #define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
 269                                        ((CONFIG) == SYSCFG_Break_SRAMParity) || \
 270                                        ((CONFIG) == SYSCFG_Break_Lockup))
 271
 272 /**
 273   * @}
 274   */
 275
 276 /** @defgroup SYSCFG_SRAMWRP_Config
 277   * @{
 278   */
 279 #define SYSCFG_SRAMWRP_Page0                 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
 280 #define SYSCFG_SRAMWRP_Page1                 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
 281 #define SYSCFG_SRAMWRP_Page2                 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
 282 #define SYSCFG_SRAMWRP_Page3                 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
 283 #define SYSCFG_SRAMWRP_Page4                 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
 284 #define SYSCFG_SRAMWRP_Page5                 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
 285 #define SYSCFG_SRAMWRP_Page6                 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
 286 #define SYSCFG_SRAMWRP_Page7                 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
 287
 288 #define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
 289
 290 /**
 291   * @}
 292   */
 293
 294 /** @defgroup SYSCFG_flags_definition
 295   * @{
 296   */
 297
 298 #define SYSCFG_FLAG_PE               SYSCFG_CFGR2_SRAM_PE
 299
 300 #define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
 301
 302 /**
 303   * @}
 304   */
 305
 306 /**
 307   * @}
 308   */
 309
 310 /* Exported macro ------------------------------------------------------------*/
 311 /* Exported functions ------------------------------------------------------- */
 312
 313 /*  Function used to set the SYSCFG configuration to the default reset state **/
 314 void SYSCFG_DeInit(void);
 315
 316 /* SYSCFG configuration functions *********************************************/
 317 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
 318 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
 319 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
 320 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
 321 void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
 322 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
 323 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
 324 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
 325 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
 326 void SYSCFG_BypassParityCheckDisable(void);
 327 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
 328 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
 329 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
 330
 331 #ifdef __cplusplus
 332 }
 333 #endif
 334
 335 #endif /*__STM32F30x_SYSCFG_H */
 336
 337 /**
 338   * @}
 339   */
 340
 341 /**
 342   * @}
 343   */
 344
 345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/