?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F30x_StdPeriph_Driver / src / stm32f30x_hrtim.c
blob06c2d33080aff4c26e77c16a5d0a16e6e2170b57
1 /**
2 ******************************************************************************
3 * @file stm32f30x_hrtim.c
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 04-April-2014
7 * @brief HRTIMx module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the HRTIMx peripheral:
11 * + Initialization/de-initialization methods
12 * + I/O operation methods
13 * + Peripheral Control methods
14 *
15 @verbatim
16 ================================================================================
17 ##### <HRTIM specific features> #####
18 ================================================================================
19
20 [..] < HRTIM introduction:
21 (#) The high-resolution timer can generate up to 10 digital signals with
22 highly accurate timings.
23 It is primarily intended to drive power conversion systems such as
24 switch mode power supplies or lighting systems,
25 but can be of general purpose usage, whenever a very fine timing
26 resolution is expected.
27
28 (#) Its modular architecture allows to generate either independent or
29 coupled waveforms.
30 The wave-shape is defined by self-contained timings
31 (using counters and compare units) and a broad range of external events,
32 such as analog or digital feedbacks and synchronisation signals.
33 This allows to produce a large variety of control signal (PWM, phase-shifted,
34 constant Ton,...) and address most of conversion topologies.
35
36 (#) For control and monitoring purposes, the timer has also timing measure
37 capabilities and links to built-in ADC and DAC converters.
38 Last, it features light-load management mode and is able to handle
39 various fault schemes for safe shut-down purposes.
40
41
42 ##### How to use this driver #####
43 ================================================================================
44 [..] This driver provides functions to configure and program the HRTIM
45 of all stm32f33x devices.
46 These functions are split in 9 groups:
47
48 (#) HRTIM Simple TimeBase management: this group includes all needed functions
49 to configure the HRTIM Timebase unit:
50 (++) Initializes the HRTIMx timer in simple time base mode
51 (++) Start/Stop the time base generation
52 (++) Deinitialize the HRTIM peripheral
53
54
55 (#) HRTIM simple Output Compare management: this group includes all needed
56 functions to configure the Compare unit used in Output compare mode:
57 (++) Initializes the HRTIMx timer time base unit
58 (++) Configure the compare unit in in simple Output Compare mode
59 (++) Start/Stop the Output compare generation
60
61 (#) HRTIM simple PWM management: this group includes all needed
62 functions to configure the Compare unit used in PWM mode:
63 (++) Initializes the HRTIMx timer time base unit
64 (++) Configure the compare unit in in simple PWM mode
65 (++) Start/Stop the PWM generation
66
67 (#) HRTIM simple Capture management: this group includes all needed
68 functions to configure the Capture unit used in Capture mode:
69 (++) Initializes the HRTIMx timer time base unit
70 (++) Configure the compare unit in in simple Capture mode
71 (++) Start/Stop the Capture mode
72
73 (#) HRTIM simple One Pulse management: this group includes all needed
74 functions to configure the Capture unit and Compare unit used in One Pulse mode:
75 (++) Initializes the HRTIMx timer time base unit
76 (++) Configure the compare unit and the capture unit in in simple One Pulse mode
77 (++) Start/Stop the One Pulse mode generation
78
79 (#) HRTIM Waveform management: this group includes all needed
80 functions to configure the HRTIM possible waveform mode:
81 (++) Initializes the HRTIMx timer Master time base unit
82 (++) Initializes the HRTIMx timer Slaves time base unit
83 (++) Configures the HRTIMx timer Compare unit
84 (++) Configures the HRTIMx Slave timer Capture unit
85 (++) Configures the HRTIMx timer Output unit
86 (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features
87 (++) Configures the HRTIMx timer Fault / External event features
88 (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,...
89 (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers
90 (++) HRTIMx timer Outputs Start/Stop
91 (++) Start/Stop the HRTIMx Timer counters
92
93 (#) HRTIM interrupts, DMA and flags management
94 (++) Enable/Disable interrupt sources
95 (++) Get flags status
96 (++) Clear flags/ Pending bits
97 (++) Enable/Disable DMA requests
98 (++) Configure DMA burst mode
99
100 (#) TIM specific interface management, this group includes all
101 needed functions to use the specific TIM interface:
102 (++) HRTIMx timer DLL calibration
103
104 @endverbatim
105 ******************************************************************************
106 * @attention
107 *
108 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
109 *
110 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
111 * You may not use this file except in compliance with the License.
112 * You may obtain a copy of the License at:
113 *
114 * http://www.st.com/software_license_agreement_liberty_v2
115 *
116 * Unless required by applicable law or agreed to in writing, software
117 * distributed under the License is distributed on an "AS IS" BASIS,
118 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
119 * See the License for the specific language governing permissions and
120 * limitations under the License.
121 *
122 ******************************************************************************
123 */
124 /* Includes ------------------------------------------------------------------*/
125 #include "stm32f30x_hrtim.h"
126 #pragma GCC diagnostic push
127 #pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
128
129 /** @addtogroup STM32F30x_StdPeriph_Driver
130 * @{
131 */
132
133 /** @defgroup HRTIM
134 * @brief HRTIM driver module
135 * @{
136 */
137
138 /* Private typedef -----------------------------------------------------------*/
139 /* Private define ------------------------------------------------------------*/
140 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
141 HRTIM_FLTR_FLT2EN |\
142 HRTIM_FLTR_FLT3EN |\
143 HRTIM_FLTR_FLT4EN | \
144 HRTIM_FLTR_FLT5EN)
145
146 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
147 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
148 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
149 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
150 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
151 HRTIM_TIMUPDATETRIGGER_TIMER_E)
152
153 #define HRTIM_TIM_OFFSET (uint32_t)0x00000080
154 /* Private macro -------------------------------------------------------------*/
155 /* Private variables ---------------------------------------------------------*/
156 static uint32_t TimerIdxToTimerId[] =
157 {
158 HRTIM_TIMERID_TIMER_A,
159 HRTIM_TIMERID_TIMER_B,
160 HRTIM_TIMERID_TIMER_C,
161 HRTIM_TIMERID_TIMER_D,
162 HRTIM_TIMERID_TIMER_E,
163 HRTIM_TIMERID_MASTER,
164 };
165
166 /* Private function prototypes -----------------------------------------------*/
167 /* Private functions ---------------------------------------------------------*/
168 static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
169 static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
170 static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
171 static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
172 uint32_t TimerIdx,
173 HRTIM_TimerInitTypeDef * TimerInit);
174 static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
175 uint32_t TimerIdx,
176 uint32_t CompareUnit,
177 HRTIM_CompareCfgTypeDef * CompareCfg);
178 static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
179 uint32_t TimerIdx,
180 uint32_t CaptureUnit,
181 uint32_t Event);
182 static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
183 uint32_t TimerIdx,
184 uint32_t Output,
185 HRTIM_OutputCfgTypeDef * OutputCfg);
186 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
187 uint32_t Event,
188 HRTIM_EventCfgTypeDef * EventCfg);
189 static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
190 uint32_t TimerIdx,
191 uint32_t Event);
192 /** @defgroup HRTIM_Private_Functions
193 * @{
194 */
195
196 /** @defgroup HRTIM_Group1 Initialization/de-initialization methods
197 * @brief Initialization and Configuration functions
198 *
199 @verbatim
200 ===============================================================================
201 ##### Initialization/de-initialization methods #####
202 ===============================================================================
203 [..] This section provides functions allowing to:
204 (+)Initializes timer in basic time base mode
205 (+)Initializes timer in basic OC mode
206 (+)Initializes timer in basic PWM mode
207 (+)Initializes timer in basic Capture mode
208 (+)Initializes timer in One Pulse mode
209 (+)Initializes a timer operating in waveform mode
210 (+)De-initializes the HRTIMx timer
211
212 @endverbatim
213 * @{
214 */
215
216 /**
217 * @brief Initializes the HRTIMx timer in basic time base mode
218 * @param HRTIMx: pointer to HRTIMx peripheral
219 * @param TimerIdx: Timer index
220 * This parameter can be one of the following values:
221 * @arg 0x0 for master timer
222 * @arg 0x1 to 0x5 for timers A to E
223 * @note The time-base unit initialization parameters specify:
224 * The timer counter operating mode (continuous, one shot)
225 * The timer clock prescaler
226 * The timer period
227 * The timer repetition counter.
228 * @retval None
229 */
230 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
231 {
232 /* Check the parameters */
233 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
234 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
235
236 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
237 {
238 /* Configure master timer */
239 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
240 }
241 else
242 {
243 /* Configure timing unit */
244 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
245 }
246 }
247
248 /**
249 * @brief De-initializes a timer operating in all mode
250 * @param HRTIMx: pointer to HRTIMx peripheral
251 * @retval None
252 */
253 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
254 {
255 (void)HRTIMx;
256 /* Check the parameters */
257 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE);
258 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE);
259 }
260
261 /**
262 * @brief Initializes the HRTIMx timer in basic output compare mode
263 * @param HRTIMx: pointer to HRTIMx peripheral
264 * @param TimerIdx: Timer index
265 * This parameter can be one of the following values:
266 * @arg 0x1 to 0x5 for timers A to E
267 * @note Initializes the time-base unit of the timer and prepare it to
268 * operate in output compare mode
269 * @retval None
270 */
271 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
272 {
273 /* Check the parameters */
274 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
275 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
276
277 /* Configure timing unit */
278 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
279 }
280
281 /**
282 * @brief Initializes the HRTIMx timer in basic PWM mode
283 * @param HRTIMx: pointer to HRTIMx peripheral
284 * @param TimerIdx: Timer index
285 * This parameter can be one of the following values:
286 * @arg 0x1 to 0x5 for timers A to E
287 * @note Initializes the time-base unit of the timer and prepare it to
288 * operate in capture mode
289 * @retval None
290 */
291 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
292 {
293 /* Check the parameters */
294 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
295 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
296
297 /* Configure timing unit */
298 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
299 }
300
301 /**
302 * @brief Initializes a timer operating in basic capture mode
303 * @param HRTIMx: pointer to HRTIMx peripheral
304 * @param TimerIdx: Timer index
305 * This parameter can be one of the following values:
306 * @arg 0x1 to 0x5 for timers A to E
307 * @retval None
308 */
309 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
310 {
311 /* Check the parameters */
312 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
313 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
314
315 /* Configure timing unit */
316 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
317 }
318
319 /**
320 * @brief Initializes the HRTIMx timer in basic one pulse mode
321 * @param HRTIMx: pointer to HRTIMx peripheral
322 * @param TimerIdx: Timer index
323 * This parameter can be one of the following values:
324 * @arg 0x1 to 0x5 for timers A to E
325 * @note Initializes the time-base unit of the timer and prepare it to
326 * operate in one pulse mode. In this mode the counter operates
327 * in single shot mode (retriggerable or not)
328 * @retval None
329 */
330 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
331 {
332 /* Check the parameters */
333 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
334 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
335
336 /* Configure timing unit */
337 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
338 }
339
340 /**
341 * @brief Initializes a timer operating in waveform mode
342 * @param HRTIMx: pointer to HRTIMx peripheral
343 * @param TimerIdx: Timer index
344 * This parameter can be one of the following values:
345 * @arg 0x0 for master timer
346 * @arg 0x1 to 0x5 for timers A to E
347 * @param pTimerInit: pointer to the timer initialization data structure
348 * @retval None
349 */
350 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
351 uint32_t TimerIdx,
352 HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
353 HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
354 {
355 /* Check the parameters */
356 assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
357 assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
358 assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
359 assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
360 assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
361 assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
362 assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate));
363
364 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
365 {
366 /* Check parameters */
367 assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
368
369 /* Configure master timer */
370 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
371 HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
372 }
373 else
374 {
375 /* Check parameters */
376 assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
377
378 /* Configure timing unit */
379 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
380 HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
381 }
382 }
383
384 /**
385 * @}
386 */
387
388 /** @defgroup HRTIM_Group2 I/O operation methods
389 * @brief Data transfers functions
390 *
391 @verbatim
392 ===============================================================================
393 ##### IO operation methods #####
394 ===============================================================================
395 [..]
396 This subsection provides a set of functions allowing to manage the HRTIMx data
397 transfers.
398 (+) Starts the DLL calibration.
399 (+) Starts / stops the counter of a timer operating in basic time base mode
400 (+) Starts / stops the output compare signal generation on the designed timer output
401 (+) Starts / stops the PWM output signal generation on the designed timer output
402 (+) Enables / disables a basic capture on the designed capture unit
403
404 @endverbatim
405 * @{
406 */
407
408 /**
409 * @brief Starts the DLL calibration
410 * @param HRTIMx: pointer to HRTIMx peripheral
411 * @param CalibrationRate: DLL calibration period
412 * This parameter can be one of the following values:
413 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
414 * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms
415 * @arg HRTIM_CALIBRATIONRATE_910: 910 us
416 * @arg HRTIM_CALIBRATIONRATE_114: 114 us
417 * @arg HRTIM_CALIBRATIONRATE_14: 14 us
418 * @retval None
419 */
420 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
421 {
422 uint32_t HRTIM_dllcr;
423
424 /* Check the parameters */
425 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
426
427 /* Configure DLL Calibration */
428 HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
429
430 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
431 {
432 /* One shot DLL calibration */
433 HRTIM_dllcr &= ~(HRTIM_DLLCR_CALEN);
434 HRTIM_dllcr |= HRTIM_DLLCR_CAL;
435 }
436 else
437 {
438 /* Periodic DLL calibration */
439 HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
440 HRTIM_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
441 }
442
443 /* Update HRTIMx register */
444 HRTIMx->HRTIM_COMMON.DLLCR = HRTIM_dllcr;
445
446 }
447 /**
448 * @brief Starts the counter of a timer operating in basic time base mode
449 * @param HRTIMx: pointer to HRTIM peripheral
450 * @param TimerIdx: Timer index
451 * This parameter can be one of the following values:
452 * @arg 0x5 for master timer
453 * @arg 0x0 to 0x4 for timers A to E
454 * @retval None
455 */
456 void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
457 {
458 /* Check the parameters */
459 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
460
461 /* Enable the timer counter */
462 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
463 }
464
465 /**
466 * @brief Stops the counter of a timer operating in basic time base mode
467 * @param HRTIMx: pointer to HRTIM peripheral
468 * @param TimerIdx: Timer index
469 * This parameter can be one of the following values:
470 * @arg 0x5 for master timer
471 * @arg 0x0 to 0x4 for timers A to E
472 * @retval None
473 */
474 void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
475 {
476 /* Check the parameters */
477 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
478
479 /* Disable the timer counter */
480 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
481 }
482
483 /**
484 * @brief Starts the output compare signal generation on the designed timer output
485 * @param HRTIMx: pointer to HRTIM peripheral
486 * @param TimerIdx: Timer index
487 * This parameter can be one of the following values:
488 * @arg 0x0 to 0x4 for timers A to E
489 * @param OCChannel: Timer output
490 * This parameter can be one of the following values:
491 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
492 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
493 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
494 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
495 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
496 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
497 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
498 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
499 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
500 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
501 * @retval None
502 */
503 void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
504 uint32_t TimerIdx,
505 uint32_t OCChannel)
506 {
507 /* Check the parameters */
508 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
509
510 /* Enable the timer output */
511 (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
512
513 /* Enable the timer counter */
514 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
515
516 }
517
518 /**
519 * @brief Stops the output compare signal generation on the designed timer output
520 * @param HRTIMx: pointer to HRTIM peripheral
521 * @param TimerIdx: Timer index
522 * This parameter can be one of the following values:
523 * @arg 0x0 to 0x4 for timers A to E
524 * @param OCChannel: Timer output
525 * This parameter can be one of the following values:
526 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
527 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
528 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
529 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
530 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
531 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
532 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
533 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
534 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
535 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
536 * @retval None
537 */
538 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
539 uint32_t TimerIdx,
540 uint32_t OCChannel)
541 {
542 /* Check the parameters */
543 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
544
545 /* Disable the timer output */
546 HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
547
548 /* Disable the timer counter */
549 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
550 }
551
552 /**
553 * @brief Starts the PWM output signal generation on the designed timer output
554 * @param HRTIMx: pointer to HRTIM peripheral
555 * @param TimerIdx: Timer index
556 * This parameter can be one of the following values:
557 * @arg 0x0 to 0x4 for timers A to E
558 * @param PWMChannel: Timer output
559 * This parameter can be one of the following values:
560 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
561 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
562 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
563 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
564 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
565 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
566 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
567 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
568 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
569 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
570 * @retval None
571 */
572 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
573 uint32_t TimerIdx,
574 uint32_t PWMChannel)
575 {
576 /* Check the parameters */
577 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
578
579 /* Enable the timer output */
580 HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
581
582 /* Enable the timer counter */
583 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
584 }
585
586 /**
587 * @brief Stops the PWM output signal generation on the designed timer output
588 * @param HRTIMx: pointer to HRTIM peripheral
589 * @param TimerIdx: Timer index
590 * This parameter can be one of the following values:
591 * @arg 0x0 to 0x4 for timers A to E
592 * @param PWMChannel: Timer output
593 * This parameter can be one of the following values:
594 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
595 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
596 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
597 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
598 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
599 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
600 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
601 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
602 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
603 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
604 * @retval None
605 */
606 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
607 uint32_t TimerIdx,
608 uint32_t PWMChannel)
609 {
610 /* Check the parameters */
611 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
612
613 /* Disable the timer output */
614 HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
615
616 /* Disable the timer counter */
617 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
618 }
619
620 /**
621 * @brief Enables a basic capture on the designed capture unit
622 * @param HRTIMx: pointer to HRTIM peripheral
623 * @param TimerIdx: Timer index
624 * This parameter can be one of the following values:
625 * @arg 0x0 to 0x4 for timers A to E
626 * @param CaptureChannel: Timer output
627 * This parameter can be one of the following values:
628 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
629 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
630 * @retval None
631 * @note The external event triggering the capture is available for all timing
632 * units. It can be used directly and is active as soon as the timing
633 * unit counter is enabled.
634 */
635 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
636 uint32_t TimerIdx,
637 uint32_t CaptureChannel)
638 {
639 (void)CaptureChannel;
640 /* Enable the timer counter */
641 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
642
643 }
644
645 /**
646 * @brief Disables a basic capture on the designed capture unit
647 * @param HRTIMx: pointer to HRTIMx peripheral
648 * @param TimerIdx: Timer index
649 * This parameter can be one of the following values:
650 * @arg 0x0 to 0x4 for timers A to E
651 * @param CaptureChannel: Timer output
652 * This parameter can be one of the following values:
653 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
654 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
655 * @retval None
656 */
657 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
658 uint32_t TimerIdx,
659 uint32_t CaptureChannel)
660 {
661 /* Check the parameters */
662 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
663 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
664
665 /* Set the capture unit trigger */
666 switch (CaptureChannel)
667 {
668 case HRTIM_CAPTUREUNIT_1:
669 {
670 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
671 }
672 break;
673 case HRTIM_CAPTUREUNIT_2:
674 {
675 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
676 }
677 break;
678 default:
679 break;
680 }
681
682 /* Disable the timer counter */
683 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
684 (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
685 {
686 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
687 }
688
689 }
690
691 /**
692 * @brief Enables the basic one pulse signal generation on the designed output
693 * @param HRTIMx: pointer to HRTIMx peripheral
694 * @param TimerIdx: Timer index
695 * This parameter can be one of the following values:
696 * @arg 0x0 to 0x4 for timers A to E
697 * @param OnePulseChannel: Timer output
698 * This parameter can be one of the following values:
699 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
700 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
701 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
702 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
703 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
704 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
705 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
706 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
707 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
708 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
709 * @retval None
710 */
711 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
712 uint32_t TimerIdx,
713 uint32_t OnePulseChannel)
714 {
715 /* Check the parameters */
716 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
717
718 /* Enable the timer output */
719 HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
720
721 /* Enable the timer counter */
722 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
723 }
724
725 /**
726 * @brief Disables the basic one pulse signal generation on the designed output
727 * @param HRTIMx: pointer to HRTIMx peripheral
728 * @param TimerIdx: Timer index
729 * This parameter can be one of the following values:
730 * @arg 0x0 to 0x4 for timers A to E
731 * @param OnePulseChannel: Timer output
732 * This parameter can be one of the following values:
733 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
734 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
735 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
736 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
737 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
738 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
739 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
740 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
741 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
742 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
743 * @retval None
744 */
745 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
746 uint32_t TimerIdx,
747 uint32_t OnePulseChannel)
748 {
749 /* Check the parameters */
750 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
751
752 /* Disable the timer output */
753 HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
754
755 /* Disable the timer counter */
756 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
757 }
758
759 /**
760 * @brief Starts the counter of the designated timer(s) operating in waveform mode
761 * Timers can be combined (ORed) to allow for simultaneous counter start
762 * @param HRTIMx: pointer to HRTIMx peripheral
763 * @param TimersToStart: Timer counter(s) to start
764 * This parameter can be any combination of the following values:
765 * @arg HRTIM_TIMERID_MASTER
766 * @arg HRTIM_TIMERID_TIMER_A
767 * @arg HRTIM_TIMERID_TIMER_B
768 * @arg HRTIM_TIMERID_TIMER_C
769 * @arg HRTIM_TIMERID_TIMER_D
770 * @arg HRTIM_TIMERID_TIMER_E
771 * @retval None
772 */
773 void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
774 uint32_t TimersToStart)
775 {
776 /* Enable timer(s) counter */
777 HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
778 }
779
780 /**
781 * @brief Stops the counter of the designated timer(s) operating in waveform mode
782 * Timers can be combined (ORed) to allow for simultaneous counter stop
783 * @param HRTIMx: pointer to HRTIMx peripheral
784 * @param TimersToStop: Timer counter(s) to stop
785 * This parameter can be any combination of the following values:
786 * @arg HRTIM_TIMERID_MASTER
787 * @arg HRTIM_TIMERID_TIMER_A
788 * @arg HRTIM_TIMERID_TIMER_B
789 * @arg HRTIM_TIMERID_TIMER_C
790 * @arg HRTIM_TIMERID_TIMER_D
791 * @arg HRTIM_TIMERID_TIMER_E
792 * @retval None
793 */
794 void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
795 uint32_t TimersToStop)
796 {
797 /* Disable timer(s) counter */
798 HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
799 }
800
801 /**
802 * @brief Enables the generation of the waveform signal on the designated output(s)
803 * Outputs can be combined (ORed) to allow for simultaneous output enabling
804 * @param HRTIMx: pointer to HRTIMx peripheral
805 * @param OutputsToStart: Timer output(s) to enable
806 * This parameter can be any combination of the following values:
807 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
808 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
809 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
810 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
811 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
812 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
813 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
814 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
815 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
816 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
817 * @retval None
818 */
819 void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
820 uint32_t OutputsToStart)
821 {
822 /* Enable the HRTIM outputs */
823 HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
824 }
825
826 /**
827 * @brief Disables the generation of the waveform signal on the designated output(s)
828 * Outputs can be combined (ORed) to allow for simultaneous output disabling
829 * @param HRTIMx: pointer to HRTIMx peripheral
830 * @param OutputsToStop: Timer output(s) to disable
831 * This parameter can be any combination of the following values:
832 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
833 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
834 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
835 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
836 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
837 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
838 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
839 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
840 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
841 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
842 * @retval None
843 */
844 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
845 uint32_t OutputsToStop)
846 {
847 /* Disable the HRTIM outputs */
848 HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
849 }
850
851 /**
852 * @brief Enables or disables the Master and slaves interrupt request
853 * @param HRTIMx: pointer to HRTIMx peripheral
854 * @param TimerIdx: Timer index
855 * This parameter can be one of the following values:
856 * @arg 0x0 to 0x4 for timers A to E
857 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
858 * This parameter can be any combination of the following values:
859 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
860 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
861 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
862 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
863 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
864 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
865 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
866 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
867 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
868 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
869 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
870 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
871 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
872 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
873 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
874 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
875 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
876 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
877 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
878 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
879 * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source
880 * @param NewState: new state of the TIM interrupts.
881 * This parameter can be: ENABLE or DISABLE.
882 * @retval None
883 */
884 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
885 {
886 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
887
888 switch(TimerIdx)
889 {
890 case HRTIM_TIMERINDEX_MASTER:
891 {
892 if(NewState != DISABLE)
893 {
894 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
895 }
896 else
897 {
898 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
899 }
900 }
901 break;
902 case HRTIM_TIMERINDEX_TIMER_A:
903 case HRTIM_TIMERINDEX_TIMER_B:
904 case HRTIM_TIMERINDEX_TIMER_C:
905 case HRTIM_TIMERINDEX_TIMER_D:
906 case HRTIM_TIMERINDEX_TIMER_E:
907 {
908 if(NewState != DISABLE)
909 {
910 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
911 }
912 else
913 {
914 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
915 }
916 }
917 break;
918
919 default:
920 break;
921 }
922 }
923
924 /**
925 * @brief Enables or disables the common interrupt request
926 * @param HRTIMx: pointer to HRTIMx peripheral
927 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
928 * This parameter can be any combination of the following values:
929 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
930 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
931 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
932 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
933 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
934 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
935 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
936 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
937 * @param NewState: new state of the TIM interrupts.
938 * This parameter can be: ENABLE or DISABLE.
939 * @retval None
940 */
941 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
942 {
943 if(NewState != DISABLE)
944 {
945 HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
946 }
947 else
948 {
949 HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
950 }
951 }
952
953 /**
954 * @brief Clears the Master and slaves interrupt flags
955 * @param HRTIMx: pointer to HRTIMx peripheral
956 * @param TimerIdx: Timer index
957 * This parameter can be one of the following values:
958 * @arg 0x0 to 0x4 for timers A to E
959 * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared.
960 * This parameter can be any combination of the following values:
961 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
962 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
963 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
964 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
965 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
966 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
967 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
968 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
969 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
970 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
971 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
972 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
973 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
974 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
975 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
976 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
977 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
978 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
979 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
980 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
981 * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag
982 * @retval None
983 */
984 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
985 {
986 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
987
988 switch(TimerIdx)
989 {
990 case HRTIM_TIMERINDEX_MASTER:
991 {
992 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
993 }
994 break;
995 case HRTIM_TIMERINDEX_TIMER_A:
996 case HRTIM_TIMERINDEX_TIMER_B:
997 case HRTIM_TIMERINDEX_TIMER_C:
998 case HRTIM_TIMERINDEX_TIMER_D:
999 case HRTIM_TIMERINDEX_TIMER_E:
1000 {
1001 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
1002 }
1003 break;
1004
1005 default:
1006 break;
1007 }
1008 }
1009
1010 /**
1011 * @brief Clears the common interrupt flags
1012 * @param HRTIMx: pointer to HRTIMx peripheral
1013 * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared.
1014 * This parameter can be any combination of the following values:
1015 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
1016 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
1017 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
1018 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
1019 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
1020 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
1021 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
1022 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
1023 * @retval None
1024 */
1025 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
1026 {
1027 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
1028 }
1029
1030 /**
1031 * @brief Clears the Master and slaves interrupt request pending bits
1032 * @param HRTIMx: pointer to HRTIMx peripheral
1033 * @param TimerIdx: Timer index
1034 * This parameter can be one of the following values:
1035 * @arg 0x0 to 0x4 for timers A to E
1036 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
1037 * This parameter can be any combination of the following values:
1038 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
1039 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
1040 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
1041 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
1042 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
1043 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
1044 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
1045 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
1046 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
1047 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
1048 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
1049 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
1050 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
1051 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
1052 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
1053 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
1054 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
1055 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
1056 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
1057 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
1058 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source
1059 * @retval None
1060 */
1061 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
1062 {
1063 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1064
1065 switch(TimerIdx)
1066 {
1067 case HRTIM_TIMERINDEX_MASTER:
1068 {
1069 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
1070 }
1071 break;
1072 case HRTIM_TIMERINDEX_TIMER_A:
1073 case HRTIM_TIMERINDEX_TIMER_B:
1074 case HRTIM_TIMERINDEX_TIMER_C:
1075 case HRTIM_TIMERINDEX_TIMER_D:
1076 case HRTIM_TIMERINDEX_TIMER_E:
1077 {
1078 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
1079 }
1080 break;
1081
1082 default:
1083 break;
1084 }
1085 }
1086
1087 /**
1088 * @brief Clears the common interrupt pending bits
1089 * @param HRTIMx: pointer to HRTIMx peripheral
1090 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared.
1091 * This parameter can be any combination of the following values:
1092 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
1093 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
1094 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
1095 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
1096 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
1097 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
1098 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
1099 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
1100 * @retval None
1101 */
1102 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
1103 {
1104 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
1105 }
1106
1107
1108 /**
1109 * @brief Checks whether the specified HRTIM flag is set or not.
1110 * @param HRTIMx: pointer to HRTIMx peripheral
1111 * @param TimerIdx: Timer index
1112 * This parameter can be one of the following values:
1113 * @arg 0x0 to 0x4 for timers A to E
1114 * @param HRTIM_FLAG: specifies the HRTIM flags to check.
1115 * This parameter can be any combination of the following values:
1116 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
1117 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
1118 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
1119 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
1120 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
1121 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
1122 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
1123 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
1124 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
1125 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
1126 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
1127 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
1128 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
1129 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
1130 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
1131 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
1132 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
1133 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
1134 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
1135 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
1136 * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag
1137 * @retval The new state of HRTIM_FLAG (SET or RESET).
1138 */
1139 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
1140 {
1141 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1142
1143 FlagStatus bitstatus = RESET;
1144
1145 switch(TimerIdx)
1146 {
1147 case HRTIM_TIMERINDEX_MASTER:
1148 {
1149 if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
1150 {
1151 bitstatus = SET;
1152 }
1153 else
1154 {
1155 bitstatus = RESET;
1156 }
1157 }
1158 break;
1159
1160 case HRTIM_TIMERINDEX_TIMER_A:
1161 case HRTIM_TIMERINDEX_TIMER_B:
1162 case HRTIM_TIMERINDEX_TIMER_C:
1163 case HRTIM_TIMERINDEX_TIMER_D:
1164 case HRTIM_TIMERINDEX_TIMER_E:
1165 {
1166 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
1167 {
1168 bitstatus = SET;
1169 }
1170 else
1171 {
1172 bitstatus = RESET;
1173 }
1174 }
1175 break;
1176
1177 default:
1178 break;
1179 }
1180 return bitstatus;
1181 }
1182
1183 /**
1184 * @brief Checks whether the specified HRTIM common flag is set or not.
1185 * @param HRTIMx: pointer to HRTIMx peripheral
1186 * @param HRTIM_FLAG: specifies the HRTIM flags to check.
1187 * This parameter can be any combination of the following values:
1188 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
1189 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
1190 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
1191 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
1192 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
1193 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
1194 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
1195 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
1196 * @retval The new state of HRTIM_FLAG (SET or RESET).
1197 */
1198 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
1199 {
1200 FlagStatus bitstatus = RESET;
1201
1202 if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
1203 {
1204 bitstatus = SET;
1205 }
1206 else
1207 {
1208 bitstatus = RESET;
1209 }
1210 return bitstatus;
1211 }
1212
1213 /**
1214 * @brief Checks whether the specified HRTIM interrupt has occurred or not.
1215 * @param HRTIMx: pointer to HRTIMx peripheral
1216 * @param TimerIdx: Timer index
1217 * This parameter can be one of the following values:
1218 * @arg 0x0 to 0x4 for timers A to E
1219 * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared.
1220 * This parameter can be any combination of the following values:
1221 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt
1222 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt
1223 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt
1224 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt
1225 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt
1226 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt
1227 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt
1228 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt
1229 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt
1230 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt
1231 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt
1232 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt
1233 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt
1234 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt
1235 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt
1236 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt
1237 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt
1238 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt
1239 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt
1240 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt
1241 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt
1242 * @retval The new state of the HRTIM_IT(SET or RESET).
1243 */
1244 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
1245 {
1246 ITStatus bitstatus = RESET;
1247 uint16_t itstatus = 0x0, itenable = 0x0;
1248
1249 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1250
1251 switch(TimerIdx)
1252 {
1253 case HRTIM_TIMERINDEX_MASTER:
1254 {
1255 itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
1256
1257 itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
1258 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1259 {
1260 bitstatus = SET;
1261 }
1262 else
1263 {
1264 bitstatus = RESET;
1265 }
1266 }
1267 break;
1268
1269 case HRTIM_TIMERINDEX_TIMER_A:
1270 case HRTIM_TIMERINDEX_TIMER_B:
1271 case HRTIM_TIMERINDEX_TIMER_C:
1272 case HRTIM_TIMERINDEX_TIMER_D:
1273 case HRTIM_TIMERINDEX_TIMER_E:
1274 {
1275 itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
1276
1277 itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
1278 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1279 {
1280 bitstatus = SET;
1281 }
1282 else
1283 {
1284 bitstatus = RESET;
1285 }
1286 }
1287 break;
1288
1289 default:
1290 break;
1291 }
1292 return bitstatus;
1293 }
1294
1295 /**
1296 * @brief Checks whether the specified HRTIM common interrupt has occurred or not.
1297 * @param HRTIMx: pointer to HRTIMx peripheral
1298 * @param HRTIM_IT: specifies the HRTIM interrupt source to check.
1299 * This parameter can be any combination of the following values:
1300 * @arg HRTIM_IT_FLT1: Fault 1 interrupt
1301 * @arg HRTIM_IT_FLT2: Fault 2 interrupt
1302 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt
1303 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt
1304 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt
1305 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt
1306 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag
1307 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt
1308 * @retval The new state of HRTIM_FLAG (SET or RESET).
1309 */
1310 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
1311 {
1312 ITStatus bitstatus = RESET;
1313 uint16_t itstatus = 0x0, itenable = 0x0;
1314
1315 itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
1316 itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
1317
1318 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1319 {
1320 bitstatus = SET;
1321 }
1322 else
1323 {
1324 bitstatus = RESET;
1325 }
1326
1327 return bitstatus;
1328 }
1329
1330 /**
1331 * @brief Enables or disables the HRTIMx's DMA Requests.
1332 * @param HRTIMx: pointer to HRTIMx peripheral
1333 * @param TimerIdx: Timer index
1334 * This parameter can be one of the following values:
1335 * @arg 0x0 to 0x4 for timers A to E
1336 * @param HRTIM_DMA: specifies the DMA Request sources.
1337 * This parameter can be any combination of the following values:
1338 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source
1339 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source
1340 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source
1341 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source
1342 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source
1343 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source
1344 * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source
1345 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source
1346 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source
1347 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source
1348 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source
1349 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source
1350 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source
1351 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source
1352 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source
1353 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source
1354 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source
1355 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source
1356 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source
1357 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source
1358 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source
1359 * @param NewState: new state of the DMA Request sources.
1360 * This parameter can be: ENABLE or DISABLE.
1361 * @retval None
1362 */
1363 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
1364 {
1365 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1366
1367 switch(TimerIdx)
1368 {
1369 case HRTIM_TIMERINDEX_MASTER:
1370 {
1371 if(NewState != DISABLE)
1372 {
1373 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
1374 }
1375 else
1376 {
1377 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
1378 }
1379 }
1380 break;
1381 case HRTIM_TIMERINDEX_TIMER_A:
1382 case HRTIM_TIMERINDEX_TIMER_B:
1383 case HRTIM_TIMERINDEX_TIMER_C:
1384 case HRTIM_TIMERINDEX_TIMER_D:
1385 case HRTIM_TIMERINDEX_TIMER_E:
1386 {
1387 if(NewState != DISABLE)
1388 {
1389 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
1390 }
1391 else
1392 {
1393 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
1394 }
1395 }
1396 break;
1397
1398 default:
1399 break;
1400 }
1401 }
1402
1403 /**
1404 * @}
1405 */
1406
1407 /** @defgroup HRTIM_Group3 Peripheral Control methods
1408 * @brief management functions
1409 *
1410 @verbatim
1411 ===============================================================================
1412 ##### Peripheral Control methods #####
1413 ===============================================================================
1414 [..]
1415 This subsection provides a set of functions allowing to control the HRTIMx data
1416 transfers.
1417
1418 @endverbatim
1419 * @{
1420 */
1421
1422 /**
1423 * @brief Configures an output in basic output compare mode
1424 * @param HRTIMx: pointer to HRTIMx peripheral
1425 * @param TimerIdx: Timer index
1426 * This parameter can be one of the following values:
1427 * @arg 0x0 to 0x4 for timers A to E
1428 * @param OCChannel: Timer output
1429 * This parameter can be one of the following values:
1430 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1431 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1432 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1433 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1434 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1435 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1436 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1437 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1438 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1439 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1440 * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure
1441 * @note When the timer operates in basic output compare mode:
1442 * Output 1 is implicitely controled by the compare unit 1
1443 * Output 2 is implicitely controled by the compare unit 2
1444 * Output Set/Reset crossbar is set according to the selected output compare mode:
1445 * Toggle: SETxyR = RSTxyR = CMPy
1446 * Active: SETxyR = CMPy, RSTxyR = 0
1447 * Inactive: SETxy =0, RSTxy = CMPy
1448 * @retval None
1449 */
1450 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIMx,
1451 uint32_t TimerIdx,
1452 uint32_t OCChannel,
1453 HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
1454 {
1455 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1456 HRTIM_CompareCfgTypeDef CompareCfg;
1457 HRTIM_OutputCfgTypeDef OutputCfg;
1458
1459 /* Check parameters */
1460 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1461 assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
1462 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
1463 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
1464
1465 /* Configure timer compare unit */
1466 switch (OCChannel)
1467 {
1468 case HRTIM_OUTPUT_TA1:
1469 case HRTIM_OUTPUT_TB1:
1470 case HRTIM_OUTPUT_TC1:
1471 case HRTIM_OUTPUT_TD1:
1472 case HRTIM_OUTPUT_TE1:
1473 {
1474 CompareUnit = HRTIM_COMPAREUNIT_1;
1475 }
1476 break;
1477 case HRTIM_OUTPUT_TA2:
1478 case HRTIM_OUTPUT_TB2:
1479 case HRTIM_OUTPUT_TC2:
1480 case HRTIM_OUTPUT_TD2:
1481 case HRTIM_OUTPUT_TE2:
1482 {
1483 CompareUnit = HRTIM_COMPAREUNIT_2;
1484 }
1485 break;
1486 default:
1487 break;
1488 }
1489
1490 CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
1491 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1492 CompareCfg.AutoDelayedTimeout = 0;
1493
1494 HRTIM_CompareUnitConfig(HRTIMx,
1495 TimerIdx,
1496 CompareUnit,
1497 &CompareCfg);
1498
1499 /* Configure timer output */
1500 OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
1501 OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
1502 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
1503 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1504 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1505 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1506
1507 switch (pBasicOCChannelCfg->Mode)
1508 {
1509 case HRTIM_BASICOCMODE_TOGGLE:
1510 {
1511 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1512 {
1513 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1514 }
1515 else
1516 {
1517 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1518 }
1519 OutputCfg.ResetSource = OutputCfg.SetSource;
1520 }
1521 break;
1522 case HRTIM_BASICOCMODE_ACTIVE:
1523 {
1524 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1525 {
1526 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1527 }
1528 else
1529 {
1530 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1531 }
1532 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1533 }
1534 break;
1535 case HRTIM_BASICOCMODE_INACTIVE:
1536 {
1537 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1538 {
1539 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1540 }
1541 else
1542 {
1543 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1544 }
1545 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1546 }
1547 break;
1548 default:
1549 break;
1550 }
1551
1552 HRTIM_OutputConfig(HRTIMx, TimerIdx, OCChannel, &OutputCfg);
1553 }
1554
1555 /**
1556 * @brief Configures an output in basic PWM mode
1557 * @param HRTIMx: pointer to HRTIMx peripheral
1558 * @param TimerIdx: Timer index
1559 * This parameter can be one of the following values:
1560 * @arg 0x0 to 0x4 for timers A to E
1561 * @param PWMChannel: Timer output
1562 * This parameter can be one of the following values:
1563 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1564 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1565 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1566 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1567 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1568 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1569 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1570 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1571 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1572 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1573 * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure
1574 * @note When the timer operates in basic PWM output mode:
1575 * Output 1 is implicitly controled by the compare unit 1
1576 * Output 2 is implicitly controled by the compare unit 2
1577 * Output Set/Reset crossbar is set as follows:
1578 * Output 1: SETx1R = CMP1, RSTx1R = PER
1579 * Output 2: SETx2R = CMP2, RST2R = PER
1580 * @retval None
1581 */
1582 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIMx,
1583 uint32_t TimerIdx,
1584 uint32_t PWMChannel,
1585 HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
1586 {
1587 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1588 HRTIM_CompareCfgTypeDef CompareCfg;
1589 HRTIM_OutputCfgTypeDef OutputCfg;
1590
1591 /* Check parameters */
1592 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1593 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
1594 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
1595
1596 /* Configure timer compare unit */
1597 switch (PWMChannel)
1598 {
1599 case HRTIM_OUTPUT_TA1:
1600 case HRTIM_OUTPUT_TB1:
1601 case HRTIM_OUTPUT_TC1:
1602 case HRTIM_OUTPUT_TD1:
1603 case HRTIM_OUTPUT_TE1:
1604 {
1605 CompareUnit = HRTIM_COMPAREUNIT_1;
1606 }
1607 break;
1608 case HRTIM_OUTPUT_TA2:
1609 case HRTIM_OUTPUT_TB2:
1610 case HRTIM_OUTPUT_TC2:
1611 case HRTIM_OUTPUT_TD2:
1612 case HRTIM_OUTPUT_TE2:
1613 {
1614 CompareUnit = HRTIM_COMPAREUNIT_2;
1615 }
1616 break;
1617 default:
1618 break;
1619 }
1620
1621 CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
1622 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1623 CompareCfg.AutoDelayedTimeout = 0;
1624
1625 HRTIM_CompareUnitConfig(HRTIMx,
1626 TimerIdx,
1627 CompareUnit,
1628 &CompareCfg);
1629
1630 /* Configure timer output */
1631 OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
1632 OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
1633 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
1634 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1635 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1636 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1637
1638 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1639 {
1640 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1641 }
1642 else
1643 {
1644 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1645 }
1646 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1647
1648 HRTIM_OutputConfig(HRTIMx, TimerIdx, PWMChannel, &OutputCfg);
1649 }
1650
1651 /**
1652 * @brief Configures a basic capture
1653 * @param HRTIMx: pointer to HRTIMx peripheral
1654 * @param TimerIdx: Timer index
1655 * This parameter can be one of the following values:
1656 * @arg 0x0 to 0x4 for timers A to E
1657 * @param CaptureChannel: Capture unit
1658 * This parameter can be one of the following values:
1659 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
1660 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
1661 * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure
1662 * @note When the timer operates in basic capture mode the capture is triggered
1663 * by the designated external event and GPIO input is implicitly used as event source.
1664 * The cature can be triggered by a rising edge, a falling edge or both
1665 * edges on event channel.
1666 * @retval None
1667 */
1668 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
1669 uint32_t TimerIdx,
1670 uint32_t CaptureChannel,
1671 HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
1672 {
1673 HRTIM_EventCfgTypeDef EventCfg;
1674
1675 /* Check parameters */
1676 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
1677 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
1678 assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
1679 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
1680 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
1681 assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
1682
1683 /* Configure external event channel */
1684 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
1685 EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
1686 EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
1687 EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
1688 EventCfg.Source = HRTIM_EVENTSRC_1;
1689
1690 HRTIM_ExternalEventConfig(HRTIMx,
1691 pBasicCaptureChannelCfg->Event,
1692 &EventCfg);
1693
1694 /* Memorize capture trigger (will be configured when the capture is started */
1695 HRTIM_CaptureUnitConfig(HRTIMx,
1696 TimerIdx,
1697 CaptureChannel,
1698 pBasicCaptureChannelCfg->Event);
1699 }
1700
1701 /**
1702 * @brief Configures an output basic one pulse mode
1703 * @param HRTIMx: pointer to HRTIMx peripheral
1704 * @param TimerIdx: Timer index
1705 * This parameter can be one of the following values:
1706 * @arg 0x0 to 0x4 for timers A to E
1707 * @param OnePulseChannel: Timer output
1708 * This parameter can be one of the following values:
1709 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1710 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1711 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1712 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1713 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1714 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1715 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1716 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1717 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1718 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1719 * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
1720 * @note When the timer operates in basic one pulse mode:
1721 * the timer counter is implicitly started by the reset event,
1722 * the reset of the timer counter is triggered by the designated external event
1723 * GPIO input is implicitly used as event source,
1724 * Output 1 is implicitly controled by the compare unit 1,
1725 * Output 2 is implicitly controled by the compare unit 2.
1726 * Output Set/Reset crossbar is set as follows:
1727 * Output 1: SETx1R = CMP1, RSTx1R = PER
1728 * Output 2: SETx2R = CMP2, RST2R = PER
1729 * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
1730 * @retval None
1731 */
1732 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIMx,
1733 uint32_t TimerIdx,
1734 uint32_t OnePulseChannel,
1735 HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
1736 {
1737 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1738 HRTIM_CompareCfgTypeDef CompareCfg;
1739 HRTIM_OutputCfgTypeDef OutputCfg;
1740 HRTIM_EventCfgTypeDef EventCfg;
1741
1742 /* Check parameters */
1743 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
1744 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
1745 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
1746 assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
1747 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
1748 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
1749 assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
1750
1751 /* Configure timer compare unit */
1752 switch (OnePulseChannel)
1753 {
1754 case HRTIM_OUTPUT_TA1:
1755 case HRTIM_OUTPUT_TB1:
1756 case HRTIM_OUTPUT_TC1:
1757 case HRTIM_OUTPUT_TD1:
1758 case HRTIM_OUTPUT_TE1:
1759 {
1760 CompareUnit = HRTIM_COMPAREUNIT_1;
1761 }
1762 break;
1763 case HRTIM_OUTPUT_TA2:
1764 case HRTIM_OUTPUT_TB2:
1765 case HRTIM_OUTPUT_TC2:
1766 case HRTIM_OUTPUT_TD2:
1767 case HRTIM_OUTPUT_TE2:
1768 {
1769 CompareUnit = HRTIM_COMPAREUNIT_2;
1770 }
1771 break;
1772 default:
1773 break;
1774 }
1775
1776 CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
1777 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1778 CompareCfg.AutoDelayedTimeout = 0;
1779
1780 HRTIM_CompareUnitConfig(HRTIMx,
1781 TimerIdx,
1782 CompareUnit,
1783 &CompareCfg);
1784
1785 /* Configure timer output */
1786 OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
1787 OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
1788 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
1789 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1790 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1791 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1792
1793 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1794 {
1795 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1796 }
1797 else
1798 {
1799 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1800 }
1801 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1802
1803 HRTIM_OutputConfig(HRTIMx,
1804 TimerIdx,
1805 OnePulseChannel,
1806 &OutputCfg);
1807
1808 /* Configure external event channel */
1809 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
1810 EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
1811 EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
1812 EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
1813 EventCfg.Source = HRTIM_EVENTSRC_1;
1814
1815 HRTIM_ExternalEventConfig(HRTIMx,
1816 pBasicOnePulseChannelCfg->Event,
1817 &EventCfg);
1818
1819 /* Configure the timer reset register */
1820 HRTIM_TIM_ResetConfig(HRTIMx,
1821 TimerIdx,
1822 pBasicOnePulseChannelCfg->Event);
1823 }
1824
1825 /**
1826 * @brief Configures the general behavior of a timer operating in waveform mode
1827 * @param HRTIMx: pointer to HRTIMx peripheral
1828 * @param TimerIdx: Timer index
1829 * This parameter can be one of the following values:
1830 * @arg 0x0 to 0x4 for timers A to E
1831 * @param pTimerCfg: pointer to the timer configuration structure
1832 * @note When the timer operates in waveform mode, all the features supported by
1833 * the HRTIMx are available without any limitation.
1834 * @retval None
1835 */
1836 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
1837 uint32_t TimerIdx,
1838 HRTIM_TimerCfgTypeDef * pTimerCfg)
1839 {
1840 uint32_t HRTIM_timcr;
1841 uint32_t HRTIM_timfltr;
1842 uint32_t HRTIM_timoutr;
1843 uint32_t HRTIM_timrstr;
1844
1845 /* Check parameters */
1846 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
1847 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
1848 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
1849 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
1850 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion));
1851 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode));
1852 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
1853 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
1854 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
1855
1856 /* Configure timing unit (Timer A to Timer E) */
1857 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1858 HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
1859 HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
1860 HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
1861
1862 /* Set the push-pull mode */
1863 HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
1864 HRTIM_timcr |= pTimerCfg->PushPull;
1865
1866 /* Enable/Disable registers update on timer counter reset */
1867 HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
1868 HRTIM_timcr |= pTimerCfg->ResetUpdate;
1869
1870 /* Set the timer update trigger */
1871 HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
1872 HRTIM_timcr |= pTimerCfg->UpdateTrigger;
1873
1874 /* Enable/Disable the fault channel at timer level */
1875 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
1876 HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
1877
1878 /* Lock/Unlock fault sources at timer level */
1879 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
1880 HRTIM_timfltr |= pTimerCfg->FaultLock;
1881
1882 /* Enable/Disable dead time insertion at timer level */
1883 HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
1884 HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
1885
1886 /* Enable/Disable delayed protection at timer level */
1887 HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
1888 HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
1889
1890 /* Set the timer counter reset trigger */
1891 HRTIM_timrstr = pTimerCfg->ResetTrigger;
1892
1893 /* Update the HRTIMx registers */
1894 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1895 HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
1896 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
1897 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
1898 }
1899
1900 /**
1901 * @brief Configures the compare unit of a timer operating in waveform mode
1902 * @param HRTIMx: pointer to HRTIMx peripheral
1903 * @param TimerIdx: Timer index
1904 * 0xFF for master timer
1905 * This parameter can be one of the following values:
1906 * @arg 0x0 to 0x4 for timers A to E
1907 * @param CompareUnit: Compare unit to configure
1908 * This parameter can be one of the following values:
1909 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
1910 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
1911 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
1912 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
1913 * @param pCompareCfg: pointer to the compare unit configuration structure
1914 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
1915 * application has to configure separately the capture unit. Capture unit
1916 * to configure in that case depends on the compare unit auto delayed mode
1917 * is applied to (see below):
1918 * Auto delayed on output compare 2: capture unit 1 must be configured
1919 * Auto delayed on output compare 4: capture unit 2 must be configured
1920 * @retval None
1921 */
1922 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
1923 uint32_t TimerIdx,
1924 uint32_t CompareUnit,
1925 HRTIM_CompareCfgTypeDef* pCompareCfg)
1926 {
1927 uint32_t HRTIM_timcr;
1928
1929 /* Check parameters */
1930 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
1931 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
1932
1933 /* Configure the compare unit */
1934 switch (CompareUnit)
1935 {
1936 case HRTIM_COMPAREUNIT_1:
1937 {
1938 /* Set the compare value */
1939 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
1940 }
1941 break;
1942 case HRTIM_COMPAREUNIT_2:
1943 {
1944 /* Set the compare value */
1945 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
1946
1947 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
1948 {
1949 /* Configure auto-delayed mode */
1950 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1951 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
1952 HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
1953 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1954
1955 /* Set the compare value for timeout compare unit (if any) */
1956 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
1957 {
1958 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
1959 }
1960 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
1961 {
1962 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
1963 }
1964 }
1965 }
1966 break;
1967 case HRTIM_COMPAREUNIT_3:
1968 {
1969 /* Set the compare value */
1970 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
1971 }
1972 break;
1973 case HRTIM_COMPAREUNIT_4:
1974 {
1975 /* Set the compare value */
1976 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
1977
1978 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
1979 {
1980 /* Configure auto-delayed mode */
1981 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1982 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
1983 HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
1984 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1985
1986 /* Set the compare value for timeout compare unit (if any) */
1987 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
1988 {
1989 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
1990 }
1991 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
1992 {
1993 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
1994 }
1995 }
1996 }
1997 break;
1998 default:
1999 break;
2000 }
2001 }
2002
2003 /**
2004 * @brief Sets the HRTIMx Master Comparex Register value
2005 * @param HRTIMx: pointer to HRTIMx peripheral
2006 * @param CompareUnit: Compare unit to configure
2007 * This parameter can be one of the following values:
2008 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
2009 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
2010 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
2011 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
2012 * @param Compare: specifies the Comparex register new value
2013 * @retval None
2014 */
2015 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
2016 uint32_t CompareUnit,
2017 uint32_t Compare)
2018 {
2019 /* Check parameters */
2020 assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
2021
2022 /* Configure the compare unit */
2023 switch (CompareUnit)
2024 {
2025 case HRTIM_COMPAREUNIT_1:
2026 {
2027 /* Set the compare value */
2028 HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
2029 }
2030 break;
2031 case HRTIM_COMPAREUNIT_2:
2032 {
2033 /* Set the compare value */
2034 HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
2035 }
2036 break;
2037 case HRTIM_COMPAREUNIT_3:
2038 {
2039 /* Set the compare value */
2040 HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
2041 }
2042 break;
2043 case HRTIM_COMPAREUNIT_4:
2044 {
2045 /* Set the compare value */
2046 HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
2047 }
2048 break;
2049 default:
2050 break;
2051 }
2052 }
2053
2054 /**
2055 * @brief Sets the HRTIMx Slave Comparex Register value
2056 * @param HRTIMx: pointer to HRTIMx peripheral
2057 * @param CompareUnit: Compare unit to configure
2058 * This parameter can be one of the following values:
2059 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
2060 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
2061 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
2062 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
2063 * @param Compare: specifies the Comparex register new value
2064 * @retval None
2065 */
2066 void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx,
2067 uint32_t TimerIdx,
2068 uint32_t CompareUnit,
2069 uint32_t Compare)
2070 {
2071 /* Check parameters */
2072 assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
2073
2074 /* Configure the compare unit */
2075 switch (CompareUnit)
2076 {
2077 case HRTIM_COMPAREUNIT_1:
2078 {
2079 /* Set the compare value */
2080 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = Compare;
2081 }
2082 break;
2083 case HRTIM_COMPAREUNIT_2:
2084 {
2085 /* Set the compare value */
2086 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = Compare;
2087 }
2088 break;
2089 case HRTIM_COMPAREUNIT_3:
2090 {
2091 /* Set the compare value */
2092 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = Compare;
2093 }
2094 break;
2095 case HRTIM_COMPAREUNIT_4:
2096 {
2097 /* Set the compare value */
2098 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = Compare;
2099 }
2100 break;
2101 default:
2102 break;
2103 }
2104 }
2105 /**
2106 * @brief Configures the capture unit of a timer operating in waveform mode
2107 * @param HRTIMx: pointer to HRTIMx peripheral
2108 * @param TimerIdx: Timer index
2109 * This parameter can be one of the following values:
2110 * @arg 0x0 to 0x4 for timers A to E
2111 * @param CaptureChannel: Capture unit to configure
2112 * This parameter can be one of the following values:
2113 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2114 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2115 * @param pCaptureCfg: pointer to the compare unit configuration structure
2116 * @retval None
2117 */
2118 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
2119 uint32_t TimerIdx,
2120 uint32_t CaptureUnit,
2121 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
2122 {
2123 /* Configure the capture unit */
2124 switch (CaptureUnit)
2125 {
2126 case HRTIM_CAPTUREUNIT_1:
2127 {
2128 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
2129 }
2130 break;
2131 case HRTIM_CAPTUREUNIT_2:
2132 {
2133 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
2134 }
2135 break;
2136 default:
2137 break;
2138 }
2139 }
2140
2141 /**
2142 * @brief Configures the output of a timer operating in waveform mode
2143 * @param HRTIMx: pointer to HRTIMx peripheral
2144 * @param TimerIdx: Timer index
2145 * This parameter can be one of the following values:
2146 * @arg 0x0 to 0x4 for timers A to E
2147 * @param Output: Timer output
2148 * This parameter can be one of the following values:
2149 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2150 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2151 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2152 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2153 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2154 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2155 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2156 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2157 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2158 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2159 * @param pOutputCfg: pointer to the timer output configuration structure
2160 * @retval None
2161 */
2162 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx,
2163 uint32_t TimerIdx,
2164 uint32_t Output,
2165 HRTIM_OutputCfgTypeDef * pOutputCfg)
2166 {
2167 /* Check parameters */
2168 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
2169 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
2170 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState));
2171 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
2172 assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState));
2173 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
2174 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
2175
2176 /* Configure the timer output */
2177 HRTIM_OutputConfig(HRTIMx, TimerIdx, Output, pOutputCfg);
2178 }
2179
2180 /**
2181 * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
2182 * @param HRTIMx: pointer to HRTIMx peripheral
2183 * @param TimerIdx: Timer index
2184 * This parameter can be one of the following values:
2185 * @arg 0x0 to 0x4 for timers A to E
2186 * @param Event: external event for which timer event filtering must be configured
2187 * This parameter can be one of the following values:
2188 * @arg HRTIM_EVENT_1: External event 1
2189 * @arg HRTIM_EVENT_2: External event 2
2190 * @arg HRTIM_EVENT_3: External event 3
2191 * @arg HRTIM_EVENT_4: External event 4
2192 * @arg HRTIM_EVENT_5: External event 5
2193 * @arg HRTIM_EVENT_6: External event 6
2194 * @arg HRTIM_EVENT_7: External event 7
2195 * @arg HRTIM_EVENT_8: External event 8
2196 * @arg HRTIM_EVENT_9: External event 9
2197 * @arg HRTIM_EVENT_10: External event 10
2198 * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
2199 * @retval None
2200 */
2201 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
2202 uint32_t TimerIdx,
2203 uint32_t Event,
2204 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
2205 {
2206 uint32_t HRTIM_eefr;
2207
2208 /* Check parameters */
2209 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2210 assert_param(IS_HRTIM_EVENT(Event));
2211 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
2212 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
2213
2214 /* Configure timer event filtering capabilities */
2215 switch (Event)
2216 {
2217 case HRTIM_TIMEVENTFILTER_NONE:
2218 {
2219 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
2220 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
2221 }
2222 break;
2223 case HRTIM_EVENT_1:
2224 {
2225 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2226 HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
2227 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
2228 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2229 }
2230 break;
2231 case HRTIM_EVENT_2:
2232 {
2233 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2234 HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
2235 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
2236 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2237 }
2238 break;
2239 case HRTIM_EVENT_3:
2240 {
2241 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2242 HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
2243 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
2244 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2245 }
2246 break;
2247 case HRTIM_EVENT_4:
2248 {
2249 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2250 HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
2251 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
2252 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2253 }
2254 break;
2255 case HRTIM_EVENT_5:
2256 {
2257 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2258 HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
2259 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
2260 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2261 }
2262 break;
2263 case HRTIM_EVENT_6:
2264 {
2265 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2266 HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
2267 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
2268 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2269 }
2270 break;
2271 case HRTIM_EVENT_7:
2272 {
2273 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2274 HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
2275 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
2276 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2277 }
2278 break;
2279 case HRTIM_EVENT_8:
2280 {
2281 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2282 HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
2283 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
2284 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2285 }
2286 break;
2287 case HRTIM_EVENT_9:
2288 {
2289 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2290 HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
2291 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
2292 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2293 }
2294 break;
2295 case HRTIM_EVENT_10:
2296 {
2297 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2298 HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
2299 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
2300 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2301 }
2302 break;
2303 default:
2304 break;
2305 }
2306 }
2307
2308 /**
2309 * @brief Configures the dead time insertion feature for a timer
2310 * @param HRTIMx: pointer to HRTIMx peripheral
2311 * @param TimerIdx: Timer index
2312 * This parameter can be one of the following values:
2313 * @arg 0x0 to 0x4 for timers A to E
2314 * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure
2315 * @retval None
2316 */
2317 void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
2318 uint32_t TimerIdx,
2319 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
2320 {
2321 uint32_t HRTIM_dtr;
2322
2323 /* Check parameters */
2324 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2325 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
2326 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
2327 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
2328 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
2329 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
2330 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
2331
2332 HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
2333
2334 /* Clear timer dead times configuration */
2335 HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
2336 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
2337 HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
2338
2339 /* Set timer dead times configuration */
2340 HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
2341 HRTIM_dtr |= pDeadTimeCfg->RisingValue;
2342 HRTIM_dtr |= pDeadTimeCfg->RisingSign;
2343 HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
2344 HRTIM_dtr |= pDeadTimeCfg->RisingLock;
2345 HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
2346 HRTIM_dtr |= pDeadTimeCfg->FallingSign;
2347 HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
2348 HRTIM_dtr |= pDeadTimeCfg->FallingLock;
2349
2350 /* Update the HRTIMx registers */
2351 HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
2352 }
2353
2354 /**
2355 * @brief Configures the chopper mode feature for a timer
2356 * @param HRTIMx: pointer to HRTIMx peripheral
2357 * @param TimerIdx: Timer index
2358 * This parameter can be one of the following values:
2359 * @arg 0x0 to 0x4 for timers A to E
2360 * @param pChopperModeCfg: pointer to the chopper mode configuration structure
2361 * @retval None
2362 */
2363 void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
2364 uint32_t TimerIdx,
2365 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
2366 {
2367 uint32_t HRTIM_chpr;
2368
2369 /* Check parameters */
2370 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2371
2372 HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
2373
2374 /* Clear timer chopper mode configuration */
2375 HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
2376
2377 /* Set timer chopper mode configuration */
2378 HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
2379 HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
2380 HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
2381
2382 /* Update the HRTIMx registers */
2383 HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
2384 }
2385
2386 /**
2387 * @brief Configures the burst DMA controller for a timer
2388 * @param HRTIMx: pointer to HRTIMx peripheral
2389 * @param TimerIdx: Timer index
2390 * This parameter can be one of the following values:
2391 * @arg 0x5 for master timer
2392 * @arg 0x0 to 0x4 for timers A to E
2393 * @param RegistersToUpdate: registers to be written by DMA
2394 * This parameter can be any combination of the following values:
2395 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
2396 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
2397 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
2398 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
2399 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
2400 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
2401 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
2402 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
2403 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
2404 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
2405 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
2406 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
2407 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
2408 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
2409 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
2410 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
2411 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
2412 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
2413 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
2414 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
2415 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
2416 * @retval None
2417 */
2418 void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
2419 uint32_t TimerIdx,
2420 uint32_t RegistersToUpdate)
2421 {
2422 /* Check parameters */
2423 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
2424
2425 /* Set the burst DMA timer update register */
2426 switch (TimerIdx)
2427 {
2428 case HRTIM_TIMERINDEX_TIMER_A:
2429 {
2430 HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
2431 }
2432 break;
2433 case HRTIM_TIMERINDEX_TIMER_B:
2434 {
2435 HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
2436 }
2437 break;
2438 case HRTIM_TIMERINDEX_TIMER_C:
2439 {
2440 HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
2441 }
2442 break;
2443 case HRTIM_TIMERINDEX_TIMER_D:
2444 {
2445 HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
2446 }
2447 break;
2448 case HRTIM_TIMERINDEX_TIMER_E:
2449 {
2450 HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
2451 }
2452 break;
2453 case HRTIM_TIMERINDEX_MASTER:
2454 {
2455 HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
2456 }
2457 break;
2458 default:
2459 break;
2460 }
2461 }
2462
2463 /**
2464 * @brief Configures the external input/output synchronization of the HRTIMx
2465 * @param HRTIMx: pointer to HRTIMx peripheral
2466 * @param pSynchroCfg: pointer to the input/output synchronization configuration structure
2467 * @retval None
2468 */
2469 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
2470 {
2471 uint32_t HRTIM_mcr;
2472
2473 /* Check parameters */
2474 assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource));
2475 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource));
2476 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity));
2477
2478 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
2479
2480 /* Set the synchronization input source */
2481 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
2482 HRTIM_mcr |= pSynchroCfg->SyncInputSource;
2483
2484 /* Set the event to be sent on the synchronization output */
2485 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
2486 HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
2487
2488 /* Set the polarity of the synchronization output */
2489 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
2490 HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
2491
2492 /* Update the HRTIMx registers */
2493 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
2494 }
2495
2496 /**
2497 * @brief Configures the burst mode feature of the HRTIMx
2498 * @param HRTIMx: pointer to HRTIMx peripheral
2499 * @param pBurstModeCfg: pointer to the burst mode configuration structure
2500 * @retval None
2501 */
2502 void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
2503 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
2504 {
2505 uint32_t HRTIM_bmcr;
2506
2507 /* Check parameters */
2508 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
2509 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
2510 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
2511 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
2512
2513 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
2514
2515 /* Set the burst mode operating mode */
2516 HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
2517 HRTIM_bmcr |= pBurstModeCfg->Mode;
2518
2519 /* Set the burst mode clock source */
2520 HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
2521 HRTIM_bmcr |= pBurstModeCfg->ClockSource;
2522
2523 /* Set the burst mode prescaler */
2524 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
2525 HRTIM_bmcr |= pBurstModeCfg->Prescaler;
2526
2527 /* Enable/disable burst mode registers preload */
2528 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
2529 HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
2530
2531 /* Set the burst mode trigger */
2532 HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
2533
2534 /* Set the burst mode compare value */
2535 HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
2536
2537 /* Set the burst mode period */
2538 HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
2539
2540 /* Update the HRTIMx registers */
2541 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
2542 }
2543
2544 /**
2545 * @brief Configures the conditioning of an external event
2546 * @param HRTIMx: pointer to HRTIMx peripheral
2547 * @param Event: external event to configure
2548 * This parameter can be one of the following values:
2549 * @arg HRTIM_EVENT_1: External event 1
2550 * @arg HRTIM_EVENT_2: External event 2
2551 * @arg HRTIM_EVENT_3: External event 3
2552 * @arg HRTIM_EVENT_4: External event 4
2553 * @arg HRTIM_EVENT_5: External event 5
2554 * @arg HRTIM_EVENT_6: External event 6
2555 * @arg HRTIM_EVENT_7: External event 7
2556 * @arg HRTIM_EVENT_8: External event 8
2557 * @arg HRTIM_EVENT_9: External event 9
2558 * @arg HRTIM_EVENT_10: External event 10
2559 * @param pEventCfg: pointer to the event conditioning configuration structure
2560 * @retval None
2561 */
2562 void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
2563 uint32_t Event,
2564 HRTIM_EventCfgTypeDef* pEventCfg)
2565 {
2566 /* Check parameters */
2567 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
2568 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity));
2569 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
2570 assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode));
2571 assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter));
2572
2573 /* Configure the event channel */
2574 HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
2575
2576 }
2577
2578 /**
2579 * @brief Configures the external event conditioning block prescaler
2580 * @param HRTIMx: pointer to HRTIMx peripheral
2581 * @param Prescaler: Prescaler value
2582 * This parameter can be one of the following values:
2583 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx
2584 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2
2585 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4
2586 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8
2587 * @retval None
2588 */
2589 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
2590 uint32_t Prescaler)
2591 {
2592 uint32_t HRTIM_eecr3;
2593
2594 /* Check parameters */
2595 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
2596
2597 /* Set the external event prescaler */
2598 HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
2599 HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
2600 HRTIM_eecr3 |= Prescaler;
2601
2602 /* Update the HRTIMx registers */
2603 HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
2604 }
2605
2606 /**
2607 * @brief Configures the conditioning of fault input
2608 * @param HRTIMx: pointer to HRTIMx peripheral
2609 * @param Fault: fault input to configure
2610 * This parameter can be one of the following values:
2611 * @arg HRTIM_FAULT_1: Fault input 1
2612 * @arg HRTIM_FAULT_2: Fault input 2
2613 * @arg HRTIM_FAULT_3: Fault input 3
2614 * @arg HRTIM_FAULT_4: Fault input 4
2615 * @arg HRTIM_FAULT_5: Fault input 5
2616 * @param pFaultCfg: pointer to the fault conditioning configuration structure
2617 * @retval None
2618 */
2619 void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
2620 HRTIM_FaultCfgTypeDef* pFaultCfg,
2621 uint32_t Fault)
2622 {
2623 uint32_t HRTIM_fltinr1;
2624 uint32_t HRTIM_fltinr2;
2625
2626 /* Check parameters */
2627 assert_param(IS_HRTIM_FAULT(Fault));
2628 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
2629 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
2630 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
2631 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
2632
2633 /* Configure fault channel */
2634 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
2635 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2636
2637 switch (Fault)
2638 {
2639 case HRTIM_FAULT_1:
2640 {
2641 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
2642 HRTIM_fltinr1 |= pFaultCfg->Polarity;
2643 HRTIM_fltinr1 |= pFaultCfg->Source;
2644 HRTIM_fltinr1 |= pFaultCfg->Filter;
2645 HRTIM_fltinr1 |= pFaultCfg->Lock;
2646 }
2647 break;
2648 case HRTIM_FAULT_2:
2649 {
2650 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
2651 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
2652 HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
2653 HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
2654 HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
2655 }
2656 break;
2657 case HRTIM_FAULT_3:
2658 {
2659 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
2660 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
2661 HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
2662 HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
2663 HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
2664 }
2665 break;
2666 case HRTIM_FAULT_4:
2667 {
2668 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
2669 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
2670 HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
2671 HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
2672 HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
2673 }
2674 break;
2675 case HRTIM_FAULT_5:
2676 {
2677 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
2678 HRTIM_fltinr2 |= pFaultCfg->Polarity;
2679 HRTIM_fltinr2 |= pFaultCfg->Source;
2680 HRTIM_fltinr2 |= pFaultCfg->Filter;
2681 HRTIM_fltinr2 |= pFaultCfg->Lock;
2682 }
2683 break;
2684 default:
2685 break;
2686 }
2687
2688 /* Update the HRTIMx registers */
2689 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
2690 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2691 }
2692
2693 /**
2694 * @brief Configures the fault conditioning block prescaler
2695 * @param HRTIMx: pointer to HRTIMx peripheral
2696 * @param Prescaler: Prescaler value
2697 * This parameter can be one of the following values:
2698 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx
2699 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2
2700 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4
2701 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8
2702 * @retval None
2703 */
2704 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
2705 uint32_t Prescaler)
2706 {
2707 uint32_t HRTIM_fltinr2;
2708
2709 /* Check parameters */
2710 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
2711
2712 /* Set the external event prescaler */
2713 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2714 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
2715 HRTIM_fltinr2 |= Prescaler;
2716
2717 /* Update the HRTIMx registers */
2718 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2719 }
2720
2721 /**
2722 * @brief Enables or disables the HRTIMx Fault mode.
2723 * @param HRTIMx: pointer to HRTIMx peripheral
2724 * @param Fault: fault input to configure
2725 * This parameter can be one of the following values:
2726 * @arg HRTIM_FAULT_1: Fault input 1
2727 * @arg HRTIM_FAULT_2: Fault input 2
2728 * @arg HRTIM_FAULT_3: Fault input 3
2729 * @arg HRTIM_FAULT_4: Fault input 4
2730 * @arg HRTIM_FAULT_5: Fault input 5
2731 * @param Enable: Fault mode controller enabling
2732 * This parameter can be one of the following values:
2733 * @arg HRTIM_FAULT_ENABLED: Fault mode enabled
2734 * @arg HRTIM_FAULT_DISABLED: Fault mode disabled
2735 * @retval None
2736 */
2737 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
2738 {
2739 uint32_t HRTIM_fltinr1;
2740 uint32_t HRTIM_fltinr2;
2741
2742 /* Check parameters */
2743 assert_param(IS_HRTIM_FAULT(Fault));
2744 assert_param(IS_HRTIM_FAULTCTL(Enable));
2745
2746 /* Configure fault channel */
2747 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
2748 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2749
2750 switch (Fault)
2751 {
2752 case HRTIM_FAULT_1:
2753 {
2754 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
2755 HRTIM_fltinr1 |= Enable;
2756 }
2757 break;
2758 case HRTIM_FAULT_2:
2759 {
2760 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
2761 HRTIM_fltinr1 |= (Enable<< 8);
2762 }
2763 break;
2764 case HRTIM_FAULT_3:
2765 {
2766 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
2767 HRTIM_fltinr1 |= (Enable << 16);
2768 }
2769 break;
2770 case HRTIM_FAULT_4:
2771 {
2772 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
2773 HRTIM_fltinr1 |= (Enable << 24);
2774 }
2775 break;
2776 case HRTIM_FAULT_5:
2777 {
2778 HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
2779 HRTIM_fltinr2 |= Enable;
2780 }
2781 break;
2782 default:
2783 break;
2784 }
2785
2786 /* Update the HRTIMx registers */
2787 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
2788 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2789 }
2790
2791 /**
2792 * @brief Configures both the ADC trigger register update source and the ADC
2793 * trigger source.
2794 * @param HRTIMx: pointer to HRTIMx peripheral
2795 * @param ADC trigger: ADC trigger to configure
2796 * This parameter can be one of the following values:
2797 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
2798 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
2799 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
2800 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
2801 * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
2802 * @retval None
2803 */
2804 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
2805 uint32_t ADCTrigger,
2806 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
2807 {
2808 uint32_t HRTIM_cr1;
2809
2810 /* Check parameters */
2811 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
2812 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
2813
2814 /* Set the ADC trigger update source */
2815 HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
2816
2817 switch (ADCTrigger)
2818 {
2819 case HRTIM_ADCTRIGGER_1:
2820 {
2821 HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
2822 HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
2823
2824 /* Set the ADC trigger 1 source */
2825 HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
2826 }
2827 break;
2828 case HRTIM_ADCTRIGGER_2:
2829 {
2830 HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
2831 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
2832
2833 /* Set the ADC trigger 2 source */
2834 HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
2835 }
2836 break;
2837 case HRTIM_ADCTRIGGER_3:
2838 {
2839 HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
2840 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
2841
2842 /* Set the ADC trigger 3 source */
2843 HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
2844 }
2845 case HRTIM_ADCTRIGGER_4:
2846 {
2847 HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
2848 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
2849
2850 /* Set the ADC trigger 4 source */
2851 HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
2852 }
2853 break;
2854 default:
2855 break;
2856 }
2857
2858 /* Update the HRTIMx registers */
2859 HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
2860 }
2861
2862
2863 /**
2864 * @brief Enables or disables the HRTIMx burst mode controller.
2865 * @param HRTIMx: pointer to HRTIMx peripheral
2866 * @param Enable: Burst mode controller enabling
2867 * This parameter can be one of the following values:
2868 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
2869 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
2870 * @retval None
2871 */
2872 void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
2873 {
2874 uint32_t HRTIM_bmcr;
2875
2876 /* Check parameters */
2877 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
2878
2879 /* Enable/Disable the burst mode controller */
2880 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
2881 HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
2882 HRTIM_bmcr |= Enable;
2883
2884 /* Update the HRTIMx registers */
2885 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
2886 }
2887
2888 /**
2889 * @brief Triggers a software capture on the designed capture unit
2890 * @param HRTIMx: pointer to HRTIMx peripheral
2891 * @param TimerIdx: Timer index
2892 * This parameter can be one of the following values:
2893 * @arg 0x0 to 0x4 for timers A to E
2894 * @param CaptureUnit: Capture unit to trig
2895 * This parameter can be one of the following values:
2896 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2897 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2898 * @retval None
2899 * @note The 'software capture' bit in the capure configuration register is
2900 * automatically reset by hardware
2901 */
2902 void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
2903 uint32_t TimerIdx,
2904 uint32_t CaptureUnit)
2905 {
2906 /* Check parameters */
2907 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2908 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
2909
2910 /* Force a software capture on concerned capture unit */
2911 switch (CaptureUnit)
2912 {
2913 case HRTIM_CAPTUREUNIT_1:
2914 {
2915 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
2916 }
2917 break;
2918 case HRTIM_CAPTUREUNIT_2:
2919 {
2920 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
2921 }
2922 break;
2923 default:
2924 break;
2925 }
2926 }
2927
2928 /**
2929 * @brief Triggers the update of the registers of one or several timers
2930 * @param HRTIMx: pointer to HRTIMx peripheral
2931 * @param TimersToUpdate: timers concerned with the software register update
2932 * This parameter can be any combination of the following values:
2933 * @arg HRTIM_TIMERUPDATE_MASTER
2934 * @arg HRTIM_TIMERUPDATE_A
2935 * @arg HRTIM_TIMERUPDATE_B
2936 * @arg HRTIM_TIMERUPDATE_C
2937 * @arg HRTIM_TIMERUPDATE_D
2938 * @arg HRTIM_TIMERUPDATE_E
2939 * @retval None
2940 * @note The 'software update' bits in the HRTIMx control register 2 register are
2941 * automatically reset by hardware
2942 */
2943 void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
2944 uint32_t TimersToUpdate)
2945 {
2946 /* Check parameters */
2947 assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
2948
2949 /* Force timer(s) registers update */
2950 HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
2951
2952 }
2953
2954 /**
2955 * @brief Triggers the reset of one or several timers
2956 * @param HRTIMx: pointer to HRTIMx peripheral
2957 * @param TimersToUpdate: timers concerned with the software counter reset
2958 * This parameter can be any combination of the following values:
2959 * @arg HRTIM_TIMER_MASTER
2960 * @arg HRTIM_TIMER_A
2961 * @arg HRTIM_TIMER_B
2962 * @arg HRTIM_TIMER_C
2963 * @arg HRTIM_TIMER_D
2964 * @arg HRTIM_TIMER_E
2965 * @retval None
2966 * @note The 'software reset' bits in the HRTIMx control register 2 are
2967 * automatically reset by hardware
2968 */
2969 void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
2970 uint32_t TimersToReset)
2971 {
2972 /* Check parameters */
2973 assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
2974
2975 /* Force timer(s) registers update */
2976 HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
2977
2978 }
2979
2980 /**
2981 * @brief Forces the timer output to its active or inactive state
2982 * @param HRTIMx: pointer to HRTIMx peripheral
2983 * @param TimerIdx: Timer index
2984 * This parameter can be one of the following values:
2985 * @arg 0x0 to 0x4 for timers A to E
2986 * @param Output: Timer output
2987 * This parameter can be one of the following values:
2988 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2989 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2990 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2991 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2992 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2993 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2994 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2995 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2996 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2997 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2998 * @param OutputLevel: indicates whether the output is forced to its active or inactive state
2999 * This parameter can be one of the following values:
3000 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state
3001 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state
3002 * @retval None
3003 * @note The 'software set/reset trigger' bit in the output set/reset registers
3004 * is automatically reset by hardware
3005 */
3006 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
3007 uint32_t TimerIdx,
3008 uint32_t Output,
3009 uint32_t OutputLevel)
3010 {
3011 /* Check parameters */
3012 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3013 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
3014
3015 /* Force timer output level */
3016 switch (Output)
3017 {
3018 case HRTIM_OUTPUT_TA1:
3019 case HRTIM_OUTPUT_TB1:
3020 case HRTIM_OUTPUT_TC1:
3021 case HRTIM_OUTPUT_TD1:
3022 case HRTIM_OUTPUT_TE1:
3023 {
3024 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
3025 {
3026 /* Force output to its active state */
3027 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
3028 }
3029 else
3030 {
3031 /* Force output to its inactive state */
3032 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
3033 }
3034 }
3035 break;
3036 case HRTIM_OUTPUT_TA2:
3037 case HRTIM_OUTPUT_TB2:
3038 case HRTIM_OUTPUT_TC2:
3039 case HRTIM_OUTPUT_TD2:
3040 case HRTIM_OUTPUT_TE2:
3041 {
3042 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
3043 {
3044 /* Force output to its active state */
3045 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
3046 }
3047 else
3048 {
3049 /* Force output to its inactive state */
3050 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
3051 }
3052 }
3053 break;
3054 default:
3055 break;
3056 }
3057 }
3058
3059
3060 /**
3061 * @}
3062 */
3063
3064 /** @defgroup HRTIM_Group4 Peripheral State methods
3065 * @brief Peripheral State functions
3066 *
3067 @verbatim
3068 ===============================================================================
3069 ##### Peripheral State methods #####
3070 ===============================================================================
3071 [..]
3072 This subsection permit to get in run-time the status of the peripheral
3073 and the data flow.
3074
3075 @endverbatim
3076 * @{
3077 */
3078
3079 /**
3080 * @brief Returns actual value of the capture register of the designated capture unit
3081 * @param HRTIMx: pointer to HRTIMx peripheral
3082 * @param TimerIdx: Timer index
3083 * This parameter can be one of the following values:
3084 * @arg 0x0 to 0x4 for timers A to E
3085 * @param CaptureUnit: Capture unit to trig
3086 * This parameter can be one of the following values:
3087 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3088 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3089 * @retval Captured value
3090 */
3091 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
3092 uint32_t TimerIdx,
3093 uint32_t CaptureUnit)
3094 {
3095 uint32_t captured_value = 0;
3096
3097 /* Check parameters */
3098 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3099 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
3100
3101 /* Read captured value */
3102 switch (CaptureUnit)
3103 {
3104 case HRTIM_CAPTUREUNIT_1:
3105 {
3106 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
3107 }
3108 break;
3109 case HRTIM_CAPTUREUNIT_2:
3110 {
3111 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
3112 }
3113 break;
3114 default:
3115 break;
3116 }
3117
3118 return captured_value;
3119 }
3120
3121 /**
3122 * @brief Returns actual level (active or inactive) of the designated output
3123 * @param HRTIMx: pointer to HRTIMx peripheral
3124 * @param TimerIdx: Timer index
3125 * This parameter can be one of the following values:
3126 * @arg 0x0 to 0x4 for timers A to E
3127 * @param Output: Timer output
3128 * This parameter can be one of the following values:
3129 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3130 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3131 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3132 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3133 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3134 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3135 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3136 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3137 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3138 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3139 * @retval Output level
3140 * @note Returned output level is taken before the output stage (chopper,
3141 * polarity).
3142 */
3143 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
3144 uint32_t TimerIdx,
3145 uint32_t Output)
3146 {
3147 uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3148
3149 /* Check parameters */
3150 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3151
3152 /* Read the output level */
3153 switch (Output)
3154 {
3155 case HRTIM_OUTPUT_TA1:
3156 case HRTIM_OUTPUT_TB1:
3157 case HRTIM_OUTPUT_TC1:
3158 case HRTIM_OUTPUT_TD1:
3159 case HRTIM_OUTPUT_TE1:
3160 {
3161 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
3162 {
3163 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
3164 }
3165 else
3166 {
3167 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3168 }
3169 }
3170 break;
3171 case HRTIM_OUTPUT_TA2:
3172 case HRTIM_OUTPUT_TB2:
3173 case HRTIM_OUTPUT_TC2:
3174 case HRTIM_OUTPUT_TD2:
3175 case HRTIM_OUTPUT_TE2:
3176 {
3177 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
3178 {
3179 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
3180 }
3181 else
3182 {
3183 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3184 }
3185 }
3186 break;
3187 default:
3188 break;
3189 }
3190
3191 return output_level;
3192 }
3193
3194 /**
3195 * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
3196 * @param HRTIMx: pointer to HRTIMx peripheral
3197 * @param TimerIdx: Timer index
3198 * This parameter can be one of the following values:
3199 * @arg 0x0 to 0x4 for timers A to E
3200 * @param Output: Timer output
3201 * This parameter can be one of the following values:
3202 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3203 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3204 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3205 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3206 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3207 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3208 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3209 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3210 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3211 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3212 * @retval Output state
3213 */
3214 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
3215 uint32_t TimerIdx,
3216 uint32_t Output)
3217 {
3218 (void)(TimerIdx);
3219 uint32_t output_bit = 0;
3220 uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
3221
3222 /* Check parameters */
3223 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3224
3225 /* Set output state according to output control status and output disable status */
3226 switch (Output)
3227 {
3228 case HRTIM_OUTPUT_TA1:
3229 {
3230 output_bit = HRTIM_OENR_TA1OEN;
3231 }
3232 break;
3233 case HRTIM_OUTPUT_TA2:
3234 {
3235 output_bit = HRTIM_OENR_TA2OEN;
3236 }
3237 break;
3238 case HRTIM_OUTPUT_TB1:
3239 {
3240 output_bit = HRTIM_OENR_TB1OEN;
3241 }
3242 break;
3243 case HRTIM_OUTPUT_TB2:
3244 {
3245 output_bit = HRTIM_OENR_TB2OEN;
3246 }
3247 break;
3248 case HRTIM_OUTPUT_TC1:
3249 {
3250 output_bit = HRTIM_OENR_TC1OEN;
3251 }
3252 break;
3253 case HRTIM_OUTPUT_TC2:
3254 {
3255 output_bit = HRTIM_OENR_TC2OEN;
3256 }
3257 break;
3258 case HRTIM_OUTPUT_TD1:
3259 {
3260 output_bit = HRTIM_OENR_TD1OEN;
3261 }
3262 break;
3263 case HRTIM_OUTPUT_TD2:
3264 {
3265 output_bit = HRTIM_OENR_TD2OEN;
3266 }
3267 break;
3268 case HRTIM_OUTPUT_TE1:
3269 {
3270 output_bit = HRTIM_OENR_TE1OEN;
3271 }
3272 break;
3273 case HRTIM_OUTPUT_TE2:
3274 {
3275 output_bit = HRTIM_OENR_TE2OEN;
3276 }
3277 break;
3278 default:
3279 break;
3280 }
3281
3282 if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
3283 {
3284 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
3285 output_state = HRTIM_OUTPUTSTATE_RUN;
3286 }
3287 else
3288 {
3289 if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
3290 {
3291 /* Output is disabled: output in FAULT state */
3292 output_state = HRTIM_OUTPUTSTATE_FAULT;
3293 }
3294 else
3295 {
3296 /* Output is disabled: output in IDLE state */
3297 output_state = HRTIM_OUTPUTSTATE_IDLE;
3298 }
3299 }
3300
3301 return(output_state);
3302 }
3303
3304 /**
3305 * @brief Returns the level (active or inactive) of the designated output
3306 * when the delayed protection was triggered
3307 * @param HRTIMx: pointer to HRTIMx peripheral
3308 * @param TimerIdx: Timer index
3309 * This parameter can be one of the following values:
3310 * @arg 0x0 to 0x4 for timers A to E
3311 * @param Output: Timer output
3312 * This parameter can be one of the following values:
3313 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3314 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3315 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3316 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3317 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3318 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3319 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3320 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3321 * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
3322 * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
3323 * @retval Delayed protection status
3324 */
3325 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
3326 uint32_t TimerIdx,
3327 uint32_t Output)
3328 {
3329 uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3330
3331 /* Check parameters */
3332 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3333
3334 /* Read the delayed protection status */
3335 switch (Output)
3336 {
3337 case HRTIM_OUTPUT_TA1:
3338 case HRTIM_OUTPUT_TB1:
3339 case HRTIM_OUTPUT_TC1:
3340 case HRTIM_OUTPUT_TD1:
3341 case HRTIM_OUTPUT_TE1:
3342 {
3343 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
3344 {
3345 /* Output 1 was active when the delayed idle protection was triggered */
3346 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
3347 }
3348 else
3349 {
3350 /* Output 1 was inactive when the delayed idle protection was triggered */
3351 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3352 }
3353 }
3354 break;
3355 case HRTIM_OUTPUT_TA2:
3356 case HRTIM_OUTPUT_TB2:
3357 case HRTIM_OUTPUT_TC2:
3358 case HRTIM_OUTPUT_TD2:
3359 case HRTIM_OUTPUT_TE2:
3360 {
3361 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
3362 {
3363 /* Output 2 was active when the delayed idle protection was triggered */
3364 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
3365 }
3366 else
3367 {
3368 /* Output 2 was inactive when the delayed idle protection was triggered */
3369 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3370 }
3371 }
3372 break;
3373 default:
3374 break;
3375 }
3376
3377 return delayed_protection_status;
3378 }
3379
3380 /**
3381 * @brief Returns the actual status (active or inactive) of the burst mode controller
3382 * @param HRTIMx: pointer to HRTIMx peripheral
3383 * @retval Burst mode controller status
3384 */
3385 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
3386 {
3387 uint32_t burst_mode_status;
3388
3389 /* Read burst mode status */
3390 burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
3391
3392 return burst_mode_status;
3393 }
3394
3395 /**
3396 * @brief Indicates on which output the signal is currently active (when the
3397 * push pull mode is enabled)
3398 * @param HRTIMx: pointer to HRTIMx peripheral
3399 * @param TimerIdx: Timer index
3400 * This parameter can be one of the following values:
3401 * @arg 0x0 to 0x4 for timers A to E
3402 * @retval Burst mode controller status
3403 */
3404 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
3405 uint32_t TimerIdx)
3406 {
3407 uint32_t current_pushpull_status;
3408
3409 /* Check the parameters */
3410 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3411
3412 /* Read current push pull status */
3413 current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
3414
3415 return current_pushpull_status;
3416 }
3417
3418
3419 /**
3420 * @brief Indicates on which output the signal was applied, in push-pull mode
3421 balanced fault mode or delayed idle mode, when the protection was triggered
3422 * @param HRTIMx: pointer to HRTIMx peripheral
3423 * @param TimerIdx: Timer index
3424 * This parameter can be one of the following values:
3425 * @arg 0x0 to 0x4 for timers A to E
3426 * @retval Idle Push Pull Status
3427 */
3428 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
3429 uint32_t TimerIdx)
3430 {
3431 uint32_t idle_pushpull_status;
3432
3433 /* Check the parameters */
3434 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3435
3436 /* Read current push pull status */
3437 idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
3438
3439 return idle_pushpull_status;
3440 }
3441
3442 /**
3443 * @brief Configures the master timer time base
3444 * @param HRTIMx: pointer to HRTIMx peripheral
3445 * @retval None
3446 */
3447 void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
3448 {
3449 /* Set the prescaler ratio */
3450 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
3451 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
3452
3453 /* Set the operating mode */
3454 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
3455 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
3456
3457 /* Update the HRTIMx registers */
3458 HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
3459 HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
3460 }
3461
3462 /**
3463 * @brief Configures timing unit (timer A to timer E) time base
3464 * @param HRTIMx: pointer to HRTIMx peripheral
3465 * @param TimerIdx: Timer index
3466 * @retval None
3467 */
3468 void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
3469 {
3470 /* Set the prescaler ratio */
3471 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
3472 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
3473
3474 /* Set the operating mode */
3475 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
3476 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
3477
3478 /* Update the HRTIMx registers */
3479 HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
3480 HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
3481 }
3482
3483 /**
3484 * @brief Configures the master timer in waveform mode
3485 * @param HRTIMx: pointer to HRTIMx peripheral
3486 * @param TimerIdx: Timer index
3487 * @param pTimerInit: pointer to the timer initialization data structure
3488 * @retval None
3489 */
3490 void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
3491 HRTIM_TimerInitTypeDef * pTimerInit)
3492 {
3493 uint32_t HRTIM_mcr;
3494 uint32_t HRTIM_bmcr;
3495
3496 /* Configure master timer */
3497 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
3498 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
3499
3500 /* Enable/Disable the half mode */
3501 HRTIM_mcr &= ~(HRTIM_MCR_HALF);
3502 HRTIM_mcr |= pTimerInit->HalfModeEnable;
3503
3504 /* Enable/Disable the timer start upon synchronization event reception */
3505 HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
3506 HRTIM_mcr |= pTimerInit->StartOnSync;
3507
3508 /* Enable/Disable the timer reset upon synchronization event reception */
3509 HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
3510 HRTIM_mcr |= pTimerInit->ResetOnSync;
3511
3512 /* Enable/Disable the DAC synchronization event generation */
3513 HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
3514 HRTIM_mcr |= pTimerInit->DACSynchro;
3515
3516 /* Enable/Disable preload mechanism for timer registers */
3517 HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
3518 HRTIM_mcr |= pTimerInit->PreloadEnable;
3519
3520 /* Master timer registers update handling */
3521 HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
3522 HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
3523
3524 /* Enable/Disable registers update on repetition */
3525 HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
3526 HRTIM_mcr |= pTimerInit->RepetitionUpdate;
3527
3528 /* Set the timer burst mode */
3529 HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
3530 HRTIM_bmcr |= pTimerInit->BurstMode;
3531
3532 /* Update the HRTIMx registers */
3533 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
3534 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
3535
3536 }
3537
3538 /**
3539 * @brief Configures timing unit (timer A to timer E) in waveform mode
3540 * @param HRTIMx: pointer to HRTIMx peripheral
3541 * @param TimerIdx: Timer index
3542 * @param pTimerInit: pointer to the timer initialization data structure
3543 * @retval None
3544 */
3545 void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
3546 uint32_t TimerIdx,
3547 HRTIM_TimerInitTypeDef * pTimerInit)
3548 {
3549 uint32_t HRTIM_timcr;
3550 uint32_t HRTIM_bmcr;
3551
3552 /* Configure timing unit */
3553 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
3554 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
3555
3556 /* Enable/Disable the half mode */
3557 HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
3558 HRTIM_timcr |= pTimerInit->HalfModeEnable;
3559
3560 /* Enable/Disable the timer start upon synchronization event reception */
3561 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
3562 HRTIM_timcr |= pTimerInit->StartOnSync;
3563
3564 /* Enable/Disable the timer reset upon synchronization event reception */
3565 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
3566 HRTIM_timcr |= pTimerInit->ResetOnSync;
3567
3568 /* Enable/Disable the DAC synchronization event generation */
3569 HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
3570 HRTIM_timcr |= pTimerInit->DACSynchro;
3571
3572 /* Enable/Disable preload mechanism for timer registers */
3573 HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
3574 HRTIM_timcr |= pTimerInit->PreloadEnable;
3575
3576 /* Timing unit registers update handling */
3577 HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
3578 HRTIM_timcr |= pTimerInit->UpdateGating;
3579
3580 /* Enable/Disable registers update on repetition */
3581 HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
3582 if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
3583 {
3584 HRTIM_timcr |= HRTIM_TIMCR_TREPU;
3585 }
3586
3587 /* Set the timer burst mode */
3588 switch (TimerIdx)
3589 {
3590 case HRTIM_TIMERINDEX_TIMER_A:
3591 {
3592 HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
3593 HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
3594 }
3595 break;
3596 case HRTIM_TIMERINDEX_TIMER_B:
3597 {
3598 HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
3599 HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
3600 }
3601 break;
3602 case HRTIM_TIMERINDEX_TIMER_C:
3603 {
3604 HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
3605 HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
3606 }
3607 break;
3608 case HRTIM_TIMERINDEX_TIMER_D:
3609 {
3610 HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
3611 HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
3612 }
3613 break;
3614 case HRTIM_TIMERINDEX_TIMER_E:
3615 {
3616 HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
3617 HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
3618 }
3619 break;
3620 default:
3621 break;
3622 }
3623
3624 /* Update the HRTIMx registers */
3625 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
3626 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
3627 }
3628
3629 /**
3630 * @brief Configures a compare unit
3631 * @param HRTIMx: pointer to HRTIMx peripheral
3632 * @param TimerIdx: Timer index
3633 * @param CompareUnit: Compare unit identifier
3634 * @param pCompareCfg: pointer to the compare unit configuration data structure
3635 * @retval None
3636 */
3637 void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
3638 uint32_t TimerIdx,
3639 uint32_t CompareUnit,
3640 HRTIM_CompareCfgTypeDef * pCompareCfg)
3641 {
3642 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
3643 {
3644 /* Configure the compare unit of the master timer */
3645 switch (CompareUnit)
3646 {
3647 case HRTIM_COMPAREUNIT_1:
3648 {
3649 HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
3650 }
3651 break;
3652 case HRTIM_COMPAREUNIT_2:
3653 {
3654 HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
3655 }
3656 break;
3657 case HRTIM_COMPAREUNIT_3:
3658 {
3659 HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
3660 }
3661 break;
3662 case HRTIM_COMPAREUNIT_4:
3663 {
3664 HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
3665 }
3666 break;
3667 default:
3668 break;
3669 }
3670 }
3671 else
3672 {
3673 /* Configure the compare unit of the timing unit */
3674 switch (CompareUnit)
3675 {
3676 case HRTIM_COMPAREUNIT_1:
3677 {
3678 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
3679 }
3680 break;
3681 case HRTIM_COMPAREUNIT_2:
3682 {
3683 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
3684 }
3685 break;
3686 case HRTIM_COMPAREUNIT_3:
3687 {
3688 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
3689 }
3690 break;
3691 case HRTIM_COMPAREUNIT_4:
3692 {
3693 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
3694 }
3695 break;
3696 default:
3697 break;
3698 }
3699 }
3700 }
3701
3702 /**
3703 * @brief Configures a capture unit
3704 * @param HRTIMx: pointer to HRTIMx peripheral
3705 * @param TimerIdx: Timer index
3706 * @param CaptureUnit: Capture unit identifier
3707 * @param pCaptureCfg: pointer to the compare unit configuration data structure
3708 * @retval None
3709 */
3710 void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
3711 uint32_t TimerIdx,
3712 uint32_t CaptureUnit,
3713 uint32_t Event)
3714 {
3715 uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
3716
3717 switch (Event)
3718 {
3719 case HRTIM_EVENT_1:
3720 {
3721 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
3722 }
3723 break;
3724 case HRTIM_EVENT_2:
3725 {
3726 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
3727 }
3728 break;
3729 case HRTIM_EVENT_3:
3730 {
3731 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
3732 }
3733 break;
3734 case HRTIM_EVENT_4:
3735 {
3736 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
3737 }
3738 break;
3739 case HRTIM_EVENT_5:
3740 {
3741 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
3742 }
3743 break;
3744 case HRTIM_EVENT_6:
3745 {
3746 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
3747 }
3748 break;
3749 case HRTIM_EVENT_7:
3750 {
3751 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
3752 }
3753 break;
3754 case HRTIM_EVENT_8:
3755 {
3756 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
3757 }
3758 break;
3759 case HRTIM_EVENT_9:
3760 {
3761 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
3762 }
3763 break;
3764 case HRTIM_EVENT_10:
3765 {
3766 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
3767 }
3768 break;
3769 default:
3770 break;
3771
3772 }
3773 switch (CaptureUnit)
3774 {
3775 case HRTIM_CAPTUREUNIT_1:
3776 {
3777 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
3778 }
3779 break;
3780 case HRTIM_CAPTUREUNIT_2:
3781 {
3782 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
3783 }
3784 break;
3785 default:
3786 break;
3787 }
3788 }
3789
3790 /**
3791 * @brief Configures the output of a timing unit
3792 * @param HRTIMx: pointer to HRTIMx peripheral
3793 * @param TimerIdx: Timer index
3794 * @param Output: timing unit output identifier
3795 * @param pOutputCfg: pointer to the output configuration data structure
3796 * @retval None
3797 */
3798 void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
3799 uint32_t TimerIdx,
3800 uint32_t Output,
3801 HRTIM_OutputCfgTypeDef * pOutputCfg)
3802 {
3803 uint32_t HRTIM_outr;
3804 uint32_t shift = 0;
3805
3806 HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
3807
3808 switch (Output)
3809 {
3810 case HRTIM_OUTPUT_TA1:
3811 case HRTIM_OUTPUT_TB1:
3812 case HRTIM_OUTPUT_TC1:
3813 case HRTIM_OUTPUT_TD1:
3814 case HRTIM_OUTPUT_TE1:
3815 {
3816 /* Set the output set/reset crossbar */
3817 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
3818 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
3819
3820 shift = 0;
3821 }
3822 break;
3823 case HRTIM_OUTPUT_TA2:
3824 case HRTIM_OUTPUT_TB2:
3825 case HRTIM_OUTPUT_TC2:
3826 case HRTIM_OUTPUT_TD2:
3827 case HRTIM_OUTPUT_TE2:
3828 {
3829 /* Set the output set/reset crossbar */
3830 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
3831 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
3832
3833 shift = 16;
3834 }
3835 break;
3836 default:
3837 break;
3838 }
3839
3840 /* Clear output config */
3841 HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
3842 HRTIM_OUTR_IDLM1 |
3843 HRTIM_OUTR_IDLES1|
3844 HRTIM_OUTR_FAULT1|
3845 HRTIM_OUTR_CHP1 |
3846 HRTIM_OUTR_DIDL1) << shift);
3847
3848 /* Set the polarity */
3849 HRTIM_outr |= (pOutputCfg->Polarity << shift);
3850
3851 /* Set the IDLE mode */
3852 HRTIM_outr |= (pOutputCfg->IdleMode << shift);
3853
3854 /* Set the IDLE state */
3855 HRTIM_outr |= (pOutputCfg->IdleState << shift);
3856
3857 /* Set the FAULT state */
3858 HRTIM_outr |= (pOutputCfg->FaultState << shift);
3859
3860 /* Set the chopper mode */
3861 HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
3862
3863 /* Set the burst mode entry mode */
3864 HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
3865
3866 /* Update HRTIMx register */
3867 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
3868 }
3869
3870 /**
3871 * @brief Configures an external event channel
3872 * @param HRTIMx: pointer to HRTIMx peripheral
3873 * @param Event: Event channel identifier
3874 * @param pEventCfg: pointer to the event channel configuration data structure
3875 * @retval None
3876 */
3877 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
3878 uint32_t Event,
3879 HRTIM_EventCfgTypeDef *pEventCfg)
3880 {
3881 uint32_t hrtim_eecr1;
3882 uint32_t hrtim_eecr2;
3883 uint32_t hrtim_eecr3;
3884
3885 /* Configure external event channel */
3886 hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
3887 hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
3888 hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
3889
3890 switch (Event)
3891 {
3892 case HRTIM_EVENT_1:
3893 {
3894 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
3895 hrtim_eecr1 |= pEventCfg->Source;
3896 hrtim_eecr1 |= pEventCfg->Polarity;
3897 hrtim_eecr1 |= pEventCfg->Sensitivity;
3898 /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
3899 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3900 /* Update the HRTIM registers (EE1FAST bit) */
3901 hrtim_eecr1 |= pEventCfg->FastMode;
3902 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3903 }
3904 break;
3905 case HRTIM_EVENT_2:
3906 {
3907 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
3908 hrtim_eecr1 |= (pEventCfg->Source << 6);
3909 hrtim_eecr1 |= (pEventCfg->Polarity << 6);
3910 hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
3911 /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
3912 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3913 /* Update the HRTIM registers (EE2FAST bit) */
3914 hrtim_eecr1 |= (pEventCfg->FastMode << 6);
3915 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3916 }
3917 break;
3918 case HRTIM_EVENT_3:
3919 {
3920 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
3921 hrtim_eecr1 |= (pEventCfg->Source << 12);
3922 hrtim_eecr1 |= (pEventCfg->Polarity << 12);
3923 hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
3924 /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
3925 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3926 /* Update the HRTIM registers (EE3FAST bit) */
3927 hrtim_eecr1 |= (pEventCfg->FastMode << 12);
3928 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3929 }
3930 break;
3931 case HRTIM_EVENT_4:
3932 {
3933 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
3934 hrtim_eecr1 |= (pEventCfg->Source << 18);
3935 hrtim_eecr1 |= (pEventCfg->Polarity << 18);
3936 hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
3937 /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
3938 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3939 /* Update the HRTIM registers (EE4FAST bit) */
3940 hrtim_eecr1 |= (pEventCfg->FastMode << 18);
3941 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3942 }
3943 break;
3944 case HRTIM_EVENT_5:
3945 {
3946 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
3947 hrtim_eecr1 |= (pEventCfg->Source << 24);
3948 hrtim_eecr1 |= (pEventCfg->Polarity << 24);
3949 hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
3950 /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
3951 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3952 /* Update the HRTIM registers (EE5FAST bit) */
3953 hrtim_eecr1 |= (pEventCfg->FastMode << 24);
3954 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3955 }
3956 break;
3957 case HRTIM_EVENT_6:
3958 {
3959 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
3960 hrtim_eecr2 |= pEventCfg->Source;
3961 hrtim_eecr2 |= pEventCfg->Polarity;
3962 hrtim_eecr2 |= pEventCfg->Sensitivity;
3963 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
3964 hrtim_eecr3 |= pEventCfg->Filter;
3965 /* Update the HRTIM registers */
3966 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
3967 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
3968 }
3969 break;
3970 case HRTIM_EVENT_7:
3971 {
3972 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
3973 hrtim_eecr2 |= (pEventCfg->Source << 6);
3974 hrtim_eecr2 |= (pEventCfg->Polarity << 6);
3975 hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
3976 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
3977 hrtim_eecr3 |= (pEventCfg->Filter << 6);
3978 /* Update the HRTIM registers */
3979 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
3980 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
3981 }
3982 break;
3983 case HRTIM_EVENT_8:
3984 {
3985 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
3986 hrtim_eecr2 |= (pEventCfg->Source << 12);
3987 hrtim_eecr2 |= (pEventCfg->Polarity << 12);
3988 hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
3989 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
3990 hrtim_eecr3 |= (pEventCfg->Filter << 12);
3991 /* Update the HRTIM registers */
3992 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
3993 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
3994 }
3995 break;
3996 case HRTIM_EVENT_9:
3997 {
3998 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
3999 hrtim_eecr2 |= (pEventCfg->Source << 18);
4000 hrtim_eecr2 |= (pEventCfg->Polarity << 18);
4001 hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
4002 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
4003 hrtim_eecr3 |= (pEventCfg->Filter << 18);
4004 /* Update the HRTIM registers */
4005 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
4006 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
4007 }
4008 break;
4009 case HRTIM_EVENT_10:
4010 {
4011 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
4012 hrtim_eecr2 |= (pEventCfg->Source << 24);
4013 hrtim_eecr2 |= (pEventCfg->Polarity << 24);
4014 hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
4015 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
4016 hrtim_eecr3 |= (pEventCfg->Filter << 24);
4017 /* Update the HRTIM registers */
4018 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
4019 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
4020 }
4021 break;
4022 default:
4023 break;
4024 }
4025 }
4026
4027 /**
4028 * @brief Configures the timer counter reset
4029 * @param HRTIMx: pointer to HRTIMx peripheral
4030 * @param TimerIdx: Timer index
4031 * @param Event: Event channel identifier
4032 * @retval None
4033 */
4034 void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
4035 uint32_t TimerIdx,
4036 uint32_t Event)
4037 {
4038 switch (Event)
4039 {
4040 case HRTIM_EVENT_1:
4041 {
4042 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
4043 }
4044 break;
4045 case HRTIM_EVENT_2:
4046 {
4047 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
4048 }
4049 break;
4050 case HRTIM_EVENT_3:
4051 {
4052 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
4053 }
4054 break;
4055 case HRTIM_EVENT_4:
4056 {
4057 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
4058 }
4059 break;
4060 case HRTIM_EVENT_5:
4061 {
4062 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
4063 }
4064 break;
4065 case HRTIM_EVENT_6:
4066 {
4067 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
4068 }
4069 break;
4070 case HRTIM_EVENT_7:
4071 {
4072 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
4073 }
4074 break;
4075 case HRTIM_EVENT_8:
4076 {
4077 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
4078 }
4079 break;
4080 case HRTIM_EVENT_9:
4081 {
4082 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
4083 }
4084 break;
4085 case HRTIM_EVENT_10:
4086 {
4087 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
4088 }
4089 break;
4090 default:
4091 break;
4092 }
4093 }
4094 /**
4095 * @}
4096 */
4097 /**
4098 * @}
4099 */
4100
4101 /**
4102 * @}
4103 */
4104
4105 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4106
4107
4108
4109 #pragma GCC diagnostic pop