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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_dac.h
blob988118ef231c34a4cb06c6648361314aeaa276a7
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dac.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of DAC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_DAC_H
40 #define __STM32F4xx_LL_DAC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx.h"
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined(DAC)
54
55 /** @defgroup DAC_LL DAC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
64 * @{
65 */
66
67 /* Internal masks for DAC channels definition */
68 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
69 /* - channel bits position into register CR */
70 /* - channel bits position into register SWTRIG */
71 /* - channel register offset of data holding register DHRx */
72 /* - channel register offset of data output register DORx */
73 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
74 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
75 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
76
77 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
78 #if defined(DAC_CHANNEL2_SUPPORT)
79 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
80 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
81 #else
82 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
83 #endif /* DAC_CHANNEL2_SUPPORT */
84
85 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
86 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
87 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
88 #if defined(DAC_CHANNEL2_SUPPORT)
89 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
90 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
91 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
92 #endif /* DAC_CHANNEL2_SUPPORT */
93 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
94 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
95 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
96 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
97
98 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
99 #if defined(DAC_CHANNEL2_SUPPORT)
100 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
102 #else
103 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
104 #endif /* DAC_CHANNEL2_SUPPORT */
105
106 /* DAC registers bits positions */
107 #if defined(DAC_CHANNEL2_SUPPORT)
108 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
109 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
110 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
111 #endif /* DAC_CHANNEL2_SUPPORT */
112
113 /* Miscellaneous data */
114 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
115
116 /**
117 * @}
118 */
119
120
121 /* Private macros ------------------------------------------------------------*/
122 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
123 * @{
124 */
125
126 /**
127 * @brief Driver macro reserved for internal use: isolate bits with the
128 * selected mask and shift them to the register LSB
129 * (shift mask on register position bit 0).
130 * @param __BITS__ Bits in register 32 bits
131 * @param __MASK__ Mask in register 32 bits
132 * @retval Bits in register 32 bits
133 */
134 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
135 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
136
137 /**
138 * @brief Driver macro reserved for internal use: set a pointer to
139 * a register from a register basis from which an offset
140 * is applied.
141 * @param __REG__ Register basis from which the offset is applied.
142 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
143 * @retval Pointer to register address
144 */
145 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
146 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
147
148 /**
149 * @}
150 */
151
152
153 /* Exported types ------------------------------------------------------------*/
154 #if defined(USE_FULL_LL_DRIVER)
155 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
156 * @{
157 */
158
159 /**
160 * @brief Structure definition of some features of DAC instance.
161 */
162 typedef struct
163 {
164 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
165 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
166
167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
168
169 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
170 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
171
172 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
173
174 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
176 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
177 @note If waveform automatic generation mode is disabled, this parameter is discarded.
178
179 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
180
181 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
182 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
183
184 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
185
186 } LL_DAC_InitTypeDef;
187
188 /**
189 * @}
190 */
191 #endif /* USE_FULL_LL_DRIVER */
192
193 /* Exported constants --------------------------------------------------------*/
194 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
195 * @{
196 */
197
198 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
199 * @brief Flags defines which can be used with LL_DAC_ReadReg function
200 * @{
201 */
202 /* DAC channel 1 flags */
203 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
204
205 #if defined(DAC_CHANNEL2_SUPPORT)
206 /* DAC channel 2 flags */
207 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
208 #endif /* DAC_CHANNEL2_SUPPORT */
209 /**
210 * @}
211 */
212
213 /** @defgroup DAC_LL_EC_IT DAC interruptions
214 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
215 * @{
216 */
217 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
218 #if defined(DAC_CHANNEL2_SUPPORT)
219 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
220 #endif /* DAC_CHANNEL2_SUPPORT */
221 /**
222 * @}
223 */
224
225 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
226 * @{
227 */
228 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
229 #if defined(DAC_CHANNEL2_SUPPORT)
230 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
231 #endif /* DAC_CHANNEL2_SUPPORT */
232 /**
233 * @}
234 */
235
236 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
237 * @{
238 */
239 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
240 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
241 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
242 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
246 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
247 /**
248 * @}
249 */
250
251 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
252 * @{
253 */
254 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
255 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
256 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
262 * @{
263 */
264 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
276 /**
277 * @}
278 */
279
280 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
281 * @{
282 */
283 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
284 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
285 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
295 /**
296 * @}
297 */
298
299 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
300 * @{
301 */
302 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
303 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
304 /**
305 * @}
306 */
307
308
309 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
310 * @{
311 */
312 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
313 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
314 /**
315 * @}
316 */
317
318 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
319 * @{
320 */
321 /* List of DAC registers intended to be used (most commonly) with */
322 /* DMA transfer. */
323 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
324 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
325 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
326 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
327 /**
328 * @}
329 */
330
331 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
332 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
333 * not timeout values.
334 * For details on delays values, refer to descriptions in source code
335 * above each literal definition.
336 * @{
337 */
338
339 /* Delay for DAC channel voltage settling time from DAC channel startup */
340 /* (transition from disable to enable). */
341 /* Note: DAC channel startup time depends on board application environment: */
342 /* impedance connected to DAC channel output. */
343 /* The delay below is specified under conditions: */
344 /* - voltage maximum transition (lowest to highest value) */
345 /* - until voltage reaches final value +-1LSB */
346 /* - DAC channel output buffer enabled */
347 /* - load impedance of 5kOhm (min), 50pF (max) */
348 /* Literal set to maximum value (refer to device datasheet, */
349 /* parameter "tWAKEUP"). */
350 /* Unit: us */
351 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
352
353 /* Delay for DAC channel voltage settling time. */
354 /* Note: DAC channel startup time depends on board application environment: */
355 /* impedance connected to DAC channel output. */
356 /* The delay below is specified under conditions: */
357 /* - voltage maximum transition (lowest to highest value) */
358 /* - until voltage reaches final value +-1LSB */
359 /* - DAC channel output buffer enabled */
360 /* - load impedance of 5kOhm min, 50pF max */
361 /* Literal set to maximum value (refer to device datasheet, */
362 /* parameter "tSETTLING"). */
363 /* Unit: us */
364 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
365 /**
366 * @}
367 */
368
369 /**
370 * @}
371 */
372
373 /* Exported macro ------------------------------------------------------------*/
374 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
375 * @{
376 */
377
378 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
379 * @{
380 */
381
382 /**
383 * @brief Write a value in DAC register
384 * @param __INSTANCE__ DAC Instance
385 * @param __REG__ Register to be written
386 * @param __VALUE__ Value to be written in the register
387 * @retval None
388 */
389 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
390
391 /**
392 * @brief Read a value in DAC register
393 * @param __INSTANCE__ DAC Instance
394 * @param __REG__ Register to be read
395 * @retval Register value
396 */
397 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
398
399 /**
400 * @}
401 */
402
403 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
404 * @{
405 */
406
407 /**
408 * @brief Helper macro to get DAC channel number in decimal format
409 * from literals LL_DAC_CHANNEL_x.
410 * Example:
411 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
412 * will return decimal number "1".
413 * @note The input can be a value from functions where a channel
414 * number is returned.
415 * @param __CHANNEL__ This parameter can be one of the following values:
416 * @arg @ref LL_DAC_CHANNEL_1
417 * @arg @ref LL_DAC_CHANNEL_2 (1)
418 *
419 * (1) On this STM32 serie, parameter not available on all devices.
420 * Refer to device datasheet for channels availability.
421 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
422 */
423 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
424 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
425
426 /**
427 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
428 * from number in decimal format.
429 * Example:
430 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
431 * will return a data equivalent to "LL_DAC_CHANNEL_1".
432 * @note If the input parameter does not correspond to a DAC channel,
433 * this macro returns value '0'.
434 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_DAC_CHANNEL_1
437 * @arg @ref LL_DAC_CHANNEL_2 (1)
438 *
439 * (1) On this STM32 serie, parameter not available on all devices.
440 * Refer to device datasheet for channels availability.
441 */
442 #if defined(DAC_CHANNEL2_SUPPORT)
443 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
444 (((__DECIMAL_NB__) == 1U) \
445 ? ( \
446 LL_DAC_CHANNEL_1 \
447 ) \
448 : \
449 (((__DECIMAL_NB__) == 2U) \
450 ? ( \
451 LL_DAC_CHANNEL_2 \
452 ) \
453 : \
454 ( \
455 0 \
456 ) \
457 ) \
458 )
459 #else
460 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
461 (((__DECIMAL_NB__) == 1U) \
462 ? ( \
463 LL_DAC_CHANNEL_1 \
464 ) \
465 : \
466 ( \
467 0 \
468 ) \
469 )
470 #endif /* DAC_CHANNEL2_SUPPORT */
471
472 /**
473 * @brief Helper macro to define the DAC conversion data full-scale digital
474 * value corresponding to the selected DAC resolution.
475 * @note DAC conversion data full-scale corresponds to voltage range
476 * determined by analog voltage references Vref+ and Vref-
477 * (refer to reference manual).
478 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
479 * @arg @ref LL_DAC_RESOLUTION_12B
480 * @arg @ref LL_DAC_RESOLUTION_8B
481 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
482 */
483 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
484 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
485
486 /**
487 * @brief Helper macro to calculate the DAC conversion data (unit: digital
488 * value) corresponding to a voltage (unit: mVolt).
489 * @note This helper macro is intended to provide input data in voltage
490 * rather than digital value,
491 * to be used with LL DAC functions such as
492 * @ref LL_DAC_ConvertData12RightAligned().
493 * @note Analog reference voltage (Vref+) must be either known from
494 * user board environment or can be calculated using ADC measurement
495 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
496 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
497 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
498 * (unit: mVolt).
499 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
500 * @arg @ref LL_DAC_RESOLUTION_12B
501 * @arg @ref LL_DAC_RESOLUTION_8B
502 * @retval DAC conversion data (unit: digital value)
503 */
504 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
505 __DAC_VOLTAGE__,\
506 __DAC_RESOLUTION__) \
507 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
508 / (__VREFANALOG_VOLTAGE__) \
509 )
510
511 /**
512 * @}
513 */
514
515 /**
516 * @}
517 */
518
519
520 /* Exported functions --------------------------------------------------------*/
521 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
522 * @{
523 */
524 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
525 * @{
526 */
527
528 /**
529 * @brief Set the conversion trigger source for the selected DAC channel.
530 * @note For conversion trigger source to be effective, DAC trigger
531 * must be enabled using function @ref LL_DAC_EnableTrigger().
532 * @note To set conversion trigger source, DAC channel must be disabled.
533 * Otherwise, the setting is discarded.
534 * @note Availability of parameters of trigger sources from timer
535 * depends on timers availability on the selected device.
536 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
537 * CR TSEL2 LL_DAC_SetTriggerSource
538 * @param DACx DAC instance
539 * @param DAC_Channel This parameter can be one of the following values:
540 * @arg @ref LL_DAC_CHANNEL_1
541 * @arg @ref LL_DAC_CHANNEL_2 (1)
542 *
543 * (1) On this STM32 serie, parameter not available on all devices.
544 * Refer to device datasheet for channels availability.
545 * @param TriggerSource This parameter can be one of the following values:
546 * @arg @ref LL_DAC_TRIG_SOFTWARE
547 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
548 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
549 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
550 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
551 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
552 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
553 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
554 * @retval None
555 */
556 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
557 {
558 MODIFY_REG(DACx->CR,
559 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
560 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
561 }
562
563 /**
564 * @brief Get the conversion trigger source for the selected DAC channel.
565 * @note For conversion trigger source to be effective, DAC trigger
566 * must be enabled using function @ref LL_DAC_EnableTrigger().
567 * @note Availability of parameters of trigger sources from timer
568 * depends on timers availability on the selected device.
569 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
570 * CR TSEL2 LL_DAC_GetTriggerSource
571 * @param DACx DAC instance
572 * @param DAC_Channel This parameter can be one of the following values:
573 * @arg @ref LL_DAC_CHANNEL_1
574 * @arg @ref LL_DAC_CHANNEL_2 (1)
575 *
576 * (1) On this STM32 serie, parameter not available on all devices.
577 * Refer to device datasheet for channels availability.
578 * @retval Returned value can be one of the following values:
579 * @arg @ref LL_DAC_TRIG_SOFTWARE
580 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
581 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
582 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
583 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
584 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
585 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
586 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
587 */
588 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
589 {
590 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
591 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
592 );
593 }
594
595 /**
596 * @brief Set the waveform automatic generation mode
597 * for the selected DAC channel.
598 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
599 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
600 * @param DACx DAC instance
601 * @param DAC_Channel This parameter can be one of the following values:
602 * @arg @ref LL_DAC_CHANNEL_1
603 * @arg @ref LL_DAC_CHANNEL_2 (1)
604 *
605 * (1) On this STM32 serie, parameter not available on all devices.
606 * Refer to device datasheet for channels availability.
607 * @param WaveAutoGeneration This parameter can be one of the following values:
608 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
609 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
610 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
611 * @retval None
612 */
613 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
614 {
615 MODIFY_REG(DACx->CR,
616 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
617 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
618 }
619
620 /**
621 * @brief Get the waveform automatic generation mode
622 * for the selected DAC channel.
623 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
624 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
625 * @param DACx DAC instance
626 * @param DAC_Channel This parameter can be one of the following values:
627 * @arg @ref LL_DAC_CHANNEL_1
628 * @arg @ref LL_DAC_CHANNEL_2 (1)
629 *
630 * (1) On this STM32 serie, parameter not available on all devices.
631 * Refer to device datasheet for channels availability.
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
634 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
635 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
636 */
637 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
638 {
639 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
640 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
641 );
642 }
643
644 /**
645 * @brief Set the noise waveform generation for the selected DAC channel:
646 * Noise mode and parameters LFSR (linear feedback shift register).
647 * @note For wave generation to be effective, DAC channel
648 * wave generation mode must be enabled using
649 * function @ref LL_DAC_SetWaveAutoGeneration().
650 * @note This setting can be set when the selected DAC channel is disabled
651 * (otherwise, the setting operation is ignored).
652 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
653 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
654 * @param DACx DAC instance
655 * @param DAC_Channel This parameter can be one of the following values:
656 * @arg @ref LL_DAC_CHANNEL_1
657 * @arg @ref LL_DAC_CHANNEL_2 (1)
658 *
659 * (1) On this STM32 serie, parameter not available on all devices.
660 * Refer to device datasheet for channels availability.
661 * @param NoiseLFSRMask This parameter can be one of the following values:
662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
665 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
666 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
667 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
668 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
669 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
670 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
671 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
672 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
673 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
674 * @retval None
675 */
676 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
677 {
678 MODIFY_REG(DACx->CR,
679 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
680 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
681 }
682
683 /**
684 * @brief Set the noise waveform generation for the selected DAC channel:
685 * Noise mode and parameters LFSR (linear feedback shift register).
686 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
687 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
688 * @param DACx DAC instance
689 * @param DAC_Channel This parameter can be one of the following values:
690 * @arg @ref LL_DAC_CHANNEL_1
691 * @arg @ref LL_DAC_CHANNEL_2 (1)
692 *
693 * (1) On this STM32 serie, parameter not available on all devices.
694 * Refer to device datasheet for channels availability.
695 * @retval Returned value can be one of the following values:
696 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
697 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
698 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
699 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
700 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
701 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
702 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
708 */
709 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
710 {
711 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
712 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
713 );
714 }
715
716 /**
717 * @brief Set the triangle waveform generation for the selected DAC channel:
718 * triangle mode and amplitude.
719 * @note For wave generation to be effective, DAC channel
720 * wave generation mode must be enabled using
721 * function @ref LL_DAC_SetWaveAutoGeneration().
722 * @note This setting can be set when the selected DAC channel is disabled
723 * (otherwise, the setting operation is ignored).
724 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
725 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
726 * @param DACx DAC instance
727 * @param DAC_Channel This parameter can be one of the following values:
728 * @arg @ref LL_DAC_CHANNEL_1
729 * @arg @ref LL_DAC_CHANNEL_2 (1)
730 *
731 * (1) On this STM32 serie, parameter not available on all devices.
732 * Refer to device datasheet for channels availability.
733 * @param TriangleAmplitude This parameter can be one of the following values:
734 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
735 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
736 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
737 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
738 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
739 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
740 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
741 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
742 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
743 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
744 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
745 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
746 * @retval None
747 */
748 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
749 {
750 MODIFY_REG(DACx->CR,
751 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
752 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
753 }
754
755 /**
756 * @brief Set the triangle waveform generation for the selected DAC channel:
757 * triangle mode and amplitude.
758 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
759 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
760 * @param DACx DAC instance
761 * @param DAC_Channel This parameter can be one of the following values:
762 * @arg @ref LL_DAC_CHANNEL_1
763 * @arg @ref LL_DAC_CHANNEL_2 (1)
764 *
765 * (1) On this STM32 serie, parameter not available on all devices.
766 * Refer to device datasheet for channels availability.
767 * @retval Returned value can be one of the following values:
768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
774 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
775 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
776 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
777 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
778 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
779 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
780 */
781 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
782 {
783 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
784 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
785 );
786 }
787
788 /**
789 * @brief Set the output buffer for the selected DAC channel.
790 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
791 * CR BOFF2 LL_DAC_SetOutputBuffer
792 * @param DACx DAC instance
793 * @param DAC_Channel This parameter can be one of the following values:
794 * @arg @ref LL_DAC_CHANNEL_1
795 * @arg @ref LL_DAC_CHANNEL_2 (1)
796 *
797 * (1) On this STM32 serie, parameter not available on all devices.
798 * Refer to device datasheet for channels availability.
799 * @param OutputBuffer This parameter can be one of the following values:
800 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
801 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
802 * @retval None
803 */
804 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
805 {
806 MODIFY_REG(DACx->CR,
807 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
808 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
809 }
810
811 /**
812 * @brief Get the output buffer state for the selected DAC channel.
813 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
814 * CR BOFF2 LL_DAC_GetOutputBuffer
815 * @param DACx DAC instance
816 * @param DAC_Channel This parameter can be one of the following values:
817 * @arg @ref LL_DAC_CHANNEL_1
818 * @arg @ref LL_DAC_CHANNEL_2 (1)
819 *
820 * (1) On this STM32 serie, parameter not available on all devices.
821 * Refer to device datasheet for channels availability.
822 * @retval Returned value can be one of the following values:
823 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
824 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
825 */
826 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
827 {
828 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
829 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
830 );
831 }
832
833 /**
834 * @}
835 */
836
837 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
838 * @{
839 */
840
841 /**
842 * @brief Enable DAC DMA transfer request of the selected channel.
843 * @note To configure DMA source address (peripheral address),
844 * use function @ref LL_DAC_DMA_GetRegAddr().
845 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
846 * CR DMAEN2 LL_DAC_EnableDMAReq
847 * @param DACx DAC instance
848 * @param DAC_Channel This parameter can be one of the following values:
849 * @arg @ref LL_DAC_CHANNEL_1
850 * @arg @ref LL_DAC_CHANNEL_2 (1)
851 *
852 * (1) On this STM32 serie, parameter not available on all devices.
853 * Refer to device datasheet for channels availability.
854 * @retval None
855 */
856 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
857 {
858 SET_BIT(DACx->CR,
859 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
860 }
861
862 /**
863 * @brief Disable DAC DMA transfer request of the selected channel.
864 * @note To configure DMA source address (peripheral address),
865 * use function @ref LL_DAC_DMA_GetRegAddr().
866 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
867 * CR DMAEN2 LL_DAC_DisableDMAReq
868 * @param DACx DAC instance
869 * @param DAC_Channel This parameter can be one of the following values:
870 * @arg @ref LL_DAC_CHANNEL_1
871 * @arg @ref LL_DAC_CHANNEL_2 (1)
872 *
873 * (1) On this STM32 serie, parameter not available on all devices.
874 * Refer to device datasheet for channels availability.
875 * @retval None
876 */
877 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
878 {
879 CLEAR_BIT(DACx->CR,
880 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
881 }
882
883 /**
884 * @brief Get DAC DMA transfer request state of the selected channel.
885 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
886 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
887 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
888 * @param DACx DAC instance
889 * @param DAC_Channel This parameter can be one of the following values:
890 * @arg @ref LL_DAC_CHANNEL_1
891 * @arg @ref LL_DAC_CHANNEL_2 (1)
892 *
893 * (1) On this STM32 serie, parameter not available on all devices.
894 * Refer to device datasheet for channels availability.
895 * @retval State of bit (1 or 0).
896 */
897 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
898 {
899 return (READ_BIT(DACx->CR,
900 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
901 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
902 }
903
904 /**
905 * @brief Function to help to configure DMA transfer to DAC: retrieve the
906 * DAC register address from DAC instance and a list of DAC registers
907 * intended to be used (most commonly) with DMA transfer.
908 * @note These DAC registers are data holding registers:
909 * when DAC conversion is requested, DAC generates a DMA transfer
910 * request to have data available in DAC data holding registers.
911 * @note This macro is intended to be used with LL DMA driver, refer to
912 * function "LL_DMA_ConfigAddresses()".
913 * Example:
914 * LL_DMA_ConfigAddresses(DMA1,
915 * LL_DMA_CHANNEL_1,
916 * (uint32_t)&< array or variable >,
917 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
918 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
919 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
920 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
921 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
922 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
923 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
924 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
925 * @param DACx DAC instance
926 * @param DAC_Channel This parameter can be one of the following values:
927 * @arg @ref LL_DAC_CHANNEL_1
928 * @arg @ref LL_DAC_CHANNEL_2 (1)
929 *
930 * (1) On this STM32 serie, parameter not available on all devices.
931 * Refer to device datasheet for channels availability.
932 * @param Register This parameter can be one of the following values:
933 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
934 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
935 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
936 * @retval DAC register address
937 */
938 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
939 {
940 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
941 /* DAC channel selected. */
942 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
943 }
944 /**
945 * @}
946 */
947
948 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
949 * @{
950 */
951
952 /**
953 * @brief Enable DAC selected channel.
954 * @rmtoll CR EN1 LL_DAC_Enable\n
955 * CR EN2 LL_DAC_Enable
956 * @note After enable from off state, DAC channel requires a delay
957 * for output voltage to reach accuracy +/- 1 LSB.
958 * Refer to device datasheet, parameter "tWAKEUP".
959 * @param DACx DAC instance
960 * @param DAC_Channel This parameter can be one of the following values:
961 * @arg @ref LL_DAC_CHANNEL_1
962 * @arg @ref LL_DAC_CHANNEL_2 (1)
963 *
964 * (1) On this STM32 serie, parameter not available on all devices.
965 * Refer to device datasheet for channels availability.
966 * @retval None
967 */
968 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
969 {
970 SET_BIT(DACx->CR,
971 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
972 }
973
974 /**
975 * @brief Disable DAC selected channel.
976 * @rmtoll CR EN1 LL_DAC_Disable\n
977 * CR EN2 LL_DAC_Disable
978 * @param DACx DAC instance
979 * @param DAC_Channel This parameter can be one of the following values:
980 * @arg @ref LL_DAC_CHANNEL_1
981 * @arg @ref LL_DAC_CHANNEL_2 (1)
982 *
983 * (1) On this STM32 serie, parameter not available on all devices.
984 * Refer to device datasheet for channels availability.
985 * @retval None
986 */
987 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
988 {
989 CLEAR_BIT(DACx->CR,
990 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
991 }
992
993 /**
994 * @brief Get DAC enable state of the selected channel.
995 * (0: DAC channel is disabled, 1: DAC channel is enabled)
996 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
997 * CR EN2 LL_DAC_IsEnabled
998 * @param DACx DAC instance
999 * @param DAC_Channel This parameter can be one of the following values:
1000 * @arg @ref LL_DAC_CHANNEL_1
1001 * @arg @ref LL_DAC_CHANNEL_2 (1)
1002 *
1003 * (1) On this STM32 serie, parameter not available on all devices.
1004 * Refer to device datasheet for channels availability.
1005 * @retval State of bit (1 or 0).
1006 */
1007 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1008 {
1009 return (READ_BIT(DACx->CR,
1010 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1011 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1012 }
1013
1014 /**
1015 * @brief Enable DAC trigger of the selected channel.
1016 * @note - If DAC trigger is disabled, DAC conversion is performed
1017 * automatically once the data holding register is updated,
1018 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1019 * @ref LL_DAC_ConvertData12RightAligned(), ...
1020 * - If DAC trigger is enabled, DAC conversion is performed
1021 * only when a hardware of software trigger event is occurring.
1022 * Select trigger source using
1023 * function @ref LL_DAC_SetTriggerSource().
1024 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1025 * CR TEN2 LL_DAC_EnableTrigger
1026 * @param DACx DAC instance
1027 * @param DAC_Channel This parameter can be one of the following values:
1028 * @arg @ref LL_DAC_CHANNEL_1
1029 * @arg @ref LL_DAC_CHANNEL_2 (1)
1030 *
1031 * (1) On this STM32 serie, parameter not available on all devices.
1032 * Refer to device datasheet for channels availability.
1033 * @retval None
1034 */
1035 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1036 {
1037 SET_BIT(DACx->CR,
1038 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1039 }
1040
1041 /**
1042 * @brief Disable DAC trigger of the selected channel.
1043 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1044 * CR TEN2 LL_DAC_DisableTrigger
1045 * @param DACx DAC instance
1046 * @param DAC_Channel This parameter can be one of the following values:
1047 * @arg @ref LL_DAC_CHANNEL_1
1048 * @arg @ref LL_DAC_CHANNEL_2 (1)
1049 *
1050 * (1) On this STM32 serie, parameter not available on all devices.
1051 * Refer to device datasheet for channels availability.
1052 * @retval None
1053 */
1054 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1055 {
1056 CLEAR_BIT(DACx->CR,
1057 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1058 }
1059
1060 /**
1061 * @brief Get DAC trigger state of the selected channel.
1062 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1063 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1064 * CR TEN2 LL_DAC_IsTriggerEnabled
1065 * @param DACx DAC instance
1066 * @param DAC_Channel This parameter can be one of the following values:
1067 * @arg @ref LL_DAC_CHANNEL_1
1068 * @arg @ref LL_DAC_CHANNEL_2 (1)
1069 *
1070 * (1) On this STM32 serie, parameter not available on all devices.
1071 * Refer to device datasheet for channels availability.
1072 * @retval State of bit (1 or 0).
1073 */
1074 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1075 {
1076 return (READ_BIT(DACx->CR,
1077 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1078 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1079 }
1080
1081 /**
1082 * @brief Trig DAC conversion by software for the selected DAC channel.
1083 * @note Preliminarily, DAC trigger must be set to software trigger
1084 * using function @ref LL_DAC_SetTriggerSource()
1085 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1086 * and DAC trigger must be enabled using
1087 * function @ref LL_DAC_EnableTrigger().
1088 * @note For devices featuring DAC with 2 channels: this function
1089 * can perform a SW start of both DAC channels simultaneously.
1090 * Two channels can be selected as parameter.
1091 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1092 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1093 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1094 * @param DACx DAC instance
1095 * @param DAC_Channel This parameter can a combination of the following values:
1096 * @arg @ref LL_DAC_CHANNEL_1
1097 * @arg @ref LL_DAC_CHANNEL_2 (1)
1098 *
1099 * (1) On this STM32 serie, parameter not available on all devices.
1100 * Refer to device datasheet for channels availability.
1101 * @retval None
1102 */
1103 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1104 {
1105 SET_BIT(DACx->SWTRIGR,
1106 (DAC_Channel & DAC_SWTR_CHX_MASK));
1107 }
1108
1109 /**
1110 * @brief Set the data to be loaded in the data holding register
1111 * in format 12 bits left alignment (LSB aligned on bit 0),
1112 * for the selected DAC channel.
1113 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1114 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1115 * @param DACx DAC instance
1116 * @param DAC_Channel This parameter can be one of the following values:
1117 * @arg @ref LL_DAC_CHANNEL_1
1118 * @arg @ref LL_DAC_CHANNEL_2 (1)
1119 *
1120 * (1) On this STM32 serie, parameter not available on all devices.
1121 * Refer to device datasheet for channels availability.
1122 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1123 * @retval None
1124 */
1125 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1126 {
1127 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1128
1129 MODIFY_REG(*preg,
1130 DAC_DHR12R1_DACC1DHR,
1131 Data);
1132 }
1133
1134 /**
1135 * @brief Set the data to be loaded in the data holding register
1136 * in format 12 bits left alignment (MSB aligned on bit 15),
1137 * for the selected DAC channel.
1138 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1139 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1140 * @param DACx DAC instance
1141 * @param DAC_Channel This parameter can be one of the following values:
1142 * @arg @ref LL_DAC_CHANNEL_1
1143 * @arg @ref LL_DAC_CHANNEL_2 (1)
1144 *
1145 * (1) On this STM32 serie, parameter not available on all devices.
1146 * Refer to device datasheet for channels availability.
1147 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1148 * @retval None
1149 */
1150 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1151 {
1152 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1153
1154 MODIFY_REG(*preg,
1155 DAC_DHR12L1_DACC1DHR,
1156 Data);
1157 }
1158
1159 /**
1160 * @brief Set the data to be loaded in the data holding register
1161 * in format 8 bits left alignment (LSB aligned on bit 0),
1162 * for the selected DAC channel.
1163 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1164 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1165 * @param DACx DAC instance
1166 * @param DAC_Channel This parameter can be one of the following values:
1167 * @arg @ref LL_DAC_CHANNEL_1
1168 * @arg @ref LL_DAC_CHANNEL_2 (1)
1169 *
1170 * (1) On this STM32 serie, parameter not available on all devices.
1171 * Refer to device datasheet for channels availability.
1172 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1173 * @retval None
1174 */
1175 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1176 {
1177 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1178
1179 MODIFY_REG(*preg,
1180 DAC_DHR8R1_DACC1DHR,
1181 Data);
1182 }
1183
1184 #if defined(DAC_CHANNEL2_SUPPORT)
1185 /**
1186 * @brief Set the data to be loaded in the data holding register
1187 * in format 12 bits left alignment (LSB aligned on bit 0),
1188 * for both DAC channels.
1189 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1190 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1191 * @param DACx DAC instance
1192 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1193 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1194 * @retval None
1195 */
1196 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1197 {
1198 MODIFY_REG(DACx->DHR12RD,
1199 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1200 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1201 }
1202
1203 /**
1204 * @brief Set the data to be loaded in the data holding register
1205 * in format 12 bits left alignment (MSB aligned on bit 15),
1206 * for both DAC channels.
1207 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1208 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1209 * @param DACx DAC instance
1210 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1211 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1212 * @retval None
1213 */
1214 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1215 {
1216 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1217 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1218 /* the 4 LSB must be taken into account for the shift value. */
1219 MODIFY_REG(DACx->DHR12LD,
1220 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1221 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1222 }
1223
1224 /**
1225 * @brief Set the data to be loaded in the data holding register
1226 * in format 8 bits left alignment (LSB aligned on bit 0),
1227 * for both DAC channels.
1228 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1229 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1230 * @param DACx DAC instance
1231 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1232 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1233 * @retval None
1234 */
1235 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1236 {
1237 MODIFY_REG(DACx->DHR8RD,
1238 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1239 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1240 }
1241
1242 #endif /* DAC_CHANNEL2_SUPPORT */
1243 /**
1244 * @brief Retrieve output data currently generated for the selected DAC channel.
1245 * @note Whatever alignment and resolution settings
1246 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1247 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1248 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1249 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1250 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1251 * @param DACx DAC instance
1252 * @param DAC_Channel This parameter can be one of the following values:
1253 * @arg @ref LL_DAC_CHANNEL_1
1254 * @arg @ref LL_DAC_CHANNEL_2 (1)
1255 *
1256 * (1) On this STM32 serie, parameter not available on all devices.
1257 * Refer to device datasheet for channels availability.
1258 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1259 */
1260 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1261 {
1262 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1263
1264 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1265 }
1266
1267 /**
1268 * @}
1269 */
1270
1271 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1272 * @{
1273 */
1274 /**
1275 * @brief Get DAC underrun flag for DAC channel 1
1276 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1277 * @param DACx DAC instance
1278 * @retval State of bit (1 or 0).
1279 */
1280 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1281 {
1282 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1283 }
1284
1285 #if defined(DAC_CHANNEL2_SUPPORT)
1286 /**
1287 * @brief Get DAC underrun flag for DAC channel 2
1288 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1289 * @param DACx DAC instance
1290 * @retval State of bit (1 or 0).
1291 */
1292 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1293 {
1294 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1295 }
1296 #endif /* DAC_CHANNEL2_SUPPORT */
1297
1298 /**
1299 * @brief Clear DAC underrun flag for DAC channel 1
1300 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1301 * @param DACx DAC instance
1302 * @retval None
1303 */
1304 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1305 {
1306 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1307 }
1308
1309 #if defined(DAC_CHANNEL2_SUPPORT)
1310 /**
1311 * @brief Clear DAC underrun flag for DAC channel 2
1312 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1313 * @param DACx DAC instance
1314 * @retval None
1315 */
1316 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1317 {
1318 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1319 }
1320 #endif /* DAC_CHANNEL2_SUPPORT */
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup DAC_LL_EF_IT_Management IT management
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Enable DMA underrun interrupt for DAC channel 1
1332 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1333 * @param DACx DAC instance
1334 * @retval None
1335 */
1336 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1337 {
1338 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1339 }
1340
1341 #if defined(DAC_CHANNEL2_SUPPORT)
1342 /**
1343 * @brief Enable DMA underrun interrupt for DAC channel 2
1344 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1345 * @param DACx DAC instance
1346 * @retval None
1347 */
1348 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1349 {
1350 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1351 }
1352 #endif /* DAC_CHANNEL2_SUPPORT */
1353
1354 /**
1355 * @brief Disable DMA underrun interrupt for DAC channel 1
1356 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1357 * @param DACx DAC instance
1358 * @retval None
1359 */
1360 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1361 {
1362 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1363 }
1364
1365 #if defined(DAC_CHANNEL2_SUPPORT)
1366 /**
1367 * @brief Disable DMA underrun interrupt for DAC channel 2
1368 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1369 * @param DACx DAC instance
1370 * @retval None
1371 */
1372 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1373 {
1374 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1375 }
1376 #endif /* DAC_CHANNEL2_SUPPORT */
1377
1378 /**
1379 * @brief Get DMA underrun interrupt for DAC channel 1
1380 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1381 * @param DACx DAC instance
1382 * @retval State of bit (1 or 0).
1383 */
1384 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1385 {
1386 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1387 }
1388
1389 #if defined(DAC_CHANNEL2_SUPPORT)
1390 /**
1391 * @brief Get DMA underrun interrupt for DAC channel 2
1392 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1393 * @param DACx DAC instance
1394 * @retval State of bit (1 or 0).
1395 */
1396 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1397 {
1398 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1399 }
1400 #endif /* DAC_CHANNEL2_SUPPORT */
1401
1402 /**
1403 * @}
1404 */
1405
1406 #if defined(USE_FULL_LL_DRIVER)
1407 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1408 * @{
1409 */
1410
1411 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1412 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1413 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1414
1415 /**
1416 * @}
1417 */
1418 #endif /* USE_FULL_LL_DRIVER */
1419
1420 /**
1421 * @}
1422 */
1423
1424 /**
1425 * @}
1426 */
1427
1428 #endif /* DAC */
1429
1430 /**
1431 * @}
1432 */
1433
1434 #ifdef __cplusplus
1435 }
1436 #endif
1437
1438 #endif /* __STM32F4xx_LL_DAC_H */
1439
1440 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/