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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_fsmc.h
blob0977510969db860b3bdb043756426c6733428894
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of FSMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FSMC_H
40 #define __STM32F4xx_LL_FSMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup FSMC_LL
54 * @{
55 */
56
57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
58 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
59 /* Private types -------------------------------------------------------------*/
60 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
61 * @{
62 */
63
64 /**
65 * @brief FSMC NORSRAM Configuration Structure definition
66 */
67 typedef struct
68 {
69 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
70 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
71
72 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
73 multiplexed on the data bus or not.
74 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
75
76 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
77 the corresponding memory device.
78 This parameter can be a value of @ref FSMC_Memory_Type */
79
80 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
81 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
82
83 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
84 valid only with synchronous burst Flash memories.
85 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
86
87 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
88 the Flash memory in burst mode.
89 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
90
91 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
92 memory, valid only when accessing Flash memories in burst mode.
93 This parameter can be a value of @ref FSMC_Wrap_Mode
94 This mode is available only for the STM32F405/407/4015/417xx devices */
95
96 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
97 clock cycle before the wait state or during the wait state,
98 valid only when accessing memories in burst mode.
99 This parameter can be a value of @ref FSMC_Wait_Timing */
100
101 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
102 This parameter can be a value of @ref FSMC_Write_Operation */
103
104 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
105 signal, valid for Flash memory access in burst mode.
106 This parameter can be a value of @ref FSMC_Wait_Signal */
107
108 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
109 This parameter can be a value of @ref FSMC_Extended_Mode */
110
111 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
112 valid only with asynchronous Flash memories.
113 This parameter can be a value of @ref FSMC_AsynchronousWait */
114
115 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
116 This parameter can be a value of @ref FSMC_Write_Burst */
117
118 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
119 This parameter is only enabled through the FMC_BCR1 register, and don't care
120 through FMC_BCR2..4 registers.
121 This parameter can be a value of @ref FMC_Continous_Clock
122 This mode is available only for the STM32F412Vx/Zx/Rx devices */
123
124 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
125 This parameter is only enabled through the FMC_BCR1 register, and don't care
126 through FMC_BCR2..4 registers.
127 This parameter can be a value of @ref FMC_Write_FIFO
128 This mode is available only for the STM32F412Vx/Vx devices */
129
130 uint32_t PageSize; /*!< Specifies the memory page size.
131 This parameter can be a value of @ref FMC_Page_Size */
132 }FSMC_NORSRAM_InitTypeDef;
133
134 /**
135 * @brief FSMC NORSRAM Timing parameters structure definition
136 */
137 typedef struct
138 {
139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
140 the duration of the address setup time.
141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
142 @note This parameter is not used with synchronous NOR Flash memories. */
143
144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
145 the duration of the address hold time.
146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
147 @note This parameter is not used with synchronous NOR Flash memories. */
148
149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
150 the duration of the data setup time.
151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
153 NOR Flash memories. */
154
155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
156 the duration of the bus turnaround.
157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
158 @note This parameter is only used for multiplexed NOR Flash memories. */
159
160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
163 accesses. */
164
165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
166 to the memory before getting the first data.
167 The parameter value depends on the memory type as shown below:
168 - It must be set to 0 in case of a CRAM
169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
171 with synchronous burst mode enable */
172
173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
174 This parameter can be a value of @ref FSMC_Access_Mode */
175
176 }FSMC_NORSRAM_TimingTypeDef;
177
178 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
179 /**
180 * @brief FSMC NAND Configuration Structure definition
181 */
182 typedef struct
183 {
184 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
185 This parameter can be a value of @ref FSMC_NAND_Bank */
186
187 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
188 This parameter can be any value of @ref FSMC_Wait_feature */
189
190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
191 This parameter can be any value of @ref FSMC_NAND_Data_Width */
192
193 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
194 This parameter can be any value of @ref FSMC_ECC */
195
196 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
197 This parameter can be any value of @ref FSMC_ECC_Page_Size */
198
199 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
200 delay between CLE low and RE low.
201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
202
203 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
204 delay between ALE low and RE low.
205 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
206
207 }FSMC_NAND_InitTypeDef;
208
209 /**
210 * @brief FSMC NAND/PCCARD Timing parameters structure definition
211 */
212 typedef struct
213 {
214 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
215 the command assertion for NAND-Flash read or write access
216 to common/Attribute or I/O memory space (depending on
217 the memory space timing to be configured).
218 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
219
220 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
221 command for NAND-Flash read or write access to
222 common/Attribute or I/O memory space (depending on the
223 memory space timing to be configured).
224 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
225
226 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
227 (and data for write access) after the command de-assertion
228 for NAND-Flash read or write access to common/Attribute
229 or I/O memory space (depending on the memory space timing
230 to be configured).
231 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
232
233 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
234 data bus is kept in HiZ after the start of a NAND-Flash
235 write access to common/Attribute or I/O memory space (depending
236 on the memory space timing to be configured).
237 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
238
239 }FSMC_NAND_PCC_TimingTypeDef;
240
241 /**
242 * @brief FSMC NAND Configuration Structure definition
243 */
244 typedef struct
245 {
246 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
247 This parameter can be any value of @ref FSMC_Wait_feature */
248
249 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
250 delay between CLE low and RE low.
251 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
252
253 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
254 delay between ALE low and RE low.
255 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
256
257 }FSMC_PCCARD_InitTypeDef;
258 /**
259 * @}
260 */
261 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
262
263 /* Private constants ---------------------------------------------------------*/
264 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
265 * @{
266 */
267
268 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
269 * @{
270 */
271 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
272 * @{
273 */
274 #define FSMC_NORSRAM_BANK1 0x00000000U
275 #define FSMC_NORSRAM_BANK2 0x00000002U
276 #define FSMC_NORSRAM_BANK3 0x00000004U
277 #define FSMC_NORSRAM_BANK4 0x00000006U
278 /**
279 * @}
280 */
281
282 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
283 * @{
284 */
285 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
286 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
287 /**
288 * @}
289 */
290
291 /** @defgroup FSMC_Memory_Type FSMC Memory Type
292 * @{
293 */
294 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U
295 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
296 #define FSMC_MEMORY_TYPE_NOR 0x00000008U
297 /**
298 * @}
299 */
300
301 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
302 * @{
303 */
304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
307 /**
308 * @}
309 */
310
311 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
312 * @{
313 */
314 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
315 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
316 /**
317 * @}
318 */
319
320 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
321 * @{
322 */
323 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
324 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
325 /**
326 * @}
327 */
328
329 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
330 * @{
331 */
332 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
333 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
334 /**
335 * @}
336 */
337
338 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
339 * @note These values are available only for the STM32F405/415/407/417xx devices.
340 * @{
341 */
342 #define FSMC_WRAP_MODE_DISABLE 0x00000000U
343 #define FSMC_WRAP_MODE_ENABLE 0x00000400U
344 /**
345 * @}
346 */
347
348 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
349 * @{
350 */
351 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
352 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
353 /**
354 * @}
355 */
356
357 /** @defgroup FSMC_Write_Operation FSMC Write Operation
358 * @{
359 */
360 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
361 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
362 /**
363 * @}
364 */
365
366 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
367 * @{
368 */
369 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
370 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
371 /**
372 * @}
373 */
374
375 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
376 * @{
377 */
378 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
379 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
380 /**
381 * @}
382 */
383
384 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
385 * @{
386 */
387 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
388 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
389 /**
390 * @}
391 */
392
393 /** @defgroup FSMC_Page_Size FSMC Page Size
394 * @{
395 */
396 #define FSMC_PAGE_SIZE_NONE 0x00000000U
397 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
398 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
399 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
400 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
401 /**
402 * @}
403 */
404
405 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
406 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
407 * @{
408 */
409 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
410 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U
411 /**
412 * @}
413 */
414
415 /** @defgroup FSMC_Write_Burst FSMC Write Burst
416 * @{
417 */
418 #define FSMC_WRITE_BURST_DISABLE 0x00000000U
419 #define FSMC_WRITE_BURST_ENABLE 0x00080000U
420 /**
421 * @}
422 */
423
424 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
425 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
426 * @{
427 */
428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
429 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
430 /**
431 * @}
432 */
433
434 /** @defgroup FSMC_Access_Mode FSMC Access Mode
435 * @{
436 */
437 #define FSMC_ACCESS_MODE_A 0x00000000U
438 #define FSMC_ACCESS_MODE_B 0x10000000U
439 #define FSMC_ACCESS_MODE_C 0x20000000U
440 #define FSMC_ACCESS_MODE_D 0x30000000U
441 /**
442 * @}
443 */
444 /**
445 * @}
446 */
447
448 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
449 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
450 * @{
451 */
452 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
453 * @{
454 */
455 #define FSMC_NAND_BANK2 0x00000010U
456 #define FSMC_NAND_BANK3 0x00000100U
457 /**
458 * @}
459 */
460
461 /** @defgroup FSMC_Wait_feature FSMC Wait feature
462 * @{
463 */
464 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
465 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
466 /**
467 * @}
468 */
469
470 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
471 * @{
472 */
473 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
474 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
475 /**
476 * @}
477 */
478
479 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
480 * @{
481 */
482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
483 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
484 /**
485 * @}
486 */
487
488 /** @defgroup FSMC_ECC FSMC ECC
489 * @{
490 */
491 #define FSMC_NAND_ECC_DISABLE 0x00000000U
492 #define FSMC_NAND_ECC_ENABLE 0x00000040U
493 /**
494 * @}
495 */
496
497 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
498 * @{
499 */
500 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
501 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
502 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
503 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
504 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
505 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
506 /**
507 * @}
508 */
509 /**
510 * @}
511 */
512 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
513
514 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
515 * @{
516 */
517 #define FSMC_IT_RISING_EDGE 0x00000008U
518 #define FSMC_IT_LEVEL 0x00000010U
519 #define FSMC_IT_FALLING_EDGE 0x00000020U
520 #define FSMC_IT_REFRESH_ERROR 0x00004000U
521 /**
522 * @}
523 */
524
525 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
526 * @{
527 */
528 #define FSMC_FLAG_RISING_EDGE 0x00000001U
529 #define FSMC_FLAG_LEVEL 0x00000002U
530 #define FSMC_FLAG_FALLING_EDGE 0x00000004U
531 #define FSMC_FLAG_FEMPT 0x00000040U
532 /**
533 * @}
534 */
535
536 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
537 * @{
538 */
539 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
540 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
541 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
542 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
543 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
545
546 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
547 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
548 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
549 #define FSMC_NAND_DEVICE FSMC_Bank2_3
550 #define FSMC_PCCARD_DEVICE FSMC_Bank4
551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
552
553 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
554 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
555 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
556
557 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
558 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
559 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
560 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
561
562 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
563 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
564 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
565 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
566 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
567 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
568
569 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
570 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
571
572 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
573 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
574 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
575 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
576
577 #define FMC_NAND_Init FSMC_NAND_Init
578 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
579 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
580 #define FMC_NAND_DeInit FSMC_NAND_DeInit
581 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
582 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
583 #define FMC_NAND_GetECC FSMC_NAND_GetECC
584 #define FMC_PCCARD_Init FSMC_PCCARD_Init
585 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
586 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
587 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
588 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
589
590 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
591 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
592 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
593 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
594 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
595 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
596 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
597 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
598 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
599 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
600 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
601 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
602 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
603
604 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
605 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
606 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
607 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
608 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
609 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
610
611 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
612 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
613 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
614 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
615 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
616
617 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
618 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
619
620 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
621 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
622 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
623
624 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
625 #define FMC_IT_LEVEL FSMC_IT_LEVEL
626 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
627 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
628
629 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
630 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
631 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
632 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
633 /**
634 * @}
635 */
636
637 /**
638 * @}
639 */
640
641 /* Private macro -------------------------------------------------------------*/
642 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
643 * @{
644 */
645
646 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
647 * @brief macros to handle NOR device enable/disable and read/write operations
648 * @{
649 */
650 /**
651 * @brief Enable the NORSRAM device access.
652 * @param __INSTANCE__: FSMC_NORSRAM Instance
653 * @param __BANK__: FSMC_NORSRAM Bank
654 * @retval none
655 */
656 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
657
658 /**
659 * @brief Disable the NORSRAM device access.
660 * @param __INSTANCE__: FSMC_NORSRAM Instance
661 * @param __BANK__: FSMC_NORSRAM Bank
662 * @retval none
663 */
664 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
665 /**
666 * @}
667 */
668
669 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
670 * @brief macros to handle NAND device enable/disable
671 * @{
672 */
673 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
674 /**
675 * @brief Enable the NAND device access.
676 * @param __INSTANCE__: FSMC_NAND Instance
677 * @param __BANK__: FSMC_NAND Bank
678 * @retval none
679 */
680 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
681 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
682
683 /**
684 * @brief Disable the NAND device access.
685 * @param __INSTANCE__: FSMC_NAND Instance
686 * @param __BANK__: FSMC_NAND Bank
687 * @retval none
688 */
689 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
690 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
691 /**
692 * @}
693 */
694
695 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
696 * @brief macros to handle SRAM read/write operations
697 * @{
698 */
699 /**
700 * @brief Enable the PCCARD device access.
701 * @param __INSTANCE__: FSMC_PCCARD Instance
702 * @retval none
703 */
704 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
705
706 /**
707 * @brief Disable the PCCARD device access.
708 * @param __INSTANCE__: FSMC_PCCARD Instance
709 * @retval none
710 */
711 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
712 /**
713 * @}
714 */
715
716 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
717 * @brief macros to handle FSMC flags and interrupts
718 * @{
719 */
720 /**
721 * @brief Enable the NAND device interrupt.
722 * @param __INSTANCE__: FSMC_NAND Instance
723 * @param __BANK__: FSMC_NAND Bank
724 * @param __INTERRUPT__: FSMC_NAND interrupt
725 * This parameter can be any combination of the following values:
726 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
727 * @arg FSMC_IT_LEVEL: Interrupt level.
728 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
729 * @retval None
730 */
731 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
732 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
733
734 /**
735 * @brief Disable the NAND device interrupt.
736 * @param __INSTANCE__: FSMC_NAND Instance
737 * @param __BANK__: FSMC_NAND Bank
738 * @param __INTERRUPT__: FSMC_NAND interrupt
739 * This parameter can be any combination of the following values:
740 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
741 * @arg FSMC_IT_LEVEL: Interrupt level.
742 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
743 * @retval None
744 */
745 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
746 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
747
748 /**
749 * @brief Get flag status of the NAND device.
750 * @param __INSTANCE__: FSMC_NAND Instance
751 * @param __BANK__ : FSMC_NAND Bank
752 * @param __FLAG__ : FSMC_NAND flag
753 * This parameter can be any combination of the following values:
754 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
755 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
756 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
757 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
758 * @retval The state of FLAG (SET or RESET).
759 */
760 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
761 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
762
763 /**
764 * @brief Clear flag status of the NAND device.
765 * @param __INSTANCE__: FSMC_NAND Instance
766 * @param __BANK__: FSMC_NAND Bank
767 * @param __FLAG__: FSMC_NAND flag
768 * This parameter can be any combination of the following values:
769 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
770 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
771 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
772 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
773 * @retval None
774 */
775 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
776 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
777
778 /**
779 * @brief Enable the PCCARD device interrupt.
780 * @param __INSTANCE__: FSMC_PCCARD Instance
781 * @param __INTERRUPT__: FSMC_PCCARD interrupt
782 * This parameter can be any combination of the following values:
783 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
784 * @arg FSMC_IT_LEVEL: Interrupt level.
785 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
786 * @retval None
787 */
788 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
789
790 /**
791 * @brief Disable the PCCARD device interrupt.
792 * @param __INSTANCE__: FSMC_PCCARD Instance
793 * @param __INTERRUPT__: FSMC_PCCARD interrupt
794 * This parameter can be any combination of the following values:
795 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
796 * @arg FSMC_IT_LEVEL: Interrupt level.
797 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
798 * @retval None
799 */
800 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
801
802 /**
803 * @brief Get flag status of the PCCARD device.
804 * @param __INSTANCE__: FSMC_PCCARD Instance
805 * @param __FLAG__: FSMC_PCCARD flag
806 * This parameter can be any combination of the following values:
807 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
808 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
809 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
810 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
811 * @retval The state of FLAG (SET or RESET).
812 */
813 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
814
815 /**
816 * @brief Clear flag status of the PCCARD device.
817 * @param __INSTANCE__: FSMC_PCCARD Instance
818 * @param __FLAG__: FSMC_PCCARD flag
819 * This parameter can be any combination of the following values:
820 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
821 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
822 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
823 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
824 * @retval None
825 */
826 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
827 /**
828 * @}
829 */
830 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
831
832 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
833 * @{
834 */
835 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
836 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
837 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
838 ((__BANK__) == FSMC_NORSRAM_BANK4))
839
840 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
841 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
842
843 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
844 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
845 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
846
847 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
849 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
850
851 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
852 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
853 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
854 ((__MODE__) == FSMC_ACCESS_MODE_D))
855
856 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
857 ((BANK) == FSMC_NAND_BANK3))
858
859 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
860 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
861
862 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
863 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
864
865 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
866 ((STATE) == FSMC_NAND_ECC_ENABLE))
867
868 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
873 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
874
875 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
876
877 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
878
879 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
880
881 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
882
883 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
884
885 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
886
887 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
888
889 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
890
891 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
892
893 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
894
895 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
896 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
897
898 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
899 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
900
901 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
902 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
903
904 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
905 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
906
907 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
908 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
909
910 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
911 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
912
913 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
914 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
915
916 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
917 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
918
919 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
920
921 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
922 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
923
924 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
925
926 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
927
928 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
929
930 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
931
932 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
933 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
934
935 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
936
937 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
938 ((SIZE) == FSMC_PAGE_SIZE_128) || \
939 ((SIZE) == FSMC_PAGE_SIZE_256) || \
940 ((SIZE) == FSMC_PAGE_SIZE_512) || \
941 ((SIZE) == FSMC_PAGE_SIZE_1024))
942
943 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
944 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
945
946 /**
947 * @}
948 */
949 /**
950 * @}
951 */
952
953 /* Private functions ---------------------------------------------------------*/
954 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
955 * @{
956 */
957
958 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
959 * @{
960 */
961
962 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
963 * @{
964 */
965 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
966 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
967 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
968 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
969 /**
970 * @}
971 */
972
973 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
974 * @{
975 */
976 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
977 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
978 /**
979 * @}
980 */
981 /**
982 * @}
983 */
984
985 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
986 /** @defgroup FSMC_LL_NAND NAND
987 * @{
988 */
989 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
990 * @{
991 */
992 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
993 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
994 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
995 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
996 /**
997 * @}
998 */
999
1000 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1001 * @{
1002 */
1003 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1004 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1005 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1006 /**
1007 * @}
1008 */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup FSMC_LL_PCCARD PCCARD
1014 * @{
1015 */
1016 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
1017 * @{
1018 */
1019 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
1020 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1021 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1022 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1023 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1024 /**
1025 * @}
1026 */
1027 /**
1028 * @}
1029 */
1030 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
1031
1032 /**
1033 * @}
1034 */
1035 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /**
1042 * @}
1043 */
1044
1045 #ifdef __cplusplus
1046 }
1047 #endif
1048
1049 #endif /* __STM32F4xx_LL_FSMC_H */
1050
1051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/