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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_dfsdm.h
blob585efa6180c4e55e7037878e367cb0a53f60ce1d
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_dfsdm.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 20-May-2016
7 * @brief This file contains all the functions prototypes for the DFSDM
8 * firmware library
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
13 *
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
17 *
18 * http://www.st.com/software_license_agreement_liberty_v2
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************
27 */
28
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4XX_DFSDM_H
31 #define __STM32F4XX_DFSDM_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 #if defined(STM32F412xG)
38 /* Includes ------------------------------------------------------------------*/
39 #include "stm32f4xx.h"
40
41 /** @addtogroup STM32F4xx_StdPeriph_Driver
42 * @{
43 */
44
45 /** @addtogroup DFSDM
46 * @{
47 */
48
49 /* Exported types ------------------------------------------------------------*/
50
51 /**
52 * @brief DFSDM Transceiver init structure definition
53 */
54 typedef struct
55 {
56 uint32_t DFSDM_Interface; /*!< Selects the serial interface type and input clock phase.
57 This parameter can be a value of @ref DFSDM_Interface_Selection */
58
59 uint32_t DFSDM_Clock; /*!< Specifies the clock source for the serial interface transceiver.
60 This parameter can be a value of @ref DFSDM_Clock_Selection */
61
62 uint32_t DFSDM_Input; /*!< Specifies the Input mode for the serial interface transceiver.
63 This parameter can be a value of @ref DFSDM_Input_Selection */
64
65 uint32_t DFSDM_Redirection; /*!< Specifies if the channel input is redirected from channel channel (y+1).
66 This parameter can be a value of @ref DFSDM_Redirection_Selection */
67
68 uint32_t DFSDM_PackingMode; /*!< Specifies the packing mode for the serial interface transceiver.
69 This parameter can be a value of @ref DFSDM_Pack_Selection */
70
71 uint32_t DFSDM_DataRightShift; /*!< Defines the final data right bit shift.
72 This parameter can be a value between 0 and 31 */
73
74 uint32_t DFSDM_Offset; /*!< Sets the calibration offset.
75 This parameter can be a value between 0 and 0xFFFFFF */
76
77 uint32_t DFSDM_CLKAbsenceDetector; /*!< Enables or disables the Clock Absence Detector.
78 This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */
79
80 uint32_t DFSDM_ShortCircuitDetector; /*!< Enables or disables the Short Circuit Detector.
81 This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */
82 }DFSDM_TransceiverInitTypeDef;
83
84 /**
85 * @brief DFSDM filter analog parameters structure definition
86 */
87 typedef struct
88 {
89 uint32_t DFSDM_SincOrder; /*!< Sets the Sinc Filter Order .
90 This parameter can be a value of @ref DFSDM_Sinc_Order */
91
92 uint32_t DFSDM_FilterOversamplingRatio; /*!< Sets the Sinc Filter Oversampling Ratio.
93 This parameter can be a value between 1 and 1024 */
94
95 uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio.
96 This parameter can be a value between 1 and 256 */
97 }DFSDM_FilterInitTypeDef;
98
99 /* Exported constants --------------------------------------------------------*/
100 /** @defgroup DFSDM_Interface_Selection
101 * @{
102 */
103 #define DFSDM_Interface_SPI_RisingEdge ((uint32_t)0x00000000) /*!< DFSDM SPI interface with rising edge to strobe data */
104 #define DFSDM_Interface_SPI_FallingEdge ((uint32_t)0x00000001) /*!< DFSDM SPI interface with falling edge to strobe data */
105 #define DFSDM_Interface_Manchester1 ((uint32_t)0x00000002) /*!< DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */
106 #define DFSDM_Interface_Manchester2 ((uint32_t)0x00000003) /*!< DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */
107
108 #define IS_DFSDM_INTERFACE(INTERFACE) (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \
109 ((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \
110 ((INTERFACE) == DFSDM_Interface_Manchester1) || \
111 ((INTERFACE) == DFSDM_Interface_Manchester2))
112 /**
113 * @}
114 */
115
116 /** @defgroup DFSDM_Clock_Selection
117 * @{
118 */
119 #define DFSDM_Clock_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
120 #define DFSDM_Clock_Internal ((uint32_t)0x00000004) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
121 #define DFSDM_Clock_InternalDiv2_Mode1 ((uint32_t)0x00000008) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
122 and clock change is on every rising edge of DFSDM_CKOUT output signal */
123 #define DFSDM_Clock_InternalDiv2_Mode2 ((uint32_t)0x0000000C) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
124 and clock change is on every falling edge of DFSDM_CKOUT output signal */
125
126 #define IS_DFSDM_CLOCK(CLOCK) (((CLOCK) == DFSDM_Clock_External) || \
127 ((CLOCK) == DFSDM_Clock_Internal) || \
128 ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \
129 ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2))
130 /**
131 * @}
132 */
133
134 /** @defgroup DFSDM_Input_Selection
135 * @{
136 */
137 #define DFSDM_Input_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
138 #define DFSDM_Input_ADC ((uint32_t)0x00001000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
139 #define DFSDM_Input_Internal ((uint32_t)0x00002000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
140 and clock change is on every rising edge of DFSDM_CKOUT output signal */
141
142 #define IS_DFSDM_Input_MODE(INPUT) (((INPUT) == DFSDM_Input_External) || \
143 ((INPUT) == DFSDM_Input_ADC) || \
144 ((INPUT) == DFSDM_Input_Internal))
145 /**
146 * @}
147 */
148
149 /** @defgroup DFSDM_Redirection_Selection
150 * @{
151 */
152 #define DFSDM_Redirection_Disabled ((uint32_t)0x00000000) /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */
153 #define DFSDM_Redirection_Enabled DFSDM_CHCFGR1_CHINSEL /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */
154
155 #define IS_DFSDM_Redirection_STATE(STATE) (((STATE) == DFSDM_Redirection_Disabled) || \
156 ((STATE) == DFSDM_Redirection_Enabled))
157 /**
158 * @}
159 */
160
161 /** @defgroup DFSDM_Pack_Selection
162 * @{
163 */
164 #define DFSDM_PackingMode_Standard ((uint32_t)0x00000000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */
165 #define DFSDM_PackingMode_Interleaved ((uint32_t)0x00004000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
166 - first sample in INDAT0[15:0] - assigned to channel y
167 - second sample INDAT1[15:0] - assigned to channel y */
168 #define DFSDM_PackingMode_Dual ((uint32_t)0x00008000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
169 - first sample INDAT0[15:0] - assigned to channel y
170 - second sample INDAT1[15:0] - assigned to channel (y+1) */
171
172 #define IS_DFSDM_PACK_MODE(MODE) (((MODE) == DFSDM_PackingMode_Standard) || \
173 ((MODE) == DFSDM_PackingMode_Interleaved) || \
174 ((MODE) == DFSDM_PackingMode_Dual))
175 /**
176 * @}
177 */
178
179 /** @defgroup DFSDM_Clock_Absence_Detector_state
180 * @{
181 */
182 #define DFSDM_CLKAbsenceDetector_Enable DFSDM_CHCFGR1_CKABEN /*!< DFSDM Clock Absence Detector is Enabled */
183 #define DFSDM_CLKAbsenceDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Clock Absence Detector is Disabled */
184
185 #define IS_DFSDM_CLK_DETECTOR_STATE(STATE) (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \
186 ((STATE) == DFSDM_CLKAbsenceDetector_Disable))
187 /**
188 * @}
189 */
190
191 /** @defgroup DFSDM_Short_Circuit_Detector_state
192 * @{
193 */
194 #define DFSDM_ShortCircuitDetector_Enable DFSDM_CHCFGR1_SCDEN /*!< DFSDM Short Circuit Detector is Enabled */
195 #define DFSDM_ShortCircuitDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Short Circuit Detector is Disabled */
196
197 #define IS_DFSDM_SC_DETECTOR_STATE(STATE) (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \
198 ((STATE) == DFSDM_ShortCircuitDetector_Disable))
199 /**
200 * @}
201 */
202
203 /** @defgroup DFSDM_Sinc_Order
204 * @{
205 */
206 #define DFSDM_SincOrder_FastSinc ((uint32_t)0x00000000) /*!< DFSDM Sinc filter order = Fast sinc */
207 #define DFSDM_SincOrder_Sinc1 ((uint32_t)0x20000000) /*!< DFSDM Sinc filter order = 1 */
208 #define DFSDM_SincOrder_Sinc2 ((uint32_t)0x40000000) /*!< DFSDM Sinc filter order = 2 */
209 #define DFSDM_SincOrder_Sinc3 ((uint32_t)0x60000000) /*!< DFSDM Sinc filter order = 3 */
210 #define DFSDM_SincOrder_Sinc4 ((uint32_t)0x80000000) /*!< DFSDM Sinc filter order = 4 */
211 #define DFSDM_SincOrder_Sinc5 ((uint32_t)0xA0000000) /*!< DFSDM Sinc filter order = 5 */
212
213 #define IS_DFSDM_SINC_ORDER(ORDER) (((ORDER) == DFSDM_SincOrder_FastSinc) || \
214 ((ORDER) == DFSDM_SincOrder_Sinc1) || \
215 ((ORDER) == DFSDM_SincOrder_Sinc2) || \
216 ((ORDER) == DFSDM_SincOrder_Sinc3) || \
217 ((ORDER) == DFSDM_SincOrder_Sinc4) || \
218 ((ORDER) == DFSDM_SincOrder_Sinc5))
219 /**
220 * @}
221 */
222
223 /** @defgroup DFSDM_Break_Signal_Assignment
224 * @{
225 */
226 #define DFSDM_SCDBreak_0 ((uint32_t)0x00001000) /*!< DFSDM Break 0 signal assigned to short circuit detector */
227 #define DFSDM_SCDBreak_1 ((uint32_t)0x00002000) /*!< DFSDM Break 1 signal assigned to short circuit detector */
228 #define DFSDM_SCDBreak_2 ((uint32_t)0x00004000) /*!< DFSDM Break 2 signal assigned to short circuit detector */
229 #define DFSDM_SCDBreak_3 ((uint32_t)0x00008000) /*!< DFSDM Break 3 signal assigned to short circuit detector */
230
231 #define IS_DFSDM_SCD_BREAK_SIGNAL(RANK) (((RANK) == DFSDM_SCDBreak_0) || \
232 ((RANK) == DFSDM_SCDBreak_1) || \
233 ((RANK) == DFSDM_SCDBreak_2) || \
234 ((RANK) == DFSDM_SCDBreak_3))
235 /**
236 * @}
237 */
238
239 /** @defgroup DFSDM_AWD_Sinc_Order
240 * @{
241 */
242 #define DFSDM_AWDSincOrder_Fast ((uint32_t)0x00000000) /*!< DFSDM Fast sinc filter */
243 #define DFSDM_AWDSincOrder_Sinc1 ((uint32_t)0x00400000) /*!< DFSDM sinc1 filter */
244 #define DFSDM_AWDSincOrder_Sinc2 ((uint32_t)0x00800000) /*!< DFSDM sinc2 filter */
245 #define DFSDM_AWDSincOrder_Sinc3 ((uint32_t)0x00C00000) /*!< DFSDM sinc3 filter */
246
247 #define IS_DFSDM_AWD_SINC_ORDER(ORDER) (((ORDER) == DFSDM_AWDSincOrder_Fast) || \
248 ((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \
249 ((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \
250 ((ORDER) == DFSDM_AWDSincOrder_Sinc3))
251 /**
252 * @}
253 */
254
255 /** @defgroup DFSDM_AWD_CHANNEL
256 * @{
257 */
258 #define DFSDM_AWDChannel0 ((uint32_t)0x00010000) /*!< DFSDM AWDx guard channel 0 */
259 #define DFSDM_AWDChannel1 ((uint32_t)0x00020000) /*!< DFSDM AWDx guard channel 1 */
260 #define DFSDM_AWDChannel2 ((uint32_t)0x00040000) /*!< DFSDM AWDx guard channel 2 */
261 #define DFSDM_AWDChannel3 ((uint32_t)0x00080000) /*!< DFSDM AWDx guard channel 3 */
262 #define DFSDM_AWDChannel4 ((uint32_t)0x00100000) /*!< DFSDM AWDx guard channel 4 */
263 #define DFSDM_AWDChannel5 ((uint32_t)0x00200000) /*!< DFSDM AWDx guard channel 5 */
264 #define DFSDM_AWDChannel6 ((uint32_t)0x00400000) /*!< DFSDM AWDx guard channel 6 */
265 #define DFSDM_AWDChannel7 ((uint32_t)0x00800000) /*!< DFSDM AWDx guard channel 7 */
266
267 #define IS_DFSDM_AWD_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_AWDChannel0) || \
268 ((CHANNEL) == DFSDM_AWDChannel1) || \
269 ((CHANNEL) == DFSDM_AWDChannel2) || \
270 ((CHANNEL) == DFSDM_AWDChannel3) || \
271 ((CHANNEL) == DFSDM_AWDChannel4) || \
272 ((CHANNEL) == DFSDM_AWDChannel5) || \
273 ((CHANNEL) == DFSDM_AWDChannel6) || \
274 ((CHANNEL) == DFSDM_AWDChannel7))
275 /**
276 * @}
277 */
278
279 /** @defgroup DFSDM_Threshold_Selection
280 * @{
281 */
282 #define DFSDM_Threshold_Low ((uint8_t)0x00) /*!< DFSDM Low threshold */
283 #define DFSDM_Threshold_High ((uint8_t)0x08) /*!< DFSDM High threshold */
284
285 #define IS_DFSDM_Threshold(THR) (((THR) == DFSDM_Threshold_Low) || \
286 ((THR) == DFSDM_Threshold_High))
287 /**
288 * @}
289 */
290
291 /** @defgroup DFSDM_AWD_Fast_Mode_Selection
292 * @{
293 */
294 #define DFSDM_AWDFastMode_Disable ((uint32_t)0x00000000) /*!< DFSDM Fast mode for AWD is disabled */
295 #define DFSDM_AWDFastMode_Enable ((uint32_t)0x40000000) /*!< DFSDM Fast mode for AWD is enabled */
296
297 #define IS_DFSDM_AWD_MODE(MODE) (((MODE) == DFSDM_AWDFastMode_Disable) || \
298 ((MODE) == DFSDM_AWDFastMode_Enable))
299 /**
300 * @}
301 */
302
303 /** @defgroup DFSDM_Clock_Output_Source_Selection
304 * @{
305 */
306 #define DFSDM_ClkOutSource_SysClock ((uint32_t)0x00000000) /*!< DFSDM Source for output clock is comming from system clock */
307 #define DFSDM_ClkOutSource_AudioClock DFSDM_CHCFGR1_CKOUTSRC /*!< DFSDM Source for output clock is comming from audio clock */
308
309 #define IS_DFSDM_CLOCK_OUT_SOURCE(SRC) (((SRC) == DFSDM_ClkOutSource_SysClock) || \
310 ((SRC) == DFSDM_ClkOutSource_AudioClock))
311 /**
312 * @}
313 */
314
315 /** @defgroup DFSDM_Conversion_Mode
316 * @{
317 */
318 #define DFSDM_DMAConversionMode_Regular ((uint32_t)0x00000010) /*!< DFSDM Regular mode */
319 #define DFSDM_DMAConversionMode_Injected ((uint32_t)0x00000000) /*!< DFSDM Injected mode */
320
321 #define IS_DFSDM_CONVERSION_MODE(MODE) ((MODE) == DFSDM_DMAConversionMode_Regular || \
322 ((MODE) == DFSDM_DMAConversionMode_Injected))
323 /**
324 * @}
325 */
326
327 /** @defgroup DFSDM_Extremes_Channel_Selection
328 * @{
329 */
330 #define DFSDM_ExtremChannel0 ((uint32_t)0x00000100) /*!< DFSDM Extreme detector guard channel 0 */
331 #define DFSDM_ExtremChannel1 ((uint32_t)0x00000200) /*!< DFSDM Extreme detector guard channel 1 */
332 #define DFSDM_ExtremChannel2 ((uint32_t)0x00000400) /*!< DFSDM Extreme detector guard channel 2 */
333 #define DFSDM_ExtremChannel3 ((uint32_t)0x00000800) /*!< DFSDM Extreme detector guard channel 3 */
334 #define DFSDM_ExtremChannel4 ((uint32_t)0x00001000) /*!< DFSDM Extreme detector guard channel 4 */
335 #define DFSDM_ExtremChannel5 ((uint32_t)0x00002000) /*!< DFSDM Extreme detector guard channel 5 */
336 #define DFSDM_ExtremChannel6 ((uint32_t)0x00004000) /*!< DFSDM Extreme detector guard channel 6 */
337 #define DFSDM_ExtremChannel7 ((uint32_t)0x00008000) /*!< DFSDM Extreme detector guard channel 7 */
338
339 #define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \
340 ((CHANNEL) == DFSDM_ExtremChannel1) || \
341 ((CHANNEL) == DFSDM_ExtremChannel2) || \
342 ((CHANNEL) == DFSDM_ExtremChannel3) || \
343 ((CHANNEL) == DFSDM_ExtremChannel4) || \
344 ((CHANNEL) == DFSDM_ExtremChannel5) || \
345 ((CHANNEL) == DFSDM_ExtremChannel6) || \
346 ((CHANNEL) == DFSDM_ExtremChannel7))
347 /**
348 * @}
349 */
350
351 /** @defgroup DFSDM_Injected_Channel_Selection
352 * @{
353 */
354 #define DFSDM_InjectedChannel0 ((uint32_t)0x00000001) /*!< DFSDM channel 0 is selected as injected channel */
355 #define DFSDM_InjectedChannel1 ((uint32_t)0x00000002) /*!< DFSDM channel 1 is selected as injected channel */
356 #define DFSDM_InjectedChannel2 ((uint32_t)0x00000004) /*!< DFSDM channel 2 is selected as injected channel */
357 #define DFSDM_InjectedChannel3 ((uint32_t)0x00000008) /*!< DFSDM channel 3 is selected as injected channel */
358 #define DFSDM_InjectedChannel4 ((uint32_t)0x00000010) /*!< DFSDM channel 4 is selected as injected channel */
359 #define DFSDM_InjectedChannel5 ((uint32_t)0x00000020) /*!< DFSDM channel 5 is selected as injected channel */
360 #define DFSDM_InjectedChannel6 ((uint32_t)0x00000040) /*!< DFSDM channel 6 is selected as injected channel */
361 #define DFSDM_InjectedChannel7 ((uint32_t)0x00000080) /*!< DFSDM channel 7 is selected as injected channel */
362
363 #define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \
364 ((CHANNEL) == DFSDM_InjectedChannel1) || \
365 ((CHANNEL) == DFSDM_InjectedChannel2) || \
366 ((CHANNEL) == DFSDM_InjectedChannel3) || \
367 ((CHANNEL) == DFSDM_InjectedChannel4) || \
368 ((CHANNEL) == DFSDM_InjectedChannel5) || \
369 ((CHANNEL) == DFSDM_InjectedChannel6) || \
370 ((CHANNEL) == DFSDM_InjectedChannel7))
371 /**
372 * @}
373 */
374
375 /** @defgroup DFSDM_Regular_Channel_Selection
376 * @{
377 */
378 #define DFSDM_RegularChannel0 ((uint32_t)0x00000000) /*!< DFSDM channel 0 is selected as regular channel */
379 #define DFSDM_RegularChannel1 ((uint32_t)0x01000000) /*!< DFSDM channel 1 is selected as regular channel */
380 #define DFSDM_RegularChannel2 ((uint32_t)0x02000000) /*!< DFSDM channel 2 is selected as regular channel */
381 #define DFSDM_RegularChannel3 ((uint32_t)0x03000000) /*!< DFSDM channel 3 is selected as regular channel */
382 #define DFSDM_RegularChannel4 ((uint32_t)0x04000000) /*!< DFSDM channel 4 is selected as regular channel */
383 #define DFSDM_RegularChannel5 ((uint32_t)0x05000000) /*!< DFSDM channel 5 is selected as regular channel */
384 #define DFSDM_RegularChannel6 ((uint32_t)0x06000000) /*!< DFSDM channel 6 is selected as regular channel */
385 #define DFSDM_RegularChannel7 ((uint32_t)0x07000000) /*!< DFSDM channel 7 is selected as regular channel */
386
387 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \
388 ((CHANNEL) == DFSDM_RegularChannel1) || \
389 ((CHANNEL) == DFSDM_RegularChannel2) || \
390 ((CHANNEL) == DFSDM_RegularChannel3) || \
391 ((CHANNEL) == DFSDM_RegularChannel4) || \
392 ((CHANNEL) == DFSDM_RegularChannel5) || \
393 ((CHANNEL) == DFSDM_RegularChannel6) || \
394 ((CHANNEL) == DFSDM_RegularChannel7))
395 /**
396 * @}
397 */
398
399 /** @defgroup DFSDM_Injected_Trigger_signal
400 * @{
401 */
402 #define DFSDM_Trigger_TIM1_TRGO ((uint32_t)0x00000000) /*!< DFSDM Internal trigger 0 */
403 #define DFSDM_Trigger_TIM1_TRGO2 ((uint32_t)0x00000100) /*!< DFSDM Internal trigger 1 */
404 #define DFSDM_Trigger_TIM8_TRGO ((uint32_t)0x00000200) /*!< DFSDM Internal trigger 2 */
405 #define DFSDM_Trigger_TIM8_TRGO2 ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 3 */
406 #define DFSDM_Trigger_TIM3_TRGO ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 4 */
407 #define DFSDM_Trigger_TIM4_TRGO ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 5 */
408 #define DFSDM_Trigger_TIM16_OC1 ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 6 */
409 #define DFSDM_Trigger_TIM6_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 7 */
410 #define DFSDM_Trigger_TIM7_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 8 */
411 #define DFSDM_Trigger_EXTI11 ((uint32_t)0x00000600) /*!< DFSDM External trigger 0 */
412 #define DFSDM_Trigger_EXTI15 ((uint32_t)0x00000700) /*!< DFSDM External trigger 1 */
413
414 #define IS_DFSDM0_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \
415 ((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \
416 ((TRIG) == DFSDM_Trigger_TIM8_TRGO) || \
417 ((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \
418 ((TRIG) == DFSDM_Trigger_TIM4_TRGO) || \
419 ((TRIG) == DFSDM_Trigger_TIM6_TRGO) || \
420 ((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \
421 ((TRIG) == DFSDM_Trigger_EXTI15))
422
423 #define IS_DFSDM1_INJ_TRIGGER(TRIG) IS_DFSDM0_INJ_TRIGGER(TRIG)
424 /**
425 * @}
426 */
427
428 /** @defgroup DFSDM_Trigger_Edge_selection
429 * @{
430 */
431 #define DFSDM_TriggerEdge_Disabled ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
432 #define DFSDM_TriggerEdge_Rising ((uint32_t)0x00002000) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
433 #define DFSDM_TriggerEdge_Falling ((uint32_t)0x00004000) /*!< DFSDM Each falling edge makes a request to launch an injected conversion */
434 #define DFSDM_TriggerEdge_BothEdges ((uint32_t)0x00006000) /*!< DFSDM Both edges make a request to launch an injected conversion */
435
436 #define IS_DFSDM_TRIGGER_EDGE(EDGE) (((EDGE) == DFSDM_TriggerEdge_Disabled) || \
437 ((EDGE) == DFSDM_TriggerEdge_Rising) || \
438 ((EDGE) == DFSDM_TriggerEdge_Falling) || \
439 ((EDGE) == DFSDM_TriggerEdge_BothEdges))
440 /**
441 * @}
442 */
443
444 /** @defgroup DFSDM_Injected_Conversion_Mode_Selection
445 * @{
446 */
447 #define DFSDM_InjectConvMode_Single ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
448 #define DFSDM_InjectConvMode_Scan ((uint32_t)0x00000010) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
449
450 #define IS_DFSDM_INJ_CONV_MODE(MODE) (((MODE) == DFSDM_InjectConvMode_Single) || \
451 ((MODE) == DFSDM_InjectConvMode_Scan))
452 /**
453 * @}
454 */
455
456 /** @defgroup DFSDM_Interrupts_Definition
457 * @{
458 */
459 #define DFSDM_IT_JEOC DFSDM_FLTCR2_JEOCIE
460 #define DFSDM_IT_REOC DFSDM_FLTCR2_REOCIE
461 #define DFSDM_IT_JOVR DFSDM_FLTCR2_JOVRIE
462 #define DFSDM_IT_ROVR DFSDM_FLTCR2_ROVRIE
463 #define DFSDM_IT_AWD DFSDM_FLTCR2_AWDIE
464 #define DFSDM_IT_SCD DFSDM_FLTCR2_SCDIE
465 #define DFSDM_IT_CKAB DFSDM_FLTCR2_CKABIE
466
467 #define IS_DFSDM_IT(IT) (((IT) == DFSDM_IT_JEOC) || \
468 ((IT) == DFSDM_IT_REOC) || \
469 ((IT) == DFSDM_IT_JOVR) || \
470 ((IT) == DFSDM_IT_ROVR) || \
471 ((IT) == DFSDM_IT_AWD) || \
472 ((IT) == DFSDM_IT_SCD) || \
473 ((IT) == DFSDM_IT_CKAB))
474 /**
475 * @}
476 */
477
478 /** @defgroup DFSDM_Flag_Definition
479 * @{
480 */
481 #define DFSDM_FLAG_JEOC DFSDM_FLTISR_JEOCF
482 #define DFSDM_FLAG_REOC DFSDM_FLTISR_REOCF
483 #define DFSDM_FLAG_JOVR DFSDM_FLTISR_JOVRF
484 #define DFSDM_FLAG_ROVR DFSDM_FLTISR_ROVRF
485 #define DFSDM_FLAG_AWD DFSDM_FLTISR_AWDF
486 #define DFSDM_FLAG_JCIP DFSDM_FLTISR_JCIP
487 #define DFSDM_FLAG_RCIP DFSDM_FLTISR_RCIP
488
489 #define IS_DFSDM_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_JEOC) || \
490 ((FLAG) == DFSDM_FLAG_REOC) || \
491 ((FLAG) == DFSDM_FLAG_JOVR) || \
492 ((FLAG) == DFSDM_FLAG_ROVR) || \
493 ((FLAG) == DFSDM_FLAG_AWD) || \
494 ((FLAG) == DFSDM_FLAG_JCIP) || \
495 ((FLAG) == DFSDM_FLAG_RCIP))
496 /**
497 * @}
498 */
499
500 /** @defgroup DFSDM_Clock_Absence_Flag_Definition
501 * @{
502 */
503 #define DFSDM_FLAG_CLKAbsence_Channel0 ((uint32_t)0x00010000)
504 #define DFSDM_FLAG_CLKAbsence_Channel1 ((uint32_t)0x00020000)
505 #define DFSDM_FLAG_CLKAbsence_Channel2 ((uint32_t)0x00040000)
506 #define DFSDM_FLAG_CLKAbsence_Channel3 ((uint32_t)0x00080000)
507 #define DFSDM_FLAG_CLKAbsence_Channel4 ((uint32_t)0x00100000)
508 #define DFSDM_FLAG_CLKAbsence_Channel5 ((uint32_t)0x00200000)
509 #define DFSDM_FLAG_CLKAbsence_Channel6 ((uint32_t)0x00400000)
510 #define DFSDM_FLAG_CLKAbsence_Channel7 ((uint32_t)0x00800000)
511
512 #define IS_DFSDM_CLK_ABS_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \
513 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \
514 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \
515 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \
516 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \
517 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \
518 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \
519 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7))
520 /**
521 * @}
522 */
523
524 /** @defgroup DFSDM_SCD_Flag_Definition
525 * @{
526 */
527 #define DFSDM_FLAG_SCD_Channel0 ((uint32_t)0x01000000)
528 #define DFSDM_FLAG_SCD_Channel1 ((uint32_t)0x02000000)
529 #define DFSDM_FLAG_SCD_Channel2 ((uint32_t)0x04000000)
530 #define DFSDM_FLAG_SCD_Channel3 ((uint32_t)0x08000000)
531 #define DFSDM_FLAG_SCD_Channel4 ((uint32_t)0x10000000)
532 #define DFSDM_FLAG_SCD_Channel5 ((uint32_t)0x20000000)
533 #define DFSDM_FLAG_SCD_Channel6 ((uint32_t)0x40000000)
534 #define DFSDM_FLAG_SCD_Channel7 ((uint32_t)0x80000000)
535
536 #define IS_DFSDM_SCD_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \
537 ((FLAG) == DFSDM_FLAG_SCD_Channel1) || \
538 ((FLAG) == DFSDM_FLAG_SCD_Channel2) || \
539 ((FLAG) == DFSDM_FLAG_SCD_Channel3) || \
540 ((FLAG) == DFSDM_FLAG_SCD_Channel4) || \
541 ((FLAG) == DFSDM_FLAG_SCD_Channel5) || \
542 ((FLAG) == DFSDM_FLAG_SCD_Channel6) || \
543 ((FLAG) == DFSDM_FLAG_SCD_Channel7))
544 /**
545 * @}
546 */
547
548 /** @defgroup DFSDM_Clear_Flag_Definition
549 * @{
550 */
551 #define DFSDM_CLEARF_JOVR DFSDM_FLTICR_CLRJOVRF
552 #define DFSDM_CLEARF_ROVR DFSDM_FLTICR_CLRROVRF
553
554 #define IS_DFSDM_CLEAR_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_JOVR) || \
555 ((FLAG) == DFSDM_CLEARF_ROVR))
556 /**
557 * @}
558 */
559
560 /** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition
561 * @{
562 */
563 #define DFSDM_CLEARF_CLKAbsence_Channel0 ((uint32_t)0x00010000)
564 #define DFSDM_CLEARF_CLKAbsence_Channel1 ((uint32_t)0x00020000)
565 #define DFSDM_CLEARF_CLKAbsence_Channel2 ((uint32_t)0x00040000)
566 #define DFSDM_CLEARF_CLKAbsence_Channel3 ((uint32_t)0x00080000)
567 #define DFSDM_CLEARF_CLKAbsence_Channel4 ((uint32_t)0x00100000)
568 #define DFSDM_CLEARF_CLKAbsence_Channel5 ((uint32_t)0x00200000)
569 #define DFSDM_CLEARF_CLKAbsence_Channel6 ((uint32_t)0x00400000)
570 #define DFSDM_CLEARF_CLKAbsence_Channel7 ((uint32_t)0x00800000)
571
572 #define IS_DFSDM_CLK_ABS_CLEARF(FLAG) (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \
573 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \
574 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \
575 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \
576 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \
577 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \
578 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \
579 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7))
580 /**
581 * @}
582 */
583
584 /** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition
585 * @{
586 */
587 #define DFSDM_CLEARF_SCD_Channel0 ((uint32_t)0x01000000)
588 #define DFSDM_CLEARF_SCD_Channel1 ((uint32_t)0x02000000)
589 #define DFSDM_CLEARF_SCD_Channel2 ((uint32_t)0x04000000)
590 #define DFSDM_CLEARF_SCD_Channel3 ((uint32_t)0x08000000)
591 #define DFSDM_CLEARF_SCD_Channel4 ((uint32_t)0x10000000)
592 #define DFSDM_CLEARF_SCD_Channel5 ((uint32_t)0x20000000)
593 #define DFSDM_CLEARF_SCD_Channel6 ((uint32_t)0x40000000)
594 #define DFSDM_CLEARF_SCD_Channel7 ((uint32_t)0x80000000)
595
596 #define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \
597 ((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \
598 ((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \
599 ((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \
600 ((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \
601 ((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \
602 ((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \
603 ((FLAG) == DFSDM_CLEARF_SCD_Channel7))
604 /**
605 * @}
606 */
607
608 /** @defgroup DFSDM_Clock_Absence_Interrupt_Definition
609 * @{
610 */
611 #define DFSDM_IT_CLKAbsence_Channel0 ((uint32_t)0x00010000)
612 #define DFSDM_IT_CLKAbsence_Channel1 ((uint32_t)0x00020000)
613 #define DFSDM_IT_CLKAbsence_Channel2 ((uint32_t)0x00040000)
614 #define DFSDM_IT_CLKAbsence_Channel3 ((uint32_t)0x00080000)
615 #define DFSDM_IT_CLKAbsence_Channel4 ((uint32_t)0x00100000)
616 #define DFSDM_IT_CLKAbsence_Channel5 ((uint32_t)0x00200000)
617 #define DFSDM_IT_CLKAbsence_Channel6 ((uint32_t)0x00400000)
618 #define DFSDM_IT_CLKAbsence_Channel7 ((uint32_t)0x00800000)
619
620 #define IS_DFSDM_CLK_ABS_IT(IT) (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \
621 ((IT) == DFSDM_IT_CLKAbsence_Channel1) || \
622 ((IT) == DFSDM_IT_CLKAbsence_Channel2) || \
623 ((IT) == DFSDM_IT_CLKAbsence_Channel3) || \
624 ((IT) == DFSDM_IT_CLKAbsence_Channel4) || \
625 ((IT) == DFSDM_IT_CLKAbsence_Channel5) || \
626 ((IT) == DFSDM_IT_CLKAbsence_Channel6) || \
627 ((IT) == DFSDM_IT_CLKAbsence_Channel7))
628 /**
629 * @}
630 */
631
632 /** @defgroup DFSDM_SCD_Interrupt_Definition
633 * @{
634 */
635 #define DFSDM_IT_SCD_Channel0 ((uint32_t)0x01000000)
636 #define DFSDM_IT_SCD_Channel1 ((uint32_t)0x02000000)
637 #define DFSDM_IT_SCD_Channel2 ((uint32_t)0x04000000)
638 #define DFSDM_IT_SCD_Channel3 ((uint32_t)0x08000000)
639 #define DFSDM_IT_SCD_Channel4 ((uint32_t)0x10000000)
640 #define DFSDM_IT_SCD_Channel5 ((uint32_t)0x20000000)
641 #define DFSDM_IT_SCD_Channel6 ((uint32_t)0x40000000)
642 #define DFSDM_IT_SCD_Channel7 ((uint32_t)0x80000000)
643
644 #define IS_DFSDM_SCD_IT(IT) (((IT) == DFSDM_IT_SCD_Channel0) || \
645 ((IT) == DFSDM_IT_SCD_Channel1) || \
646 ((IT) == DFSDM_IT_SCD_Channel2) || \
647 ((IT) == DFSDM_IT_SCD_Channel3) || \
648 ((IT) == DFSDM_IT_SCD_Channel4) || \
649 ((IT) == DFSDM_IT_SCD_Channel5) || \
650 ((IT) == DFSDM_IT_SCD_Channel6) || \
651 ((IT) == DFSDM_IT_SCD_Channel7))
652 /**
653 * @}
654 */
655
656 #define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT) (SHIFT < 0x20 )
657
658 #define IS_DFSDM_OFFSET(OFFSET) (OFFSET < 0x01000000 )
659
660 #define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \
661 ((CHANNEL) == DFSDM1_Channel1) || \
662 ((CHANNEL) == DFSDM1_Channel2) || \
663 ((CHANNEL) == DFSDM1_Channel3))
664
665 #define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM0) || \
666 ((FILTER) == DFSDM1))
667
668 #define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1))
669
670 #define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO) ( RATIO < 0x401 ) & ( RATIO >= 0x001 )
671
672 #define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO) ( RATIO < 0x101 ) & ( RATIO >= 0x001 )
673
674 #define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ( DIVIDER < 0x101 )
675
676 #define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ( VALUE < 256 )
677
678 #define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO) ( RATIO < 33 ) & ( RATIO >= 0x001 )
679
680 #define IS_DFSDM_HIGH_THRESHOLD(VALUE) (VALUE < 0x1000000 )
681 #define IS_DFSDM_LOW_THRESHOLD(VALUE) (VALUE < 0x1000000 )
682 /**
683 * @}
684 */
685
686 /* Exported macro ------------------------------------------------------------*/
687 /* Exported functions ------------------------------------------------------- */
688
689 /* Initialization functions ***************************************************/
690 void DFSDM_DeInit(void);
691 void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
692 void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
693 void DFSDM_FilterInit(DFSDM_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
694 void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
695
696 /* Configuration functions ****************************************************/
697 void DFSDM_Cmd(FunctionalState NewState);
698 void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState);
699 void DFSDM_FilterCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
700 void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision);
701 void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource);
702 void DFSDM_SelectInjectedConversionMode(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode);
703 void DFSDM_SelectInjectedChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx);
704 void DFSDM_SelectRegularChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx);
705 void DFSDM_StartSoftwareInjectedConversion(DFSDM_TypeDef* DFSDMx);
706 void DFSDM_StartSoftwareRegularConversion(DFSDM_TypeDef* DFSDMx);
707 void DFSDM_SynchronousFilter0InjectedStart(DFSDM_TypeDef* DFSDMx);
708 void DFSDM_SynchronousFilter0RegularStart(DFSDM_TypeDef* DFSDMx);
709 void DFSDM_RegularContinuousModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
710 void DFSDM_InjectedContinuousModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
711 void DFSDM_FastModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
712 void DFSDM_ConfigInjectedTrigger(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge);
713 void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
714 void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
715 void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold);
716 void DFSDM_ConfigAnalogWatchdog(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode);
717 void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t AWD_SincOrder, uint32_t AWD_SincOverSampleRatio);
718 uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx);
719 void DFSDM_SetAWDThreshold(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold);
720 void DFSDM_SelectExtremesDetectorChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx);
721 int32_t DFSDM_GetRegularConversionData(DFSDM_TypeDef* DFSDMx);
722 int32_t DFSDM_GetInjectedConversionData(DFSDM_TypeDef* DFSDMx);
723 int32_t DFSDM_GetMaxValue(DFSDM_TypeDef* DFSDMx);
724 int32_t DFSDM_GetMinValue(DFSDM_TypeDef* DFSDMx);
725 int32_t DFSDM_GetMaxValueChannel(DFSDM_TypeDef* DFSDMx);
726 int32_t DFSDM_GetMinValueChannel(DFSDM_TypeDef* DFSDMx);
727 uint32_t DFSDM_GetConversionTime(DFSDM_TypeDef* DFSDMx);
728 void DFSDM_DMATransferConfig(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState);
729 /* Interrupts and flags management functions **********************************/
730 void DFSDM_ITConfig(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState);
731 void DFSDM_ITClockAbsenceCmd(FunctionalState NewState);
732 void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState);
733
734 FlagStatus DFSDM_GetFlagStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_FLAG);
735 FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence);
736 FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD);
737 FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
738
739 void DFSDM_ClearFlag(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF);
740 void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence);
741 void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD);
742 void DFSDM_ClearAnalogWatchdogFlag(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
743
744 ITStatus DFSDM_GetITStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_IT);
745 ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence);
746 ITStatus DFSDM_GetGetShortCircuitITStatus(uint32_t DFSDM_IT_SCR);
747
748 #endif /* STM32F412xG */
749
750 #ifdef __cplusplus
751 }
752 #endif
753
754 #endif /*__STM32F4XX_DFSDM_H */
755
756 /**
757 * @}
758 */
759
760 /**
761 * @}
762 */
763
764 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/