?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_dsi.h
blob5755b32d2cd46a48c7d5e45ca15a16a4577ed997
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_dsi.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 20-May-2016
7 * @brief Header file of DSI module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
12 *
13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 * You may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at:
16 *
17 * http://www.st.com/software_license_agreement_liberty_v2
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *
25 ******************************************************************************
26 */
27
28 /* Define to prevent recursive inclusion -------------------------------------*/
29 #ifndef __STM32F4xx_DSI_H
30 #define __STM32F4xx_DSI_H
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f4xx.h"
38
39 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @{
41 */
42
43 /** @defgroup DSI
44 * @{
45 */
46 #if defined(STM32F469_479xx)
47 /* Exported types ------------------------------------------------------------*/
48 /**
49 * @brief DSI Init Structure definition
50 */
51 typedef struct
52 {
53 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
54 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
55
56 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
57 The values 0 and 1 stop the TX_ESC clock generation */
58
59 uint32_t NumberOfLanes; /*!< Number of lanes
60 This parameter can be any value of @ref DSI_Number_Of_Lanes */
61
62 }DSI_InitTypeDef;
63
64 /**
65 * @brief DSI PLL Clock structure definition
66 */
67 typedef struct
68 {
69 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
70 This parameter must be a value between 10 and 125 */
71
72 uint32_t PLLIDF; /*!< PLL Input Division Factor
73 This parameter can be any value of @ref DSI_PLL_IDF */
74
75 uint32_t PLLODF; /*!< PLL Output Division Factor
76 This parameter can be any value of @ref DSI_PLL_ODF */
77
78 }DSI_PLLInitTypeDef;
79
80 /**
81 * @brief DSI Video mode configuration
82 */
83 typedef struct
84 {
85 uint32_t VirtualChannelID; /*!< Virtual channel ID */
86
87 uint32_t ColorCoding; /*!< Color coding for LTDC interface
88 This parameter can be any value of @ref DSI_Color_Coding */
89
90 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
91 18-bit configuration).
92 This parameter can be any value of @ref DSI_LooselyPacked */
93
94 uint32_t Mode; /*!< Video mode type
95 This parameter can be any value of @ref DSI_Video_Mode_Type */
96
97 uint32_t PacketSize; /*!< Video packet size */
98
99 uint32_t NumberOfChunks; /*!< Number of chunks */
100
101 uint32_t NullPacketSize; /*!< Null packet size */
102
103 uint32_t HSPolarity; /*!< HSYNC pin polarity
104 This parameter can be any value of @ref DSI_HSYNC_Polarity */
105
106 uint32_t VSPolarity; /*!< VSYNC pin polarity
107 This parameter can be any value of @ref DSI_VSYNC_Polarity */
108
109 uint32_t DEPolarity; /*!< Data Enable pin polarity
110 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
111
112 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
113
114 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
115
116 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
117
118 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
119
120 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
121
122 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
123
124 uint32_t VerticalActive; /*!< Vertical active duration */
125
126 uint32_t LPCommandEnable; /*!< Low-power command enable
127 This parameter can be any value of @ref DSI_LP_Command */
128
129 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
130 can fit in a line during VSA, VBP and VFP regions */
131
132 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
133 can fit in a line during VACT region */
134
135 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
136 This parameter can be any value of @ref DSI_LP_HFP */
137
138 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
139 This parameter can be any value of @ref DSI_LP_HBP */
140
141 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
142 This parameter can be any value of @ref DSI_LP_VACT */
143
144 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
145 This parameter can be any value of @ref DSI_LP_VFP */
146
147 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
148 This parameter can be any value of @ref DSI_LP_VBP */
149
150 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
151 This parameter can be any value of @ref DSI_LP_VSYNC */
152
153 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
154 This parameter can be any value of @ref DSI_FBTA_acknowledge */
155
156 }DSI_VidCfgTypeDef;
157
158 /**
159 * @brief DSI Adapted command mode configuration
160 */
161 typedef struct
162 {
163 uint32_t VirtualChannelID; /*!< Virtual channel ID */
164
165 uint32_t ColorCoding; /*!< Color coding for LTDC interface
166 This parameter can be any value of @ref DSI_Color_Coding */
167
168 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
169 pixels. This parameter can be any value between 0x00 and 0xFFFF */
170
171 uint32_t TearingEffectSource; /*!< Tearing effect source
172 This parameter can be any value of @ref DSI_TearingEffectSource */
173
174 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
175 This parameter can be any value of @ref DSI_TearingEffectPolarity */
176
177 uint32_t HSPolarity; /*!< HSYNC pin polarity
178 This parameter can be any value of @ref DSI_HSYNC_Polarity */
179
180 uint32_t VSPolarity; /*!< VSYNC pin polarity
181 This parameter can be any value of @ref DSI_VSYNC_Polarity */
182
183 uint32_t DEPolarity; /*!< Data Enable pin polarity
184 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
185
186 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
187 This parameter can be any value of @ref DSI_Vsync_Polarity */
188
189 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
190 This parameter can be any value of @ref DSI_AutomaticRefresh */
191
192 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
193 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
194
195 }DSI_CmdCfgTypeDef;
196
197 /**
198 * @brief DSI command transmission mode configuration
199 */
200 typedef struct
201 {
202 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
203 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
204
205 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
206 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
207
208 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
209 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
210
211 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
212 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
213
214 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
215 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
216
217 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
218 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
219
220 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
221 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
222
223 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
224 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
225
226 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
227 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
228
229 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
230 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
231
232 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
233 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
234
235 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
236 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
237
238 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
239 This parameter can be any value of @ref DSI_AcknowledgeRequest */
240
241 }DSI_LPCmdTypeDef;
242
243 /**
244 * @brief DSI PHY Timings definition
245 */
246 typedef struct
247 {
248 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
249 to low-power transmission */
250
251 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
252 to high-speed transmission */
253
254 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
255 to low-power transmission */
256
257 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
258 to high-speed transmission */
259
260 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
261
262 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
263 Stop state */
264
265 }DSI_PHY_TimerTypeDef;
266
267 /**
268 * @brief DSI HOST Timeouts definition
269 */
270 typedef struct
271 {
272 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
273
274 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
275
276 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
277
278 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
279
280 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
281
282 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
283
284 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
285 This parameter can be any value of @ref DSI_HS_PrespMode */
286
287 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
288
289 uint32_t BTATimeout; /*!< BTA time-out */
290
291 }DSI_HOST_TimeoutTypeDef;
292
293 /* Exported constants --------------------------------------------------------*/
294 /** @defgroup DSI_DCS_Command
295 * @{
296 */
297 #define DSI_ENTER_IDLE_MODE 0x39
298 #define DSI_ENTER_INVERT_MODE 0x21
299 #define DSI_ENTER_NORMAL_MODE 0x13
300 #define DSI_ENTER_PARTIAL_MODE 0x12
301 #define DSI_ENTER_SLEEP_MODE 0x10
302 #define DSI_EXIT_IDLE_MODE 0x38
303 #define DSI_EXIT_INVERT_MODE 0x20
304 #define DSI_EXIT_SLEEP_MODE 0x11
305 #define DSI_GET_3D_CONTROL 0x3F
306 #define DSI_GET_ADDRESS_MODE 0x0B
307 #define DSI_GET_BLUE_CHANNEL 0x08
308 #define DSI_GET_DIAGNOSTIC_RESULT 0x0F
309 #define DSI_GET_DISPLAY_MODE 0x0D
310 #define DSI_GET_GREEN_CHANNEL 0x07
311 #define DSI_GET_PIXEL_FORMAT 0x0C
312 #define DSI_GET_POWER_MODE 0x0A
313 #define DSI_GET_RED_CHANNEL 0x06
314 #define DSI_GET_SCANLINE 0x45
315 #define DSI_GET_SIGNAL_MODE 0x0E
316 #define DSI_NOP 0x00
317 #define DSI_READ_DDB_CONTINUE 0xA8
318 #define DSI_READ_DDB_START 0xA1
319 #define DSI_READ_MEMORY_CONTINUE 0x3E
320 #define DSI_READ_MEMORY_START 0x2E
321 #define DSI_SET_3D_CONTROL 0x3D
322 #define DSI_SET_ADDRESS_MODE 0x36
323 #define DSI_SET_COLUMN_ADDRESS 0x2A
324 #define DSI_SET_DISPLAY_OFF 0x28
325 #define DSI_SET_DISPLAY_ON 0x29
326 #define DSI_SET_GAMMA_CURVE 0x26
327 #define DSI_SET_PAGE_ADDRESS 0x2B
328 #define DSI_SET_PARTIAL_COLUMNS 0x31
329 #define DSI_SET_PARTIAL_ROWS 0x30
330 #define DSI_SET_PIXEL_FORMAT 0x3A
331 #define DSI_SET_SCROLL_AREA 0x33
332 #define DSI_SET_SCROLL_START 0x37
333 #define DSI_SET_TEAR_OFF 0x34
334 #define DSI_SET_TEAR_ON 0x35
335 #define DSI_SET_TEAR_SCANLINE 0x44
336 #define DSI_SET_VSYNC_TIMING 0x40
337 #define DSI_SOFT_RESET 0x01
338 #define DSI_WRITE_LUT 0x2D
339 #define DSI_WRITE_MEMORY_CONTINUE 0x3C
340 #define DSI_WRITE_MEMORY_START 0x2C
341 /**
342 * @}
343 */
344
345 /** @defgroup DSI_Video_Mode_Type
346 * @{
347 */
348 #define DSI_VID_MODE_NB_PULSES 0
349 #define DSI_VID_MODE_NB_EVENTS 1
350 #define DSI_VID_MODE_BURST 2
351 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
352 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
353 ((VideoModeType) == DSI_VID_MODE_BURST))
354 /**
355 * @}
356 */
357
358 /** @defgroup DSI_Color_Mode
359 * @{
360 */
361 #define DSI_COLOR_MODE_FULL 0
362 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
363 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
364 /**
365 * @}
366 */
367
368 /** @defgroup DSI_ShutDown
369 * @{
370 */
371 #define DSI_DISPLAY_ON 0
372 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
373 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
374 /**
375 * @}
376 */
377
378 /** @defgroup DSI_LP_Command
379 * @{
380 */
381 #define DSI_LP_COMMAND_DISABLE 0
382 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
383 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
384 /**
385 * @}
386 */
387
388 /** @defgroup DSI_LP_HFP
389 * @{
390 */
391 #define DSI_LP_HFP_DISABLE 0
392 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
393 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
394 /**
395 * @}
396 */
397
398 /** @defgroup DSI_LP_HBP
399 * @{
400 */
401 #define DSI_LP_HBP_DISABLE 0
402 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
403 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
404 /**
405 * @}
406 */
407
408 /** @defgroup DSI_LP_VACT
409 * @{
410 */
411 #define DSI_LP_VACT_DISABLE 0
412 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
413 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
414 /**
415 * @}
416 */
417
418 /** @defgroup DSI_LP_VFP
419 * @{
420 */
421 #define DSI_LP_VFP_DISABLE 0
422 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
423 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
424 /**
425 * @}
426 */
427
428 /** @defgroup DSI_LP_VBP
429 * @{
430 */
431 #define DSI_LP_VBP_DISABLE 0
432 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
433 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
434 /**
435 * @}
436 */
437
438 /** @defgroup DSI_LP_VSYNC
439 * @{
440 */
441 #define DSI_LP_VSYNC_DISABLE 0
442 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
443 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
444 /**
445 * @}
446 */
447
448 /** @defgroup DSI_FBTA_acknowledge
449 * @{
450 */
451 #define DSI_FBTAA_DISABLE 0
452 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
453 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
454 /**
455 * @}
456 */
457
458 /** @defgroup DSI_TearingEffectSource
459 * @{
460 */
461 #define DSI_TE_DSILINK 0
462 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
463 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
464 /**
465 * @}
466 */
467
468 /** @defgroup DSI_TearingEffectPolarity
469 * @{
470 */
471 #define DSI_TE_RISING_EDGE 0
472 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
473 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
474 /**
475 * @}
476 */
477
478 /** @defgroup DSI_Vsync_Polarity
479 * @{
480 */
481 #define DSI_VSYNC_FALLING 0
482 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
483 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
484 /**
485 * @}
486 */
487
488 /** @defgroup DSI_AutomaticRefresh
489 * @{
490 */
491 #define DSI_AR_DISABLE 0
492 #define DSI_AR_ENABLE DSI_WCFGR_AR
493 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
494 /**
495 * @}
496 */
497
498 /** @defgroup DSI_TE_AcknowledgeRequest
499 * @{
500 */
501 #define DSI_TE_ACKNOWLEDGE_DISABLE 0
502 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
503 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
504 /**
505 * @}
506 */
507
508 /** @defgroup DSI_AcknowledgeRequest
509 * @{
510 */
511 #define DSI_ACKNOWLEDGE_DISABLE 0
512 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
513 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
514
515 /**
516 * @}
517 */
518
519 /** @defgroup DSI_LP_LPGenShortWriteNoP
520 * @{
521 */
522 #define DSI_LP_GSW0P_DISABLE 0
523 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
524 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
525 /**
526 * @}
527 */
528
529 /** @defgroup DSI_LP_LPGenShortWriteOneP
530 * @{
531 */
532 #define DSI_LP_GSW1P_DISABLE 0
533 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
534 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
535 /**
536 * @}
537 */
538
539 /** @defgroup DSI_LP_LPGenShortWriteTwoP
540 * @{
541 */
542 #define DSI_LP_GSW2P_DISABLE 0
543 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
544 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
545 /**
546 * @}
547 */
548
549 /** @defgroup DSI_LP_LPGenShortReadNoP
550 * @{
551 */
552 #define DSI_LP_GSR0P_DISABLE 0
553 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
554 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
555 /**
556 * @}
557 */
558
559 /** @defgroup DSI_LP_LPGenShortReadOneP
560 * @{
561 */
562 #define DSI_LP_GSR1P_DISABLE 0
563 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
564 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
565 /**
566 * @}
567 */
568
569 /** @defgroup DSI_LP_LPGenShortReadTwoP
570 * @{
571 */
572 #define DSI_LP_GSR2P_DISABLE 0
573 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
574 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
575 /**
576 * @}
577 */
578
579 /** @defgroup DSI_LP_LPGenLongWrite
580 * @{
581 */
582 #define DSI_LP_GLW_DISABLE 0
583 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
584 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
585 /**
586 * @}
587 */
588
589 /** @defgroup DSI_LP_LPDcsShortWriteNoP
590 * @{
591 */
592 #define DSI_LP_DSW0P_DISABLE 0
593 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
594 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
595 /**
596 * @}
597 */
598
599 /** @defgroup DSI_LP_LPDcsShortWriteOneP
600 * @{
601 */
602 #define DSI_LP_DSW1P_DISABLE 0
603 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
604 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
605 /**
606 * @}
607 */
608
609 /** @defgroup DSI_LP_LPDcsShortReadNoP
610 * @{
611 */
612 #define DSI_LP_DSR0P_DISABLE 0
613 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
614 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
615 /**
616 * @}
617 */
618
619 /** @defgroup DSI_LP_LPDcsLongWrite
620 * @{
621 */
622 #define DSI_LP_DLW_DISABLE 0
623 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
624 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
625 /**
626 * @}
627 */
628
629 /** @defgroup DSI_LP_LPMaxReadPacket
630 * @{
631 */
632 #define DSI_LP_MRDP_DISABLE 0
633 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
634 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
635 /**
636 * @}
637 */
638
639 /** @defgroup DSI_HS_PrespMode
640 * @{
641 */
642 #define DSI_HS_PM_DISABLE 0
643 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
644 /**
645 * @}
646 */
647
648
649 /** @defgroup DSI_Automatic_Clk_Lane_Control
650 * @{
651 */
652 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0
653 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
654 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
655 /**
656 * @}
657 */
658
659 /** @defgroup DSI_Number_Of_Lanes
660 * @{
661 */
662 #define DSI_ONE_DATA_LANE 0
663 #define DSI_TWO_DATA_LANES 1
664 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
665 /**
666 * @}
667 */
668
669 /** @defgroup DSI_FlowControl
670 * @{
671 */
672 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
673 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
674 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
675 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
676 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
677 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
678 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
679 DSI_FLOW_CONTROL_EOTP_TX)
680 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
681 /**
682 * @}
683 */
684
685 /** @defgroup DSI_Color_Coding
686 * @{
687 */
688 #define DSI_RGB565 ((uint32_t)0x00000000) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
689 #define DSI_RGB666 ((uint32_t)0x00000003) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
690 #define DSI_RGB888 ((uint32_t)0x00000005)
691 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
692
693 /**
694 * @}
695 */
696
697 /** @defgroup DSI_LooselyPacked
698 * @{
699 */
700 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
701 #define DSI_LOOSELY_PACKED_DISABLE 0
702 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
703
704 /**
705 * @}
706 */
707
708 /** @defgroup DSI_HSYNC_Polarity
709 * @{
710 */
711 #define DSI_HSYNC_ACTIVE_HIGH 0
712 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
713 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
714 /**
715 * @}
716 */
717
718 /** @defgroup DSI_VSYNC_Polarity
719 * @{
720 */
721 #define DSI_VSYNC_ACTIVE_HIGH 0
722 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
723 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
724 /**
725 * @}
726 */
727
728 /** @defgroup DSI_DATA_ENABLE_Polarity
729 * @{
730 */
731 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0
732 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
733 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
734 /**
735 * @}
736 */
737
738 /** @defgroup DSI_PLL_IDF
739 * @{
740 */
741 #define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001)
742 #define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002)
743 #define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003)
744 #define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004)
745 #define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005)
746 #define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006)
747 #define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007)
748 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
749 ((IDF) == DSI_PLL_IN_DIV2) || \
750 ((IDF) == DSI_PLL_IN_DIV3) || \
751 ((IDF) == DSI_PLL_IN_DIV4) || \
752 ((IDF) == DSI_PLL_IN_DIV5) || \
753 ((IDF) == DSI_PLL_IN_DIV6) || \
754 ((IDF) == DSI_PLL_IN_DIV7))
755 /**
756 * @}
757 */
758
759 /** @defgroup DSI_PLL_ODF
760 * @{
761 */
762 #define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000)
763 #define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001)
764 #define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002)
765 #define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003)
766 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
767 ((ODF) == DSI_PLL_OUT_DIV2) || \
768 ((ODF) == DSI_PLL_OUT_DIV4) || \
769 ((ODF) == DSI_PLL_OUT_DIV8))
770 #define IS_DSI_PLL_NDIV(NDIV) ((10 <= (NDIV)) && ((NDIV) <= 125))
771 /**
772 * @}
773 */
774
775 /** @defgroup DSI_Flags
776 * @{
777 */
778 #define DSI_FLAG_TE DSI_WISR_TEIF
779 #define DSI_FLAG_ER DSI_WISR_ERIF
780 #define DSI_FLAG_BUSY DSI_WISR_BUSY
781 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
782 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
783 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
784 #define DSI_FLAG_RRS DSI_WISR_RRS
785 #define DSI_FLAG_RR DSI_WISR_RRIF
786
787 #define IS_DSI_CLEAR_FLAG(FLAG) (((FLAG) == DSI_FLAG_TE) || ((FLAG) == DSI_FLAG_ER) || \
788 ((FLAG) == DSI_FLAG_PLLL) || ((FLAG) == DSI_FLAG_PLLU) || \
789 ((FLAG) == DSI_FLAG_RR))
790 #define IS_DSI_GET_FLAG(FLAG) (((FLAG) == DSI_FLAG_TE) || ((FLAG) == DSI_FLAG_ER) || \
791 ((FLAG) == DSI_FLAG_BUSY) || ((FLAG) == DSI_FLAG_PLLLS) || \
792 ((FLAG) == DSI_FLAG_PLLL) || ((FLAG) == DSI_FLAG_PLLU) || \
793 ((FLAG) == DSI_FLAG_RRS) || ((FLAG) == DSI_FLAG_RR))
794 /**
795 * @}
796 */
797
798 /** @defgroup DSI_Interrupts
799 * @{
800 */
801 #define DSI_IT_TE DSI_WIER_TEIE
802 #define DSI_IT_ER DSI_WIER_ERIE
803 #define DSI_IT_PLLL DSI_WIER_PLLLIE
804 #define DSI_IT_PLLU DSI_WIER_PLLUIE
805 #define DSI_IT_RR DSI_WIER_RRIE
806
807 #define IS_DSI_IT(IT) (((IT) == DSI_IT_TE) || ((IT) == DSI_IT_ER) || \
808 ((IT) == DSI_IT_PLLL) || ((IT) == DSI_IT_PLLU) || \
809 ((IT) == DSI_IT_RR))
810 /**
811 * @}
812 */
813
814 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type
815 * @{
816 */
817 #define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005) /*!< DCS short write, no parameters */
818 #define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015) /*!< DCS short write, one parameter */
819 #define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003) /*!< Generic short write, no parameters */
820 #define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013) /*!< Generic short write, one parameter */
821 #define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023) /*!< Generic short write, two parameters */
822 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
823 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
824 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
825 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
826 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
827 /**
828 * @}
829 */
830
831 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type
832 * @{
833 */
834 #define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039) /*!< DCS long write */
835 #define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029) /*!< Generic long write */
836 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
837 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
838 /**
839 * @}
840 */
841
842 /** @defgroup DSI_SHORT_READ_PKT_Data_Type
843 * @{
844 */
845 #define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006) /*!< DCS short read */
846 #define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004) /*!< Generic short read, no parameters */
847 #define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014) /*!< Generic short read, one parameter */
848 #define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024) /*!< Generic short read, two parameters */
849 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
850 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
851 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
852 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
853 /**
854 * @}
855 */
856
857 /** @defgroup DSI_Error_Data_Type
858 * @{
859 */
860 #define DSI_ERROR_NONE 0
861 #define DSI_ERROR_ACK ((uint32_t)0x00000001) /*!< acknowledge errors */
862 #define DSI_ERROR_PHY ((uint32_t)0x00000002) /*!< PHY related errors */
863 #define DSI_ERROR_TX ((uint32_t)0x00000004) /*!< transmission error */
864 #define DSI_ERROR_RX ((uint32_t)0x00000008) /*!< reception error */
865 #define DSI_ERROR_ECC ((uint32_t)0x00000010) /*!< ECC errors */
866 #define DSI_ERROR_CRC ((uint32_t)0x00000020) /*!< CRC error */
867 #define DSI_ERROR_PSE ((uint32_t)0x00000040) /*!< Packet Size error */
868 #define DSI_ERROR_EOT ((uint32_t)0x00000080) /*!< End Of Transmission error */
869 #define DSI_ERROR_OVF ((uint32_t)0x00000100) /*!< FIFO overflow error */
870 #define DSI_ERROR_GEN ((uint32_t)0x00000200) /*!< Generic FIFO related errors */
871 /**
872 * @}
873 */
874
875 /** @defgroup DSI_Lane_Group
876 * @{
877 */
878 #define DSI_CLOCK_LANE ((uint32_t)0x00000000)
879 #define DSI_DATA_LANES ((uint32_t)0x00000001)
880 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
881 /**
882 * @}
883 */
884
885 /** @defgroup DSI_Communication_Delay
886 * @{
887 */
888 #define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000)
889 #define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001)
890 #define DSI_HS_DELAY ((uint32_t)0x00000002)
891 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
892 /**
893 * @}
894 */
895
896 /** @defgroup DSI_CustomLane
897 * @{
898 */
899 #define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000)
900 #define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001)
901 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
902 /**
903 * @}
904 */
905
906 /** @defgroup DSI_Lane_Select
907 * @{
908 */
909 #define DSI_CLOCK_LANE ((uint32_t)0x00000000)
910 #define DSI_DATA_LANE0 ((uint32_t)0x00000001)
911 #define DSI_DATA_LANE1 ((uint32_t)0x00000002)
912 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
913 /**
914 * @}
915 */
916
917 /** @defgroup DSI_PHY_Timing
918 * @{
919 */
920 #define DSI_TCLK_POST ((uint32_t)0x00000000)
921 #define DSI_TLPX_CLK ((uint32_t)0x00000001)
922 #define DSI_THS_EXIT ((uint32_t)0x00000002)
923 #define DSI_TLPX_DATA ((uint32_t)0x00000003)
924 #define DSI_THS_ZERO ((uint32_t)0x00000004)
925 #define DSI_THS_TRAIL ((uint32_t)0x00000005)
926 #define DSI_THS_PREPARE ((uint32_t)0x00000006)
927 #define DSI_TCLK_ZERO ((uint32_t)0x00000007)
928 #define DSI_TCLK_PREPARE ((uint32_t)0x00000008)
929 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
930 ((Timing) == DSI_TLPX_CLK ) || \
931 ((Timing) == DSI_THS_EXIT ) || \
932 ((Timing) == DSI_TLPX_DATA ) || \
933 ((Timing) == DSI_THS_ZERO ) || \
934 ((Timing) == DSI_THS_TRAIL ) || \
935 ((Timing) == DSI_THS_PREPARE ) || \
936 ((Timing) == DSI_TCLK_ZERO ) || \
937 ((Timing) == DSI_TCLK_PREPARE))
938 /**
939 * @}
940 */
941 #define IS_DSI_ALL_PERIPH(PERIPH) ((PERIPH) == DSI)
942
943 /* Exported macros -----------------------------------------------------------*/
944 /* Exported functions --------------------------------------------------------*/
945 /* Initialization and Configuration functions *********************************/
946 void DSI_DeInit(DSI_TypeDef *DSIx);
947 void DSI_Init(DSI_TypeDef *DSIx,DSI_InitTypeDef* DSI_InitStruct, DSI_PLLInitTypeDef *PLLInit);
948 void DSI_StructInit(DSI_InitTypeDef* DSI_InitStruct, DSI_HOST_TimeoutTypeDef* DSI_HOST_TimeoutInitStruct);
949 void DSI_SetGenericVCID(DSI_TypeDef *DSIx, uint32_t VirtualChannelID);
950 void DSI_ConfigVideoMode(DSI_TypeDef *DSIx, DSI_VidCfgTypeDef *VidCfg);
951 void DSI_ConfigAdaptedCommandMode(DSI_TypeDef *DSIx, DSI_CmdCfgTypeDef *CmdCfg);
952 void DSI_ConfigCommand(DSI_TypeDef *DSIx, DSI_LPCmdTypeDef *LPCmd);
953 void DSI_ConfigFlowControl(DSI_TypeDef *DSIx, uint32_t FlowControl);
954 void DSI_ConfigPhyTimer(DSI_TypeDef *DSIx, DSI_PHY_TimerTypeDef *PhyTimers);
955 void DSI_ConfigHostTimeouts(DSI_TypeDef *DSIx, DSI_HOST_TimeoutTypeDef *HostTimeouts);
956 void DSI_PatternGeneratorStart(DSI_TypeDef *DSIx, uint32_t Mode, uint32_t Orientation);
957 void DSI_PatternGeneratorStop(DSI_TypeDef *DSIx);
958 void DSI_Start(DSI_TypeDef *DSIx);
959 void DSI_Stop(DSI_TypeDef *DSIx);
960 void DSI_Refresh(DSI_TypeDef *DSIx);
961 void DSI_ColorMode(DSI_TypeDef *DSIx, uint32_t ColorMode);
962 void DSI_Shutdown(DSI_TypeDef *DSIx, uint32_t Shutdown);
963
964 /* Alias for compatibility with STM32F4XX Standard Peripherals Library version number V1.6.0 */
965 #define DSI_ConfigLowPowerCommand DSI_ConfigCommand
966
967 /* Data transfers management functions ****************************************/
968 void DSI_ShortWrite(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t Mode, uint32_t Param1, uint32_t Param2);
969 void DSI_LongWrite(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t Mode, uint32_t NbParams, uint32_t Param1, uint8_t* ParametersTable);
970 void DSI_Read(DSI_TypeDef *DSIx, uint32_t ChannelNbr, uint8_t* Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t* ParametersTable);
971
972 /* Low Power functions ********************************************************/
973 void DSI_EnterULPMData(DSI_TypeDef *DSIx);
974 void DSI_ExitULPMData(DSI_TypeDef *DSIx);
975 void DSI_EnterULPM(DSI_TypeDef *DSIx);
976 void DSI_ExitULPM(DSI_TypeDef *DSIx);
977 void DSI_SetSlewRateAndDelayTuning(DSI_TypeDef *DSIx, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
978 void DSI_SetLowPowerRXFilter(DSI_TypeDef *DSIx, uint32_t Frequency);
979 void DSI_SetSDD(DSI_TypeDef *DSIx, FunctionalState State);
980 void DSI_SetLanePinsConfiguration(DSI_TypeDef *DSIx, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
981 void DSI_SetPHYTimings(DSI_TypeDef *DSIx, uint32_t Timing, FunctionalState State, uint32_t Value);
982 void DSI_ForceTXStopMode(DSI_TypeDef *DSIx, uint32_t Lane, FunctionalState State);
983 void DSI_ForceRXLowPower(DSI_TypeDef *DSIx, FunctionalState State);
984 void DSI_ForceDataLanesInRX(DSI_TypeDef *DSIx, FunctionalState State);
985 void DSI_SetPullDown(DSI_TypeDef *DSIx, FunctionalState State);
986 void DSI_SetContentionDetectionOff(DSI_TypeDef *DSIx, FunctionalState State);
987
988 /* Interrupts and flags management functions **********************************/
989 void DSI_ITConfig(DSI_TypeDef* DSIx, uint32_t DSI_IT, FunctionalState NewState);
990 FlagStatus DSI_GetFlagStatus(DSI_TypeDef* DSIx, uint16_t DSI_FLAG);
991 void DSI_ClearFlag(DSI_TypeDef* DSIx, uint16_t DSI_FLAG);
992 ITStatus DSI_GetITStatus(DSI_TypeDef* DSIx, uint32_t DSI_IT);
993 void DSI_ClearITPendingBit(DSI_TypeDef* DSIx, uint32_t DSI_IT);
994 void DSI_ConfigErrorMonitor(DSI_TypeDef *DSIx, uint32_t ActiveErrors);
995
996 #endif /* STM32F469_479xx */
997 /**
998 * @}
999 */
1000
1001 /**
1002 * @}
1003 */
1004
1005 #ifdef __cplusplus
1006 }
1007 #endif
1008
1009 #endif /* __STM32F4xx_DSI_H */
1010
1011 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/