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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_fmc.h
bloba99c194f5f135ae20d27234309d0a3bd8eee7b03
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_fmc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 20-May-2016
7 * @brief This file contains all the functions prototypes for the FMC firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
13 *
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
17 *
18 * http://www.st.com/software_license_agreement_liberty_v2
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************
27 */
28
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4xx_FMC_H
31 #define __STM32F4xx_FMC_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx.h"
39
40 /** @addtogroup STM32F4xx_StdPeriph_Driver
41 * @{
42 */
43
44 /** @addtogroup FMC
45 * @{
46 */
47
48 /* Exported types ------------------------------------------------------------*/
49
50 /**
51 * @brief Timing parameters For NOR/SRAM Banks
52 */
53 typedef struct
54 {
55 uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
56 the duration of the address setup time.
57 This parameter can be a value between 0 and 15.
58 @note This parameter is not used with synchronous NOR Flash memories. */
59
60 uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
61 the duration of the address hold time.
62 This parameter can be a value between 1 and 15.
63 @note This parameter is not used with synchronous NOR Flash memories.*/
64
65 uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
66 the duration of the data setup time.
67 This parameter can be a value between 1 and 255.
68 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
69
70 uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
71 the duration of the bus turnaround.
72 This parameter can be a value between 0 and 15.
73 @note This parameter is only used for multiplexed NOR Flash memories. */
74
75 uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
76 This parameter can be a value between 1 and 15.
77 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
78
79 uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
80 to the memory before getting the first data.
81 The parameter value depends on the memory type as shown below:
82 - It must be set to 0 in case of a CRAM
83 - It is don't care in asynchronous NOR, SRAM or ROM accesses
84 - It may assume a value between 0 and 15 in NOR Flash memories
85 with synchronous burst mode enable */
86
87 uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
88 This parameter can be a value of @ref FMC_Access_Mode */
89 }FMC_NORSRAMTimingInitTypeDef;
90
91 /**
92 * @brief FMC NOR/SRAM Init structure definition
93 */
94 typedef struct
95 {
96 uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
97 This parameter can be a value of @ref FMC_NORSRAM_Bank */
98
99 uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
100 multiplexed on the databus or not.
101 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
102
103 uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
104 the corresponding memory bank.
105 This parameter can be a value of @ref FMC_Memory_Type */
106
107 uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
108 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
109
110 uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
111 valid only with synchronous burst Flash memories.
112 This parameter can be a value of @ref FMC_Burst_Access_Mode */
113
114 uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
115 the Flash memory in burst mode.
116 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
117
118 uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
119 memory, valid only when accessing Flash memories in burst mode.
120 This parameter can be a value of @ref FMC_Wrap_Mode */
121
122 uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
123 clock cycle before the wait state or during the wait state,
124 valid only when accessing memories in burst mode.
125 This parameter can be a value of @ref FMC_Wait_Timing */
126
127 uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
128 This parameter can be a value of @ref FMC_Write_Operation */
129
130 uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
131 signal, valid for Flash memory access in burst mode.
132 This parameter can be a value of @ref FMC_Wait_Signal */
133
134 uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
135 This parameter can be a value of @ref FMC_Extended_Mode */
136
137 uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
138 valid only with asynchronous Flash memories.
139 This parameter can be a value of @ref FMC_AsynchronousWait */
140
141 uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
142 This parameter can be a value of @ref FMC_Write_Burst */
143
144 uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices.
145 This parameter is only enabled through the FMC_BCR1 register, and don't care
146 through FMC_BCR2..4 registers.
147 This parameter can be a value of @ref FMC_Continous_Clock */
148
149
150 FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
151
152 FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
153 }FMC_NORSRAMInitTypeDef;
154
155 /**
156 * @brief Timing parameters For FMC NAND and PCCARD Banks
157 */
158 typedef struct
159 {
160 uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
161 the command assertion for NAND-Flash read or write access
162 to common/Attribute or I/O memory space (depending on
163 the memory space timing to be configured).
164 This parameter can be a value between 0 and 255.*/
165
166 uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
167 command for NAND-Flash read or write access to
168 common/Attribute or I/O memory space (depending on the
169 memory space timing to be configured).
170 This parameter can be a number between 0 and 255 */
171
172 uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
173 (and data for write access) after the command de-assertion
174 for NAND-Flash read or write access to common/Attribute
175 or I/O memory space (depending on the memory space timing
176 to be configured).
177 This parameter can be a number between 0 and 255 */
178
179 uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
180 databus is kept in HiZ after the start of a NAND-Flash
181 write access to common/Attribute or I/O memory space (depending
182 on the memory space timing to be configured).
183 This parameter can be a number between 0 and 255 */
184 }FMC_NAND_PCCARDTimingInitTypeDef;
185
186 /**
187 * @brief FMC NAND Init structure definition
188 */
189 typedef struct
190 {
191 uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
192 This parameter can be a value of @ref FMC_NAND_Bank */
193
194 uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
195 This parameter can be any value of @ref FMC_Wait_feature */
196
197 uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
198 This parameter can be any value of @ref FMC_NAND_Data_Width */
199
200 uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
201 This parameter can be any value of @ref FMC_ECC */
202
203 uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
204 This parameter can be any value of @ref FMC_ECC_Page_Size */
205
206 uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
207 delay between CLE low and RE low.
208 This parameter can be a value between 0 and 255. */
209
210 uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
211 delay between ALE low and RE low.
212 This parameter can be a number between 0 and 255 */
213
214 FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
215
216 FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
217 }FMC_NANDInitTypeDef;
218
219 /**
220 * @brief FMC PCCARD Init structure definition
221 */
222
223 typedef struct
224 {
225 uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
226 This parameter can be any value of @ref FMC_Wait_feature */
227
228 uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
229 delay between CLE low and RE low.
230 This parameter can be a value between 0 and 255. */
231
232 uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
233 delay between ALE low and RE low.
234 This parameter can be a number between 0 and 255 */
235
236
237 FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
238
239 FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
240
241 FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
242 }FMC_PCCARDInitTypeDef;
243
244 /**
245 * @brief Timing parameters for FMC SDRAM Banks
246 */
247
248 typedef struct
249 {
250 uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
251 an active or Refresh command in number of memory clock cycles.
252 This parameter can be a value between 1 and 16. */
253
254 uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
255 issuing the Activate command in number of memory clock cycles.
256 This parameter can be a value between 1 and 16. */
257
258 uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
259 cycles.
260 This parameter can be a value between 1 and 16. */
261
262 uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
263 and the delay between two consecutive Refresh commands in number of
264 memory clock cycles.
265 This parameter can be a value between 1 and 16. */
266
267 uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
268 This parameter can be a value between 1 and 16. */
269
270 uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command
271 in number of memory clock cycles.
272 This parameter can be a value between 1 and 16. */
273
274 uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command
275 in number of memory clock cycles.
276 This parameter can be a value between 1 and 16. */
277
278 }FMC_SDRAMTimingInitTypeDef;
279
280 /**
281 * @brief Command parameters for FMC SDRAM Banks
282 */
283
284
285 typedef struct
286 {
287 uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device.
288 This parameter can be a value of @ref FMC_Command_Mode. */
289
290 uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to.
291 This parameter can be a value of @ref FMC_Command_Target. */
292
293 uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
294 in auto refresh mode.
295 This parameter can be a value between 1 and 16. */
296
297 uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
298
299 }FMC_SDRAMCommandTypeDef;
300
301 /**
302 * @brief FMC SDRAM Init structure definition
303 */
304
305 typedef struct
306 {
307 uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used.
308 This parameter can be a value of @ref FMC_SDRAM_Bank */
309
310 uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address.
311 This parameter can be a value of @ref FMC_ColumnBits_Number. */
312
313 uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address..
314 This parameter can be a value of @ref FMC_RowBits_Number. */
315
316 uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width.
317 This parameter can be a value of @ref FMC_SDMemory_Data_Width. */
318
319 uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address.
320 This parameter can be of @ref FMC_InternalBank_Number. */
321
322 uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
323 This parameter can be a value of @ref FMC_CAS_Latency. */
324
325 uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode.
326 This parameter can be a value of @ref FMC_Write_Protection. */
327
328 uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable
329 the clock before changing frequency.
330 This parameter can be a value of @ref FMC_SDClock_Period. */
331
332 uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands
333 during the CAS latency and stores data in the Read FIFO.
334 This parameter can be a value of @ref FMC_Read_Burst. */
335
336 uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
337 This parameter can be a value of @ref FMC_ReadPipe_Delay. */
338
339 FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/
340
341 }FMC_SDRAMInitTypeDef;
342
343
344 /* Exported constants --------------------------------------------------------*/
345
346 /** @defgroup FMC_Exported_Constants
347 * @{
348 */
349
350 /** @defgroup FMC_NORSRAM_Bank
351 * @{
352 */
353 #define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
354 #define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
355 #define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
356 #define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
357
358 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
359 ((BANK) == FMC_Bank1_NORSRAM2) || \
360 ((BANK) == FMC_Bank1_NORSRAM3) || \
361 ((BANK) == FMC_Bank1_NORSRAM4))
362 /**
363 * @}
364 */
365
366 /** @defgroup FMC_NAND_Bank
367 * @{
368 */
369 #define FMC_Bank2_NAND ((uint32_t)0x00000010)
370 #define FMC_Bank3_NAND ((uint32_t)0x00000100)
371
372 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
373 ((BANK) == FMC_Bank3_NAND))
374 /**
375 * @}
376 */
377
378 /** @defgroup FMC_PCCARD_Bank
379 * @{
380 */
381 #define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
382 /**
383 * @}
384 */
385
386 /** @defgroup FMC_SDRAM_Bank
387 * @{
388 */
389 #define FMC_Bank1_SDRAM ((uint32_t)0x00000000)
390 #define FMC_Bank2_SDRAM ((uint32_t)0x00000001)
391
392 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \
393 ((BANK) == FMC_Bank2_SDRAM))
394
395 /**
396 * @}
397 */
398
399
400 /** @defgroup FMC_NOR_SRAM_Controller
401 * @{
402 */
403
404 /** @defgroup FMC_Data_Address_Bus_Multiplexing
405 * @{
406 */
407
408 #define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
409 #define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
410
411 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
412 ((MUX) == FMC_DataAddressMux_Enable))
413 /**
414 * @}
415 */
416
417 /** @defgroup FMC_Memory_Type
418 * @{
419 */
420
421 #define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
422 #define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
423 #define FMC_MemoryType_NOR ((uint32_t)0x00000008)
424
425 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
426 ((MEMORY) == FMC_MemoryType_PSRAM)|| \
427 ((MEMORY) == FMC_MemoryType_NOR))
428 /**
429 * @}
430 */
431
432 /** @defgroup FMC_NORSRAM_Data_Width
433 * @{
434 */
435
436 #define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
437 #define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
438 #define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020)
439
440 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
441 ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \
442 ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b))
443 /**
444 * @}
445 */
446
447 /** @defgroup FMC_Burst_Access_Mode
448 * @{
449 */
450
451 #define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
452 #define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
453
454 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
455 ((STATE) == FMC_BurstAccessMode_Enable))
456 /**
457 * @}
458 */
459
460 /** @defgroup FMC_AsynchronousWait
461 * @{
462 */
463 #define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
464 #define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
465
466 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
467 ((STATE) == FMC_AsynchronousWait_Enable))
468 /**
469 * @}
470 */
471
472 /** @defgroup FMC_Wait_Signal_Polarity
473 * @{
474 */
475 #define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
476 #define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
477
478 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
479 ((POLARITY) == FMC_WaitSignalPolarity_High))
480 /**
481 * @}
482 */
483
484 /** @defgroup FMC_Wrap_Mode
485 * @{
486 */
487 #define FMC_WrapMode_Disable ((uint32_t)0x00000000)
488 #define FMC_WrapMode_Enable ((uint32_t)0x00000400)
489
490 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
491 ((MODE) == FMC_WrapMode_Enable))
492 /**
493 * @}
494 */
495
496 /** @defgroup FMC_Wait_Timing
497 * @{
498 */
499 #define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
500 #define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
501
502 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
503 ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
504 /**
505 * @}
506 */
507
508 /** @defgroup FMC_Write_Operation
509 * @{
510 */
511 #define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
512 #define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
513
514 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
515 ((OPERATION) == FMC_WriteOperation_Enable))
516 /**
517 * @}
518 */
519
520 /** @defgroup FMC_Wait_Signal
521 * @{
522 */
523 #define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
524 #define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
525
526 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
527 ((SIGNAL) == FMC_WaitSignal_Enable))
528 /**
529 * @}
530 */
531
532 /** @defgroup FMC_Extended_Mode
533 * @{
534 */
535 #define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
536 #define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
537
538 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
539 ((MODE) == FMC_ExtendedMode_Enable))
540 /**
541 * @}
542 */
543
544 /** @defgroup FMC_Write_Burst
545 * @{
546 */
547
548 #define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
549 #define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
550
551 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
552 ((BURST) == FMC_WriteBurst_Enable))
553 /**
554 * @}
555 */
556
557 /** @defgroup FMC_Continous_Clock
558 * @{
559 */
560
561 #define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
562 #define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
563
564 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
565 ((CCLOCK) == FMC_CClock_SyncAsync))
566 /**
567 * @}
568 */
569
570 /** @defgroup FMC_Address_Setup_Time
571 * @{
572 */
573 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
574 /**
575 * @}
576 */
577
578 /** @defgroup FMC_Address_Hold_Time
579 * @{
580 */
581 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
582 /**
583 * @}
584 */
585
586 /** @defgroup FMC_Data_Setup_Time
587 * @{
588 */
589 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
590 /**
591 * @}
592 */
593
594 /** @defgroup FMC_Bus_Turn_around_Duration
595 * @{
596 */
597 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
598 /**
599 * @}
600 */
601
602 /** @defgroup FMC_CLK_Division
603 * @{
604 */
605 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15))
606 /**
607 * @}
608 */
609
610 /** @defgroup FMC_Data_Latency
611 * @{
612 */
613 #define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15)
614 /**
615 * @}
616 */
617
618 /** @defgroup FMC_Access_Mode
619 * @{
620 */
621 #define FMC_AccessMode_A ((uint32_t)0x00000000)
622 #define FMC_AccessMode_B ((uint32_t)0x10000000)
623 #define FMC_AccessMode_C ((uint32_t)0x20000000)
624 #define FMC_AccessMode_D ((uint32_t)0x30000000)
625
626 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
627 ((MODE) == FMC_AccessMode_B) || \
628 ((MODE) == FMC_AccessMode_C) || \
629 ((MODE) == FMC_AccessMode_D))
630 /**
631 * @}
632 */
633
634 /**
635 * @}
636 */
637
638 /** @defgroup FMC_NAND_PCCARD_Controller
639 * @{
640 */
641
642 /** @defgroup FMC_Wait_feature
643 * @{
644 */
645 #define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
646 #define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
647
648 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
649 ((FEATURE) == FMC_Waitfeature_Enable))
650 /**
651 * @}
652 */
653
654 /** @defgroup FMC_NAND_Data_Width
655 * @{
656 */
657 #define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
658 #define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
659
660 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
661 ((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
662 /**
663 * @}
664 */
665
666 /** @defgroup FMC_ECC
667 * @{
668 */
669 #define FMC_ECC_Disable ((uint32_t)0x00000000)
670 #define FMC_ECC_Enable ((uint32_t)0x00000040)
671
672 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
673 ((STATE) == FMC_ECC_Enable))
674 /**
675 * @}
676 */
677
678 /** @defgroup FMC_ECC_Page_Size
679 * @{
680 */
681 #define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
682 #define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
683 #define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
684 #define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
685 #define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
686 #define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
687
688 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
689 ((SIZE) == FMC_ECCPageSize_512Bytes) || \
690 ((SIZE) == FMC_ECCPageSize_1024Bytes) || \
691 ((SIZE) == FMC_ECCPageSize_2048Bytes) || \
692 ((SIZE) == FMC_ECCPageSize_4096Bytes) || \
693 ((SIZE) == FMC_ECCPageSize_8192Bytes))
694 /**
695 * @}
696 */
697
698 /** @defgroup FMC_TCLR_Setup_Time
699 * @{
700 */
701 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
702 /**
703 * @}
704 */
705
706 /** @defgroup FMC_TAR_Setup_Time
707 * @{
708 */
709 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
710 /**
711 * @}
712 */
713
714 /** @defgroup FMC_Setup_Time
715 * @{
716 */
717 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
718 /**
719 * @}
720 */
721
722 /** @defgroup FMC_Wait_Setup_Time
723 * @{
724 */
725 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
726 /**
727 * @}
728 */
729
730 /** @defgroup FMC_Hold_Setup_Time
731 * @{
732 */
733 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
734 /**
735 * @}
736 */
737
738 /** @defgroup FMC_HiZ_Setup_Time
739 * @{
740 */
741 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
742 /**
743 * @}
744 */
745
746 /**
747 * @}
748 */
749
750
751 /** @defgroup FMC_NOR_SRAM_Controller
752 * @{
753 */
754
755 /** @defgroup FMC_ColumnBits_Number
756 * @{
757 */
758 #define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
759 #define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
760 #define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
761 #define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
762
763 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \
764 ((COLUMN) == FMC_ColumnBits_Number_9b) || \
765 ((COLUMN) == FMC_ColumnBits_Number_10b) || \
766 ((COLUMN) == FMC_ColumnBits_Number_11b))
767
768 /**
769 * @}
770 */
771
772 /** @defgroup FMC_RowBits_Number
773 * @{
774 */
775 #define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
776 #define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
777 #define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
778
779 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \
780 ((ROW) == FMC_RowBits_Number_12b) || \
781 ((ROW) == FMC_RowBits_Number_13b))
782
783 /**
784 * @}
785 */
786
787 /** @defgroup FMC_SDMemory_Data_Width
788 * @{
789 */
790 #define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
791 #define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
792 #define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
793
794 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \
795 ((WIDTH) == FMC_SDMemory_Width_16b) || \
796 ((WIDTH) == FMC_SDMemory_Width_32b))
797
798 /**
799 * @}
800 */
801
802 /** @defgroup FMC_InternalBank_Number
803 * @{
804 */
805 #define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
806 #define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
807
808 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \
809 ((NUMBER) == FMC_InternalBank_Number_4))
810
811 /**
812 * @}
813 */
814
815
816 /** @defgroup FMC_CAS_Latency
817 * @{
818 */
819 #define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
820 #define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
821 #define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
822
823 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \
824 ((LATENCY) == FMC_CAS_Latency_2) || \
825 ((LATENCY) == FMC_CAS_Latency_3))
826
827 /**
828 * @}
829 */
830
831 /** @defgroup FMC_Write_Protection
832 * @{
833 */
834 #define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
835 #define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
836
837 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \
838 ((WRITE) == FMC_Write_Protection_Enable))
839
840 /**
841 * @}
842 */
843
844
845 /** @defgroup FMC_SDClock_Period
846 * @{
847 */
848 #define FMC_SDClock_Disable ((uint32_t)0x00000000)
849 #define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
850 #define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
851
852 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \
853 ((PERIOD) == FMC_SDClock_Period_2) || \
854 ((PERIOD) == FMC_SDClock_Period_3))
855
856 /**
857 * @}
858 */
859
860 /** @defgroup FMC_Read_Burst
861 * @{
862 */
863 #define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
864 #define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
865
866 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \
867 ((RBURST) == FMC_Read_Burst_Enable))
868
869 /**
870 * @}
871 */
872
873 /** @defgroup FMC_ReadPipe_Delay
874 * @{
875 */
876 #define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
877 #define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
878 #define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
879
880 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \
881 ((DELAY) == FMC_ReadPipe_Delay_1) || \
882 ((DELAY) == FMC_ReadPipe_Delay_2))
883
884 /**
885 * @}
886 */
887
888 /** @defgroup FMC_LoadToActive_Delay
889 * @{
890 */
891 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
892 /**
893 * @}
894 */
895
896 /** @defgroup FMC_ExitSelfRefresh_Delay
897 * @{
898 */
899 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
900 /**
901 * @}
902 */
903
904 /** @defgroup FMC_SelfRefresh_Time
905 * @{
906 */
907 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
908 /**
909 * @}
910 */
911
912 /** @defgroup FMC_RowCycle_Delay
913 * @{
914 */
915 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
916 /**
917 * @}
918 */
919
920 /** @defgroup FMC_Write_Recovery_Time
921 * @{
922 */
923 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
924 /**
925 * @}
926 */
927
928 /** @defgroup FMC_RP_Delay
929 * @{
930 */
931 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
932 /**
933 * @}
934 */
935
936 /** @defgroup FMC_RCD_Delay
937 * @{
938 */
939 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
940
941 /**
942 * @}
943 */
944
945 /** @defgroup FMC_Command_Mode
946 * @{
947 */
948 #define FMC_Command_Mode_normal ((uint32_t)0x00000000)
949 #define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001)
950 #define FMC_Command_Mode_PALL ((uint32_t)0x00000002)
951 #define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003)
952 #define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004)
953 #define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005)
954 #define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006)
955
956 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \
957 ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \
958 ((COMMAND) == FMC_Command_Mode_PALL) || \
959 ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \
960 ((COMMAND) == FMC_Command_Mode_LoadMode) || \
961 ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \
962 ((COMMAND) == FMC_Command_Mode_PowerDown))
963
964 /**
965 * @}
966 */
967
968 /** @defgroup FMC_Command_Target
969 * @{
970 */
971 #define FMC_Command_Target_bank2 ((uint32_t)0x00000008)
972 #define FMC_Command_Target_bank1 ((uint32_t)0x00000010)
973 #define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018)
974
975 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \
976 ((TARGET) == FMC_Command_Target_bank2) || \
977 ((TARGET) == FMC_Command_Target_bank1_2))
978
979 /**
980 * @}
981 */
982
983 /** @defgroup FMC_AutoRefresh_Number
984 * @{
985 */
986 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
987
988 /**
989 * @}
990 */
991
992 /** @defgroup FMC_ModeRegister_Definition
993 * @{
994 */
995 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
996
997 /**
998 * @}
999 */
1000
1001
1002 /** @defgroup FMC_Mode_Status
1003 * @{
1004 */
1005 #define FMC_NormalMode_Status ((uint32_t)0x00000000)
1006 #define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0
1007 #define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1
1008
1009 #define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \
1010 ((STATUS) == FMC_SelfRefreshMode_Status) || \
1011 ((STATUS) == FMC_PowerDownMode_Status))
1012
1013
1014 /**
1015 * @}
1016 */
1017
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup FMC_Interrupt_sources
1023 * @{
1024 */
1025 #define FMC_IT_RisingEdge ((uint32_t)0x00000008)
1026 #define FMC_IT_Level ((uint32_t)0x00000010)
1027 #define FMC_IT_FallingEdge ((uint32_t)0x00000020)
1028 #define FMC_IT_Refresh ((uint32_t)0x00004000)
1029
1030 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
1031 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
1032 ((IT) == FMC_IT_Level) || \
1033 ((IT) == FMC_IT_FallingEdge) || \
1034 ((IT) == FMC_IT_Refresh))
1035
1036 #define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
1037 ((BANK) == FMC_Bank3_NAND) || \
1038 ((BANK) == FMC_Bank4_PCCARD) || \
1039 ((BANK) == FMC_Bank1_SDRAM) || \
1040 ((BANK) == FMC_Bank2_SDRAM))
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup FMC_Flags
1046 * @{
1047 */
1048 #define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
1049 #define FMC_FLAG_Level ((uint32_t)0x00000002)
1050 #define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
1051 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
1052 #define FMC_FLAG_Refresh FMC_SDSR_RE
1053 #define FMC_FLAG_Busy FMC_SDSR_BUSY
1054
1055 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
1056 ((FLAG) == FMC_FLAG_Level) || \
1057 ((FLAG) == FMC_FLAG_FallingEdge) || \
1058 ((FLAG) == FMC_FLAG_FEMPT) || \
1059 ((FLAG) == FMC_FLAG_Refresh) || \
1060 ((FLAG) == FMC_SDSR_BUSY))
1061
1062 #define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
1063 ((BANK) == FMC_Bank3_NAND) || \
1064 ((BANK) == FMC_Bank4_PCCARD) || \
1065 ((BANK) == FMC_Bank1_SDRAM) || \
1066 ((BANK) == FMC_Bank2_SDRAM) || \
1067 ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM)))
1068
1069 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
1070
1071
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup FMC_Refresh_count
1077 * @{
1078 */
1079 #define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191)
1080
1081 /**
1082 * @}
1083 */
1084
1085 /**
1086 * @}
1087 */
1088
1089
1090 /* Exported macro ------------------------------------------------------------*/
1091 /* Exported functions --------------------------------------------------------*/
1092
1093 /* NOR/SRAM Controller functions **********************************************/
1094 void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
1095 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
1096 void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
1097 void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
1098
1099 /* NAND Controller functions **************************************************/
1100 void FMC_NANDDeInit(uint32_t FMC_Bank);
1101 void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
1102 void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
1103 void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
1104 void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
1105 uint32_t FMC_GetECC(uint32_t FMC_Bank);
1106
1107 /* PCCARD Controller functions ************************************************/
1108 void FMC_PCCARDDeInit(void);
1109 void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
1110 void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
1111 void FMC_PCCARDCmd(FunctionalState NewState);
1112
1113 /* SDRAM Controller functions ************************************************/
1114 void FMC_SDRAMDeInit(uint32_t FMC_Bank);
1115 void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
1116 void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
1117 void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct);
1118 uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank);
1119 void FMC_SetRefreshCount(uint32_t FMC_Count);
1120 void FMC_SetAutoRefresh_Number(uint32_t FMC_Number);
1121 void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState);
1122
1123 /* Interrupts and flags management functions **********************************/
1124 void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
1125 FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
1126 void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
1127 ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
1128 void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
1129
1130 #ifdef __cplusplus
1131 }
1132 #endif
1133
1134 #endif /*__STM32F4xx_FMC_H */
1135 /**
1136 * @}
1137 */
1138
1139 /**
1140 * @}
1141 */
1142
1143 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/