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Move telemetry displayport init and cms device registering
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_rcc.h
blob06ddee14701d9744b1a879ae552e3220915cee7b
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_rcc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 20-May-2016
7 * @brief This file contains all the functions prototypes for the RCC firmware library.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
12 *
13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 * You may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at:
16 *
17 * http://www.st.com/software_license_agreement_liberty_v2
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *
25 ******************************************************************************
26 */
27
28 /* Define to prevent recursive inclusion -------------------------------------*/
29 #ifndef __STM32F4xx_RCC_H
30 #define __STM32F4xx_RCC_H
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f4xx.h"
38
39 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @{
41 */
42
43 /** @addtogroup RCC
44 * @{
45 */
46
47 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
51 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
52 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
53 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
54 }RCC_ClocksTypeDef;
55
56 /* Exported constants --------------------------------------------------------*/
57
58 /** @defgroup RCC_Exported_Constants
59 * @{
60 */
61
62 /** @defgroup RCC_HSE_configuration
63 * @{
64 */
65 #define RCC_HSE_OFF ((uint8_t)0x00)
66 #define RCC_HSE_ON ((uint8_t)0x01)
67 #define RCC_HSE_Bypass ((uint8_t)0x05)
68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
69 ((HSE) == RCC_HSE_Bypass))
70 /**
71 * @}
72 */
73
74 /** @defgroup RCC_LSE_Dual_Mode_Selection
75 * @{
76 */
77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
80 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
81 /**
82 * @}
83 */
84
85 /** @defgroup RCC_PLLSAIDivR_Factor
86 * @{
87 */
88 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
89 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
90 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
91 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
92 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
93 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
94 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
95 ((VALUE) == RCC_PLLSAIDivR_Div16))
96 /**
97 * @}
98 */
99
100 /** @defgroup RCC_PLL_Clock_Source
101 * @{
102 */
103 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
104 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
105 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
106 ((SOURCE) == RCC_PLLSource_HSE))
107 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
108 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
109 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
110 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
111 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
112 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
113 #endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
114
115 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
116 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
117 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
118 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
119 #if defined(STM32F446xx)
120 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
121 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
122 #elif defined(STM32F412xG)
123 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
124 #else
125 #endif /* STM32F446xx */
126 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
127 #if defined(STM32F446xx) || defined(STM32F469_479xx)
128 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
129 #endif /* STM32F446xx || STM32F469_479xx */
130 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
131 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
132
133 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
134 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
135 /**
136 * @}
137 */
138
139 /** @defgroup RCC_System_Clock_Source
140 * @{
141 */
142
143 #if defined(STM32F412xG) || defined(STM32F446xx)
144 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
145 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
146 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
147 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
148 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
149 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
150 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
151 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
152 /* Add legacy definition */
153 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
154 #endif /* STM32F446xx */
155
156 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
157 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
158 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
159 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
160 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
161 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
162 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
163 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
164 /**
165 * @}
166 */
167
168 /** @defgroup RCC_AHB_Clock_Source
169 * @{
170 */
171 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
172 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
173 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
174 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
175 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
176 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
177 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
178 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
179 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
180 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
181 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
182 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
183 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
184 ((HCLK) == RCC_SYSCLK_Div512))
185 /**
186 * @}
187 */
188
189 /** @defgroup RCC_APB1_APB2_Clock_Source
190 * @{
191 */
192 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
193 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
194 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
195 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
196 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
197 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
198 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
199 ((PCLK) == RCC_HCLK_Div16))
200 /**
201 * @}
202 */
203
204 /** @defgroup RCC_Interrupt_Source
205 * @{
206 */
207 #define RCC_IT_LSIRDY ((uint8_t)0x01)
208 #define RCC_IT_LSERDY ((uint8_t)0x02)
209 #define RCC_IT_HSIRDY ((uint8_t)0x04)
210 #define RCC_IT_HSERDY ((uint8_t)0x08)
211 #define RCC_IT_PLLRDY ((uint8_t)0x10)
212 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
213 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
214 #define RCC_IT_CSS ((uint8_t)0x80)
215
216 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
217 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
218 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
219 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
220 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
221 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
222
223 /**
224 * @}
225 */
226
227 /** @defgroup RCC_LSE_Configuration
228 * @{
229 */
230 #define RCC_LSE_OFF ((uint8_t)0x00)
231 #define RCC_LSE_ON ((uint8_t)0x01)
232 #define RCC_LSE_Bypass ((uint8_t)0x04)
233 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
234 ((LSE) == RCC_LSE_Bypass))
235 /**
236 * @}
237 */
238
239 /** @defgroup RCC_RTC_Clock_Source
240 * @{
241 */
242 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
243 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
244 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
245 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
246 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
247 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
248 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
249 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
250 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
251 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
252 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
253 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
254 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
255 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
256 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
257 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
258 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
259 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
260 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
261 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
262 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
263 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
264 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
265 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
266 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
267 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
268 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
269 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
270 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
271 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
272 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
273 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
274 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
275 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
276 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
277 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
278 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
279 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
280 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
303 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
304 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
305 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
306 /**
307 * @}
308 */
309
310 #if defined(STM32F410xx)
311 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
312 * @{
313 */
314 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
315 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
316 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
317 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
318
319 #define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
320 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
321 /* Legacy Defines */
322 #define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
323 /**
324 * @}
325 */
326
327 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
328 * @{
329 */
330 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
331 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
332 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
333 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
334 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
335 /**
336 * @}
337 */
338
339 #endif /* STM32F410xx */
340
341 #if defined(STM32F412xG) || defined(STM32F446xx)
342 /** @defgroup RCC_I2S_Clock_Source
343 * @{
344 */
345 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
346 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
347 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
348 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
349
350 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
351 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
352 /**
353 * @}
354 */
355
356 /** @defgroup RCC_I2S_APBBus
357 * @{
358 */
359 #define RCC_I2SBus_APB1 ((uint8_t)0x00)
360 #define RCC_I2SBus_APB2 ((uint8_t)0x01)
361 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
362 /**
363 * @}
364 */
365 #if defined(STM32F446xx)
366 /** @defgroup RCC_SAI_Clock_Source
367 * @{
368 */
369 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
370 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
371 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
372 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
373
374 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
375 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
376 /**
377 * @}
378 */
379
380 /** @defgroup RCC_SAI_Instance
381 * @{
382 */
383 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
384 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
385 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
386 /**
387 * @}
388 */
389 #endif /* STM32F446xx */
390 #endif /* STM32F412xG || STM32F446xx */
391
392 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
393 /** @defgroup RCC_I2S_Clock_Source
394 * @{
395 */
396 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
397 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
398
399 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
400 /**
401 * @}
402 */
403
404 /** @defgroup RCC_SAI_BlockA_Clock_Source
405 * @{
406 */
407 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
408 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
409 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
410
411 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
412 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
413 ((SOURCE) == RCC_SAIACLKSource_Ext))
414 /**
415 * @}
416 */
417
418 /** @defgroup RCC_SAI_BlockB_Clock_Source
419 * @{
420 */
421 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
422 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
423 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
424
425 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
426 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
427 ((SOURCE) == RCC_SAIBCLKSource_Ext))
428 /**
429 * @}
430 */
431 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
432
433 /** @defgroup RCC_TIM_PRescaler_Selection
434 * @{
435 */
436 #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
437 #define RCC_TIMPrescActivated ((uint8_t)0x01)
438
439 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
440 /**
441 * @}
442 */
443
444 #if defined(STM32F469_479xx)
445 /** @defgroup RCC_DSI_Clock_Source_Selection
446 * @{
447 */
448 #define RCC_DSICLKSource_PHY ((uint8_t)0x00)
449 #define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
450 #define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
451 ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
452 /**
453 * @}
454 */
455 #endif /* STM32F469_479xx */
456
457 #if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
458 /** @defgroup RCC_SDIO_Clock_Source_Selection
459 * @{
460 */
461 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
462 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
463 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
464 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
465 /**
466 * @}
467 */
468
469
470 /** @defgroup RCC_48MHZ_Clock_Source_Selection
471 * @{
472 */
473 #if defined(STM32F446xx) || defined(STM32F469_479xx)
474 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
475 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
476 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
477 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
478 #endif /* STM32F446xx || STM32F469_479xx */
479 #if defined(STM32F412xG)
480 #define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
481 #define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */
482 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
483 ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
484 #endif /* STM32F412xG */
485 /**
486 * @}
487 */
488 #endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
489
490 #if defined(STM32F446xx)
491 /** @defgroup RCC_SPDIFRX_Clock_Source_Selection
492 * @{
493 */
494 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
495 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
496 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
497 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
498 /**
499 * @}
500 */
501
502 /** @defgroup RCC_CEC_Clock_Source_Selection
503 * @{
504 */
505 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
506 #define RCC_CECCLKSource_LSE ((uint8_t)0x01)
507 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
508 ((CLKSOURCE) == RCC_CECCLKSource_LSE))
509 /**
510 * @}
511 */
512
513 /** @defgroup RCC_AHB1_ClockGating
514 * @{
515 */
516 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
517 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
518 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
519 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
520 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
521 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
522 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
523
524 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
525
526 /**
527 * @}
528 */
529 #endif /* STM32F446xx */
530
531 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
532 /** @defgroup RCC_FMPI2C1_Clock_Source
533 * @{
534 */
535 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
536 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
537 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
538
539 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
540 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
541 /**
542 * @}
543 */
544 #endif /* STM32F410xx || STM32F412xG || STM32F446xx */
545
546 #if defined(STM32F412xG)
547 /** @defgroup RCC_DFSDM_Clock_Source
548 * @{
549 */
550 #define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00)
551 #define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01)
552 #define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
553 /**
554 * @}
555 */
556
557 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
558 * @{
559 */
560 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
561 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
562 #define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
563 /**
564 * @}
565 */
566 #endif /* STM32F412xG */
567
568 /** @defgroup RCC_AHB1_Peripherals
569 * @{
570 */
571 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
572 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
573 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
574 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
575 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
576 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
577 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
578 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
579 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
580 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
581 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
582 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
583 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
584 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
585 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
586 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
587 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
588 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
589 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
590 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
591 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
592 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
593 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
594 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
595 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
596 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
597 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
598 #if defined(STM32F410xx)
599 #define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
600 #endif /* STM32F410xx */
601 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
602 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
603 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
604
605 /**
606 * @}
607 */
608
609 /** @defgroup RCC_AHB2_Peripherals
610 * @{
611 */
612 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
613 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
614 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
615 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
616 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
617 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
618 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
619 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
620 /**
621 * @}
622 */
623
624 /** @defgroup RCC_AHB3_Peripherals
625 * @{
626 */
627 #if defined(STM32F40_41xxx)
628 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
629 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
630 #endif /* STM32F40_41xxx */
631
632 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
633 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
634 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
635 #endif /* STM32F427_437xx || STM32F429_439xx */
636
637 #if defined(STM32F446xx) || defined(STM32F469_479xx)
638 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
639 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
640 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
641 #endif /* STM32F446xx || STM32F469_479xx */
642
643 #if defined(STM32F412xG)
644 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
645 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
646 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
647 #endif /* STM32F412xG */
648
649 /**
650 * @}
651 */
652
653 /** @defgroup RCC_APB1_Peripherals
654 * @{
655 */
656 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
657 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
658 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
659 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
660 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
661 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
662 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
663 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
664 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
665 #if defined(STM32F410xx)
666 #define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
667 #endif /* STM32F410xx */
668 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
669 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
670 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
671 #if defined(STM32F446xx)
672 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
673 #endif /* STM32F446xx */
674 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
675 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
676 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
677 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
678 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
679 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
680 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
681 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
682 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
683 #endif /* STM32F410xx || STM32F446xx */
684 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
685 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
686 #if defined(STM32F446xx)
687 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
688 #endif /* STM32F446xx */
689 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
690 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
691 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
692 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
693 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
694 /**
695 * @}
696 */
697
698 /** @defgroup RCC_APB2_Peripherals
699 * @{
700 */
701 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
702 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
703 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
704 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
705 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
706 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
707 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
708 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
709 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
710 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
711 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
712 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
713 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
714 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
715 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
716 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
717 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
718 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
719 #if defined(STM32F446xx) || defined(STM32F469_479xx)
720 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
721 #endif /* STM32F446xx || STM32F469_479xx */
722 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
723 #if defined(STM32F469_479xx)
724 #define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
725 #endif /* STM32F469_479xx */
726 #if defined(STM32F412xG)
727 #define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000)
728 #endif /* STM32F412xG */
729
730 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
731 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
732
733 /**
734 * @}
735 */
736
737 /** @defgroup RCC_MCO1_Clock_Source_Prescaler
738 * @{
739 */
740 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
741 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
742 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
743 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
744 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
745 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
746 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
747 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
748 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
749 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
750 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
751
752 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
753 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
754 ((DIV) == RCC_MCO1Div_5))
755 /**
756 * @}
757 */
758
759 /** @defgroup RCC_MCO2_Clock_Source_Prescaler
760 * @{
761 */
762 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
763 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
764 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
765 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
766 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
767 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
768 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
769 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
770 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
771 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
772 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
773
774 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
775 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
776 ((DIV) == RCC_MCO2Div_5))
777 /**
778 * @}
779 */
780
781 /** @defgroup RCC_Flag
782 * @{
783 */
784 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
785 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
786 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
787 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
788 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
789 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
790 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
791 #define RCC_FLAG_BORRST ((uint8_t)0x79)
792 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
793 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
794 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
795 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
796 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
797 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
798
799 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
800 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
801 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
802 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
803 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
804 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
805 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
806
807 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
808 /**
809 * @}
810 */
811
812 /**
813 * @}
814 */
815
816 /* Exported macro ------------------------------------------------------------*/
817 /* Exported functions --------------------------------------------------------*/
818
819 /* Function used to set the RCC clock configuration to the default reset state */
820 void RCC_DeInit(void);
821
822 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
823 void RCC_HSEConfig(uint8_t RCC_HSE);
824 ErrorStatus RCC_WaitForHSEStartUp(void);
825 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
826 void RCC_HSICmd(FunctionalState NewState);
827 void RCC_LSEConfig(uint8_t RCC_LSE);
828 void RCC_LSICmd(FunctionalState NewState);
829
830 void RCC_PLLCmd(FunctionalState NewState);
831
832 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
833 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
834 #endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
835
836 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
837 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
838 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
839
840 void RCC_PLLI2SCmd(FunctionalState NewState);
841
842 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
843 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
844 #endif /* STM32F40_41xxx || STM32F401xx */
845 #if defined(STM32F411xE)
846 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
847 #endif /* STM32F411xE */
848 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
849 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
850 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
851 #if defined(STM32F412xG) || defined(STM32F446xx)
852 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
853 #endif /* STM32F412xG || STM32F446xx */
854
855 void RCC_PLLSAICmd(FunctionalState NewState);
856 #if defined(STM32F469_479xx)
857 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
858 #endif /* STM32F469_479xx */
859 #if defined(STM32F446xx)
860 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
861 #endif /* STM32F446xx */
862 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
863 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
864 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
865
866 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
867 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
868 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
869
870 /* System, AHB and APB busses clocks configuration functions ******************/
871 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
872 uint8_t RCC_GetSYSCLKSource(void);
873 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
874 void RCC_PCLK1Config(uint32_t RCC_HCLK);
875 void RCC_PCLK2Config(uint32_t RCC_HCLK);
876 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
877
878 /* Peripheral clocks configuration functions **********************************/
879 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
880 void RCC_RTCCLKCmd(FunctionalState NewState);
881 void RCC_BackupResetCmd(FunctionalState NewState);
882
883 #if defined(STM32F412xG) || defined(STM32F446xx)
884 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
885 #if defined(STM32F446xx)
886 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
887 #endif /* STM32F446xx */
888 #endif /* STM32F412xG || STM32F446xx */
889
890 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
891 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
892 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
893
894 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
895 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
896 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
897 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
898
899 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
900 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
901
902 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
903 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
904
905 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
906 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
907 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
908 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
909 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
910
911 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
912 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
913 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
914 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
915 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
916
917 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
918 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
919 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
920 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
921 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
922
923 /* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
924 void RCC_LSEModeConfig(uint8_t RCC_Mode);
925
926 /* Features available only for STM32F469_479xx devices */
927 #if defined(STM32F469_479xx)
928 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
929 #endif /* STM32F469_479xx */
930
931 /* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
932 #if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
933 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
934 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
935 #endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
936
937 /* Features available only for STM32F446xx devices */
938 #if defined(STM32F446xx)
939 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
940 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
941 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
942 #endif /* STM32F446xx */
943
944 /* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
945 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
946 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
947 #endif /* STM32F410xx || STM32F412xG || STM32F446xx */
948
949 /* Features available only for STM32F410xx devices */
950 #if defined(STM32F410xx)
951 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
952
953 void RCC_MCO1Cmd(FunctionalState NewState);
954 void RCC_MCO2Cmd(FunctionalState NewState);
955 #endif /* STM32F410xx */
956
957 #if defined(STM32F412xG)
958 void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
959 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
960 #endif /* STM32F412xG */
961 /* Interrupts and flags management functions **********************************/
962 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
963 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
964 void RCC_ClearFlag(void);
965 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
966 void RCC_ClearITPendingBit(uint8_t RCC_IT);
967
968 #ifdef __cplusplus
969 }
970 #endif
971
972 #endif /* __STM32F4xx_RCC_H */
973
974 /**
975 * @}
976 */
977
978 /**
979 * @}
980 */
981
982 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/