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duplicate emptyline removal (#14027)
[betaflight.git] / src / platform / AT32 / startup / at32f435_437.h
blob05b26f4ac54daf03dab807dfe8940a14c5ea158f
1 /**
2 **************************************************************************
3 * @file at32f435_437.h
4 * @version v2.0.4
5 * @date 2021-12-31
6 * @brief at32f435_437 header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 #ifndef __AT32F435_437_H
28 #define __AT32F435_437_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 #if defined(__CC_ARM)
35 #pragma anon_unions
36 #endif
37
38 /** @addtogroup CMSIS
39 * @{
40 */
41
42 /** @addtogroup AT32F435_437
43 * @{
44 */
45
46 /** @addtogroup Library_configuration_section
47 * @{
48 */
49
50 /**
51 * tip: to avoid modifying this file each time you need to switch between these
52 * devices, you can define the device in your toolchain compiler preprocessor.
53 */
54
55 #if !defined(AT32F435CCU7) && !defined(AT32F435CGU7) && !defined(AT32F435CMU7) && \
56 !defined(AT32F435CCT7) && !defined(AT32F435CGT7) && !defined(AT32F435CMT7) && \
57 !defined(AT32F435RCT7) && !defined(AT32F435RGT7) && !defined(AT32F435RMT7) && \
58 !defined(AT32F435VCT7) && !defined(AT32F435VGT7) && !defined(AT32F435VMT7) && \
59 !defined(AT32F435ZCT7) && !defined(AT32F435ZGT7) && !defined(AT32F435ZMT7) && \
60 !defined(AT32F437RCT7) && !defined(AT32F437RGT7) && !defined(AT32F437RMT7) && \
61 !defined(AT32F437VCT7) && !defined(AT32F437VGT7) && !defined(AT32F437VMT7) && \
62 !defined(AT32F437ZCT7) && !defined(AT32F437ZGT7) && !defined(AT32F437ZMT7)
63
64 #error "Please select first the target device used in your application (in at32f435_437.h file)"
65 #endif
66
67 #if defined(AT32F435CCU7) || defined(AT32F435CGU7) || defined(AT32F435CMU7) || \
68 defined(AT32F435CCT7) || defined(AT32F435CGT7) || defined(AT32F435CMT7) || \
69 defined(AT32F435RCT7) || defined(AT32F435RGT7) || defined(AT32F435RMT7) || \
70 defined(AT32F435VCT7) || defined(AT32F435VGT7) || defined(AT32F435VMT7) || \
71 defined(AT32F435ZCT7) || defined(AT32F435ZGT7) || defined(AT32F435ZMT7)
72
73 #define AT32F435xx
74 #endif
75
76 #if defined(AT32F437RCT7) || defined(AT32F437RGT7) || defined(AT32F437RMT7) || \
77 defined(AT32F437VCT7) || defined(AT32F437VGT7) || defined(AT32F437VMT7) || \
78 defined(AT32F437ZCT7) || defined(AT32F437ZGT7) || defined(AT32F437ZMT7)
79
80 #define AT32F437xx
81 #endif
82
83 #ifndef USE_STDPERIPH_DRIVER
84 /**
85 * @brief comment the line below if you will not use the peripherals drivers.
86 * in this case, these drivers will not be included and the application code will
87 * be based on direct access to peripherals registers
88 */
89 #ifdef _RTE_
90 #include "RTE_Components.h"
91 #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
92 #define USE_STDPERIPH_DRIVER
93 #endif
94 #endif
95 #endif
96
97 /**
98 * @brief at32f435_437 standard peripheral library version number
99 */
100 #define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
101 #define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
102 #define __AT32F435_437_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
103 #define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
104 #define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
105 (__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
106 (__AT32F435_437_LIBRARY_VERSION_MINOR << 8) | \
107 (__AT32F435_437_LIBRARY_VERSION_RC))
108
109 /**
110 * @}
111 */
112
113 /** @addtogroup configuration_section_for_cmsis
114 * @{
115 */
116
117 /**
118 * @brief configuration of the cortex-m4 processor and core peripherals
119 */
120 #define __CM4_REV 0x0001U /*!< core revision r0p1 */
121 #define __MPU_PRESENT 1 /*!< mpu present */
122 #define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
123 #define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
124 #define __FPU_PRESENT 1U /*!< fpu present */
125
126 /**
127 * @brief at32f435_437 interrupt number definition, according to the selected device
128 * in @ref library_configuration_section
129 */
130 typedef enum IRQn
131 {
132 /****** cortex-m4 processor exceptions numbers ***************************************************/
133 Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
134 NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
135 HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
136 MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
137 BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
138 UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
139 SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
140 DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
141 PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
142 SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
143
144 /****** at32 specific interrupt numbers *********************************************************/
145 WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
146 PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
147 TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */
148 ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */
149 FLASH_IRQn = 4, /*!< flash global interrupt */
150 CRM_IRQn = 5, /*!< crm global interrupt */
151 EXINT0_IRQn = 6, /*!< exint line0 interrupt */
152 EXINT1_IRQn = 7, /*!< exint line1 interrupt */
153 EXINT2_IRQn = 8, /*!< exint line2 interrupt */
154 EXINT3_IRQn = 9, /*!< exint line3 interrupt */
155 EXINT4_IRQn = 10, /*!< exint line4 interrupt */
156 EDMA_Stream1_IRQn = 11, /*!< edma stream 1 global interrupt */
157 EDMA_Stream2_IRQn = 12, /*!< edma stream 2 global interrupt */
158 EDMA_Stream3_IRQn = 13, /*!< edma stream 3 global interrupt */
159 EDMA_Stream4_IRQn = 14, /*!< edma stream 4 global interrupt */
160 EDMA_Stream5_IRQn = 15, /*!< edma stream 5 global interrupt */
161 EDMA_Stream6_IRQn = 16, /*!< edma stream 6 global interrupt */
162 EDMA_Stream7_IRQn = 17, /*!< edma stream 7 global interrupt */
163
164 #if defined(AT32F435xx)
165 ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
166 CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
167 CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
168 CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
169 CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
170 EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
171 TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
172 TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
173 TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
174 TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
175 TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
176 TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
177 TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
178 I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
179 I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
180 I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
181 I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
182 SPI1_IRQn = 35, /*!< spi1 global interrupt */
183 SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
184 USART1_IRQn = 37, /*!< usart1 global interrupt */
185 USART2_IRQn = 38, /*!< usart2 global interrupt */
186 USART3_IRQn = 39, /*!< usart3 global interrupt */
187 EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
188 ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
189 OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
190 TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
191 TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
192 TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
193 TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
194 EDMA_Stream8_IRQn = 47, /*!< edma stream 8 global interrupt */
195 XMC_IRQn = 48, /*!< xmc global interrupt */
196 SDIO1_IRQn = 49, /*!< sdio global interrupt */
197 TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
198 SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
199 UART4_IRQn = 52, /*!< uart4 global interrupt */
200 UART5_IRQn = 53, /*!< uart5 global interrupt */
201 TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
202 TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
203 DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
204 DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
205 DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
206 DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
207 DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
208 CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
209 CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
210 CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
211 CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
212 OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
213 DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
214 DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
215 USART6_IRQn = 71, /*!< usart6 interrupt */
216 I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
217 I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
218 OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
219 OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
220 DVP_IRQn = 78, /*!< dvp interrupt */
221 FPU_IRQn = 81, /*!< fpu interrupt */
222 UART7_IRQn = 82, /*!< uart7 interrupt */
223 UART8_IRQn = 83, /*!< uart8 interrupt */
224 SPI4_IRQn = 84, /*!< spi4 global interrupt */
225 QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
226 QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
227 DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
228 SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
229 ACC_IRQn = 103, /*!< acc interrupt */
230 TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
231 TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
232 TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
233 TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
234 DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
235 DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
236 DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
237 DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
238 DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
239 DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
240 DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
241 #endif
242
243 #if defined(AT32F437xx)
244 ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
245 CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
246 CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
247 CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
248 CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
249 EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
250 TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
251 TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
252 TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
253 TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
254 TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
255 TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
256 TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
257 I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
258 I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
259 I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
260 I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
261 SPI1_IRQn = 35, /*!< spi1 global interrupt */
262 SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
263 USART1_IRQn = 37, /*!< usart1 global interrupt */
264 USART2_IRQn = 38, /*!< usart2 global interrupt */
265 USART3_IRQn = 39, /*!< usart3 global interrupt */
266 EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
267 ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
268 OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
269 TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
270 TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
271 TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
272 TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
273 EDMA_Stream8_IRQn = 47, /*!< dma1 stream 8 global interrupt */
274 XMC_IRQn = 48, /*!< xmc global interrupt */
275 SDIO1_IRQn = 49, /*!< sdio global interrupt */
276 TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
277 SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
278 UART4_IRQn = 52, /*!< uart4 global interrupt */
279 UART5_IRQn = 53, /*!< uart5 global interrupt */
280 TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
281 TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
282 DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
283 DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
284 DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
285 DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
286 DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
287 EMAC_IRQn = 61, /*!< emac interrupt */
288 EMAC_WKUP_IRQn = 62, /*!< emac wakeup interrupt */
289 CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
290 CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
291 CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
292 CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
293 OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
294 DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
295 DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
296 USART6_IRQn = 71, /*!< usart6 interrupt */
297 I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
298 I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
299 OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
300 OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
301 DVP_IRQn = 78, /*!< dvp interrupt */
302 FPU_IRQn = 81, /*!< fpu interrupt */
303 UART7_IRQn = 82, /*!< uart7 interrupt */
304 UART8_IRQn = 83, /*!< uart8 interrupt */
305 SPI4_IRQn = 84, /*!< spi4 global interrupt */
306 QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
307 QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
308 DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
309 SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
310 ACC_IRQn = 103, /*!< acc interrupt */
311 TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
312 TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
313 TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
314 TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
315 DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
316 DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
317 DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
318 DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
319 DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
320 DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
321 DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
322 #endif
323
324 } IRQn_Type;
325
326 /**
327 * @}
328 */
329
330 #include "core_cm4.h"
331 #include "system_at32f435_437.h"
332 #include <stdint.h>
333
334 /** @addtogroup Exported_types
335 * @{
336 */
337
338 typedef int32_t INT32;
339 typedef int16_t INT16;
340 typedef int8_t INT8;
341 typedef uint32_t UINT32;
342 typedef uint16_t UINT16;
343 typedef uint8_t UINT8;
344
345 typedef int32_t s32;
346 typedef int16_t s16;
347 typedef int8_t s8;
348
349 typedef const int32_t sc32; /*!< read only */
350 typedef const int16_t sc16; /*!< read only */
351 typedef const int8_t sc8; /*!< read only */
352
353 typedef __IO int32_t vs32;
354 typedef __IO int16_t vs16;
355 typedef __IO int8_t vs8;
356
357 typedef __I int32_t vsc32; /*!< read only */
358 typedef __I int16_t vsc16; /*!< read only */
359 typedef __I int8_t vsc8; /*!< read only */
360
361 typedef uint32_t u32;
362 typedef uint16_t u16;
363 typedef uint8_t u8;
364
365 typedef const uint32_t uc32; /*!< read only */
366 typedef const uint16_t uc16; /*!< read only */
367 typedef const uint8_t uc8; /*!< read only */
368
369 typedef __IO uint32_t vu32;
370 typedef __IO uint16_t vu16;
371 typedef __IO uint8_t vu8;
372
373 typedef __I uint32_t vuc32; /*!< read only */
374 typedef __I uint16_t vuc16; /*!< read only */
375 typedef __I uint8_t vuc8; /*!< read only */
376
377 typedef enum {RESET = 0, SET = !RESET} flag_status;
378 typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
379 typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
380
381 /**
382 * @}
383 */
384
385 /** @addtogroup Exported_macro
386 * @{
387 */
388
389 #define REG8(addr) *(volatile uint8_t *)(addr)
390 #define REG16(addr) *(volatile uint16_t *)(addr)
391 #define REG32(addr) *(volatile uint32_t *)(addr)
392
393 #define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f))
394
395 #define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
396 #define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f))
397
398 /**
399 * @}
400 */
401
402 /** @addtogroup Peripheral_memory_map
403 * @{
404 */
405
406 #define XMC_SDRAM_MEM_BASE ((uint32_t)0xC0000000)
407 #define QSPI2_MEM_BASE ((uint32_t)0xB0000000)
408 #define XMC_CARD_MEM_BASE ((uint32_t)0xA8000000)
409 #define QSPI2_REG_BASE ((uint32_t)0xA0002000)
410 #define QSPI1_REG_BASE ((uint32_t)0xA0001000)
411 #define XMC_REG_BASE ((uint32_t)0xA0000000)
412 #define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
413 #define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
414 #define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
415 #define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
416 #define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
417 #define QSPI1_MEM_BASE ((uint32_t)0x90000000)
418 #define XMC_MEM_BASE ((uint32_t)0x60000000)
419 #define PERIPH_BASE ((uint32_t)0x40000000)
420 #define SRAM_BB_BASE ((uint32_t)0x22000000)
421 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
422 #define SRAM_BASE ((uint32_t)0x20000000)
423 #define USD_BASE ((uint32_t)0x1FFFC000)
424 #define FLASH_BASE ((uint32_t)0x08000000)
425
426 #define DEBUG_BASE ((uint32_t)0xE0042000)
427
428 #define APB1PERIPH_BASE (PERIPH_BASE)
429 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
430 #define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
431 #define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000)
432
433 #if defined(AT32F435xx)
434 /* apb1 bus base address */
435 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
436 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
437 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
438 #define PWC_BASE (APB1PERIPH_BASE + 0x7000)
439 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
440 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
441 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
442 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
443 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
444 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
445 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
446 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
447 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
448 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
449 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
450 #define WDT_BASE (APB1PERIPH_BASE + 0x3000)
451 #define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
452 #define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
453 #define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
454 #define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
455 #define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
456 #define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
457 #define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
458 #define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
459 #define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
460 #define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
461 #define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
462 /* apb2 bus base address */
463 #define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
464 #define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
465 #define ACC_BASE (APB2PERIPH_BASE + 0x7400)
466 #define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
467 #define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
468 #define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
469 #define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
470 #define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
471 #define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
472 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
473 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
474 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
475 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
476 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
477 #define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
478 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
479 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
480 #define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
481 #define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
482 /* ahb bus base address */
483 #define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
484 #define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
485 #define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
486 #define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
487 #define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
488 #define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
489 #define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
490 #define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
491 #define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
492 #define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
493
494 #define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
495 #define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
496 #define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
497 #define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
498 #define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
499 #define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
500 #define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
501 #define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
502
503 #define DMA1MUX_BASE (DMA1_BASE + 0x0104)
504 #define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
505 #define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
506 #define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
507 #define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
508 #define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
509 #define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
510 #define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
511
512 #define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
513 #define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
514 #define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
515 #define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
516
517 #define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
518 #define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
519 #define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
520 #define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
521 #define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
522 #define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
523 #define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
524 #define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
525
526 #define DMA2MUX_BASE (DMA2_BASE + 0x0104)
527 #define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
528 #define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
529 #define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
530 #define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
531 #define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
532 #define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
533 #define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
534
535 #define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
536 #define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
537 #define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
538 #define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
539
540 #define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
541 #define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
542 #define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
543 #define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
544 #define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
545 #define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
546 #define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
547 #define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
548 #define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
549
550 #define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
551 #define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
552 #define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
553 #define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
554 #define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
555 #define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
556 #define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
557 #define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
558 #define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
559
560 #define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
561 #define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
562 #define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
563 #define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
564 #define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
565 #define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
566 #define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
567 #define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
568 #define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
569
570 #define EDMAMUX_BASE (EDMA_BASE + 0x0140)
571 #define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
572 #define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
573 #define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
574 #define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
575 #define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
576 #define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
577 #define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
578 #define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
579
580 #define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
581 #define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
582 #define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
583 #define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
584
585 #define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
586 #define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
587 #define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
588 #define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
589 #define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
590 #define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
591 #endif
592
593 #if defined(AT32F437xx)
594 /* apb1 bus base address */
595 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
596 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
597 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
598 #define PWC_BASE (APB1PERIPH_BASE + 0x7000)
599 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
600 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
601 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
602 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
603 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
604 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
605 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
606 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
607 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
608 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
609 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
610 #define WDT_BASE (APB1PERIPH_BASE + 0x3000)
611 #define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
612 #define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
613 #define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
614 #define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
615 #define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
616 #define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
617 #define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
618 #define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
619 #define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
620 #define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
621 #define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
622 /* apb2 bus base address */
623 #define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
624 #define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
625 #define ACC_BASE (APB2PERIPH_BASE + 0x7400)
626 #define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
627 #define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
628 #define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
629 #define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
630 #define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
631 #define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
632 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
633 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
634 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
635 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
636 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
637 #define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
638 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
639 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
640 #define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
641 #define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
642 /* ahb bus base address */
643 #define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
644 #define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
645 #define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
646 #define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
647 #define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
648 #define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
649 #define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
650 #define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
651 #define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
652 #define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
653 #define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
654
655 #define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
656 #define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
657 #define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
658 #define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
659 #define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
660 #define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
661 #define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
662 #define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
663
664 #define DMA1MUX_BASE (DMA1_BASE + 0x0104)
665 #define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
666 #define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
667 #define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
668 #define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
669 #define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
670 #define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
671 #define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
672
673 #define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
674 #define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
675 #define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
676 #define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
677
678 #define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
679 #define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
680 #define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
681 #define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
682 #define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
683 #define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
684 #define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
685 #define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
686
687 #define DMA2MUX_BASE (DMA2_BASE + 0x0104)
688 #define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
689 #define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
690 #define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
691 #define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
692 #define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
693 #define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
694 #define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
695
696 #define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
697 #define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
698 #define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
699 #define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
700
701 #define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
702 #define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
703 #define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
704 #define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
705 #define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
706 #define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
707 #define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
708 #define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
709 #define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
710
711 #define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
712 #define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
713 #define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
714 #define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
715 #define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
716 #define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
717 #define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
718 #define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
719 #define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
720
721 #define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
722 #define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
723 #define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
724 #define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
725 #define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
726 #define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
727 #define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
728 #define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
729 #define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
730
731 #define EDMAMUX_BASE (EDMA_BASE + 0x0140)
732 #define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
733 #define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
734 #define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
735 #define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
736 #define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
737 #define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
738 #define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
739 #define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
740
741 #define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
742 #define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
743 #define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
744 #define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
745
746 #define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
747 #define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
748 #define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
749 #define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
750 #define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
751 #define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
752
753 #define EMAC_MAC_BASE (EMAC_BASE)
754 #define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
755 #define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
756 #define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
757 #endif
758
759 /**
760 * @}
761 */
762
763 /**
764 * @}
765 */
766
767 /**
768 * @}
769 */
770
771 #include "at32f435_437_def.h"
772 #include "at32f435_437_conf.h"
773
774 #ifdef __cplusplus
775 }
776 #endif
777
778 #endif