src/platform/STM32/bus_octospi_stm32h7xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * Author: Dominic Clifton
  21  */
  22
  23 /*
  24  *
  25  */
  26 #include <stdbool.h>
  27 #include <stdint.h>
  28 #include <string.h>
  29
  30 #include "platform.h"
  31
  32 #ifdef USE_OCTOSPI
  33
  34 #include "drivers/system.h"
  35
  36 #include "drivers/bus_octospi.h"
  37 #include "drivers/bus_octospi_impl.h"
  38
  39 #if !(defined(STM32H730xx) || defined(STM32H723xx))
  40 #error MCU not supported.
  41 #endif
  42
  43 #define OCTOSPI_INTERFACE_COUNT         1
  44
  45 #define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
  46 #define OSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)OCTOSPI_CR_FMODE_0)
  47 #define OSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)OCTOSPI_CR_FMODE_1)
  48 #define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)OCTOSPI_CR_FMODE)
  49
  50 #define OSPI_DHQC_DISABLE                ((uint32_t)0x00000000U)
  51 #define OSPI_DHQC_ENABLE                 ((uint32_t)OCTOSPI_TCR_DHQC)
  52
  53 #define OSPI_OPTYPE_COMMON_CFG           ((uint32_t)0x00000000U)
  54
  55 #define OSPI_OPTYPE_READ_CFG             ((uint32_t)0x00000001U)
  56 #define OSPI_OPTYPE_WRITE_CFG            ((uint32_t)0x00000002U)
  57 #define OSPI_OPTYPE_WRAP_CFG             ((uint32_t)0x00000003U)
  58
  59 #define OSPI_INSTRUCTION_NONE            ((uint32_t)0x00000000U)
  60 #define OSPI_INSTRUCTION_1_LINE          ((uint32_t)OCTOSPI_CCR_IMODE_0)
  61 #define OSPI_INSTRUCTION_2_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_1)
  62 #define OSPI_INSTRUCTION_4_LINES         ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))
  63 #define OSPI_INSTRUCTION_8_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_2)
  64
  65 #define OSPI_INSTRUCTION_8_BITS          ((uint32_t)0x00000000U)
  66 #define OSPI_INSTRUCTION_16_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_0)
  67 #define OSPI_INSTRUCTION_24_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_1)
  68 #define OSPI_INSTRUCTION_32_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE)
  69
  70 #define OSPI_INSTRUCTION_DTR_DISABLE     ((uint32_t)0x00000000U)
  71 #define OSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)OCTOSPI_CCR_IDTR)
  72
  73 #define OSPI_ADDRESS_NONE                ((uint32_t)0x00000000U)                                         /*!< No address               */
  74 #define OSPI_ADDRESS_1_LINE              ((uint32_t)OCTOSPI_CCR_ADMODE_0)                                /*!< Address on a single line */
  75 #define OSPI_ADDRESS_2_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_1)                                /*!< Address on two lines     */
  76 #define OSPI_ADDRESS_4_LINES             ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))       /*!< Address on four lines    */
  77 #define OSPI_ADDRESS_8_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_2)                                /*!< Address on eight lines   */
  78
  79 #define OSPI_ADDRESS_8_BITS              ((uint32_t)0x00000000U)                                         /*!< 8-bit address  */
  80 #define OSPI_ADDRESS_16_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_0)                                /*!< 16-bit address */
  81 #define OSPI_ADDRESS_24_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_1)                                /*!< 24-bit address */
  82 #define OSPI_ADDRESS_32_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE)                                  /*!< 32-bit address */
  83
  84 #define OSPI_ADDRESS_DTR_DISABLE         ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for address phase */
  85 #define OSPI_ADDRESS_DTR_ENABLE          ((uint32_t)OCTOSPI_CCR_ADDTR)
  86
  87 #define OSPI_DATA_NONE                   ((uint32_t)0x00000000U)
  88 #define OSPI_DATA_1_LINE                 ((uint32_t)OCTOSPI_CCR_DMODE_0)
  89 #define OSPI_DATA_2_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_1)
  90 #define OSPI_DATA_4_LINES                ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))
  91 #define OSPI_DATA_8_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_2)
  92
  93 #define OSPI_DATA_DTR_DISABLE            ((uint32_t)0x00000000U)
  94 #define OSPI_DATA_DTR_ENABLE             ((uint32_t)OCTOSPI_CCR_DDTR)
  95
  96 #define OSPI_ALTERNATE_BYTES_NONE        ((uint32_t)0x00000000U)
  97 #define OSPI_ALTERNATE_BYTES_1_LINE      ((uint32_t)OCTOSPI_CCR_ABMODE_0)
  98 #define OSPI_ALTERNATE_BYTES_2_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_1)
  99 #define OSPI_ALTERNATE_BYTES_4_LINES     ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))
 100 #define OSPI_ALTERNATE_BYTES_8_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_2)
 101
 102 #define OSPI_ALTERNATE_BYTES_8_BITS      ((uint32_t)0x00000000U)
 103 #define OSPI_ALTERNATE_BYTES_16_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_0)
 104 #define OSPI_ALTERNATE_BYTES_24_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_1)
 105 #define OSPI_ALTERNATE_BYTES_32_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE)
 106
 107 #define OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)
 108 #define OSPI_ALTERNATE_BYTES_DTR_ENABLE  ((uint32_t)OCTOSPI_CCR_ABDTR)
 109
 110 #define OSPI_DQS_DISABLE                 ((uint32_t)0x00000000U)
 111 #define OSPI_DQS_ENABLE                  ((uint32_t)OCTOSPI_CCR_DQSE)
 112
 113 #define OSPI_SIOO_INST_EVERY_CMD         ((uint32_t)0x00000000U)
 114 #define OSPI_SIOO_INST_ONLY_FIRST_CMD    ((uint32_t)OCTOSPI_CCR_SIOO)
 115
 116 MMFLASH_CODE_NOINLINE static void Error_Handler(void) {
 117     while (1) {
 118         NOOP;
 119     }
 120 }
 121
 122 #define __OSPI_GET_FLAG(__INSTANCE__, __FLAG__)           ((READ_BIT((__INSTANCE__)->SR, (__FLAG__)) != 0U) ? SET : RESET)
 123 #define __OSPI_CLEAR_FLAG(__INSTANCE__, __FLAG__)           WRITE_REG((__INSTANCE__)->FCR, (__FLAG__))
 124 #define __OSPI_ENABLE(__INSTANCE__)                       SET_BIT((__INSTANCE__)->CR, OCTOSPI_CR_EN)
 125 #define __OSPI_DISABLE(__INSTANCE__)                      CLEAR_BIT((__INSTANCE__)->CR, OCTOSPI_CR_EN)
 126 #define __OSPI_IS_ENABLED(__INSTANCE__)                   (READ_BIT((__INSTANCE__)->CR, OCTOSPI_CR_EN) != 0U)
 127
 128 MMFLASH_CODE_NOINLINE static void octoSpiAbort(OCTOSPI_TypeDef *instance)
 129 {
 130     SET_BIT(instance->CR, OCTOSPI_CR_ABORT);
 131 }
 132
 133 MMFLASH_CODE_NOINLINE static void octoSpiWaitStatusFlags(OCTOSPI_TypeDef *instance, uint32_t mask, FlagStatus flagStatus)
 134 {
 135     uint32_t regval;
 136
 137     switch (flagStatus) {
 138     case SET:
 139         while (!((regval = READ_REG(instance->SR)) & mask))
 140             {}
 141         break;
 142     case RESET:
 143         while (((regval = READ_REG(instance->SR)) & mask))
 144             {}
 145         break;
 146     }
 147 }
 148
 149 typedef struct {
 150     uint32_t OperationType;
 151
 152     uint32_t Instruction;
 153     uint32_t InstructionMode;
 154     uint32_t InstructionSize;
 155     uint32_t InstructionDtrMode;
 156
 157     uint32_t Address;
 158     uint32_t AddressMode;
 159     uint32_t AddressSize;
 160     uint32_t AddressDtrMode;
 161
 162     uint32_t AlternateBytes;
 163     uint32_t AlternateBytesMode;
 164     uint32_t AlternateBytesSize;
 165     uint32_t AlternateBytesDtrMode;
 166
 167     uint32_t DummyCycles; // 0-31
 168
 169     uint32_t DataMode;
 170     uint32_t DataDtrMode;
 171     uint32_t NbData;
 172
 173     uint32_t DQSMode;
 174     uint32_t SIOOMode;
 175 } OSPI_Command_t;
 176
 177 // TODO rename cmd to command
 178 MMFLASH_CODE_NOINLINE static ErrorStatus octoSpiConfigureCommand(OCTOSPI_TypeDef *instance, OSPI_Command_t *cmd)
 179 {
 180     ErrorStatus status = SUCCESS;
 181
 182     MODIFY_REG(instance->CR, OCTOSPI_CR_FMODE, 0U);
 183
 184     instance->CCR = (cmd->DQSMode | cmd->SIOOMode);
 185
 186     if (cmd->AlternateBytesMode != OSPI_ALTERNATE_BYTES_NONE)
 187     {
 188         instance->ABR = cmd->AlternateBytes;
 189
 190         MODIFY_REG(
 191             instance->ABR,
 192             (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
 193             (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)
 194         );
 195     }
 196
 197     MODIFY_REG(instance->TCR, OCTOSPI_TCR_DCYC, cmd->DummyCycles);
 198
 199     if (cmd->DataMode != OSPI_DATA_NONE)
 200     {
 201       if (cmd->OperationType == OSPI_OPTYPE_COMMON_CFG)
 202       {
 203         instance->DLR = (cmd->NbData - 1U);
 204       }
 205     }
 206
 207     if (cmd->InstructionMode != OSPI_INSTRUCTION_NONE)
 208     {
 209       if (cmd->AddressMode != OSPI_ADDRESS_NONE)
 210       {
 211         if (cmd->DataMode != OSPI_DATA_NONE)
 212         {
 213           // instruction, address and data
 214
 215           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
 216                                   OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
 217                                   OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
 218                                  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
 219                                   cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize     |
 220                                   cmd->DataMode        | cmd->DataDtrMode));
 221         }
 222         else
 223         {
 224           // instruction and address
 225
 226           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
 227                                   OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
 228                                  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
 229                                   cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize));
 230
 231           // DHQC bit is linked with DDTR
 232           if (((instance->TCR & OCTOSPI_TCR_DHQC_Msk) == OSPI_DHQC_ENABLE) &&
 233               (cmd->InstructionDtrMode == OSPI_INSTRUCTION_DTR_ENABLE))
 234           {
 235             MODIFY_REG(instance->CCR, OCTOSPI_CCR_DDTR, OSPI_DATA_DTR_ENABLE);
 236           }
 237         }
 238
 239         instance->IR = cmd->Instruction;
 240
 241         instance->AR = cmd->Address;
 242       }
 243       else
 244       {
 245         if (cmd->DataMode != OSPI_DATA_NONE)
 246         {
 247           // instruction and data
 248
 249           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
 250                                   OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
 251                                  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
 252                                   cmd->DataMode        | cmd->DataDtrMode));
 253         }
 254         else
 255         {
 256           // instruction only
 257
 258           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
 259                                  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
 260
 261           // DHQC bit is linked with DDTR
 262           if (((instance->TCR & OCTOSPI_TCR_DHQC_Msk) == OSPI_DHQC_ENABLE) &&
 263               (cmd->InstructionDtrMode == OSPI_INSTRUCTION_DTR_ENABLE))
 264           {
 265             MODIFY_REG(instance->CCR, OCTOSPI_CCR_DDTR, OSPI_DATA_DTR_ENABLE);
 266           }
 267         }
 268
 269         instance->IR = cmd->Instruction;
 270
 271       }
 272     }
 273     else
 274     {
 275       if (cmd->AddressMode != OSPI_ADDRESS_NONE)
 276       {
 277         if (cmd->DataMode != OSPI_DATA_NONE)
 278         {
 279           // address and data
 280
 281           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
 282                                   OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
 283                                  (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize     |
 284                                   cmd->DataMode    | cmd->DataDtrMode));
 285         }
 286         else
 287         {
 288           // address only
 289
 290           MODIFY_REG(instance->CCR, (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
 291                                  (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
 292         }
 293
 294         instance->AR = cmd->Address;
 295       }
 296       else
 297       {
 298         // no instruction, no address
 299         status = ERROR;
 300       }
 301     }
 302
 303     return status;
 304 }
 305
 306 MMFLASH_CODE_NOINLINE ErrorStatus octoSpiCommand(OCTOSPI_TypeDef *instance, OSPI_Command_t *cmd)
 307 {
 308     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET);
 309
 310     ErrorStatus status = octoSpiConfigureCommand(instance, cmd);
 311     if (status == SUCCESS) {
 312         if (cmd->DataMode == OSPI_DATA_NONE)
 313         {
 314             // transfer is already started, wait now.
 315             octoSpiWaitStatusFlags(instance, OCTOSPI_SR_TCF, SET);
 316             __OSPI_CLEAR_FLAG(instance, OCTOSPI_SR_TCF);
 317         }
 318     }
 319
 320     return status;
 321 }
 322
 323 /*
 324  * Transmit
 325  *
 326  * Call optoSpiCommand first to configure the transaction stages.
 327  */
 328 MMFLASH_CODE_NOINLINE ErrorStatus octoSpiTransmit(OCTOSPI_TypeDef *instance, uint8_t *data)
 329 {
 330     if (data == NULL) {
 331         return ERROR;
 332     }
 333
 334     __IO uint32_t              XferCount = READ_REG(instance->DLR) + 1U;
 335     uint8_t                    *pBuffPtr = data;
 336
 337     MODIFY_REG(instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
 338
 339     __IO uint32_t *data_reg = &instance->DR;
 340     do
 341     {
 342       octoSpiWaitStatusFlags(instance, OCTOSPI_SR_FTF, SET);
 343
 344       *((__IO uint8_t *)data_reg) = *pBuffPtr;
 345       pBuffPtr++;
 346       XferCount--;
 347     } while (XferCount > 0U);
 348
 349     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_TCF, SET);
 350     __OSPI_CLEAR_FLAG(instance, OCTOSPI_SR_TCF);
 351
 352     return SUCCESS;
 353 }
 354
 355 /*
 356  * Receive
 357  *
 358  * Call optoSpiCommand first to configure the transaction stages.
 359  */
 360 MMFLASH_CODE_NOINLINE ErrorStatus octoSpiReceive(OCTOSPI_TypeDef *instance, uint8_t *data)
 361 {
 362     if (data == NULL) {
 363         return ERROR;
 364     }
 365
 366     __IO uint32_t              XferCount = READ_REG(instance->DLR) + 1U;
 367     uint8_t                    *pBuffPtr = data;
 368
 369     MODIFY_REG(instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
 370
 371     uint32_t addr_reg = instance->AR;
 372     uint32_t ir_reg = instance->IR;
 373
 374     // Trigger the transfer by re-writing the address or instruction register
 375     if (READ_BIT(instance->CCR, OCTOSPI_CCR_ADMODE) != OSPI_ADDRESS_NONE)
 376     {
 377       WRITE_REG(instance->AR, addr_reg);
 378     }
 379     else
 380     {
 381       WRITE_REG(instance->IR, ir_reg);
 382     }
 383
 384     __IO uint32_t *data_reg = &instance->DR;
 385
 386     do
 387     {
 388       octoSpiWaitStatusFlags(instance, OCTOSPI_SR_FTF | OCTOSPI_SR_TCF, SET);
 389
 390       *pBuffPtr = *((__IO uint8_t *)data_reg);
 391       pBuffPtr++;
 392       XferCount--;
 393     } while(XferCount > 0U);
 394
 395     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_TCF, SET);
 396     __OSPI_CLEAR_FLAG(instance, OCTOSPI_SR_TCF);
 397
 398     return SUCCESS;
 399 }
 400
 401 typedef struct
 402 {
 403     // CR register contains the all-important FMODE bits.
 404     uint32_t CR;
 405
 406     // flash chip specific configuration set by the bootloader
 407     uint32_t CCR;
 408     uint32_t TCR;
 409     uint32_t IR;
 410     uint32_t ABR;
 411     // address register - no meaning.
 412     // data length register no meaning.
 413
 414 } octoSpiMemoryMappedModeConfigurationRegisterBackup_t;
 415
 416 octoSpiMemoryMappedModeConfigurationRegisterBackup_t ospiMMMCRBackups[OCTOSPI_INTERFACE_COUNT];
 417
 418 void octoSpiBackupMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance)
 419 {
 420     OCTOSPIDevice device = octoSpiDeviceByInstance(instance);
 421     if (device == OCTOSPIINVALID) {
 422         return;
 423     }
 424
 425     octoSpiMemoryMappedModeConfigurationRegisterBackup_t *ospiMMMCRBackup = &ospiMMMCRBackups[device];
 426
 427     // backup all the registers used by memory mapped mode that:
 428     // a) the bootloader configured.
 429     // b) that other code in this implementation may have modified when memory mapped mode is disabled.
 430
 431     ospiMMMCRBackup->CR = instance->CR;
 432     ospiMMMCRBackup->IR = instance->IR;
 433     ospiMMMCRBackup->CCR = instance->CCR;
 434     ospiMMMCRBackup->TCR = instance->TCR;
 435     ospiMMMCRBackup->ABR = instance->ABR;
 436 }
 437
 438 MMFLASH_CODE_NOINLINE void octoSpiRestoreMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance)
 439 {
 440     OCTOSPIDevice device = octoSpiDeviceByInstance(instance);
 441     if (device == OCTOSPIINVALID) {
 442         return;
 443     }
 444
 445     octoSpiMemoryMappedModeConfigurationRegisterBackup_t *ospiMMMCRBackup = &ospiMMMCRBackups[device];
 446
 447     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET);
 448
 449     instance->ABR = ospiMMMCRBackup->ABR;
 450     instance->TCR = ospiMMMCRBackup->TCR;
 451
 452     instance->DLR = 0; // "no meaning" in MM mode.
 453
 454     instance->CCR = ospiMMMCRBackup->CCR;
 455
 456     instance->IR = ospiMMMCRBackup->IR;
 457     instance->AR = 0; // "no meaning" in MM mode.
 458
 459     octoSpiAbort(instance);
 460     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET);
 461
 462     instance->CR = ospiMMMCRBackup->CR;
 463 }
 464
 465 /*
 466  * Disable memory mapped mode.
 467  *
 468  * @See octoSpiEnableMemoryMappedMode
 469  * @See MMFLASH_CODE_NOINLINE
 470  *
 471  * Once this is called any code or data in the memory mapped region cannot be accessed.
 472  * Thus, this function itself must be in RAM, and the caller's code and data should all be in RAM
 473  * and this requirement continues until octoSpiEnableMemoryMappedMode is called.
 474  * This applies to ISR code that runs from the memory mapped region, so likely the caller should
 475  * also disable IRQs before calling this.
 476  */
 477 MMFLASH_CODE_NOINLINE void octoSpiDisableMemoryMappedMode(OCTOSPI_TypeDef *instance)
 478 {
 479     if (READ_BIT(OCTOSPI1->CR, OCTOSPI_CR_FMODE) != OCTOSPI_CR_FMODE) {
 480         failureMode(FAILURE_DEVELOPER); // likely not booted with memory mapped mode enabled, or mismatched calls to enable/disable memory map mode.
 481     }
 482
 483     octoSpiAbort(instance);
 484     if (__OSPI_GET_FLAG(instance, OCTOSPI_SR_BUSY) == SET) {
 485
 486         __OSPI_DISABLE(instance);
 487         octoSpiAbort(instance);
 488     }
 489     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET);
 490
 491     uint32_t fmode = 0x0;  // b00 = indirect write, see OCTOSPI->CR->FMODE
 492     MODIFY_REG(instance->CR, OCTOSPI_CR_FMODE, fmode);
 493
 494     uint32_t regval = READ_REG(instance->CR);
 495     if ((regval & OCTOSPI_CR_FMODE) != fmode) {
 496         Error_Handler();
 497     }
 498
 499     if (!__OSPI_IS_ENABLED(instance)) {
 500         __OSPI_ENABLE(instance);
 501     }
 502 }
 503
 504 /*
 505  * Enable memory mapped mode.
 506  *
 507  * @See octoSpiDisableMemoryMappedMode
 508  * @See MMFLASH_CODE_NOINLINE
 509  */
 510
 511 MMFLASH_CODE_NOINLINE void octoSpiEnableMemoryMappedMode(OCTOSPI_TypeDef *instance)
 512 {
 513     octoSpiAbort(instance);
 514     octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET);
 515
 516     octoSpiRestoreMemoryMappedModeConfiguration(instance);
 517 }
 518
 519 MMFLASH_CODE_NOINLINE void octoSpiTestEnableDisableMemoryMappedMode(octoSpiDevice_t *octoSpi)
 520 {
 521     OCTOSPI_TypeDef *instance = octoSpi->dev;
 522
 523     __disable_irq();
 524     octoSpiDisableMemoryMappedMode(instance);
 525     octoSpiEnableMemoryMappedMode(instance);
 526     __enable_irq();
 527 }
 528
 529 MMFLASH_DATA static const uint32_t octoSpi_addressSizeMap[] = {
 530     OSPI_ADDRESS_8_BITS,
 531     OSPI_ADDRESS_16_BITS,
 532     OSPI_ADDRESS_24_BITS,
 533     OSPI_ADDRESS_32_BITS
 534 };
 535
 536 MMFLASH_CODE static uint32_t octoSpi_addressSizeFromValue(uint8_t addressSize)
 537 {
 538     return octoSpi_addressSizeMap[((addressSize + 1) / 8) - 1]; // rounds to nearest OSPI_ADDRESS_* value that will hold the address.
 539 }
 540
 541 MMFLASH_CODE_NOINLINE bool octoSpiTransmit1LINE(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, const uint8_t *out, int length)
 542 {
 543     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 544
 545     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 546
 547     cmd.Instruction        = instruction;
 548     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 549     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 550     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 551
 552     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 553     cmd.AddressMode        = OSPI_ADDRESS_NONE;
 554     cmd.AddressSize        = OSPI_ADDRESS_32_BITS;
 555
 556     cmd.DummyCycles        = dummyCycles;
 557
 558     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 559
 560     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 561     cmd.DataMode           = OSPI_DATA_NONE;
 562     cmd.NbData             = length;
 563
 564     cmd.DQSMode            = OSPI_DQS_DISABLE;
 565     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 566
 567     if (out) {
 568         cmd.DataMode       = OSPI_DATA_1_LINE;
 569     }
 570
 571     ErrorStatus status = octoSpiCommand(instance, &cmd);
 572
 573     if (status == SUCCESS && out && length > 0) {
 574         status = octoSpiTransmit(instance, (uint8_t *)out);
 575     }
 576     return status == SUCCESS;
 577 }
 578
 579 MMFLASH_CODE_NOINLINE bool octoSpiReceive1LINE(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint8_t *in, int length)
 580 {
 581     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 582
 583     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 584
 585     cmd.Instruction        = instruction;
 586     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 587     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 588     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 589
 590     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 591     cmd.AddressMode        = OSPI_ADDRESS_NONE;
 592     cmd.AddressSize        = OSPI_ADDRESS_32_BITS;
 593
 594     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 595
 596     cmd.DummyCycles        = dummyCycles;
 597
 598     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 599     cmd.DataMode           = OSPI_DATA_1_LINE;
 600     cmd.NbData             = length;
 601
 602     cmd.DQSMode            = OSPI_DQS_DISABLE;
 603     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 604
 605     ErrorStatus status = octoSpiCommand(instance, &cmd);
 606
 607     if (status == SUCCESS) {
 608         status = octoSpiReceive(instance, in);
 609     }
 610
 611     return status == SUCCESS;
 612 }
 613
 614 MMFLASH_CODE_NOINLINE bool octoSpiReceive4LINES(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint8_t *in, int length)
 615 {
 616     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 617
 618     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 619
 620     cmd.Instruction        = instruction;
 621     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 622     cmd.InstructionMode    = OSPI_INSTRUCTION_4_LINES;
 623     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 624
 625     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 626     cmd.AddressMode        = OSPI_ADDRESS_NONE;
 627     cmd.AddressSize        = OSPI_ADDRESS_32_BITS;
 628
 629     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 630
 631     cmd.DummyCycles        = dummyCycles;
 632
 633     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 634     cmd.DataMode           = OSPI_DATA_4_LINES;
 635     cmd.NbData             = length;
 636
 637     cmd.DQSMode            = OSPI_DQS_DISABLE;
 638     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 639
 640     ErrorStatus status = octoSpiCommand(instance, &cmd);
 641
 642     if (status == SUCCESS) {
 643         status = octoSpiReceive(instance, in);
 644     }
 645
 646     return status == SUCCESS;
 647 }
 648
 649 MMFLASH_CODE_NOINLINE bool octoSpiReceiveWithAddress1LINE(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, uint8_t *in, int length)
 650 {
 651     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 652
 653     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 654
 655     cmd.Instruction        = instruction;
 656     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 657     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 658     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 659
 660     cmd.Address            = address;
 661     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 662     cmd.AddressMode        = OSPI_ADDRESS_1_LINE;
 663     cmd.AddressSize        = octoSpi_addressSizeFromValue(addressSize);
 664
 665     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 666
 667     cmd.DummyCycles        = dummyCycles;
 668
 669     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 670     cmd.DataMode           = OSPI_DATA_1_LINE;
 671     cmd.NbData             = length;
 672
 673     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 674     cmd.DQSMode            = OSPI_DQS_DISABLE;
 675
 676     ErrorStatus status = octoSpiCommand(instance, &cmd);
 677
 678     if (status == SUCCESS) {
 679         status = octoSpiReceive(instance, in);
 680     }
 681
 682     return status == SUCCESS;
 683 }
 684
 685 MMFLASH_CODE_NOINLINE bool octoSpiReceiveWithAddress4LINES(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, uint8_t *in, int length)
 686 {
 687     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 688
 689     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 690
 691     cmd.Instruction        = instruction;
 692     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 693     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 694     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 695
 696     cmd.Address            = address;
 697     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 698     cmd.AddressMode        = OSPI_ADDRESS_1_LINE;
 699     cmd.AddressSize        = octoSpi_addressSizeFromValue(addressSize);
 700
 701     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 702
 703     cmd.DummyCycles        = dummyCycles;
 704
 705     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 706     cmd.DataMode           = OSPI_DATA_4_LINES;
 707     cmd.NbData             = length;
 708
 709     cmd.DQSMode            = OSPI_DQS_DISABLE;
 710     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 711
 712     ErrorStatus status = octoSpiCommand(instance, &cmd);
 713
 714     if (status == SUCCESS) {
 715         status = octoSpiReceive(instance, in);
 716     }
 717
 718     return status == SUCCESS;
 719 }
 720
 721 MMFLASH_CODE_NOINLINE bool octoSpiTransmitWithAddress1LINE(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, const uint8_t *out, int length)
 722 {
 723     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 724
 725     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 726
 727     cmd.Instruction        = instruction;
 728     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 729     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 730     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 731
 732     cmd.Address            = address;
 733     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 734     cmd.AddressMode        = OSPI_ADDRESS_1_LINE;
 735     cmd.AddressSize        = octoSpi_addressSizeFromValue(addressSize);
 736
 737     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 738
 739     cmd.DummyCycles        = dummyCycles;
 740
 741     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 742     cmd.DataMode           = OSPI_DATA_1_LINE;
 743     cmd.NbData             = length;
 744
 745     cmd.DQSMode            = OSPI_DQS_DISABLE;
 746     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 747
 748     ErrorStatus status = octoSpiCommand(instance, &cmd);
 749
 750     if (status == SUCCESS) {
 751         status = octoSpiTransmit(instance, (uint8_t *)out);
 752     }
 753
 754     return status == SUCCESS;
 755 }
 756
 757 MMFLASH_CODE_NOINLINE bool octoSpiTransmitWithAddress4LINES(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, const uint8_t *out, int length)
 758 {
 759     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 760
 761     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 762
 763     cmd.Instruction        = instruction;
 764     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 765     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 766     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 767
 768     cmd.Address            = address;
 769     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 770     cmd.AddressMode        = OSPI_ADDRESS_1_LINE;
 771     cmd.AddressSize        = octoSpi_addressSizeFromValue(addressSize);
 772
 773     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 774
 775     cmd.DummyCycles        = dummyCycles;
 776
 777     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 778     cmd.DataMode           = OSPI_DATA_4_LINES;
 779     cmd.NbData             = length;
 780
 781     cmd.DQSMode            = OSPI_DQS_DISABLE;
 782     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 783
 784     ErrorStatus status = octoSpiCommand(instance, &cmd);
 785
 786     if (status == SUCCESS) {
 787         status = octoSpiTransmit(instance, (uint8_t *)out);
 788     }
 789
 790     return status == SUCCESS;
 791 }
 792
 793 MMFLASH_CODE_NOINLINE bool octoSpiInstructionWithAddress1LINE(OCTOSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize)
 794 {
 795     OSPI_Command_t cmd; // Can't initialise to zero as compiler optimization will use memset() which is not in RAM.
 796
 797     cmd.OperationType      = OSPI_OPTYPE_COMMON_CFG;
 798
 799     cmd.Instruction        = instruction;
 800     cmd.InstructionDtrMode = OSPI_INSTRUCTION_DTR_DISABLE;
 801     cmd.InstructionMode    = OSPI_INSTRUCTION_1_LINE;
 802     cmd.InstructionSize    = OSPI_INSTRUCTION_8_BITS;
 803
 804     cmd.Address            = address;
 805     cmd.AddressDtrMode     = OSPI_ADDRESS_DTR_DISABLE;
 806     cmd.AddressMode        = OSPI_ADDRESS_1_LINE;
 807     cmd.AddressSize        = octoSpi_addressSizeFromValue(addressSize);
 808
 809     cmd.AlternateBytesMode = OSPI_ALTERNATE_BYTES_NONE;
 810
 811     cmd.DummyCycles        = dummyCycles;
 812
 813     cmd.DataDtrMode        = OSPI_DATA_DTR_DISABLE;
 814     cmd.DataMode           = OSPI_DATA_NONE;
 815     cmd.NbData             = 0;
 816
 817     cmd.DQSMode            = OSPI_DQS_DISABLE;
 818     cmd.SIOOMode           = OSPI_SIOO_INST_EVERY_CMD;
 819
 820     ErrorStatus status = octoSpiCommand(instance, &cmd);
 821
 822     return status == SUCCESS;
 823 }
 824
 825 void octoSpiInitDevice(OCTOSPIDevice device)
 826 {
 827     octoSpiDevice_t *octoSpi = &(octoSpiDevice[device]);
 828
 829 #if defined(STM32H730xx) || defined(STM32H723xx)
 830     if (isMemoryMappedModeEnabledOnBoot()) {
 831         // Bootloader has already configured the IO, clocks and peripherals.
 832         octoSpiBackupMemoryMappedModeConfiguration(octoSpi->dev);
 833
 834         octoSpiTestEnableDisableMemoryMappedMode(octoSpi);
 835     } else {
 836         failureMode(FAILURE_DEVELOPER); // trying to use this implementation when memory mapped mode is not already enabled by a bootloader
 837
 838         // Here is where we would configure the OCTOSPI1/2 and OCTOSPIM peripherals for the non-memory-mapped use case.
 839     }
 840 #else
 841 #error MCU not supported.
 842 #endif
 843
 844 }
 845
 846 #endif